assembler_sparc.hpp revision 1472:c18cbe5936b8
1/* 2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25class BiasedLockingCounters; 26 27// <sys/trap.h> promises that the system will not use traps 16-31 28#define ST_RESERVED_FOR_USER_0 0x10 29 30/* Written: David Ungar 4/19/97 */ 31 32// Contains all the definitions needed for sparc assembly code generation. 33 34// Register aliases for parts of the system: 35 36// 64 bit values can be kept in g1-g5, o1-o5 and o7 and all 64 bits are safe 37// across context switches in V8+ ABI. Of course, there are no 64 bit regs 38// in V8 ABI. All 64 bits are preserved in V9 ABI for all registers. 39 40// g2-g4 are scratch registers called "application globals". Their 41// meaning is reserved to the "compilation system"--which means us! 42// They are are not supposed to be touched by ordinary C code, although 43// highly-optimized C code might steal them for temps. They are safe 44// across thread switches, and the ABI requires that they be safe 45// across function calls. 46// 47// g1 and g3 are touched by more modules. V8 allows g1 to be clobbered 48// across func calls, and V8+ also allows g5 to be clobbered across 49// func calls. Also, g1 and g5 can get touched while doing shared 50// library loading. 51// 52// We must not touch g7 (it is the thread-self register) and g6 is 53// reserved for certain tools. g0, of course, is always zero. 54// 55// (Sources: SunSoft Compilers Group, thread library engineers.) 56 57// %%%% The interpreter should be revisited to reduce global scratch regs. 58 59// This global always holds the current JavaThread pointer: 60 61REGISTER_DECLARATION(Register, G2_thread , G2); 62REGISTER_DECLARATION(Register, G6_heapbase , G6); 63 64// The following globals are part of the Java calling convention: 65 66REGISTER_DECLARATION(Register, G5_method , G5); 67REGISTER_DECLARATION(Register, G5_megamorphic_method , G5_method); 68REGISTER_DECLARATION(Register, G5_inline_cache_reg , G5_method); 69 70// The following globals are used for the new C1 & interpreter calling convention: 71REGISTER_DECLARATION(Register, Gargs , G4); // pointing to the last argument 72 73// This local is used to preserve G2_thread in the interpreter and in stubs: 74REGISTER_DECLARATION(Register, L7_thread_cache , L7); 75 76// These globals are used as scratch registers in the interpreter: 77 78REGISTER_DECLARATION(Register, Gframe_size , G1); // SAME REG as G1_scratch 79REGISTER_DECLARATION(Register, G1_scratch , G1); // also SAME 80REGISTER_DECLARATION(Register, G3_scratch , G3); 81REGISTER_DECLARATION(Register, G4_scratch , G4); 82 83// These globals are used as short-lived scratch registers in the compiler: 84 85REGISTER_DECLARATION(Register, Gtemp , G5); 86 87// JSR 292 fixed register usages: 88REGISTER_DECLARATION(Register, G5_method_type , G5); 89REGISTER_DECLARATION(Register, G3_method_handle , G3); 90 91// The compiler requires that G5_megamorphic_method is G5_inline_cache_klass, 92// because a single patchable "set" instruction (NativeMovConstReg, 93// or NativeMovConstPatching for compiler1) instruction 94// serves to set up either quantity, depending on whether the compiled 95// call site is an inline cache or is megamorphic. See the function 96// CompiledIC::set_to_megamorphic. 97// 98// If a inline cache targets an interpreted method, then the 99// G5 register will be used twice during the call. First, 100// the call site will be patched to load a compiledICHolder 101// into G5. (This is an ordered pair of ic_klass, method.) 102// The c2i adapter will first check the ic_klass, then load 103// G5_method with the method part of the pair just before 104// jumping into the interpreter. 105// 106// Note that G5_method is only the method-self for the interpreter, 107// and is logically unrelated to G5_megamorphic_method. 108// 109// Invariants on G2_thread (the JavaThread pointer): 110// - it should not be used for any other purpose anywhere 111// - it must be re-initialized by StubRoutines::call_stub() 112// - it must be preserved around every use of call_VM 113 114// We can consider using g2/g3/g4 to cache more values than the 115// JavaThread, such as the card-marking base or perhaps pointers into 116// Eden. It's something of a waste to use them as scratch temporaries, 117// since they are not supposed to be volatile. (Of course, if we find 118// that Java doesn't benefit from application globals, then we can just 119// use them as ordinary temporaries.) 120// 121// Since g1 and g5 (and/or g6) are the volatile (caller-save) registers, 122// it makes sense to use them routinely for procedure linkage, 123// whenever the On registers are not applicable. Examples: G5_method, 124// G5_inline_cache_klass, and a double handful of miscellaneous compiler 125// stubs. This means that compiler stubs, etc., should be kept to a 126// maximum of two or three G-register arguments. 127 128 129// stub frames 130 131REGISTER_DECLARATION(Register, Lentry_args , L0); // pointer to args passed to callee (interpreter) not stub itself 132 133// Interpreter frames 134 135#ifdef CC_INTERP 136REGISTER_DECLARATION(Register, Lstate , L0); // interpreter state object pointer 137REGISTER_DECLARATION(Register, L1_scratch , L1); // scratch 138REGISTER_DECLARATION(Register, Lmirror , L1); // mirror (for native methods only) 139REGISTER_DECLARATION(Register, L2_scratch , L2); 140REGISTER_DECLARATION(Register, L3_scratch , L3); 141REGISTER_DECLARATION(Register, L4_scratch , L4); 142REGISTER_DECLARATION(Register, Lscratch , L5); // C1 uses 143REGISTER_DECLARATION(Register, Lscratch2 , L6); // C1 uses 144REGISTER_DECLARATION(Register, L7_scratch , L7); // constant pool cache 145REGISTER_DECLARATION(Register, O5_savedSP , O5); 146REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply 147 // a copy SP, so in 64-bit it's a biased value. The bias 148 // is added and removed as needed in the frame code. 149// Interface to signature handler 150REGISTER_DECLARATION(Register, Llocals , L7); // pointer to locals for signature handler 151REGISTER_DECLARATION(Register, Lmethod , L6); // methodOop when calling signature handler 152 153#else 154REGISTER_DECLARATION(Register, Lesp , L0); // expression stack pointer 155REGISTER_DECLARATION(Register, Lbcp , L1); // pointer to next bytecode 156REGISTER_DECLARATION(Register, Lmethod , L2); 157REGISTER_DECLARATION(Register, Llocals , L3); 158REGISTER_DECLARATION(Register, Largs , L3); // pointer to locals for signature handler 159 // must match Llocals in asm interpreter 160REGISTER_DECLARATION(Register, Lmonitors , L4); 161REGISTER_DECLARATION(Register, Lbyte_code , L5); 162// When calling out from the interpreter we record SP so that we can remove any extra stack 163// space allocated during adapter transitions. This register is only live from the point 164// of the call until we return. 165REGISTER_DECLARATION(Register, Llast_SP , L5); 166REGISTER_DECLARATION(Register, Lscratch , L5); 167REGISTER_DECLARATION(Register, Lscratch2 , L6); 168REGISTER_DECLARATION(Register, LcpoolCache , L6); // constant pool cache 169 170REGISTER_DECLARATION(Register, O5_savedSP , O5); 171REGISTER_DECLARATION(Register, I5_savedSP , I5); // Saved SP before bumping for locals. This is simply 172 // a copy SP, so in 64-bit it's a biased value. The bias 173 // is added and removed as needed in the frame code. 174REGISTER_DECLARATION(Register, IdispatchTables , I4); // Base address of the bytecode dispatch tables 175REGISTER_DECLARATION(Register, IdispatchAddress , I3); // Register which saves the dispatch address for each bytecode 176REGISTER_DECLARATION(Register, ImethodDataPtr , I2); // Pointer to the current method data 177#endif /* CC_INTERP */ 178 179// NOTE: Lscratch2 and LcpoolCache point to the same registers in 180// the interpreter code. If Lscratch2 needs to be used for some 181// purpose than LcpoolCache should be restore after that for 182// the interpreter to work right 183// (These assignments must be compatible with L7_thread_cache; see above.) 184 185// Since Lbcp points into the middle of the method object, 186// it is temporarily converted into a "bcx" during GC. 187 188// Exception processing 189// These registers are passed into exception handlers. 190// All exception handlers require the exception object being thrown. 191// In addition, an nmethod's exception handler must be passed 192// the address of the call site within the nmethod, to allow 193// proper selection of the applicable catch block. 194// (Interpreter frames use their own bcp() for this purpose.) 195// 196// The Oissuing_pc value is not always needed. When jumping to a 197// handler that is known to be interpreted, the Oissuing_pc value can be 198// omitted. An actual catch block in compiled code receives (from its 199// nmethod's exception handler) the thrown exception in the Oexception, 200// but it doesn't need the Oissuing_pc. 201// 202// If an exception handler (either interpreted or compiled) 203// discovers there is no applicable catch block, it updates 204// the Oissuing_pc to the continuation PC of its own caller, 205// pops back to that caller's stack frame, and executes that 206// caller's exception handler. Obviously, this process will 207// iterate until the control stack is popped back to a method 208// containing an applicable catch block. A key invariant is 209// that the Oissuing_pc value is always a value local to 210// the method whose exception handler is currently executing. 211// 212// Note: The issuing PC value is __not__ a raw return address (I7 value). 213// It is a "return pc", the address __following__ the call. 214// Raw return addresses are converted to issuing PCs by frame::pc(), 215// or by stubs. Issuing PCs can be used directly with PC range tables. 216// 217REGISTER_DECLARATION(Register, Oexception , O0); // exception being thrown 218REGISTER_DECLARATION(Register, Oissuing_pc , O1); // where the exception is coming from 219 220 221// These must occur after the declarations above 222#ifndef DONT_USE_REGISTER_DEFINES 223 224#define Gthread AS_REGISTER(Register, Gthread) 225#define Gmethod AS_REGISTER(Register, Gmethod) 226#define Gmegamorphic_method AS_REGISTER(Register, Gmegamorphic_method) 227#define Ginline_cache_reg AS_REGISTER(Register, Ginline_cache_reg) 228#define Gargs AS_REGISTER(Register, Gargs) 229#define Lthread_cache AS_REGISTER(Register, Lthread_cache) 230#define Gframe_size AS_REGISTER(Register, Gframe_size) 231#define Gtemp AS_REGISTER(Register, Gtemp) 232 233#ifdef CC_INTERP 234#define Lstate AS_REGISTER(Register, Lstate) 235#define Lesp AS_REGISTER(Register, Lesp) 236#define L1_scratch AS_REGISTER(Register, L1_scratch) 237#define Lmirror AS_REGISTER(Register, Lmirror) 238#define L2_scratch AS_REGISTER(Register, L2_scratch) 239#define L3_scratch AS_REGISTER(Register, L3_scratch) 240#define L4_scratch AS_REGISTER(Register, L4_scratch) 241#define Lscratch AS_REGISTER(Register, Lscratch) 242#define Lscratch2 AS_REGISTER(Register, Lscratch2) 243#define L7_scratch AS_REGISTER(Register, L7_scratch) 244#define Ostate AS_REGISTER(Register, Ostate) 245#else 246#define Lesp AS_REGISTER(Register, Lesp) 247#define Lbcp AS_REGISTER(Register, Lbcp) 248#define Lmethod AS_REGISTER(Register, Lmethod) 249#define Llocals AS_REGISTER(Register, Llocals) 250#define Lmonitors AS_REGISTER(Register, Lmonitors) 251#define Lbyte_code AS_REGISTER(Register, Lbyte_code) 252#define Lscratch AS_REGISTER(Register, Lscratch) 253#define Lscratch2 AS_REGISTER(Register, Lscratch2) 254#define LcpoolCache AS_REGISTER(Register, LcpoolCache) 255#endif /* ! CC_INTERP */ 256 257#define Lentry_args AS_REGISTER(Register, Lentry_args) 258#define I5_savedSP AS_REGISTER(Register, I5_savedSP) 259#define O5_savedSP AS_REGISTER(Register, O5_savedSP) 260#define IdispatchAddress AS_REGISTER(Register, IdispatchAddress) 261#define ImethodDataPtr AS_REGISTER(Register, ImethodDataPtr) 262#define IdispatchTables AS_REGISTER(Register, IdispatchTables) 263 264#define Oexception AS_REGISTER(Register, Oexception) 265#define Oissuing_pc AS_REGISTER(Register, Oissuing_pc) 266 267 268#endif 269 270// Address is an abstraction used to represent a memory location. 271// 272// Note: A register location is represented via a Register, not 273// via an address for efficiency & simplicity reasons. 274 275class Address VALUE_OBJ_CLASS_SPEC { 276 private: 277 Register _base; // Base register. 278 RegisterOrConstant _index_or_disp; // Index register or constant displacement. 279 RelocationHolder _rspec; 280 281 public: 282 Address() : _base(noreg), _index_or_disp(noreg) {} 283 284 Address(Register base, RegisterOrConstant index_or_disp) 285 : _base(base), 286 _index_or_disp(index_or_disp) { 287 } 288 289 Address(Register base, Register index) 290 : _base(base), 291 _index_or_disp(index) { 292 } 293 294 Address(Register base, int disp) 295 : _base(base), 296 _index_or_disp(disp) { 297 } 298 299#ifdef ASSERT 300 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. 301 Address(Register base, ByteSize disp) 302 : _base(base), 303 _index_or_disp(in_bytes(disp)) { 304 } 305#endif 306 307 // accessors 308 Register base() const { return _base; } 309 Register index() const { return _index_or_disp.as_register(); } 310 int disp() const { return _index_or_disp.as_constant(); } 311 312 bool has_index() const { return _index_or_disp.is_register(); } 313 bool has_disp() const { return _index_or_disp.is_constant(); } 314 315 const relocInfo::relocType rtype() { return _rspec.type(); } 316 const RelocationHolder& rspec() { return _rspec; } 317 318 RelocationHolder rspec(int offset) const { 319 return offset == 0 ? _rspec : _rspec.plus(offset); 320 } 321 322 inline bool is_simm13(int offset = 0); // check disp+offset for overflow 323 324 Address plus_disp(int plusdisp) const { // bump disp by a small amount 325 assert(_index_or_disp.is_constant(), "must have a displacement"); 326 Address a(base(), disp() + plusdisp); 327 return a; 328 } 329 330 Address after_save() const { 331 Address a = (*this); 332 a._base = a._base->after_save(); 333 return a; 334 } 335 336 Address after_restore() const { 337 Address a = (*this); 338 a._base = a._base->after_restore(); 339 return a; 340 } 341 342 // Convert the raw encoding form into the form expected by the 343 // constructor for Address. 344 static Address make_raw(int base, int index, int scale, int disp, bool disp_is_oop); 345 346 friend class Assembler; 347}; 348 349 350class AddressLiteral VALUE_OBJ_CLASS_SPEC { 351 private: 352 address _address; 353 RelocationHolder _rspec; 354 355 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { 356 switch (rtype) { 357 case relocInfo::external_word_type: 358 return external_word_Relocation::spec(addr); 359 case relocInfo::internal_word_type: 360 return internal_word_Relocation::spec(addr); 361#ifdef _LP64 362 case relocInfo::opt_virtual_call_type: 363 return opt_virtual_call_Relocation::spec(); 364 case relocInfo::static_call_type: 365 return static_call_Relocation::spec(); 366 case relocInfo::runtime_call_type: 367 return runtime_call_Relocation::spec(); 368#endif 369 case relocInfo::none: 370 return RelocationHolder(); 371 default: 372 ShouldNotReachHere(); 373 return RelocationHolder(); 374 } 375 } 376 377 protected: 378 // creation 379 AddressLiteral() : _address(NULL), _rspec(NULL) {} 380 381 public: 382 AddressLiteral(address addr, RelocationHolder const& rspec) 383 : _address(addr), 384 _rspec(rspec) {} 385 386 // Some constructors to avoid casting at the call site. 387 AddressLiteral(jobject obj, RelocationHolder const& rspec) 388 : _address((address) obj), 389 _rspec(rspec) {} 390 391 AddressLiteral(intptr_t value, RelocationHolder const& rspec) 392 : _address((address) value), 393 _rspec(rspec) {} 394 395 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) 396 : _address((address) addr), 397 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 398 399 // Some constructors to avoid casting at the call site. 400 AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none) 401 : _address((address) addr), 402 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 403 404 AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none) 405 : _address((address) addr), 406 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 407 408 AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none) 409 : _address((address) addr), 410 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 411 412 AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none) 413 : _address((address) addr), 414 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 415 416 AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none) 417 : _address((address) addr), 418 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 419 420 AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none) 421 : _address((address) addr), 422 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 423 424#ifdef _LP64 425 // 32-bit complains about a multiple declaration for int*. 426 AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none) 427 : _address((address) addr), 428 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 429#endif 430 431 AddressLiteral(oop addr, relocInfo::relocType rtype = relocInfo::none) 432 : _address((address) addr), 433 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 434 435 AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none) 436 : _address((address) addr), 437 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 438 439 AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none) 440 : _address((address) addr), 441 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 442 443 intptr_t value() const { return (intptr_t) _address; } 444 int low10() const; 445 446 const relocInfo::relocType rtype() const { return _rspec.type(); } 447 const RelocationHolder& rspec() const { return _rspec; } 448 449 RelocationHolder rspec(int offset) const { 450 return offset == 0 ? _rspec : _rspec.plus(offset); 451 } 452}; 453 454 455inline Address RegisterImpl::address_in_saved_window() const { 456 return (Address(SP, (sp_offset_in_saved_window() * wordSize) + STACK_BIAS)); 457} 458 459 460 461// Argument is an abstraction used to represent an outgoing 462// actual argument or an incoming formal parameter, whether 463// it resides in memory or in a register, in a manner consistent 464// with the SPARC Application Binary Interface, or ABI. This is 465// often referred to as the native or C calling convention. 466 467class Argument VALUE_OBJ_CLASS_SPEC { 468 private: 469 int _number; 470 bool _is_in; 471 472 public: 473#ifdef _LP64 474 enum { 475 n_register_parameters = 6, // only 6 registers may contain integer parameters 476 n_float_register_parameters = 16 // Can have up to 16 floating registers 477 }; 478#else 479 enum { 480 n_register_parameters = 6 // only 6 registers may contain integer parameters 481 }; 482#endif 483 484 // creation 485 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {} 486 487 int number() const { return _number; } 488 bool is_in() const { return _is_in; } 489 bool is_out() const { return !is_in(); } 490 491 Argument successor() const { return Argument(number() + 1, is_in()); } 492 Argument as_in() const { return Argument(number(), true ); } 493 Argument as_out() const { return Argument(number(), false); } 494 495 // locating register-based arguments: 496 bool is_register() const { return _number < n_register_parameters; } 497 498#ifdef _LP64 499 // locating Floating Point register-based arguments: 500 bool is_float_register() const { return _number < n_float_register_parameters; } 501 502 FloatRegister as_float_register() const { 503 assert(is_float_register(), "must be a register argument"); 504 return as_FloatRegister(( number() *2 ) + 1); 505 } 506 FloatRegister as_double_register() const { 507 assert(is_float_register(), "must be a register argument"); 508 return as_FloatRegister(( number() *2 )); 509 } 510#endif 511 512 Register as_register() const { 513 assert(is_register(), "must be a register argument"); 514 return is_in() ? as_iRegister(number()) : as_oRegister(number()); 515 } 516 517 // locating memory-based arguments 518 Address as_address() const { 519 assert(!is_register(), "must be a memory argument"); 520 return address_in_frame(); 521 } 522 523 // When applied to a register-based argument, give the corresponding address 524 // into the 6-word area "into which callee may store register arguments" 525 // (This is a different place than the corresponding register-save area location.) 526 Address address_in_frame() const; 527 528 // debugging 529 const char* name() const; 530 531 friend class Assembler; 532}; 533 534 535// The SPARC Assembler: Pure assembler doing NO optimizations on the instruction 536// level; i.e., what you write 537// is what you get. The Assembler is generating code into a CodeBuffer. 538 539class Assembler : public AbstractAssembler { 540 protected: 541 542 static void print_instruction(int inst); 543 static int patched_branch(int dest_pos, int inst, int inst_pos); 544 static int branch_destination(int inst, int pos); 545 546 547 friend class AbstractAssembler; 548 friend class AddressLiteral; 549 550 // code patchers need various routines like inv_wdisp() 551 friend class NativeInstruction; 552 friend class NativeGeneralJump; 553 friend class Relocation; 554 friend class Label; 555 556 public: 557 // op carries format info; see page 62 & 267 558 559 enum ops { 560 call_op = 1, // fmt 1 561 branch_op = 0, // also sethi (fmt2) 562 arith_op = 2, // fmt 3, arith & misc 563 ldst_op = 3 // fmt 3, load/store 564 }; 565 566 enum op2s { 567 bpr_op2 = 3, 568 fb_op2 = 6, 569 fbp_op2 = 5, 570 br_op2 = 2, 571 bp_op2 = 1, 572 cb_op2 = 7, // V8 573 sethi_op2 = 4 574 }; 575 576 enum op3s { 577 // selected op3s 578 add_op3 = 0x00, 579 and_op3 = 0x01, 580 or_op3 = 0x02, 581 xor_op3 = 0x03, 582 sub_op3 = 0x04, 583 andn_op3 = 0x05, 584 orn_op3 = 0x06, 585 xnor_op3 = 0x07, 586 addc_op3 = 0x08, 587 mulx_op3 = 0x09, 588 umul_op3 = 0x0a, 589 smul_op3 = 0x0b, 590 subc_op3 = 0x0c, 591 udivx_op3 = 0x0d, 592 udiv_op3 = 0x0e, 593 sdiv_op3 = 0x0f, 594 595 addcc_op3 = 0x10, 596 andcc_op3 = 0x11, 597 orcc_op3 = 0x12, 598 xorcc_op3 = 0x13, 599 subcc_op3 = 0x14, 600 andncc_op3 = 0x15, 601 orncc_op3 = 0x16, 602 xnorcc_op3 = 0x17, 603 addccc_op3 = 0x18, 604 umulcc_op3 = 0x1a, 605 smulcc_op3 = 0x1b, 606 subccc_op3 = 0x1c, 607 udivcc_op3 = 0x1e, 608 sdivcc_op3 = 0x1f, 609 610 taddcc_op3 = 0x20, 611 tsubcc_op3 = 0x21, 612 taddcctv_op3 = 0x22, 613 tsubcctv_op3 = 0x23, 614 mulscc_op3 = 0x24, 615 sll_op3 = 0x25, 616 sllx_op3 = 0x25, 617 srl_op3 = 0x26, 618 srlx_op3 = 0x26, 619 sra_op3 = 0x27, 620 srax_op3 = 0x27, 621 rdreg_op3 = 0x28, 622 membar_op3 = 0x28, 623 624 flushw_op3 = 0x2b, 625 movcc_op3 = 0x2c, 626 sdivx_op3 = 0x2d, 627 popc_op3 = 0x2e, 628 movr_op3 = 0x2f, 629 630 sir_op3 = 0x30, 631 wrreg_op3 = 0x30, 632 saved_op3 = 0x31, 633 634 fpop1_op3 = 0x34, 635 fpop2_op3 = 0x35, 636 impdep1_op3 = 0x36, 637 impdep2_op3 = 0x37, 638 jmpl_op3 = 0x38, 639 rett_op3 = 0x39, 640 trap_op3 = 0x3a, 641 flush_op3 = 0x3b, 642 save_op3 = 0x3c, 643 restore_op3 = 0x3d, 644 done_op3 = 0x3e, 645 retry_op3 = 0x3e, 646 647 lduw_op3 = 0x00, 648 ldub_op3 = 0x01, 649 lduh_op3 = 0x02, 650 ldd_op3 = 0x03, 651 stw_op3 = 0x04, 652 stb_op3 = 0x05, 653 sth_op3 = 0x06, 654 std_op3 = 0x07, 655 ldsw_op3 = 0x08, 656 ldsb_op3 = 0x09, 657 ldsh_op3 = 0x0a, 658 ldx_op3 = 0x0b, 659 660 ldstub_op3 = 0x0d, 661 stx_op3 = 0x0e, 662 swap_op3 = 0x0f, 663 664 stwa_op3 = 0x14, 665 stxa_op3 = 0x1e, 666 667 ldf_op3 = 0x20, 668 ldfsr_op3 = 0x21, 669 ldqf_op3 = 0x22, 670 lddf_op3 = 0x23, 671 stf_op3 = 0x24, 672 stfsr_op3 = 0x25, 673 stqf_op3 = 0x26, 674 stdf_op3 = 0x27, 675 676 prefetch_op3 = 0x2d, 677 678 679 ldc_op3 = 0x30, 680 ldcsr_op3 = 0x31, 681 lddc_op3 = 0x33, 682 stc_op3 = 0x34, 683 stcsr_op3 = 0x35, 684 stdcq_op3 = 0x36, 685 stdc_op3 = 0x37, 686 687 casa_op3 = 0x3c, 688 casxa_op3 = 0x3e, 689 690 alt_bit_op3 = 0x10, 691 cc_bit_op3 = 0x10 692 }; 693 694 enum opfs { 695 // selected opfs 696 fmovs_opf = 0x01, 697 fmovd_opf = 0x02, 698 699 fnegs_opf = 0x05, 700 fnegd_opf = 0x06, 701 702 fadds_opf = 0x41, 703 faddd_opf = 0x42, 704 fsubs_opf = 0x45, 705 fsubd_opf = 0x46, 706 707 fmuls_opf = 0x49, 708 fmuld_opf = 0x4a, 709 fdivs_opf = 0x4d, 710 fdivd_opf = 0x4e, 711 712 fcmps_opf = 0x51, 713 fcmpd_opf = 0x52, 714 715 fstox_opf = 0x81, 716 fdtox_opf = 0x82, 717 fxtos_opf = 0x84, 718 fxtod_opf = 0x88, 719 fitos_opf = 0xc4, 720 fdtos_opf = 0xc6, 721 fitod_opf = 0xc8, 722 fstod_opf = 0xc9, 723 fstoi_opf = 0xd1, 724 fdtoi_opf = 0xd2 725 }; 726 727 enum RCondition { rc_z = 1, rc_lez = 2, rc_lz = 3, rc_nz = 5, rc_gz = 6, rc_gez = 7 }; 728 729 enum Condition { 730 // for FBfcc & FBPfcc instruction 731 f_never = 0, 732 f_notEqual = 1, 733 f_notZero = 1, 734 f_lessOrGreater = 2, 735 f_unorderedOrLess = 3, 736 f_less = 4, 737 f_unorderedOrGreater = 5, 738 f_greater = 6, 739 f_unordered = 7, 740 f_always = 8, 741 f_equal = 9, 742 f_zero = 9, 743 f_unorderedOrEqual = 10, 744 f_greaterOrEqual = 11, 745 f_unorderedOrGreaterOrEqual = 12, 746 f_lessOrEqual = 13, 747 f_unorderedOrLessOrEqual = 14, 748 f_ordered = 15, 749 750 // V8 coproc, pp 123 v8 manual 751 752 cp_always = 8, 753 cp_never = 0, 754 cp_3 = 7, 755 cp_2 = 6, 756 cp_2or3 = 5, 757 cp_1 = 4, 758 cp_1or3 = 3, 759 cp_1or2 = 2, 760 cp_1or2or3 = 1, 761 cp_0 = 9, 762 cp_0or3 = 10, 763 cp_0or2 = 11, 764 cp_0or2or3 = 12, 765 cp_0or1 = 13, 766 cp_0or1or3 = 14, 767 cp_0or1or2 = 15, 768 769 770 // for integers 771 772 never = 0, 773 equal = 1, 774 zero = 1, 775 lessEqual = 2, 776 less = 3, 777 lessEqualUnsigned = 4, 778 lessUnsigned = 5, 779 carrySet = 5, 780 negative = 6, 781 overflowSet = 7, 782 always = 8, 783 notEqual = 9, 784 notZero = 9, 785 greater = 10, 786 greaterEqual = 11, 787 greaterUnsigned = 12, 788 greaterEqualUnsigned = 13, 789 carryClear = 13, 790 positive = 14, 791 overflowClear = 15 792 }; 793 794 enum CC { 795 icc = 0, xcc = 2, 796 // ptr_cc is the correct condition code for a pointer or intptr_t: 797 ptr_cc = NOT_LP64(icc) LP64_ONLY(xcc), 798 fcc0 = 0, fcc1 = 1, fcc2 = 2, fcc3 = 3 799 }; 800 801 enum PrefetchFcn { 802 severalReads = 0, oneRead = 1, severalWritesAndPossiblyReads = 2, oneWrite = 3, page = 4 803 }; 804 805 public: 806 // Helper functions for groups of instructions 807 808 enum Predict { pt = 1, pn = 0 }; // pt = predict taken 809 810 enum Membar_mask_bits { // page 184, v9 811 StoreStore = 1 << 3, 812 LoadStore = 1 << 2, 813 StoreLoad = 1 << 1, 814 LoadLoad = 1 << 0, 815 816 Sync = 1 << 6, 817 MemIssue = 1 << 5, 818 Lookaside = 1 << 4 819 }; 820 821 // test if x is within signed immediate range for nbits 822 static bool is_simm(int x, int nbits) { return -( 1 << nbits-1 ) <= x && x < ( 1 << nbits-1 ); } 823 824 // test if -4096 <= x <= 4095 825 static bool is_simm13(int x) { return is_simm(x, 13); } 826 827 enum ASIs { // page 72, v9 828 ASI_PRIMARY = 0x80, 829 ASI_PRIMARY_LITTLE = 0x88 830 // add more from book as needed 831 }; 832 833 protected: 834 // helpers 835 836 // x is supposed to fit in a field "nbits" wide 837 // and be sign-extended. Check the range. 838 839 static void assert_signed_range(intptr_t x, int nbits) { 840 assert( nbits == 32 841 || -(1 << nbits-1) <= x && x < ( 1 << nbits-1), 842 "value out of range"); 843 } 844 845 static void assert_signed_word_disp_range(intptr_t x, int nbits) { 846 assert( (x & 3) == 0, "not word aligned"); 847 assert_signed_range(x, nbits + 2); 848 } 849 850 static void assert_unsigned_const(int x, int nbits) { 851 assert( juint(x) < juint(1 << nbits), "unsigned constant out of range"); 852 } 853 854 // fields: note bits numbered from LSB = 0, 855 // fields known by inclusive bit range 856 857 static int fmask(juint hi_bit, juint lo_bit) { 858 assert( hi_bit >= lo_bit && 0 <= lo_bit && hi_bit < 32, "bad bits"); 859 return (1 << ( hi_bit-lo_bit + 1 )) - 1; 860 } 861 862 // inverse of u_field 863 864 static int inv_u_field(int x, int hi_bit, int lo_bit) { 865 juint r = juint(x) >> lo_bit; 866 r &= fmask( hi_bit, lo_bit); 867 return int(r); 868 } 869 870 871 // signed version: extract from field and sign-extend 872 873 static int inv_s_field(int x, int hi_bit, int lo_bit) { 874 int sign_shift = 31 - hi_bit; 875 return inv_u_field( ((x << sign_shift) >> sign_shift), hi_bit, lo_bit); 876 } 877 878 // given a field that ranges from hi_bit to lo_bit (inclusive, 879 // LSB = 0), and an unsigned value for the field, 880 // shift it into the field 881 882#ifdef ASSERT 883 static int u_field(int x, int hi_bit, int lo_bit) { 884 assert( ( x & ~fmask(hi_bit, lo_bit)) == 0, 885 "value out of range"); 886 int r = x << lo_bit; 887 assert( inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); 888 return r; 889 } 890#else 891 // make sure this is inlined as it will reduce code size significantly 892 #define u_field(x, hi_bit, lo_bit) ((x) << (lo_bit)) 893#endif 894 895 static int inv_op( int x ) { return inv_u_field(x, 31, 30); } 896 static int inv_op2( int x ) { return inv_u_field(x, 24, 22); } 897 static int inv_op3( int x ) { return inv_u_field(x, 24, 19); } 898 static int inv_cond( int x ){ return inv_u_field(x, 28, 25); } 899 900 static bool inv_immed( int x ) { return (x & Assembler::immed(true)) != 0; } 901 902 static Register inv_rd( int x ) { return as_Register(inv_u_field(x, 29, 25)); } 903 static Register inv_rs1( int x ) { return as_Register(inv_u_field(x, 18, 14)); } 904 static Register inv_rs2( int x ) { return as_Register(inv_u_field(x, 4, 0)); } 905 906 static int op( int x) { return u_field(x, 31, 30); } 907 static int rd( Register r) { return u_field(r->encoding(), 29, 25); } 908 static int fcn( int x) { return u_field(x, 29, 25); } 909 static int op3( int x) { return u_field(x, 24, 19); } 910 static int rs1( Register r) { return u_field(r->encoding(), 18, 14); } 911 static int rs2( Register r) { return u_field(r->encoding(), 4, 0); } 912 static int annul( bool a) { return u_field(a ? 1 : 0, 29, 29); } 913 static int cond( int x) { return u_field(x, 28, 25); } 914 static int cond_mov( int x) { return u_field(x, 17, 14); } 915 static int rcond( RCondition x) { return u_field(x, 12, 10); } 916 static int op2( int x) { return u_field(x, 24, 22); } 917 static int predict( bool p) { return u_field(p ? 1 : 0, 19, 19); } 918 static int branchcc( CC fcca) { return u_field(fcca, 21, 20); } 919 static int cmpcc( CC fcca) { return u_field(fcca, 26, 25); } 920 static int imm_asi( int x) { return u_field(x, 12, 5); } 921 static int immed( bool i) { return u_field(i ? 1 : 0, 13, 13); } 922 static int opf_low6( int w) { return u_field(w, 10, 5); } 923 static int opf_low5( int w) { return u_field(w, 9, 5); } 924 static int trapcc( CC cc) { return u_field(cc, 12, 11); } 925 static int sx( int i) { return u_field(i, 12, 12); } // shift x=1 means 64-bit 926 static int opf( int x) { return u_field(x, 13, 5); } 927 928 static int opf_cc( CC c, bool useFloat ) { return u_field((useFloat ? 0 : 4) + c, 13, 11); } 929 static int mov_cc( CC c, bool useFloat ) { return u_field(useFloat ? 0 : 1, 18, 18) | u_field(c, 12, 11); } 930 931 static int fd( FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 29, 25); }; 932 static int fs1(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 18, 14); }; 933 static int fs2(FloatRegister r, FloatRegisterImpl::Width fwa) { return u_field(r->encoding(fwa), 4, 0); }; 934 935 // some float instructions use this encoding on the op3 field 936 static int alt_op3(int op, FloatRegisterImpl::Width w) { 937 int r; 938 switch(w) { 939 case FloatRegisterImpl::S: r = op + 0; break; 940 case FloatRegisterImpl::D: r = op + 3; break; 941 case FloatRegisterImpl::Q: r = op + 2; break; 942 default: ShouldNotReachHere(); break; 943 } 944 return op3(r); 945 } 946 947 948 // compute inverse of simm 949 static int inv_simm(int x, int nbits) { 950 return (int)(x << (32 - nbits)) >> (32 - nbits); 951 } 952 953 static int inv_simm13( int x ) { return inv_simm(x, 13); } 954 955 // signed immediate, in low bits, nbits long 956 static int simm(int x, int nbits) { 957 assert_signed_range(x, nbits); 958 return x & (( 1 << nbits ) - 1); 959 } 960 961 // compute inverse of wdisp16 962 static intptr_t inv_wdisp16(int x, intptr_t pos) { 963 int lo = x & (( 1 << 14 ) - 1); 964 int hi = (x >> 20) & 3; 965 if (hi >= 2) hi |= ~1; 966 return (((hi << 14) | lo) << 2) + pos; 967 } 968 969 // word offset, 14 bits at LSend, 2 bits at B21, B20 970 static int wdisp16(intptr_t x, intptr_t off) { 971 intptr_t xx = x - off; 972 assert_signed_word_disp_range(xx, 16); 973 int r = (xx >> 2) & ((1 << 14) - 1) 974 | ( ( (xx>>(2+14)) & 3 ) << 20 ); 975 assert( inv_wdisp16(r, off) == x, "inverse is not inverse"); 976 return r; 977 } 978 979 980 // word displacement in low-order nbits bits 981 982 static intptr_t inv_wdisp( int x, intptr_t pos, int nbits ) { 983 int pre_sign_extend = x & (( 1 << nbits ) - 1); 984 int r = pre_sign_extend >= ( 1 << (nbits-1) ) 985 ? pre_sign_extend | ~(( 1 << nbits ) - 1) 986 : pre_sign_extend; 987 return (r << 2) + pos; 988 } 989 990 static int wdisp( intptr_t x, intptr_t off, int nbits ) { 991 intptr_t xx = x - off; 992 assert_signed_word_disp_range(xx, nbits); 993 int r = (xx >> 2) & (( 1 << nbits ) - 1); 994 assert( inv_wdisp( r, off, nbits ) == x, "inverse not inverse"); 995 return r; 996 } 997 998 999 // Extract the top 32 bits in a 64 bit word 1000 static int32_t hi32( int64_t x ) { 1001 int32_t r = int32_t( (uint64_t)x >> 32 ); 1002 return r; 1003 } 1004 1005 // given a sethi instruction, extract the constant, left-justified 1006 static int inv_hi22( int x ) { 1007 return x << 10; 1008 } 1009 1010 // create an imm22 field, given a 32-bit left-justified constant 1011 static int hi22( int x ) { 1012 int r = int( juint(x) >> 10 ); 1013 assert( (r & ~((1 << 22) - 1)) == 0, "just checkin'"); 1014 return r; 1015 } 1016 1017 // create a low10 __value__ (not a field) for a given a 32-bit constant 1018 static int low10( int x ) { 1019 return x & ((1 << 10) - 1); 1020 } 1021 1022 // instruction only in v9 1023 static void v9_only() { assert( VM_Version::v9_instructions_work(), "This instruction only works on SPARC V9"); } 1024 1025 // instruction only in v8 1026 static void v8_only() { assert( VM_Version::v8_instructions_work(), "This instruction only works on SPARC V8"); } 1027 1028 // instruction deprecated in v9 1029 static void v9_dep() { } // do nothing for now 1030 1031 // some float instructions only exist for single prec. on v8 1032 static void v8_s_only(FloatRegisterImpl::Width w) { if (w != FloatRegisterImpl::S) v9_only(); } 1033 1034 // v8 has no CC field 1035 static void v8_no_cc(CC cc) { if (cc) v9_only(); } 1036 1037 protected: 1038 // Simple delay-slot scheme: 1039 // In order to check the programmer, the assembler keeps track of deley slots. 1040 // It forbids CTIs in delay slots (conservative, but should be OK). 1041 // Also, when putting an instruction into a delay slot, you must say 1042 // asm->delayed()->add(...), in order to check that you don't omit 1043 // delay-slot instructions. 1044 // To implement this, we use a simple FSA 1045 1046#ifdef ASSERT 1047 #define CHECK_DELAY 1048#endif 1049#ifdef CHECK_DELAY 1050 enum Delay_state { no_delay, at_delay_slot, filling_delay_slot } delay_state; 1051#endif 1052 1053 public: 1054 // Tells assembler next instruction must NOT be in delay slot. 1055 // Use at start of multinstruction macros. 1056 void assert_not_delayed() { 1057 // This is a separate overloading to avoid creation of string constants 1058 // in non-asserted code--with some compilers this pollutes the object code. 1059#ifdef CHECK_DELAY 1060 assert_not_delayed("next instruction should not be a delay slot"); 1061#endif 1062 } 1063 void assert_not_delayed(const char* msg) { 1064#ifdef CHECK_DELAY 1065 assert(delay_state == no_delay, msg); 1066#endif 1067 } 1068 1069 protected: 1070 // Delay slot helpers 1071 // cti is called when emitting control-transfer instruction, 1072 // BEFORE doing the emitting. 1073 // Only effective when assertion-checking is enabled. 1074 void cti() { 1075#ifdef CHECK_DELAY 1076 assert_not_delayed("cti should not be in delay slot"); 1077#endif 1078 } 1079 1080 // called when emitting cti with a delay slot, AFTER emitting 1081 void has_delay_slot() { 1082#ifdef CHECK_DELAY 1083 assert_not_delayed("just checking"); 1084 delay_state = at_delay_slot; 1085#endif 1086 } 1087 1088public: 1089 // Tells assembler you know that next instruction is delayed 1090 Assembler* delayed() { 1091#ifdef CHECK_DELAY 1092 assert ( delay_state == at_delay_slot, "delayed instruction is not in delay slot"); 1093 delay_state = filling_delay_slot; 1094#endif 1095 return this; 1096 } 1097 1098 void flush() { 1099#ifdef CHECK_DELAY 1100 assert ( delay_state == no_delay, "ending code with a delay slot"); 1101#endif 1102 AbstractAssembler::flush(); 1103 } 1104 1105 inline void emit_long(int); // shadows AbstractAssembler::emit_long 1106 inline void emit_data(int x) { emit_long(x); } 1107 inline void emit_data(int, RelocationHolder const&); 1108 inline void emit_data(int, relocInfo::relocType rtype); 1109 // helper for above fcns 1110 inline void check_delay(); 1111 1112 1113 public: 1114 // instructions, refer to page numbers in the SPARC Architecture Manual, V9 1115 1116 // pp 135 (addc was addx in v8) 1117 1118 inline void add(Register s1, Register s2, Register d ); 1119 inline void add(Register s1, int simm13a, Register d, relocInfo::relocType rtype = relocInfo::none); 1120 inline void add(Register s1, int simm13a, Register d, RelocationHolder const& rspec); 1121 inline void add(Register s1, RegisterOrConstant s2, Register d, int offset = 0); 1122 inline void add(const Address& a, Register d, int offset = 0) { add( a.base(), a.disp() + offset, d, a.rspec(offset)); } 1123 1124 void addcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1125 void addcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(add_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1126 void addc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | rs2(s2) ); } 1127 void addc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1128 void addccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1129 void addccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(addc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1130 1131 // pp 136 1132 1133 inline void bpr( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none ); 1134 inline void bpr( RCondition c, bool a, Predict p, Register s1, Label& L); 1135 1136 protected: // use MacroAssembler::br instead 1137 1138 // pp 138 1139 1140 inline void fb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); 1141 inline void fb( Condition c, bool a, Label& L ); 1142 1143 // pp 141 1144 1145 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 1146 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); 1147 1148 public: 1149 1150 // pp 144 1151 1152 inline void br( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); 1153 inline void br( Condition c, bool a, Label& L ); 1154 1155 // pp 146 1156 1157 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 1158 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); 1159 1160 // pp 121 (V8) 1161 1162 inline void cb( Condition c, bool a, address d, relocInfo::relocType rt = relocInfo::none ); 1163 inline void cb( Condition c, bool a, Label& L ); 1164 1165 // pp 149 1166 1167 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); 1168 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); 1169 1170 // pp 150 1171 1172 // These instructions compare the contents of s2 with the contents of 1173 // memory at address in s1. If the values are equal, the contents of memory 1174 // at address s1 is swapped with the data in d. If the values are not equal, 1175 // the the contents of memory at s1 is loaded into d, without the swap. 1176 1177 void casa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casa_op3 ) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } 1178 void casxa( Register s1, Register s2, Register d, int ia = -1 ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(casxa_op3) | rs1(s1) | (ia == -1 ? immed(true) : imm_asi(ia)) | rs2(s2)); } 1179 1180 // pp 152 1181 1182 void udiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | rs2(s2)); } 1183 void udiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1184 void sdiv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | rs2(s2)); } 1185 void sdiv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1186 void udivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } 1187 void udivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(udiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1188 void sdivcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | rs2(s2)); } 1189 void sdivcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sdiv_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1190 1191 // pp 155 1192 1193 void done() { v9_only(); cti(); emit_long( op(arith_op) | fcn(0) | op3(done_op3) ); } 1194 void retry() { v9_only(); cti(); emit_long( op(arith_op) | fcn(1) | op3(retry_op3) ); } 1195 1196 // pp 156 1197 1198 void fadd( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x40 + w) | fs2(s2, w)); } 1199 void fsub( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x44 + w) | fs2(s2, w)); } 1200 1201 // pp 157 1202 1203 void fcmp( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x50 + w) | fs2(s2, w)); } 1204 void fcmpe( FloatRegisterImpl::Width w, CC cc, FloatRegister s1, FloatRegister s2) { v8_no_cc(cc); emit_long( op(arith_op) | cmpcc(cc) | op3(fpop2_op3) | fs1(s1, w) | opf(0x54 + w) | fs2(s2, w)); } 1205 1206 // pp 159 1207 1208 void ftox( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w) | fs2(s, w)); } 1209 void ftoi( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xd0 + w) | fs2(s, w)); } 1210 1211 // pp 160 1212 1213 void ftof( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | opf(0xc0 + sw + dw*4) | fs2(s, sw)); } 1214 1215 // pp 161 1216 1217 void fxtof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x80 + w*4) | fs2(s, w)); } 1218 void fitof( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0xc0 + w*4) | fs2(s, w)); } 1219 1220 // pp 162 1221 1222 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x00 + w) | fs2(s, w)); } 1223 1224 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(s, w)); } 1225 1226 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fnegs is the only instruction available 1227 // on v8 to do negation of single, double and quad precision floats. 1228 1229 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x04 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x05) | fs2(sd, w)); } 1230 1231 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { v8_s_only(w); emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(s, w)); } 1232 1233 // page 144 sparc v8 architecture (double prec works on v8 if the source and destination registers are the same). fabss is the only instruction available 1234 // on v8 to do abs operation on single/double/quad precision floats. 1235 1236 void fabs( FloatRegisterImpl::Width w, FloatRegister sd ) { if (VM_Version::v9_instructions_work()) emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x08 + w) | fs2(sd, w)); else emit_long( op(arith_op) | fd(sd, w) | op3(fpop1_op3) | opf(0x09) | fs2(sd, w)); } 1237 1238 // pp 163 1239 1240 void fmul( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x48 + w) | fs2(s2, w)); } 1241 void fmul( FloatRegisterImpl::Width sw, FloatRegisterImpl::Width dw, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, dw) | op3(fpop1_op3) | fs1(s1, sw) | opf(0x60 + sw + dw*4) | fs2(s2, sw)); } 1242 void fdiv( FloatRegisterImpl::Width w, FloatRegister s1, FloatRegister s2, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | fs1(s1, w) | opf(0x4c + w) | fs2(s2, w)); } 1243 1244 // pp 164 1245 1246 void fsqrt( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d ) { emit_long( op(arith_op) | fd(d, w) | op3(fpop1_op3) | opf(0x28 + w) | fs2(s, w)); } 1247 1248 // pp 165 1249 1250 inline void flush( Register s1, Register s2 ); 1251 inline void flush( Register s1, int simm13a); 1252 1253 // pp 167 1254 1255 void flushw() { v9_only(); emit_long( op(arith_op) | op3(flushw_op3) ); } 1256 1257 // pp 168 1258 1259 void illtrap( int const22a) { if (const22a != 0) v9_only(); emit_long( op(branch_op) | u_field(const22a, 21, 0) ); } 1260 // v8 unimp == illtrap(0) 1261 1262 // pp 169 1263 1264 void impdep1( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep1_op3) | u_field(const19a, 18, 0)); } 1265 void impdep2( int id1, int const19a ) { v9_only(); emit_long( op(arith_op) | fcn(id1) | op3(impdep2_op3) | u_field(const19a, 18, 0)); } 1266 1267 // pp 149 (v8) 1268 1269 void cpop1( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep1_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); } 1270 void cpop2( int opc, int cr1, int cr2, int crd ) { v8_only(); emit_long( op(arith_op) | fcn(crd) | op3(impdep2_op3) | u_field(cr1, 18, 14) | opf(opc) | u_field(cr2, 4, 0)); } 1271 1272 // pp 170 1273 1274 void jmpl( Register s1, Register s2, Register d ); 1275 void jmpl( Register s1, int simm13a, Register d, RelocationHolder const& rspec = RelocationHolder() ); 1276 1277 // 171 1278 1279 inline void ldf(FloatRegisterImpl::Width w, Register s1, RegisterOrConstant s2, FloatRegister d); 1280 inline void ldf(FloatRegisterImpl::Width w, Register s1, Register s2, FloatRegister d); 1281 inline void ldf(FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d, RelocationHolder const& rspec = RelocationHolder()); 1282 1283 inline void ldf(FloatRegisterImpl::Width w, const Address& a, FloatRegister d, int offset = 0); 1284 1285 1286 inline void ldfsr( Register s1, Register s2 ); 1287 inline void ldfsr( Register s1, int simm13a); 1288 inline void ldxfsr( Register s1, Register s2 ); 1289 inline void ldxfsr( Register s1, int simm13a); 1290 1291 // pp 94 (v8) 1292 1293 inline void ldc( Register s1, Register s2, int crd ); 1294 inline void ldc( Register s1, int simm13a, int crd); 1295 inline void lddc( Register s1, Register s2, int crd ); 1296 inline void lddc( Register s1, int simm13a, int crd); 1297 inline void ldcsr( Register s1, Register s2, int crd ); 1298 inline void ldcsr( Register s1, int simm13a, int crd); 1299 1300 1301 // 173 1302 1303 void ldfa( FloatRegisterImpl::Width w, Register s1, Register s2, int ia, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1304 void ldfa( FloatRegisterImpl::Width w, Register s1, int simm13a, FloatRegister d ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(ldf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1305 1306 // pp 175, lduw is ld on v8 1307 1308 inline void ldsb( Register s1, Register s2, Register d ); 1309 inline void ldsb( Register s1, int simm13a, Register d); 1310 inline void ldsh( Register s1, Register s2, Register d ); 1311 inline void ldsh( Register s1, int simm13a, Register d); 1312 inline void ldsw( Register s1, Register s2, Register d ); 1313 inline void ldsw( Register s1, int simm13a, Register d); 1314 inline void ldub( Register s1, Register s2, Register d ); 1315 inline void ldub( Register s1, int simm13a, Register d); 1316 inline void lduh( Register s1, Register s2, Register d ); 1317 inline void lduh( Register s1, int simm13a, Register d); 1318 inline void lduw( Register s1, Register s2, Register d ); 1319 inline void lduw( Register s1, int simm13a, Register d); 1320 inline void ldx( Register s1, Register s2, Register d ); 1321 inline void ldx( Register s1, int simm13a, Register d); 1322 inline void ld( Register s1, Register s2, Register d ); 1323 inline void ld( Register s1, int simm13a, Register d); 1324 inline void ldd( Register s1, Register s2, Register d ); 1325 inline void ldd( Register s1, int simm13a, Register d); 1326 1327#ifdef ASSERT 1328 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. 1329 inline void ld( Register s1, ByteSize simm13a, Register d); 1330#endif 1331 1332 inline void ldsb(const Address& a, Register d, int offset = 0); 1333 inline void ldsh(const Address& a, Register d, int offset = 0); 1334 inline void ldsw(const Address& a, Register d, int offset = 0); 1335 inline void ldub(const Address& a, Register d, int offset = 0); 1336 inline void lduh(const Address& a, Register d, int offset = 0); 1337 inline void lduw(const Address& a, Register d, int offset = 0); 1338 inline void ldx( const Address& a, Register d, int offset = 0); 1339 inline void ld( const Address& a, Register d, int offset = 0); 1340 inline void ldd( const Address& a, Register d, int offset = 0); 1341 1342 inline void ldub( Register s1, RegisterOrConstant s2, Register d ); 1343 inline void ldsb( Register s1, RegisterOrConstant s2, Register d ); 1344 inline void lduh( Register s1, RegisterOrConstant s2, Register d ); 1345 inline void ldsh( Register s1, RegisterOrConstant s2, Register d ); 1346 inline void lduw( Register s1, RegisterOrConstant s2, Register d ); 1347 inline void ldsw( Register s1, RegisterOrConstant s2, Register d ); 1348 inline void ldx( Register s1, RegisterOrConstant s2, Register d ); 1349 inline void ld( Register s1, RegisterOrConstant s2, Register d ); 1350 inline void ldd( Register s1, RegisterOrConstant s2, Register d ); 1351 1352 // pp 177 1353 1354 void ldsba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1355 void ldsba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1356 void ldsha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1357 void ldsha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldsh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1358 void ldswa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1359 void ldswa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldsw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1360 void lduba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1361 void lduba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1362 void lduha( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1363 void lduha( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduh_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1364 void lduwa( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1365 void lduwa( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(lduw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1366 void ldxa( Register s1, Register s2, int ia, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1367 void ldxa( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(ldx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1368 void ldda( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1369 void ldda( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(ldd_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1370 1371 // pp 179 1372 1373 inline void ldstub( Register s1, Register s2, Register d ); 1374 inline void ldstub( Register s1, int simm13a, Register d); 1375 1376 // pp 180 1377 1378 void ldstuba( Register s1, Register s2, int ia, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1379 void ldstuba( Register s1, int simm13a, Register d ) { emit_long( op(ldst_op) | rd(d) | op3(ldstub_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1380 1381 // pp 181 1382 1383 void and3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | rs2(s2) ); } 1384 void and3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1385 void andcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1386 void andcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(and_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1387 void andn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | rs2(s2) ); } 1388 void andn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1389 void andn( Register s1, RegisterOrConstant s2, Register d); 1390 void andncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1391 void andncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(andn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1392 void or3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | rs2(s2) ); } 1393 void or3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1394 void orcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1395 void orcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(or_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1396 void orn( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | rs2(s2) ); } 1397 void orn( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1398 void orncc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1399 void orncc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(orn_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1400 void xor3( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | rs2(s2) ); } 1401 void xor3( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1402 void xorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1403 void xorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1404 void xnor( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | rs2(s2) ); } 1405 void xnor( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1406 void xnorcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1407 void xnorcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(xnor_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1408 1409 // pp 183 1410 1411 void membar( Membar_mask_bits const7a ) { v9_only(); emit_long( op(arith_op) | op3(membar_op3) | rs1(O7) | immed(true) | u_field( int(const7a), 6, 0)); } 1412 1413 // pp 185 1414 1415 void fmov( FloatRegisterImpl::Width w, Condition c, bool floatCC, CC cca, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | cond_mov(c) | opf_cc(cca, floatCC) | opf_low6(w) | fs2(s2, w)); } 1416 1417 // pp 189 1418 1419 void fmov( FloatRegisterImpl::Width w, RCondition c, Register s1, FloatRegister s2, FloatRegister d ) { v9_only(); emit_long( op(arith_op) | fd(d, w) | op3(fpop2_op3) | rs1(s1) | rcond(c) | opf_low5(4 + w) | fs2(s2, w)); } 1420 1421 // pp 191 1422 1423 void movcc( Condition c, bool floatCC, CC cca, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | rs2(s2) ); } 1424 void movcc( Condition c, bool floatCC, CC cca, int simm11a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movcc_op3) | mov_cc(cca, floatCC) | cond_mov(c) | immed(true) | simm(simm11a, 11) ); } 1425 1426 // pp 195 1427 1428 void movr( RCondition c, Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | rs2(s2) ); } 1429 void movr( RCondition c, Register s1, int simm10a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(movr_op3) | rs1(s1) | rcond(c) | immed(true) | simm(simm10a, 10) ); } 1430 1431 // pp 196 1432 1433 void mulx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | rs2(s2) ); } 1434 void mulx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(mulx_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1435 void sdivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | rs2(s2) ); } 1436 void sdivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sdivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1437 void udivx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | rs2(s2) ); } 1438 void udivx( Register s1, int simm13a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(udivx_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1439 1440 // pp 197 1441 1442 void umul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | rs2(s2) ); } 1443 void umul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1444 void smul( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | rs2(s2) ); } 1445 void smul( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1446 void umulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1447 void umulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(umul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1448 void smulcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1449 void smulcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(smul_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1450 1451 // pp 199 1452 1453 void mulscc( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | rs2(s2) ); } 1454 void mulscc( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(mulscc_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1455 1456 // pp 201 1457 1458 void nop() { emit_long( op(branch_op) | op2(sethi_op2) ); } 1459 1460 1461 // pp 202 1462 1463 void popc( Register s, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | rs2(s)); } 1464 void popc( int simm13a, Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(popc_op3) | immed(true) | simm(simm13a, 13)); } 1465 1466 // pp 203 1467 1468 void prefetch( Register s1, Register s2, PrefetchFcn f); 1469 void prefetch( Register s1, int simm13a, PrefetchFcn f); 1470 void prefetcha( Register s1, Register s2, int ia, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1471 void prefetcha( Register s1, int simm13a, PrefetchFcn f ) { v9_only(); emit_long( op(ldst_op) | fcn(f) | op3(prefetch_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1472 1473 inline void prefetch(const Address& a, PrefetchFcn F, int offset = 0); 1474 1475 // pp 208 1476 1477 // not implementing read privileged register 1478 1479 inline void rdy( Register d) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(0, 18, 14)); } 1480 inline void rdccr( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(2, 18, 14)); } 1481 inline void rdasi( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(3, 18, 14)); } 1482 inline void rdtick( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(4, 18, 14)); } // Spoon! 1483 inline void rdpc( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(5, 18, 14)); } 1484 inline void rdfprs( Register d) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(rdreg_op3) | u_field(6, 18, 14)); } 1485 1486 // pp 213 1487 1488 inline void rett( Register s1, Register s2); 1489 inline void rett( Register s1, int simm13a, relocInfo::relocType rt = relocInfo::none); 1490 1491 // pp 214 1492 1493 void save( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | rs2(s2) ); } 1494 void save( Register s1, int simm13a, Register d ) { 1495 // make sure frame is at least large enough for the register save area 1496 assert(-simm13a >= 16 * wordSize, "frame too small"); 1497 emit_long( op(arith_op) | rd(d) | op3(save_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); 1498 } 1499 1500 void restore( Register s1 = G0, Register s2 = G0, Register d = G0 ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | rs2(s2) ); } 1501 void restore( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(restore_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1502 1503 // pp 216 1504 1505 void saved() { v9_only(); emit_long( op(arith_op) | fcn(0) | op3(saved_op3)); } 1506 void restored() { v9_only(); emit_long( op(arith_op) | fcn(1) | op3(saved_op3)); } 1507 1508 // pp 217 1509 1510 inline void sethi( int imm22a, Register d, RelocationHolder const& rspec = RelocationHolder() ); 1511 // pp 218 1512 1513 void sll( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | rs2(s2) ); } 1514 void sll( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } 1515 void srl( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | rs2(s2) ); } 1516 void srl( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } 1517 void sra( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | rs2(s2) ); } 1518 void sra( Register s1, int imm5a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(0) | immed(true) | u_field(imm5a, 4, 0) ); } 1519 1520 void sllx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | rs2(s2) ); } 1521 void sllx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sll_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } 1522 void srlx( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | rs2(s2) ); } 1523 void srlx( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(srl_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } 1524 void srax( Register s1, Register s2, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | rs2(s2) ); } 1525 void srax( Register s1, int imm6a, Register d ) { v9_only(); emit_long( op(arith_op) | rd(d) | op3(sra_op3) | rs1(s1) | sx(1) | immed(true) | u_field(imm6a, 5, 0) ); } 1526 1527 // pp 220 1528 1529 void sir( int simm13a ) { emit_long( op(arith_op) | fcn(15) | op3(sir_op3) | immed(true) | simm(simm13a, 13)); } 1530 1531 // pp 221 1532 1533 void stbar() { emit_long( op(arith_op) | op3(membar_op3) | u_field(15, 18, 14)); } 1534 1535 // pp 222 1536 1537 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, RegisterOrConstant s2); 1538 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2); 1539 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a); 1540 inline void stf( FloatRegisterImpl::Width w, FloatRegister d, const Address& a, int offset = 0); 1541 1542 inline void stfsr( Register s1, Register s2 ); 1543 inline void stfsr( Register s1, int simm13a); 1544 inline void stxfsr( Register s1, Register s2 ); 1545 inline void stxfsr( Register s1, int simm13a); 1546 1547 // pp 224 1548 1549 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1550 void stfa( FloatRegisterImpl::Width w, FloatRegister d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | fd(d, w) | alt_op3(stf_op3 | alt_bit_op3, w) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1551 1552 // p 226 1553 1554 inline void stb( Register d, Register s1, Register s2 ); 1555 inline void stb( Register d, Register s1, int simm13a); 1556 inline void sth( Register d, Register s1, Register s2 ); 1557 inline void sth( Register d, Register s1, int simm13a); 1558 inline void stw( Register d, Register s1, Register s2 ); 1559 inline void stw( Register d, Register s1, int simm13a); 1560 inline void st( Register d, Register s1, Register s2 ); 1561 inline void st( Register d, Register s1, int simm13a); 1562 inline void stx( Register d, Register s1, Register s2 ); 1563 inline void stx( Register d, Register s1, int simm13a); 1564 inline void std( Register d, Register s1, Register s2 ); 1565 inline void std( Register d, Register s1, int simm13a); 1566 1567#ifdef ASSERT 1568 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. 1569 inline void st( Register d, Register s1, ByteSize simm13a); 1570#endif 1571 1572 inline void stb( Register d, const Address& a, int offset = 0 ); 1573 inline void sth( Register d, const Address& a, int offset = 0 ); 1574 inline void stw( Register d, const Address& a, int offset = 0 ); 1575 inline void stx( Register d, const Address& a, int offset = 0 ); 1576 inline void st( Register d, const Address& a, int offset = 0 ); 1577 inline void std( Register d, const Address& a, int offset = 0 ); 1578 1579 inline void stb( Register d, Register s1, RegisterOrConstant s2 ); 1580 inline void sth( Register d, Register s1, RegisterOrConstant s2 ); 1581 inline void stw( Register d, Register s1, RegisterOrConstant s2 ); 1582 inline void stx( Register d, Register s1, RegisterOrConstant s2 ); 1583 inline void std( Register d, Register s1, RegisterOrConstant s2 ); 1584 inline void st( Register d, Register s1, RegisterOrConstant s2 ); 1585 1586 // pp 177 1587 1588 void stba( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1589 void stba( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stb_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1590 void stha( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1591 void stha( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(sth_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1592 void stwa( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1593 void stwa( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(stw_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1594 void stxa( Register d, Register s1, Register s2, int ia ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1595 void stxa( Register d, Register s1, int simm13a ) { v9_only(); emit_long( op(ldst_op) | rd(d) | op3(stx_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1596 void stda( Register d, Register s1, Register s2, int ia ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1597 void stda( Register d, Register s1, int simm13a ) { emit_long( op(ldst_op) | rd(d) | op3(std_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1598 1599 // pp 97 (v8) 1600 1601 inline void stc( int crd, Register s1, Register s2 ); 1602 inline void stc( int crd, Register s1, int simm13a); 1603 inline void stdc( int crd, Register s1, Register s2 ); 1604 inline void stdc( int crd, Register s1, int simm13a); 1605 inline void stcsr( int crd, Register s1, Register s2 ); 1606 inline void stcsr( int crd, Register s1, int simm13a); 1607 inline void stdcq( int crd, Register s1, Register s2 ); 1608 inline void stdcq( int crd, Register s1, int simm13a); 1609 1610 // pp 230 1611 1612 void sub( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | rs2(s2) ); } 1613 void sub( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1614 void subcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | rs2(s2) ); } 1615 void subcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(sub_op3 | cc_bit_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1616 void subc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | rs2(s2) ); } 1617 void subc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1618 void subccc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | rs2(s2) ); } 1619 void subccc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(subc_op3 | cc_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1620 1621 // pp 231 1622 1623 inline void swap( Register s1, Register s2, Register d ); 1624 inline void swap( Register s1, int simm13a, Register d); 1625 inline void swap( Address& a, Register d, int offset = 0 ); 1626 1627 // pp 232 1628 1629 void swapa( Register s1, Register s2, int ia, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | imm_asi(ia) | rs2(s2) ); } 1630 void swapa( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(ldst_op) | rd(d) | op3(swap_op3 | alt_bit_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1631 1632 // pp 234, note op in book is wrong, see pp 268 1633 1634 void taddcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | rs2(s2) ); } 1635 void taddcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(taddcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1636 void taddcctv( Register s1, Register s2, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | rs2(s2) ); } 1637 void taddcctv( Register s1, int simm13a, Register d ) { v9_dep(); emit_long( op(arith_op) | rd(d) | op3(taddcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1638 1639 // pp 235 1640 1641 void tsubcc( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | rs2(s2) ); } 1642 void tsubcc( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcc_op3 ) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1643 void tsubcctv( Register s1, Register s2, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | rs2(s2) ); } 1644 void tsubcctv( Register s1, int simm13a, Register d ) { emit_long( op(arith_op) | rd(d) | op3(tsubcctv_op3) | rs1(s1) | immed(true) | simm(simm13a, 13) ); } 1645 1646 // pp 237 1647 1648 void trap( Condition c, CC cc, Register s1, Register s2 ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | rs2(s2)); } 1649 void trap( Condition c, CC cc, Register s1, int trapa ) { v8_no_cc(cc); emit_long( op(arith_op) | cond(c) | op3(trap_op3) | rs1(s1) | trapcc(cc) | immed(true) | u_field(trapa, 6, 0)); } 1650 // simple uncond. trap 1651 void trap( int trapa ) { trap( always, icc, G0, trapa ); } 1652 1653 // pp 239 omit write priv register for now 1654 1655 inline void wry( Register d) { v9_dep(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(0, 29, 25)); } 1656 inline void wrccr(Register s) { v9_only(); emit_long( op(arith_op) | rs1(s) | op3(wrreg_op3) | u_field(2, 29, 25)); } 1657 inline void wrccr(Register s, int simm13a) { v9_only(); emit_long( op(arith_op) | 1658 rs1(s) | 1659 op3(wrreg_op3) | 1660 u_field(2, 29, 25) | 1661 u_field(1, 13, 13) | 1662 simm(simm13a, 13)); } 1663 inline void wrasi( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(3, 29, 25)); } 1664 inline void wrfprs( Register d) { v9_only(); emit_long( op(arith_op) | rs1(d) | op3(wrreg_op3) | u_field(6, 29, 25)); } 1665 1666 // For a given register condition, return the appropriate condition code 1667 // Condition (the one you would use to get the same effect after "tst" on 1668 // the target register.) 1669 Assembler::Condition reg_cond_to_cc_cond(RCondition in); 1670 1671 1672 // Creation 1673 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 1674#ifdef CHECK_DELAY 1675 delay_state = no_delay; 1676#endif 1677 } 1678 1679 // Testing 1680#ifndef PRODUCT 1681 void test_v9(); 1682 void test_v8_onlys(); 1683#endif 1684}; 1685 1686 1687class RegistersForDebugging : public StackObj { 1688 public: 1689 intptr_t i[8], l[8], o[8], g[8]; 1690 float f[32]; 1691 double d[32]; 1692 1693 void print(outputStream* s); 1694 1695 static int i_offset(int j) { return offset_of(RegistersForDebugging, i[j]); } 1696 static int l_offset(int j) { return offset_of(RegistersForDebugging, l[j]); } 1697 static int o_offset(int j) { return offset_of(RegistersForDebugging, o[j]); } 1698 static int g_offset(int j) { return offset_of(RegistersForDebugging, g[j]); } 1699 static int f_offset(int j) { return offset_of(RegistersForDebugging, f[j]); } 1700 static int d_offset(int j) { return offset_of(RegistersForDebugging, d[j / 2]); } 1701 1702 // gen asm code to save regs 1703 static void save_registers(MacroAssembler* a); 1704 1705 // restore global registers in case C code disturbed them 1706 static void restore_registers(MacroAssembler* a, Register r); 1707 1708 1709}; 1710 1711 1712// MacroAssembler extends Assembler by a few frequently used macros. 1713// 1714// Most of the standard SPARC synthetic ops are defined here. 1715// Instructions for which a 'better' code sequence exists depending 1716// on arguments should also go in here. 1717 1718#define JMP2(r1, r2) jmp(r1, r2, __FILE__, __LINE__) 1719#define JMP(r1, off) jmp(r1, off, __FILE__, __LINE__) 1720#define JUMP(a, temp, off) jump(a, temp, off, __FILE__, __LINE__) 1721#define JUMPL(a, temp, d, off) jumpl(a, temp, d, off, __FILE__, __LINE__) 1722 1723 1724class MacroAssembler: public Assembler { 1725 protected: 1726 // Support for VM calls 1727 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 1728 // may customize this version by overriding it for its purposes (e.g., to save/restore 1729 // additional registers when doing a VM call). 1730#ifdef CC_INTERP 1731 #define VIRTUAL 1732#else 1733 #define VIRTUAL virtual 1734#endif 1735 1736 VIRTUAL void call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments); 1737 1738 // 1739 // It is imperative that all calls into the VM are handled via the call_VM macros. 1740 // They make sure that the stack linkage is setup correctly. call_VM's correspond 1741 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 1742 // 1743 // This is the base routine called by the different versions of call_VM. The interpreter 1744 // may customize this version by overriding it for its purposes (e.g., to save/restore 1745 // additional registers when doing a VM call). 1746 // 1747 // A non-volatile java_thread_cache register should be specified so 1748 // that the G2_thread value can be preserved across the call. 1749 // (If java_thread_cache is noreg, then a slow get_thread call 1750 // will re-initialize the G2_thread.) call_VM_base returns the register that contains the 1751 // thread. 1752 // 1753 // If no last_java_sp is specified (noreg) than SP will be used instead. 1754 1755 virtual void call_VM_base( 1756 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 1757 Register java_thread_cache, // the thread if computed before ; use noreg otherwise 1758 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 1759 address entry_point, // the entry point 1760 int number_of_arguments, // the number of arguments (w/o thread) to pop after call 1761 bool check_exception=true // flag which indicates if exception should be checked 1762 ); 1763 1764 // This routine should emit JVMTI PopFrame and ForceEarlyReturn handling code. 1765 // The implementation is only non-empty for the InterpreterMacroAssembler, 1766 // as only the interpreter handles and ForceEarlyReturn PopFrame requests. 1767 virtual void check_and_handle_popframe(Register scratch_reg); 1768 virtual void check_and_handle_earlyret(Register scratch_reg); 1769 1770 public: 1771 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 1772 1773 // Support for NULL-checks 1774 // 1775 // Generates code that causes a NULL OS exception if the content of reg is NULL. 1776 // If the accessed location is M[reg + offset] and the offset is known, provide the 1777 // offset. No explicit code generation is needed if the offset is within a certain 1778 // range (0 <= offset <= page_size). 1779 // 1780 // %%%%%% Currently not done for SPARC 1781 1782 void null_check(Register reg, int offset = -1); 1783 static bool needs_explicit_null_check(intptr_t offset); 1784 1785 // support for delayed instructions 1786 MacroAssembler* delayed() { Assembler::delayed(); return this; } 1787 1788 // branches that use right instruction for v8 vs. v9 1789 inline void br( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 1790 inline void br( Condition c, bool a, Predict p, Label& L ); 1791 inline void fb( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 1792 inline void fb( Condition c, bool a, Predict p, Label& L ); 1793 1794 // compares register with zero and branches (V9 and V8 instructions) 1795 void br_zero( Condition c, bool a, Predict p, Register s1, Label& L); 1796 // Compares a pointer register with zero and branches on (not)null. 1797 // Does a test & branch on 32-bit systems and a register-branch on 64-bit. 1798 void br_null ( Register s1, bool a, Predict p, Label& L ); 1799 void br_notnull( Register s1, bool a, Predict p, Label& L ); 1800 1801 // These versions will do the most efficient thing on v8 and v9. Perhaps 1802 // this is what the routine above was meant to do, but it didn't (and 1803 // didn't cover both target address kinds.) 1804 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, address d, relocInfo::relocType rt = relocInfo::none ); 1805 void br_on_reg_cond( RCondition c, bool a, Predict p, Register s1, Label& L); 1806 1807 inline void bp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 1808 inline void bp( Condition c, bool a, CC cc, Predict p, Label& L ); 1809 1810 // Branch that tests xcc in LP64 and icc in !LP64 1811 inline void brx( Condition c, bool a, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 1812 inline void brx( Condition c, bool a, Predict p, Label& L ); 1813 1814 // unconditional short branch 1815 inline void ba( bool a, Label& L ); 1816 1817 // Branch that tests fp condition codes 1818 inline void fbp( Condition c, bool a, CC cc, Predict p, address d, relocInfo::relocType rt = relocInfo::none ); 1819 inline void fbp( Condition c, bool a, CC cc, Predict p, Label& L ); 1820 1821 // get PC the best way 1822 inline int get_pc( Register d ); 1823 1824 // Sparc shorthands(pp 85, V8 manual, pp 289 V9 manual) 1825 inline void cmp( Register s1, Register s2 ) { subcc( s1, s2, G0 ); } 1826 inline void cmp( Register s1, int simm13a ) { subcc( s1, simm13a, G0 ); } 1827 1828 inline void jmp( Register s1, Register s2 ); 1829 inline void jmp( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); 1830 1831 inline void call( address d, relocInfo::relocType rt = relocInfo::runtime_call_type ); 1832 inline void call( Label& L, relocInfo::relocType rt = relocInfo::runtime_call_type ); 1833 inline void callr( Register s1, Register s2 ); 1834 inline void callr( Register s1, int simm13a, RelocationHolder const& rspec = RelocationHolder() ); 1835 1836 // Emits nothing on V8 1837 inline void iprefetch( address d, relocInfo::relocType rt = relocInfo::none ); 1838 inline void iprefetch( Label& L); 1839 1840 inline void tst( Register s ) { orcc( G0, s, G0 ); } 1841 1842#ifdef PRODUCT 1843 inline void ret( bool trace = TraceJumps ) { if (trace) { 1844 mov(I7, O7); // traceable register 1845 JMP(O7, 2 * BytesPerInstWord); 1846 } else { 1847 jmpl( I7, 2 * BytesPerInstWord, G0 ); 1848 } 1849 } 1850 1851 inline void retl( bool trace = TraceJumps ) { if (trace) JMP(O7, 2 * BytesPerInstWord); 1852 else jmpl( O7, 2 * BytesPerInstWord, G0 ); } 1853#else 1854 void ret( bool trace = TraceJumps ); 1855 void retl( bool trace = TraceJumps ); 1856#endif /* PRODUCT */ 1857 1858 // Required platform-specific helpers for Label::patch_instructions. 1859 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 1860 void pd_patch_instruction(address branch, address target); 1861#ifndef PRODUCT 1862 static void pd_print_patched_instruction(address branch); 1863#endif 1864 1865 // sethi Macro handles optimizations and relocations 1866private: 1867 void internal_sethi(const AddressLiteral& addrlit, Register d, bool ForceRelocatable); 1868public: 1869 void sethi(const AddressLiteral& addrlit, Register d); 1870 void patchable_sethi(const AddressLiteral& addrlit, Register d); 1871 1872 // compute the size of a sethi/set 1873 static int size_of_sethi( address a, bool worst_case = false ); 1874 static int worst_case_size_of_set(); 1875 1876 // set may be either setsw or setuw (high 32 bits may be zero or sign) 1877private: 1878 void internal_set(const AddressLiteral& al, Register d, bool ForceRelocatable); 1879public: 1880 void set(const AddressLiteral& addrlit, Register d); 1881 void set(intptr_t value, Register d); 1882 void set(address addr, Register d, RelocationHolder const& rspec); 1883 void patchable_set(const AddressLiteral& addrlit, Register d); 1884 void patchable_set(intptr_t value, Register d); 1885 void set64(jlong value, Register d, Register tmp); 1886 1887 // sign-extend 32 to 64 1888 inline void signx( Register s, Register d ) { sra( s, G0, d); } 1889 inline void signx( Register d ) { sra( d, G0, d); } 1890 1891 inline void not1( Register s, Register d ) { xnor( s, G0, d ); } 1892 inline void not1( Register d ) { xnor( d, G0, d ); } 1893 1894 inline void neg( Register s, Register d ) { sub( G0, s, d ); } 1895 inline void neg( Register d ) { sub( G0, d, d ); } 1896 1897 inline void cas( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY); } 1898 inline void casx( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY); } 1899 // Functions for isolating 64 bit atomic swaps for LP64 1900 // cas_ptr will perform cas for 32 bit VM's and casx for 64 bit VM's 1901 inline void cas_ptr( Register s1, Register s2, Register d) { 1902#ifdef _LP64 1903 casx( s1, s2, d ); 1904#else 1905 cas( s1, s2, d ); 1906#endif 1907 } 1908 1909 // Functions for isolating 64 bit shifts for LP64 1910 inline void sll_ptr( Register s1, Register s2, Register d ); 1911 inline void sll_ptr( Register s1, int imm6a, Register d ); 1912 inline void sll_ptr( Register s1, RegisterOrConstant s2, Register d ); 1913 inline void srl_ptr( Register s1, Register s2, Register d ); 1914 inline void srl_ptr( Register s1, int imm6a, Register d ); 1915 1916 // little-endian 1917 inline void casl( Register s1, Register s2, Register d) { casa( s1, s2, d, ASI_PRIMARY_LITTLE); } 1918 inline void casxl( Register s1, Register s2, Register d) { casxa(s1, s2, d, ASI_PRIMARY_LITTLE); } 1919 1920 inline void inc( Register d, int const13 = 1 ) { add( d, const13, d); } 1921 inline void inccc( Register d, int const13 = 1 ) { addcc( d, const13, d); } 1922 1923 inline void dec( Register d, int const13 = 1 ) { sub( d, const13, d); } 1924 inline void deccc( Register d, int const13 = 1 ) { subcc( d, const13, d); } 1925 1926 inline void btst( Register s1, Register s2 ) { andcc( s1, s2, G0 ); } 1927 inline void btst( int simm13a, Register s ) { andcc( s, simm13a, G0 ); } 1928 1929 inline void bset( Register s1, Register s2 ) { or3( s1, s2, s2 ); } 1930 inline void bset( int simm13a, Register s ) { or3( s, simm13a, s ); } 1931 1932 inline void bclr( Register s1, Register s2 ) { andn( s1, s2, s2 ); } 1933 inline void bclr( int simm13a, Register s ) { andn( s, simm13a, s ); } 1934 1935 inline void btog( Register s1, Register s2 ) { xor3( s1, s2, s2 ); } 1936 inline void btog( int simm13a, Register s ) { xor3( s, simm13a, s ); } 1937 1938 inline void clr( Register d ) { or3( G0, G0, d ); } 1939 1940 inline void clrb( Register s1, Register s2); 1941 inline void clrh( Register s1, Register s2); 1942 inline void clr( Register s1, Register s2); 1943 inline void clrx( Register s1, Register s2); 1944 1945 inline void clrb( Register s1, int simm13a); 1946 inline void clrh( Register s1, int simm13a); 1947 inline void clr( Register s1, int simm13a); 1948 inline void clrx( Register s1, int simm13a); 1949 1950 // copy & clear upper word 1951 inline void clruw( Register s, Register d ) { srl( s, G0, d); } 1952 // clear upper word 1953 inline void clruwu( Register d ) { srl( d, G0, d); } 1954 1955 // membar psuedo instruction. takes into account target memory model. 1956 inline void membar( Assembler::Membar_mask_bits const7a ); 1957 1958 // returns if membar generates anything. 1959 inline bool membar_has_effect( Assembler::Membar_mask_bits const7a ); 1960 1961 // mov pseudo instructions 1962 inline void mov( Register s, Register d) { 1963 if ( s != d ) or3( G0, s, d); 1964 else assert_not_delayed(); // Put something useful in the delay slot! 1965 } 1966 1967 inline void mov_or_nop( Register s, Register d) { 1968 if ( s != d ) or3( G0, s, d); 1969 else nop(); 1970 } 1971 1972 inline void mov( int simm13a, Register d) { or3( G0, simm13a, d); } 1973 1974 // address pseudos: make these names unlike instruction names to avoid confusion 1975 inline intptr_t load_pc_address( Register reg, int bytes_to_skip ); 1976 inline void load_contents(AddressLiteral& addrlit, Register d, int offset = 0); 1977 inline void load_ptr_contents(AddressLiteral& addrlit, Register d, int offset = 0); 1978 inline void store_contents(Register s, AddressLiteral& addrlit, Register temp, int offset = 0); 1979 inline void store_ptr_contents(Register s, AddressLiteral& addrlit, Register temp, int offset = 0); 1980 inline void jumpl_to(AddressLiteral& addrlit, Register temp, Register d, int offset = 0); 1981 inline void jump_to(AddressLiteral& addrlit, Register temp, int offset = 0); 1982 inline void jump_indirect_to(Address& a, Register temp, int ld_offset = 0, int jmp_offset = 0); 1983 1984 // ring buffer traceable jumps 1985 1986 void jmp2( Register r1, Register r2, const char* file, int line ); 1987 void jmp ( Register r1, int offset, const char* file, int line ); 1988 1989 void jumpl(AddressLiteral& addrlit, Register temp, Register d, int offset, const char* file, int line); 1990 void jump (AddressLiteral& addrlit, Register temp, int offset, const char* file, int line); 1991 1992 1993 // argument pseudos: 1994 1995 inline void load_argument( Argument& a, Register d ); 1996 inline void store_argument( Register s, Argument& a ); 1997 inline void store_ptr_argument( Register s, Argument& a ); 1998 inline void store_float_argument( FloatRegister s, Argument& a ); 1999 inline void store_double_argument( FloatRegister s, Argument& a ); 2000 inline void store_long_argument( Register s, Argument& a ); 2001 2002 // handy macros: 2003 2004 inline void round_to( Register r, int modulus ) { 2005 assert_not_delayed(); 2006 inc( r, modulus - 1 ); 2007 and3( r, -modulus, r ); 2008 } 2009 2010 // -------------------------------------------------- 2011 2012 // Functions for isolating 64 bit loads for LP64 2013 // ld_ptr will perform ld for 32 bit VM's and ldx for 64 bit VM's 2014 // st_ptr will perform st for 32 bit VM's and stx for 64 bit VM's 2015 inline void ld_ptr(Register s1, Register s2, Register d); 2016 inline void ld_ptr(Register s1, int simm13a, Register d); 2017 inline void ld_ptr(Register s1, RegisterOrConstant s2, Register d); 2018 inline void ld_ptr(const Address& a, Register d, int offset = 0); 2019 inline void st_ptr(Register d, Register s1, Register s2); 2020 inline void st_ptr(Register d, Register s1, int simm13a); 2021 inline void st_ptr(Register d, Register s1, RegisterOrConstant s2); 2022 inline void st_ptr(Register d, const Address& a, int offset = 0); 2023 2024#ifdef ASSERT 2025 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. 2026 inline void ld_ptr(Register s1, ByteSize simm13a, Register d); 2027 inline void st_ptr(Register d, Register s1, ByteSize simm13a); 2028#endif 2029 2030 // ld_long will perform ldd for 32 bit VM's and ldx for 64 bit VM's 2031 // st_long will perform std for 32 bit VM's and stx for 64 bit VM's 2032 inline void ld_long(Register s1, Register s2, Register d); 2033 inline void ld_long(Register s1, int simm13a, Register d); 2034 inline void ld_long(Register s1, RegisterOrConstant s2, Register d); 2035 inline void ld_long(const Address& a, Register d, int offset = 0); 2036 inline void st_long(Register d, Register s1, Register s2); 2037 inline void st_long(Register d, Register s1, int simm13a); 2038 inline void st_long(Register d, Register s1, RegisterOrConstant s2); 2039 inline void st_long(Register d, const Address& a, int offset = 0); 2040 2041 // Helpers for address formation. 2042 // - They emit only a move if s2 is a constant zero. 2043 // - If dest is a constant and either s1 or s2 is a register, the temp argument is required and becomes the result. 2044 // - If dest is a register and either s1 or s2 is a non-simm13 constant, the temp argument is required and used to materialize the constant. 2045 RegisterOrConstant regcon_andn_ptr(RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); 2046 RegisterOrConstant regcon_inc_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); 2047 RegisterOrConstant regcon_sll_ptr( RegisterOrConstant s1, RegisterOrConstant s2, RegisterOrConstant d, Register temp = noreg); 2048 2049 RegisterOrConstant ensure_simm13_or_reg(RegisterOrConstant src, Register temp) { 2050 if (is_simm13(src.constant_or_zero())) 2051 return src; // register or short constant 2052 guarantee(temp != noreg, "constant offset overflow"); 2053 set(src.as_constant(), temp); 2054 return temp; 2055 } 2056 2057 // -------------------------------------------------- 2058 2059 public: 2060 // traps as per trap.h (SPARC ABI?) 2061 2062 void breakpoint_trap(); 2063 void breakpoint_trap(Condition c, CC cc = icc); 2064 void flush_windows_trap(); 2065 void clean_windows_trap(); 2066 void get_psr_trap(); 2067 void set_psr_trap(); 2068 2069 // V8/V9 flush_windows 2070 void flush_windows(); 2071 2072 // Support for serializing memory accesses between threads 2073 void serialize_memory(Register thread, Register tmp1, Register tmp2); 2074 2075 // Stack frame creation/removal 2076 void enter(); 2077 void leave(); 2078 2079 // V8/V9 integer multiply 2080 void mult(Register s1, Register s2, Register d); 2081 void mult(Register s1, int simm13a, Register d); 2082 2083 // V8/V9 read and write of condition codes. 2084 void read_ccr(Register d); 2085 void write_ccr(Register s); 2086 2087 // Manipulation of C++ bools 2088 // These are idioms to flag the need for care with accessing bools but on 2089 // this platform we assume byte size 2090 2091 inline void stbool(Register d, const Address& a) { stb(d, a); } 2092 inline void ldbool(const Address& a, Register d) { ldsb(a, d); } 2093 inline void tstbool( Register s ) { tst(s); } 2094 inline void movbool( bool boolconst, Register d) { mov( (int) boolconst, d); } 2095 2096 // klass oop manipulations if compressed 2097 void load_klass(Register src_oop, Register klass); 2098 void store_klass(Register klass, Register dst_oop); 2099 void store_klass_gap(Register s, Register dst_oop); 2100 2101 // oop manipulations 2102 void load_heap_oop(const Address& s, Register d); 2103 void load_heap_oop(Register s1, Register s2, Register d); 2104 void load_heap_oop(Register s1, int simm13a, Register d); 2105 void store_heap_oop(Register d, Register s1, Register s2); 2106 void store_heap_oop(Register d, Register s1, int simm13a); 2107 void store_heap_oop(Register d, const Address& a, int offset = 0); 2108 2109 void encode_heap_oop(Register src, Register dst); 2110 void encode_heap_oop(Register r) { 2111 encode_heap_oop(r, r); 2112 } 2113 void decode_heap_oop(Register src, Register dst); 2114 void decode_heap_oop(Register r) { 2115 decode_heap_oop(r, r); 2116 } 2117 void encode_heap_oop_not_null(Register r); 2118 void decode_heap_oop_not_null(Register r); 2119 void encode_heap_oop_not_null(Register src, Register dst); 2120 void decode_heap_oop_not_null(Register src, Register dst); 2121 2122 // Support for managing the JavaThread pointer (i.e.; the reference to 2123 // thread-local information). 2124 void get_thread(); // load G2_thread 2125 void verify_thread(); // verify G2_thread contents 2126 void save_thread (const Register threache); // save to cache 2127 void restore_thread(const Register thread_cache); // restore from cache 2128 2129 // Support for last Java frame (but use call_VM instead where possible) 2130 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc); 2131 void reset_last_Java_frame(void); 2132 2133 // Call into the VM. 2134 // Passes the thread pointer (in O0) as a prepended argument. 2135 // Makes sure oop return values are visible to the GC. 2136 void call_VM(Register oop_result, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 2137 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true); 2138 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 2139 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 2140 2141 // these overloadings are not presently used on SPARC: 2142 void call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 2143 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 2144 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 2145 void call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 2146 2147 void call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments = 0); 2148 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1); 2149 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2); 2150 void call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3); 2151 2152 void get_vm_result (Register oop_result); 2153 void get_vm_result_2(Register oop_result); 2154 2155 // vm result is currently getting hijacked to for oop preservation 2156 void set_vm_result(Register oop_result); 2157 2158 // if call_VM_base was called with check_exceptions=false, then call 2159 // check_and_forward_exception to handle exceptions when it is safe 2160 void check_and_forward_exception(Register scratch_reg); 2161 2162 private: 2163 // For V8 2164 void read_ccr_trap(Register ccr_save); 2165 void write_ccr_trap(Register ccr_save1, Register scratch1, Register scratch2); 2166 2167#ifdef ASSERT 2168 // For V8 debugging. Uses V8 instruction sequence and checks 2169 // result with V9 insturctions rdccr and wrccr. 2170 // Uses Gscatch and Gscatch2 2171 void read_ccr_v8_assert(Register ccr_save); 2172 void write_ccr_v8_assert(Register ccr_save); 2173#endif // ASSERT 2174 2175 public: 2176 2177 // Write to card table for - register is destroyed afterwards. 2178 void card_table_write(jbyte* byte_map_base, Register tmp, Register obj); 2179 2180 void card_write_barrier_post(Register store_addr, Register new_val, Register tmp); 2181 2182#ifndef SERIALGC 2183 // Array store and offset 2184 void g1_write_barrier_pre(Register obj, Register index, int offset, Register tmp, bool preserve_o_regs); 2185 2186 void g1_write_barrier_post(Register store_addr, Register new_val, Register tmp); 2187 2188 // May do filtering, depending on the boolean arguments. 2189 void g1_card_table_write(jbyte* byte_map_base, 2190 Register tmp, Register obj, Register new_val, 2191 bool region_filter, bool null_filter); 2192#endif // SERIALGC 2193 2194 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack 2195 void push_fTOS(); 2196 2197 // pops double TOS element from CPU stack and pushes on FPU stack 2198 void pop_fTOS(); 2199 2200 void empty_FPU_stack(); 2201 2202 void push_IU_state(); 2203 void pop_IU_state(); 2204 2205 void push_FPU_state(); 2206 void pop_FPU_state(); 2207 2208 void push_CPU_state(); 2209 void pop_CPU_state(); 2210 2211 // if heap base register is used - reinit it with the correct value 2212 void reinit_heapbase(); 2213 2214 // Debugging 2215 void _verify_oop(Register reg, const char * msg, const char * file, int line); 2216 void _verify_oop_addr(Address addr, const char * msg, const char * file, int line); 2217 2218#define verify_oop(reg) _verify_oop(reg, "broken oop " #reg, __FILE__, __LINE__) 2219#define verify_oop_addr(addr) _verify_oop_addr(addr, "broken oop addr ", __FILE__, __LINE__) 2220 2221 // only if +VerifyOops 2222 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 2223 // only if +VerifyFPU 2224 void stop(const char* msg); // prints msg, dumps registers and stops execution 2225 void warn(const char* msg); // prints msg, but don't stop 2226 void untested(const char* what = ""); 2227 void unimplemented(const char* what = "") { char* b = new char[1024]; sprintf(b, "unimplemented: %s", what); stop(b); } 2228 void should_not_reach_here() { stop("should not reach here"); } 2229 void print_CPU_state(); 2230 2231 // oops in code 2232 AddressLiteral allocate_oop_address(jobject obj); // allocate_index 2233 AddressLiteral constant_oop_address(jobject obj); // find_index 2234 inline void set_oop (jobject obj, Register d); // uses allocate_oop_address 2235 inline void set_oop_constant (jobject obj, Register d); // uses constant_oop_address 2236 inline void set_oop (const AddressLiteral& obj_addr, Register d); // same as load_address 2237 2238 void set_narrow_oop( jobject obj, Register d ); 2239 2240 // nop padding 2241 void align(int modulus); 2242 2243 // declare a safepoint 2244 void safepoint(); 2245 2246 // factor out part of stop into subroutine to save space 2247 void stop_subroutine(); 2248 // factor out part of verify_oop into subroutine to save space 2249 void verify_oop_subroutine(); 2250 2251 // side-door communication with signalHandler in os_solaris.cpp 2252 static address _verify_oop_implicit_branch[3]; 2253 2254#ifndef PRODUCT 2255 static void test(); 2256#endif 2257 2258 // convert an incoming arglist to varargs format; put the pointer in d 2259 void set_varargs( Argument a, Register d ); 2260 2261 int total_frame_size_in_bytes(int extraWords); 2262 2263 // used when extraWords known statically 2264 void save_frame(int extraWords); 2265 void save_frame_c1(int size_in_bytes); 2266 // make a frame, and simultaneously pass up one or two register value 2267 // into the new register window 2268 void save_frame_and_mov(int extraWords, Register s1, Register d1, Register s2 = Register(), Register d2 = Register()); 2269 2270 // give no. (outgoing) params, calc # of words will need on frame 2271 void calc_mem_param_words(Register Rparam_words, Register Rresult); 2272 2273 // used to calculate frame size dynamically 2274 // result is in bytes and must be negated for save inst 2275 void calc_frame_size(Register extraWords, Register resultReg); 2276 2277 // calc and also save 2278 void calc_frame_size_and_save(Register extraWords, Register resultReg); 2279 2280 static void debug(char* msg, RegistersForDebugging* outWindow); 2281 2282 // implementations of bytecodes used by both interpreter and compiler 2283 2284 void lcmp( Register Ra_hi, Register Ra_low, 2285 Register Rb_hi, Register Rb_low, 2286 Register Rresult); 2287 2288 void lneg( Register Rhi, Register Rlow ); 2289 2290 void lshl( Register Rin_high, Register Rin_low, Register Rcount, 2291 Register Rout_high, Register Rout_low, Register Rtemp ); 2292 2293 void lshr( Register Rin_high, Register Rin_low, Register Rcount, 2294 Register Rout_high, Register Rout_low, Register Rtemp ); 2295 2296 void lushr( Register Rin_high, Register Rin_low, Register Rcount, 2297 Register Rout_high, Register Rout_low, Register Rtemp ); 2298 2299#ifdef _LP64 2300 void lcmp( Register Ra, Register Rb, Register Rresult); 2301#endif 2302 2303 // Loading values by size and signed-ness 2304 void load_sized_value(Address src, Register dst, size_t size_in_bytes, bool is_signed); 2305 2306 void float_cmp( bool is_float, int unordered_result, 2307 FloatRegister Fa, FloatRegister Fb, 2308 Register Rresult); 2309 2310 void fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); 2311 void fneg( FloatRegisterImpl::Width w, FloatRegister sd ) { Assembler::fneg(w, sd); } 2312 void fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); 2313 void fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d); 2314 2315 void save_all_globals_into_locals(); 2316 void restore_globals_from_locals(); 2317 2318 void casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, 2319 address lock_addr=0, bool use_call_vm=false); 2320 void cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, 2321 address lock_addr=0, bool use_call_vm=false); 2322 void casn (Register addr_reg, Register cmp_reg, Register set_reg) ; 2323 2324 // These set the icc condition code to equal if the lock succeeded 2325 // and notEqual if it failed and requires a slow case 2326 void compiler_lock_object(Register Roop, Register Rmark, Register Rbox, 2327 Register Rscratch, 2328 BiasedLockingCounters* counters = NULL, 2329 bool try_bias = UseBiasedLocking); 2330 void compiler_unlock_object(Register Roop, Register Rmark, Register Rbox, 2331 Register Rscratch, 2332 bool try_bias = UseBiasedLocking); 2333 2334 // Biased locking support 2335 // Upon entry, lock_reg must point to the lock record on the stack, 2336 // obj_reg must contain the target object, and mark_reg must contain 2337 // the target object's header. 2338 // Destroys mark_reg if an attempt is made to bias an anonymously 2339 // biased lock. In this case a failure will go either to the slow 2340 // case or fall through with the notEqual condition code set with 2341 // the expectation that the slow case in the runtime will be called. 2342 // In the fall-through case where the CAS-based lock is done, 2343 // mark_reg is not destroyed. 2344 void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg, 2345 Label& done, Label* slow_case = NULL, 2346 BiasedLockingCounters* counters = NULL); 2347 // Upon entry, the base register of mark_addr must contain the oop. 2348 // Destroys temp_reg. 2349 2350 // If allow_delay_slot_filling is set to true, the next instruction 2351 // emitted after this one will go in an annulled delay slot if the 2352 // biased locking exit case failed. 2353 void biased_locking_exit(Address mark_addr, Register temp_reg, Label& done, bool allow_delay_slot_filling = false); 2354 2355 // allocation 2356 void eden_allocate( 2357 Register obj, // result: pointer to object after successful allocation 2358 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 2359 int con_size_in_bytes, // object size in bytes if known at compile time 2360 Register t1, // temp register 2361 Register t2, // temp register 2362 Label& slow_case // continuation point if fast allocation fails 2363 ); 2364 void tlab_allocate( 2365 Register obj, // result: pointer to object after successful allocation 2366 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 2367 int con_size_in_bytes, // object size in bytes if known at compile time 2368 Register t1, // temp register 2369 Label& slow_case // continuation point if fast allocation fails 2370 ); 2371 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); 2372 2373 // interface method calling 2374 void lookup_interface_method(Register recv_klass, 2375 Register intf_klass, 2376 RegisterOrConstant itable_index, 2377 Register method_result, 2378 Register temp_reg, Register temp2_reg, 2379 Label& no_such_interface); 2380 2381 // Test sub_klass against super_klass, with fast and slow paths. 2382 2383 // The fast path produces a tri-state answer: yes / no / maybe-slow. 2384 // One of the three labels can be NULL, meaning take the fall-through. 2385 // If super_check_offset is -1, the value is loaded up from super_klass. 2386 // No registers are killed, except temp_reg and temp2_reg. 2387 // If super_check_offset is not -1, temp2_reg is not used and can be noreg. 2388 void check_klass_subtype_fast_path(Register sub_klass, 2389 Register super_klass, 2390 Register temp_reg, 2391 Register temp2_reg, 2392 Label* L_success, 2393 Label* L_failure, 2394 Label* L_slow_path, 2395 RegisterOrConstant super_check_offset = RegisterOrConstant(-1), 2396 Register instanceof_hack = noreg); 2397 2398 // The rest of the type check; must be wired to a corresponding fast path. 2399 // It does not repeat the fast path logic, so don't use it standalone. 2400 // The temp_reg can be noreg, if no temps are available. 2401 // It can also be sub_klass or super_klass, meaning it's OK to kill that one. 2402 // Updates the sub's secondary super cache as necessary. 2403 void check_klass_subtype_slow_path(Register sub_klass, 2404 Register super_klass, 2405 Register temp_reg, 2406 Register temp2_reg, 2407 Register temp3_reg, 2408 Register temp4_reg, 2409 Label* L_success, 2410 Label* L_failure); 2411 2412 // Simplified, combined version, good for typical uses. 2413 // Falls through on failure. 2414 void check_klass_subtype(Register sub_klass, 2415 Register super_klass, 2416 Register temp_reg, 2417 Register temp2_reg, 2418 Label& L_success); 2419 2420 // method handles (JSR 292) 2421 void check_method_handle_type(Register mtype_reg, Register mh_reg, 2422 Register temp_reg, 2423 Label& wrong_method_type); 2424 void load_method_handle_vmslots(Register vmslots_reg, Register mh_reg, 2425 Register temp_reg); 2426 void jump_to_method_handle_entry(Register mh_reg, Register temp_reg, bool emit_delayed_nop = true); 2427 // offset relative to Gargs of argument at tos[arg_slot]. 2428 // (arg_slot == 0 means the last argument, not the first). 2429 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, 2430 int extra_slot_offset = 0); 2431 // Address of Gargs and argument_offset. 2432 Address argument_address(RegisterOrConstant arg_slot, 2433 int extra_slot_offset = 0); 2434 2435 // Stack overflow checking 2436 2437 // Note: this clobbers G3_scratch 2438 void bang_stack_with_offset(int offset) { 2439 // stack grows down, caller passes positive offset 2440 assert(offset > 0, "must bang with negative offset"); 2441 set((-offset)+STACK_BIAS, G3_scratch); 2442 st(G0, SP, G3_scratch); 2443 } 2444 2445 // Writes to stack successive pages until offset reached to check for 2446 // stack overflow + shadow pages. Clobbers tsp and scratch registers. 2447 void bang_stack_size(Register Rsize, Register Rtsp, Register Rscratch); 2448 2449 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, Register tmp, int offset); 2450 2451 void verify_tlab(); 2452 2453 Condition negate_condition(Condition cond); 2454 2455 // Helper functions for statistics gathering. 2456 // Conditionally (non-atomically) increments passed counter address, preserving condition codes. 2457 void cond_inc(Condition cond, address counter_addr, Register Rtemp1, Register Rtemp2); 2458 // Unconditional increment. 2459 void inc_counter(address counter_addr, Register Rtmp1, Register Rtmp2); 2460 void inc_counter(int* counter_addr, Register Rtmp1, Register Rtmp2); 2461 2462 // Compare char[] arrays aligned to 4 bytes. 2463 void char_arrays_equals(Register ary1, Register ary2, 2464 Register limit, Register result, 2465 Register chr1, Register chr2, Label& Ldone); 2466 2467#undef VIRTUAL 2468 2469}; 2470 2471/** 2472 * class SkipIfEqual: 2473 * 2474 * Instantiating this class will result in assembly code being output that will 2475 * jump around any code emitted between the creation of the instance and it's 2476 * automatic destruction at the end of a scope block, depending on the value of 2477 * the flag passed to the constructor, which will be checked at run-time. 2478 */ 2479class SkipIfEqual : public StackObj { 2480 private: 2481 MacroAssembler* _masm; 2482 Label _label; 2483 2484 public: 2485 // 'temp' is a temp register that this object can use (and trash) 2486 SkipIfEqual(MacroAssembler*, Register temp, 2487 const bool* flag_addr, Assembler::Condition condition); 2488 ~SkipIfEqual(); 2489}; 2490 2491#ifdef ASSERT 2492// On RISC, there's no benefit to verifying instruction boundaries. 2493inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } 2494#endif 2495