ppc.ad revision 10049:73443d24e529
1// 2// Copyright (c) 2011, 2016, Oracle and/or its affiliates. All rights reserved. 3// Copyright (c) 2012, 2015 SAP SE. All rights reserved. 4// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5// 6// This code is free software; you can redistribute it and/or modify it 7// under the terms of the GNU General Public License version 2 only, as 8// published by the Free Software Foundation. 9// 10// This code is distributed in the hope that it will be useful, but WITHOUT 11// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13// version 2 for more details (a copy is included in the LICENSE file that 14// accompanied this code). 15// 16// You should have received a copy of the GNU General Public License version 17// 2 along with this work; if not, write to the Free Software Foundation, 18// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19// 20// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21// or visit www.oracle.com if you need additional information or have any 22// questions. 23// 24// 25 26// 27// PPC64 Architecture Description File 28// 29 30//----------REGISTER DEFINITION BLOCK------------------------------------------ 31// This information is used by the matcher and the register allocator to 32// describe individual registers and classes of registers within the target 33// architecture. 34register %{ 35//----------Architecture Description Register Definitions---------------------- 36// General Registers 37// "reg_def" name (register save type, C convention save type, 38// ideal register type, encoding); 39// 40// Register Save Types: 41// 42// NS = No-Save: The register allocator assumes that these registers 43// can be used without saving upon entry to the method, & 44// that they do not need to be saved at call sites. 45// 46// SOC = Save-On-Call: The register allocator assumes that these registers 47// can be used without saving upon entry to the method, 48// but that they must be saved at call sites. 49// These are called "volatiles" on ppc. 50// 51// SOE = Save-On-Entry: The register allocator assumes that these registers 52// must be saved before using them upon entry to the 53// method, but they do not need to be saved at call 54// sites. 55// These are called "nonvolatiles" on ppc. 56// 57// AS = Always-Save: The register allocator assumes that these registers 58// must be saved before using them upon entry to the 59// method, & that they must be saved at call sites. 60// 61// Ideal Register Type is used to determine how to save & restore a 62// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 63// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 64// 65// The encoding number is the actual bit-pattern placed into the opcodes. 66// 67// PPC64 register definitions, based on the 64-bit PowerPC ELF ABI 68// Supplement Version 1.7 as of 2003-10-29. 69// 70// For each 64-bit register we must define two registers: the register 71// itself, e.g. R3, and a corresponding virtual other (32-bit-)'half', 72// e.g. R3_H, which is needed by the allocator, but is not used 73// for stores, loads, etc. 74 75// ---------------------------- 76// Integer/Long Registers 77// ---------------------------- 78 79 // PPC64 has 32 64-bit integer registers. 80 81 // types: v = volatile, nv = non-volatile, s = system 82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs 83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() ); 84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP 85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() ); 86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC 87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() ); 88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret 89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() ); 90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2 91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() ); 92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3 93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() ); 94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4 95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() ); 96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5 97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() ); 98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6 99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() ); 100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7 101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() ); 102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8 103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next()); 104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch 105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next()); 106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch 107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next()); 108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id 109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next()); 110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv 111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next()); 112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv 113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next()); 114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv 115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next()); 116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv 117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next()); 118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv 119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next()); 120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv 121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next()); 122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv 123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next()); 124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv 125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next()); 126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv 127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next()); 128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv 129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next()); 130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv 131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next()); 132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv 133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next()); 134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv 135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next()); 136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv 137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next()); 138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv 139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next()); 140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv 141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next()); 142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv 143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next()); 144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv 145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next()); 146 147 148// ---------------------------- 149// Float/Double Registers 150// ---------------------------- 151 152 // Double Registers 153 // The rules of ADL require that double registers be defined in pairs. 154 // Each pair must be two 32-bit values, but not necessarily a pair of 155 // single float registers. In each pair, ADLC-assigned register numbers 156 // must be adjacent, with the lower number even. Finally, when the 157 // CPU stores such a register pair to memory, the word associated with 158 // the lower ADLC-assigned number must be stored to the lower address. 159 160 // PPC64 has 32 64-bit floating-point registers. Each can store a single 161 // or double precision floating-point value. 162 163 // types: v = volatile, nv = non-volatile, s = system 164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch 165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() ); 166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret 167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() ); 168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2 169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() ); 170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3 171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() ); 172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4 173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() ); 174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5 175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() ); 176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6 177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() ); 178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7 179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() ); 180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8 181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() ); 182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9 183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() ); 184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10 185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next()); 186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11 187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next()); 188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12 189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next()); 190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13 191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next()); 192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv 193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next()); 194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv 195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next()); 196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv 197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next()); 198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv 199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next()); 200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv 201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next()); 202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv 203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next()); 204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv 205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next()); 206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv 207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next()); 208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv 209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next()); 210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv 211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next()); 212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv 213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next()); 214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv 215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next()); 216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv 217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next()); 218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv 219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next()); 220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv 221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next()); 222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv 223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next()); 224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv 225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next()); 226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv 227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next()); 228 229// ---------------------------- 230// Special Registers 231// ---------------------------- 232 233// Condition Codes Flag Registers 234 235 // PPC64 has 8 condition code "registers" which are all contained 236 // in the CR register. 237 238 // types: v = volatile, nv = non-volatile, s = system 239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v 240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v 241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv 242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv 243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv 244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v 245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v 246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v 247 248 // Special registers of PPC64 249 250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v 251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v 252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v 253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v 254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v 255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v 256 257 258// ---------------------------- 259// Specify priority of register selection within phases of register 260// allocation. Highest priority is first. A useful heuristic is to 261// give registers a low priority when they are required by machine 262// instructions, like EAX and EDX on I486, and choose no-save registers 263// before save-on-call, & save-on-call before save-on-entry. Registers 264// which participate in fixed calling sequences should come last. 265// Registers which are used as pairs must fall on an even boundary. 266 267// It's worth about 1% on SPEC geomean to get this right. 268 269// Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration 270// in adGlobals_ppc.hpp which defines the <register>_num values, e.g. 271// R3_num. Therefore, R3_num may not be (and in reality is not) 272// the same as R3->encoding()! Furthermore, we cannot make any 273// assumptions on ordering, e.g. R3_num may be less than R2_num. 274// Additionally, the function 275// static enum RC rc_class(OptoReg::Name reg ) 276// maps a given <register>_num value to its chunk type (except for flags) 277// and its current implementation relies on chunk0 and chunk1 having a 278// size of 64 each. 279 280// If you change this allocation class, please have a look at the 281// default values for the parameters RoundRobinIntegerRegIntervalStart 282// and RoundRobinFloatRegIntervalStart 283 284alloc_class chunk0 ( 285 // Chunk0 contains *all* 64 integer registers halves. 286 287 // "non-volatile" registers 288 R14, R14_H, 289 R15, R15_H, 290 R17, R17_H, 291 R18, R18_H, 292 R19, R19_H, 293 R20, R20_H, 294 R21, R21_H, 295 R22, R22_H, 296 R23, R23_H, 297 R24, R24_H, 298 R25, R25_H, 299 R26, R26_H, 300 R27, R27_H, 301 R28, R28_H, 302 R29, R29_H, 303 R30, R30_H, 304 R31, R31_H, 305 306 // scratch/special registers 307 R11, R11_H, 308 R12, R12_H, 309 310 // argument registers 311 R10, R10_H, 312 R9, R9_H, 313 R8, R8_H, 314 R7, R7_H, 315 R6, R6_H, 316 R5, R5_H, 317 R4, R4_H, 318 R3, R3_H, 319 320 // special registers, not available for allocation 321 R16, R16_H, // R16_thread 322 R13, R13_H, // system thread id 323 R2, R2_H, // may be used for TOC 324 R1, R1_H, // SP 325 R0, R0_H // R0 (scratch) 326); 327 328// If you change this allocation class, please have a look at the 329// default values for the parameters RoundRobinIntegerRegIntervalStart 330// and RoundRobinFloatRegIntervalStart 331 332alloc_class chunk1 ( 333 // Chunk1 contains *all* 64 floating-point registers halves. 334 335 // scratch register 336 F0, F0_H, 337 338 // argument registers 339 F13, F13_H, 340 F12, F12_H, 341 F11, F11_H, 342 F10, F10_H, 343 F9, F9_H, 344 F8, F8_H, 345 F7, F7_H, 346 F6, F6_H, 347 F5, F5_H, 348 F4, F4_H, 349 F3, F3_H, 350 F2, F2_H, 351 F1, F1_H, 352 353 // non-volatile registers 354 F14, F14_H, 355 F15, F15_H, 356 F16, F16_H, 357 F17, F17_H, 358 F18, F18_H, 359 F19, F19_H, 360 F20, F20_H, 361 F21, F21_H, 362 F22, F22_H, 363 F23, F23_H, 364 F24, F24_H, 365 F25, F25_H, 366 F26, F26_H, 367 F27, F27_H, 368 F28, F28_H, 369 F29, F29_H, 370 F30, F30_H, 371 F31, F31_H 372); 373 374alloc_class chunk2 ( 375 // Chunk2 contains *all* 8 condition code registers. 376 377 CCR0, 378 CCR1, 379 CCR2, 380 CCR3, 381 CCR4, 382 CCR5, 383 CCR6, 384 CCR7 385); 386 387alloc_class chunk3 ( 388 // special registers 389 // These registers are not allocated, but used for nodes generated by postalloc expand. 390 SR_XER, 391 SR_LR, 392 SR_CTR, 393 SR_VRSAVE, 394 SR_SPEFSCR, 395 SR_PPR 396); 397 398//-------Architecture Description Register Classes----------------------- 399 400// Several register classes are automatically defined based upon 401// information in this architecture description. 402 403// 1) reg_class inline_cache_reg ( as defined in frame section ) 404// 2) reg_class compiler_method_oop_reg ( as defined in frame section ) 405// 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 406// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 407// 408 409// ---------------------------- 410// 32 Bit Register Classes 411// ---------------------------- 412 413// We specify registers twice, once as read/write, and once read-only. 414// We use the read-only registers for source operands. With this, we 415// can include preset read only registers in this class, as a hard-coded 416// '0'-register. (We used to simulate this on ppc.) 417 418// 32 bit registers that can be read and written i.e. these registers 419// can be dest (or src) of normal instructions. 420reg_class bits32_reg_rw( 421/*R0*/ // R0 422/*R1*/ // SP 423 R2, // TOC 424 R3, 425 R4, 426 R5, 427 R6, 428 R7, 429 R8, 430 R9, 431 R10, 432 R11, 433 R12, 434/*R13*/ // system thread id 435 R14, 436 R15, 437/*R16*/ // R16_thread 438 R17, 439 R18, 440 R19, 441 R20, 442 R21, 443 R22, 444 R23, 445 R24, 446 R25, 447 R26, 448 R27, 449 R28, 450/*R29,*/ // global TOC 451 R30, 452 R31 453); 454 455// 32 bit registers that can only be read i.e. these registers can 456// only be src of all instructions. 457reg_class bits32_reg_ro( 458/*R0*/ // R0 459/*R1*/ // SP 460 R2 // TOC 461 R3, 462 R4, 463 R5, 464 R6, 465 R7, 466 R8, 467 R9, 468 R10, 469 R11, 470 R12, 471/*R13*/ // system thread id 472 R14, 473 R15, 474/*R16*/ // R16_thread 475 R17, 476 R18, 477 R19, 478 R20, 479 R21, 480 R22, 481 R23, 482 R24, 483 R25, 484 R26, 485 R27, 486 R28, 487/*R29,*/ 488 R30, 489 R31 490); 491 492reg_class rscratch1_bits32_reg(R11); 493reg_class rscratch2_bits32_reg(R12); 494reg_class rarg1_bits32_reg(R3); 495reg_class rarg2_bits32_reg(R4); 496reg_class rarg3_bits32_reg(R5); 497reg_class rarg4_bits32_reg(R6); 498 499// ---------------------------- 500// 64 Bit Register Classes 501// ---------------------------- 502// 64-bit build means 64-bit pointers means hi/lo pairs 503 504reg_class rscratch1_bits64_reg(R11_H, R11); 505reg_class rscratch2_bits64_reg(R12_H, R12); 506reg_class rarg1_bits64_reg(R3_H, R3); 507reg_class rarg2_bits64_reg(R4_H, R4); 508reg_class rarg3_bits64_reg(R5_H, R5); 509reg_class rarg4_bits64_reg(R6_H, R6); 510// Thread register, 'written' by tlsLoadP, see there. 511reg_class thread_bits64_reg(R16_H, R16); 512 513reg_class r19_bits64_reg(R19_H, R19); 514 515// 64 bit registers that can be read and written i.e. these registers 516// can be dest (or src) of normal instructions. 517reg_class bits64_reg_rw( 518/*R0_H, R0*/ // R0 519/*R1_H, R1*/ // SP 520 R2_H, R2, // TOC 521 R3_H, R3, 522 R4_H, R4, 523 R5_H, R5, 524 R6_H, R6, 525 R7_H, R7, 526 R8_H, R8, 527 R9_H, R9, 528 R10_H, R10, 529 R11_H, R11, 530 R12_H, R12, 531/*R13_H, R13*/ // system thread id 532 R14_H, R14, 533 R15_H, R15, 534/*R16_H, R16*/ // R16_thread 535 R17_H, R17, 536 R18_H, R18, 537 R19_H, R19, 538 R20_H, R20, 539 R21_H, R21, 540 R22_H, R22, 541 R23_H, R23, 542 R24_H, R24, 543 R25_H, R25, 544 R26_H, R26, 545 R27_H, R27, 546 R28_H, R28, 547/*R29_H, R29,*/ 548 R30_H, R30, 549 R31_H, R31 550); 551 552// 64 bit registers used excluding r2, r11 and r12 553// Used to hold the TOC to avoid collisions with expanded LeafCall which uses 554// r2, r11 and r12 internally. 555reg_class bits64_reg_leaf_call( 556/*R0_H, R0*/ // R0 557/*R1_H, R1*/ // SP 558/*R2_H, R2*/ // TOC 559 R3_H, R3, 560 R4_H, R4, 561 R5_H, R5, 562 R6_H, R6, 563 R7_H, R7, 564 R8_H, R8, 565 R9_H, R9, 566 R10_H, R10, 567/*R11_H, R11*/ 568/*R12_H, R12*/ 569/*R13_H, R13*/ // system thread id 570 R14_H, R14, 571 R15_H, R15, 572/*R16_H, R16*/ // R16_thread 573 R17_H, R17, 574 R18_H, R18, 575 R19_H, R19, 576 R20_H, R20, 577 R21_H, R21, 578 R22_H, R22, 579 R23_H, R23, 580 R24_H, R24, 581 R25_H, R25, 582 R26_H, R26, 583 R27_H, R27, 584 R28_H, R28, 585/*R29_H, R29,*/ 586 R30_H, R30, 587 R31_H, R31 588); 589 590// Used to hold the TOC to avoid collisions with expanded DynamicCall 591// which uses r19 as inline cache internally and expanded LeafCall which uses 592// r2, r11 and r12 internally. 593reg_class bits64_constant_table_base( 594/*R0_H, R0*/ // R0 595/*R1_H, R1*/ // SP 596/*R2_H, R2*/ // TOC 597 R3_H, R3, 598 R4_H, R4, 599 R5_H, R5, 600 R6_H, R6, 601 R7_H, R7, 602 R8_H, R8, 603 R9_H, R9, 604 R10_H, R10, 605/*R11_H, R11*/ 606/*R12_H, R12*/ 607/*R13_H, R13*/ // system thread id 608 R14_H, R14, 609 R15_H, R15, 610/*R16_H, R16*/ // R16_thread 611 R17_H, R17, 612 R18_H, R18, 613/*R19_H, R19*/ 614 R20_H, R20, 615 R21_H, R21, 616 R22_H, R22, 617 R23_H, R23, 618 R24_H, R24, 619 R25_H, R25, 620 R26_H, R26, 621 R27_H, R27, 622 R28_H, R28, 623/*R29_H, R29,*/ 624 R30_H, R30, 625 R31_H, R31 626); 627 628// 64 bit registers that can only be read i.e. these registers can 629// only be src of all instructions. 630reg_class bits64_reg_ro( 631/*R0_H, R0*/ // R0 632 R1_H, R1, 633 R2_H, R2, // TOC 634 R3_H, R3, 635 R4_H, R4, 636 R5_H, R5, 637 R6_H, R6, 638 R7_H, R7, 639 R8_H, R8, 640 R9_H, R9, 641 R10_H, R10, 642 R11_H, R11, 643 R12_H, R12, 644/*R13_H, R13*/ // system thread id 645 R14_H, R14, 646 R15_H, R15, 647 R16_H, R16, // R16_thread 648 R17_H, R17, 649 R18_H, R18, 650 R19_H, R19, 651 R20_H, R20, 652 R21_H, R21, 653 R22_H, R22, 654 R23_H, R23, 655 R24_H, R24, 656 R25_H, R25, 657 R26_H, R26, 658 R27_H, R27, 659 R28_H, R28, 660/*R29_H, R29,*/ // TODO: let allocator handle TOC!! 661 R30_H, R30, 662 R31_H, R31 663); 664 665 666// ---------------------------- 667// Special Class for Condition Code Flags Register 668 669reg_class int_flags( 670/*CCR0*/ // scratch 671/*CCR1*/ // scratch 672/*CCR2*/ // nv! 673/*CCR3*/ // nv! 674/*CCR4*/ // nv! 675 CCR5, 676 CCR6, 677 CCR7 678); 679 680reg_class int_flags_ro( 681 CCR0, 682 CCR1, 683 CCR2, 684 CCR3, 685 CCR4, 686 CCR5, 687 CCR6, 688 CCR7 689); 690 691reg_class int_flags_CR0(CCR0); 692reg_class int_flags_CR1(CCR1); 693reg_class int_flags_CR6(CCR6); 694reg_class ctr_reg(SR_CTR); 695 696// ---------------------------- 697// Float Register Classes 698// ---------------------------- 699 700reg_class flt_reg( 701 F0, 702 F1, 703 F2, 704 F3, 705 F4, 706 F5, 707 F6, 708 F7, 709 F8, 710 F9, 711 F10, 712 F11, 713 F12, 714 F13, 715 F14, // nv! 716 F15, // nv! 717 F16, // nv! 718 F17, // nv! 719 F18, // nv! 720 F19, // nv! 721 F20, // nv! 722 F21, // nv! 723 F22, // nv! 724 F23, // nv! 725 F24, // nv! 726 F25, // nv! 727 F26, // nv! 728 F27, // nv! 729 F28, // nv! 730 F29, // nv! 731 F30, // nv! 732 F31 // nv! 733); 734 735// Double precision float registers have virtual `high halves' that 736// are needed by the allocator. 737reg_class dbl_reg( 738 F0, F0_H, 739 F1, F1_H, 740 F2, F2_H, 741 F3, F3_H, 742 F4, F4_H, 743 F5, F5_H, 744 F6, F6_H, 745 F7, F7_H, 746 F8, F8_H, 747 F9, F9_H, 748 F10, F10_H, 749 F11, F11_H, 750 F12, F12_H, 751 F13, F13_H, 752 F14, F14_H, // nv! 753 F15, F15_H, // nv! 754 F16, F16_H, // nv! 755 F17, F17_H, // nv! 756 F18, F18_H, // nv! 757 F19, F19_H, // nv! 758 F20, F20_H, // nv! 759 F21, F21_H, // nv! 760 F22, F22_H, // nv! 761 F23, F23_H, // nv! 762 F24, F24_H, // nv! 763 F25, F25_H, // nv! 764 F26, F26_H, // nv! 765 F27, F27_H, // nv! 766 F28, F28_H, // nv! 767 F29, F29_H, // nv! 768 F30, F30_H, // nv! 769 F31, F31_H // nv! 770); 771 772 %} 773 774//----------DEFINITION BLOCK--------------------------------------------------- 775// Define name --> value mappings to inform the ADLC of an integer valued name 776// Current support includes integer values in the range [0, 0x7FFFFFFF] 777// Format: 778// int_def <name> ( <int_value>, <expression>); 779// Generated Code in ad_<arch>.hpp 780// #define <name> (<expression>) 781// // value == <int_value> 782// Generated code in ad_<arch>.cpp adlc_verification() 783// assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 784// 785definitions %{ 786 // The default cost (of an ALU instruction). 787 int_def DEFAULT_COST_LOW ( 30, 30); 788 int_def DEFAULT_COST ( 100, 100); 789 int_def HUGE_COST (1000000, 1000000); 790 791 // Memory refs 792 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2); 793 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3); 794 795 // Branches are even more expensive. 796 int_def BRANCH_COST ( 900, DEFAULT_COST * 9); 797 int_def CALL_COST ( 1300, DEFAULT_COST * 13); 798%} 799 800 801//----------SOURCE BLOCK------------------------------------------------------- 802// This is a block of C++ code which provides values, functions, and 803// definitions necessary in the rest of the architecture description. 804source_hpp %{ 805 // Header information of the source block. 806 // Method declarations/definitions which are used outside 807 // the ad-scope can conveniently be defined here. 808 // 809 // To keep related declarations/definitions/uses close together, 810 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 811 812 // Returns true if Node n is followed by a MemBar node that 813 // will do an acquire. If so, this node must not do the acquire 814 // operation. 815 bool followed_by_acquire(const Node *n); 816%} 817 818source %{ 819 820// Optimize load-acquire. 821// 822// Check if acquire is unnecessary due to following operation that does 823// acquire anyways. 824// Walk the pattern: 825// 826// n: Load.acq 827// | 828// MemBarAcquire 829// | | 830// Proj(ctrl) Proj(mem) 831// | | 832// MemBarRelease/Volatile 833// 834bool followed_by_acquire(const Node *load) { 835 assert(load->is_Load(), "So far implemented only for loads."); 836 837 // Find MemBarAcquire. 838 const Node *mba = NULL; 839 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) { 840 const Node *out = load->fast_out(i); 841 if (out->Opcode() == Op_MemBarAcquire) { 842 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge. 843 mba = out; 844 break; 845 } 846 } 847 if (!mba) return false; 848 849 // Find following MemBar node. 850 // 851 // The following node must be reachable by control AND memory 852 // edge to assure no other operations are in between the two nodes. 853 // 854 // So first get the Proj node, mem_proj, to use it to iterate forward. 855 Node *mem_proj = NULL; 856 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) { 857 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found 858 assert(mem_proj->is_Proj(), "only projections here"); 859 ProjNode *proj = mem_proj->as_Proj(); 860 if (proj->_con == TypeFunc::Memory && 861 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only 862 break; 863 } 864 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken"); 865 866 // Search MemBar behind Proj. If there are other memory operations 867 // behind the Proj we lost. 868 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) { 869 Node *x = mem_proj->fast_out(j); 870 // Proj might have an edge to a store or load node which precedes the membar. 871 if (x->is_Mem()) return false; 872 873 // On PPC64 release and volatile are implemented by an instruction 874 // that also has acquire semantics. I.e. there is no need for an 875 // acquire before these. 876 int xop = x->Opcode(); 877 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) { 878 // Make sure we're not missing Call/Phi/MergeMem by checking 879 // control edges. The control edge must directly lead back 880 // to the MemBarAcquire 881 Node *ctrl_proj = x->in(0); 882 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) { 883 return true; 884 } 885 } 886 } 887 888 return false; 889} 890 891#define __ _masm. 892 893// Tertiary op of a LoadP or StoreP encoding. 894#define REGP_OP true 895 896// **************************************************************************** 897 898// REQUIRED FUNCTIONALITY 899 900// !!!!! Special hack to get all type of calls to specify the byte offset 901// from the start of the call to the point where the return address 902// will point. 903 904// PPC port: Removed use of lazy constant construct. 905 906int MachCallStaticJavaNode::ret_addr_offset() { 907 // It's only a single branch-and-link instruction. 908 return 4; 909} 910 911int MachCallDynamicJavaNode::ret_addr_offset() { 912 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use 913 // postalloc expanded calls if we use inline caches and do not update method data. 914 if (UseInlineCaches) 915 return 4; 916 917 int vtable_index = this->_vtable_index; 918 if (vtable_index < 0) { 919 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 920 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 921 return 12; 922 } else { 923 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 924 return 24; 925 } 926} 927 928int MachCallRuntimeNode::ret_addr_offset() { 929#if defined(ABI_ELFv2) 930 return 28; 931#else 932 return 40; 933#endif 934} 935 936//============================================================================= 937 938// condition code conversions 939 940static int cc_to_boint(int cc) { 941 return Assembler::bcondCRbiIs0 | (cc & 8); 942} 943 944static int cc_to_inverse_boint(int cc) { 945 return Assembler::bcondCRbiIs0 | (8-(cc & 8)); 946} 947 948static int cc_to_biint(int cc, int flags_reg) { 949 return (flags_reg << 2) | (cc & 3); 950} 951 952//============================================================================= 953 954// Compute padding required for nodes which need alignment. The padding 955// is the number of bytes (not instructions) which will be inserted before 956// the instruction. The padding must match the size of a NOP instruction. 957 958int string_indexOf_imm1_charNode::compute_padding(int current_offset) const { 959 return (3*4-current_offset)&31; // see MacroAssembler::string_indexof_1 960} 961 962int string_indexOf_imm1Node::compute_padding(int current_offset) const { 963 return (3*4-current_offset)&31; // see MacroAssembler::string_indexof_1 964} 965 966int string_indexOfCharNode::compute_padding(int current_offset) const { 967 return (3*4-current_offset)&31; // see MacroAssembler::string_indexof_1 968} 969 970int string_indexOf_immNode::compute_padding(int current_offset) const { 971 return (3*4-current_offset)&31; // see MacroAssembler::string_indexof(constant needlecount) 972} 973 974int string_indexOfNode::compute_padding(int current_offset) const { 975 return (1*4-current_offset)&31; // see MacroAssembler::string_indexof(variable needlecount) 976} 977 978int string_compareNode::compute_padding(int current_offset) const { 979 return (2*4-current_offset)&31; // see MacroAssembler::string_compare 980} 981 982int string_equals_immNode::compute_padding(int current_offset) const { 983 if (opnd_array(3)->constant() < 16) return 0; // For strlen < 16 no nops because loop completely unrolled 984 return (2*4-current_offset)&31; // Genral case - see MacroAssembler::char_arrays_equalsImm 985} 986 987int string_equalsNode::compute_padding(int current_offset) const { 988 return (7*4-current_offset)&31; // see MacroAssembler::char_arrays_equals 989} 990 991int inlineCallClearArrayNode::compute_padding(int current_offset) const { 992 return (2*4-current_offset)&31; // see MacroAssembler::clear_memory_doubleword 993} 994 995//============================================================================= 996 997// Indicate if the safepoint node needs the polling page as an input. 998bool SafePointNode::needs_polling_address_input() { 999 // The address is loaded from thread by a seperate node. 1000 return true; 1001} 1002 1003//============================================================================= 1004 1005// Emit an interrupt that is caught by the debugger (for debugging compiler). 1006void emit_break(CodeBuffer &cbuf) { 1007 MacroAssembler _masm(&cbuf); 1008 __ illtrap(); 1009} 1010 1011#ifndef PRODUCT 1012void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1013 st->print("BREAKPOINT"); 1014} 1015#endif 1016 1017void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1018 emit_break(cbuf); 1019} 1020 1021uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 1022 return MachNode::size(ra_); 1023} 1024 1025//============================================================================= 1026 1027void emit_nop(CodeBuffer &cbuf) { 1028 MacroAssembler _masm(&cbuf); 1029 __ nop(); 1030} 1031 1032static inline void emit_long(CodeBuffer &cbuf, int value) { 1033 *((int*)(cbuf.insts_end())) = value; 1034 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord); 1035} 1036 1037//============================================================================= 1038 1039%} // interrupt source 1040 1041source_hpp %{ // Header information of the source block. 1042 1043//-------------------------------------------------------------- 1044//---< Used for optimization in Compile::Shorten_branches >--- 1045//-------------------------------------------------------------- 1046 1047class CallStubImpl { 1048 1049 public: 1050 1051 // Emit call stub, compiled java to interpreter. 1052 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset); 1053 1054 // Size of call trampoline stub. 1055 // This doesn't need to be accurate to the byte, but it 1056 // must be larger than or equal to the real size of the stub. 1057 static uint size_call_trampoline() { 1058 return MacroAssembler::trampoline_stub_size; 1059 } 1060 1061 // number of relocations needed by a call trampoline stub 1062 static uint reloc_call_trampoline() { 1063 return 5; 1064 } 1065 1066}; 1067 1068%} // end source_hpp 1069 1070source %{ 1071 1072// Emit a trampoline stub for a call to a target which is too far away. 1073// 1074// code sequences: 1075// 1076// call-site: 1077// branch-and-link to <destination> or <trampoline stub> 1078// 1079// Related trampoline stub for this call-site in the stub section: 1080// load the call target from the constant pool 1081// branch via CTR (LR/link still points to the call-site above) 1082 1083void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) { 1084 address stub = __ emit_trampoline_stub(destination_toc_offset, insts_call_instruction_offset); 1085 if (stub == NULL) { 1086 ciEnv::current()->record_out_of_memory_failure(); 1087 } 1088} 1089 1090//============================================================================= 1091 1092// Emit an inline branch-and-link call and a related trampoline stub. 1093// 1094// code sequences: 1095// 1096// call-site: 1097// branch-and-link to <destination> or <trampoline stub> 1098// 1099// Related trampoline stub for this call-site in the stub section: 1100// load the call target from the constant pool 1101// branch via CTR (LR/link still points to the call-site above) 1102// 1103 1104typedef struct { 1105 int insts_call_instruction_offset; 1106 int ret_addr_offset; 1107} EmitCallOffsets; 1108 1109// Emit a branch-and-link instruction that branches to a trampoline. 1110// - Remember the offset of the branch-and-link instruction. 1111// - Add a relocation at the branch-and-link instruction. 1112// - Emit a branch-and-link. 1113// - Remember the return pc offset. 1114EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) { 1115 EmitCallOffsets offsets = { -1, -1 }; 1116 const int start_offset = __ offset(); 1117 offsets.insts_call_instruction_offset = __ offset(); 1118 1119 // No entry point given, use the current pc. 1120 if (entry_point == NULL) entry_point = __ pc(); 1121 1122 if (!Compile::current()->in_scratch_emit_size()) { 1123 // Put the entry point as a constant into the constant pool. 1124 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 1125 if (entry_point_toc_addr == NULL) { 1126 ciEnv::current()->record_out_of_memory_failure(); 1127 return offsets; 1128 } 1129 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 1130 1131 // Emit the trampoline stub which will be related to the branch-and-link below. 1132 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset); 1133 if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full. 1134 __ relocate(rtype); 1135 } 1136 1137 // Note: At this point we do not have the address of the trampoline 1138 // stub, and the entry point might be too far away for bl, so __ pc() 1139 // serves as dummy and the bl will be patched later. 1140 __ bl((address) __ pc()); 1141 1142 offsets.ret_addr_offset = __ offset() - start_offset; 1143 1144 return offsets; 1145} 1146 1147//============================================================================= 1148 1149// Factory for creating loadConL* nodes for large/small constant pool. 1150 1151static inline jlong replicate_immF(float con) { 1152 // Replicate float con 2 times and pack into vector. 1153 int val = *((int*)&con); 1154 jlong lval = val; 1155 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 1156 return lval; 1157} 1158 1159//============================================================================= 1160 1161const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask(); 1162int Compile::ConstantTable::calculate_table_base_offset() const { 1163 return 0; // absolute addressing, no offset 1164} 1165 1166bool MachConstantBaseNode::requires_postalloc_expand() const { return true; } 1167void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1168 iRegPdstOper *op_dst = new iRegPdstOper(); 1169 MachNode *m1 = new loadToc_hiNode(); 1170 MachNode *m2 = new loadToc_loNode(); 1171 1172 m1->add_req(NULL); 1173 m2->add_req(NULL, m1); 1174 m1->_opnds[0] = op_dst; 1175 m2->_opnds[0] = op_dst; 1176 m2->_opnds[1] = op_dst; 1177 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 1178 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 1179 nodes->push(m1); 1180 nodes->push(m2); 1181} 1182 1183void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1184 // Is postalloc expanded. 1185 ShouldNotReachHere(); 1186} 1187 1188uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 1189 return 0; 1190} 1191 1192#ifndef PRODUCT 1193void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1194 st->print("-- \t// MachConstantBaseNode (empty encoding)"); 1195} 1196#endif 1197 1198//============================================================================= 1199 1200#ifndef PRODUCT 1201void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1202 Compile* C = ra_->C; 1203 const long framesize = C->frame_slots() << LogBytesPerInt; 1204 1205 st->print("PROLOG\n\t"); 1206 if (C->need_stack_bang(framesize)) { 1207 st->print("stack_overflow_check\n\t"); 1208 } 1209 1210 if (!false /* TODO: PPC port C->is_frameless_method()*/) { 1211 st->print("save return pc\n\t"); 1212 st->print("push frame %ld\n\t", -framesize); 1213 } 1214} 1215#endif 1216 1217// Macro used instead of the common __ to emulate the pipes of PPC. 1218// Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the 1219// micro scheduler to cope with "hand written" assembler like in the prolog. Though 1220// still no scheduling of this code is possible, the micro scheduler is aware of the 1221// code and can update its internal data. The following mechanism is used to achieve this: 1222// The micro scheduler calls size() of each compound node during scheduling. size() does a 1223// dummy emit and only during this dummy emit C->hb_scheduling() is not NULL. 1224#if 0 // TODO: PPC port 1225#define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1226 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \ 1227 _masm. 1228#define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1229 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none) 1230#define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1231 C->hb_scheduling()->_pdScheduling->advance_offset 1232#else 1233#define ___(op) if (UsePower6SchedulerPPC64) \ 1234 Unimplemented(); \ 1235 _masm. 1236#define ___stop if (UsePower6SchedulerPPC64) \ 1237 Unimplemented() 1238#define ___advance if (UsePower6SchedulerPPC64) \ 1239 Unimplemented() 1240#endif 1241 1242void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1243 Compile* C = ra_->C; 1244 MacroAssembler _masm(&cbuf); 1245 1246 const long framesize = C->frame_size_in_bytes(); 1247 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment"); 1248 1249 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; 1250 1251 const Register return_pc = R20; // Must match return_addr() in frame section. 1252 const Register callers_sp = R21; 1253 const Register push_frame_temp = R22; 1254 const Register toc_temp = R23; 1255 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp); 1256 1257 if (method_is_frameless) { 1258 // Add nop at beginning of all frameless methods to prevent any 1259 // oop instructions from getting overwritten by make_not_entrant 1260 // (patching attempt would fail). 1261 ___(nop) nop(); 1262 } else { 1263 // Get return pc. 1264 ___(mflr) mflr(return_pc); 1265 } 1266 1267 // Calls to C2R adapters often do not accept exceptional returns. 1268 // We require that their callers must bang for them. But be 1269 // careful, because some VM calls (such as call site linkage) can 1270 // use several kilobytes of stack. But the stack safety zone should 1271 // account for that. See bugs 4446381, 4468289, 4497237. 1272 1273 int bangsize = C->bang_size_in_bytes(); 1274 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect"); 1275 if (C->need_stack_bang(bangsize) && UseStackBanging) { 1276 // Unfortunately we cannot use the function provided in 1277 // assembler.cpp as we have to emulate the pipes. So I had to 1278 // insert the code of generate_stack_overflow_check(), see 1279 // assembler.cpp for some illuminative comments. 1280 const int page_size = os::vm_page_size(); 1281 int bang_end = JavaThread::stack_shadow_zone_size(); 1282 1283 // This is how far the previous frame's stack banging extended. 1284 const int bang_end_safe = bang_end; 1285 1286 if (bangsize > page_size) { 1287 bang_end += bangsize; 1288 } 1289 1290 int bang_offset = bang_end_safe; 1291 1292 while (bang_offset <= bang_end) { 1293 // Need at least one stack bang at end of shadow zone. 1294 1295 // Again I had to copy code, this time from assembler_ppc.cpp, 1296 // bang_stack_with_offset - see there for comments. 1297 1298 // Stack grows down, caller passes positive offset. 1299 assert(bang_offset > 0, "must bang with positive offset"); 1300 1301 long stdoffset = -bang_offset; 1302 1303 if (Assembler::is_simm(stdoffset, 16)) { 1304 // Signed 16 bit offset, a simple std is ok. 1305 if (UseLoadInstructionsForStackBangingPPC64) { 1306 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP); 1307 } else { 1308 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP); 1309 } 1310 } else if (Assembler::is_simm(stdoffset, 31)) { 1311 // Use largeoffset calculations for addis & ld/std. 1312 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset); 1313 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset); 1314 1315 Register tmp = R11; 1316 ___(addis) addis(tmp, R1_SP, hi); 1317 if (UseLoadInstructionsForStackBangingPPC64) { 1318 ___(ld) ld(R0, lo, tmp); 1319 } else { 1320 ___(std) std(R0, lo, tmp); 1321 } 1322 } else { 1323 ShouldNotReachHere(); 1324 } 1325 1326 bang_offset += page_size; 1327 } 1328 // R11 trashed 1329 } // C->need_stack_bang(framesize) && UseStackBanging 1330 1331 unsigned int bytes = (unsigned int)framesize; 1332 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); 1333 ciMethod *currMethod = C->method(); 1334 1335 // Optimized version for most common case. 1336 if (UsePower6SchedulerPPC64 && 1337 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) && 1338 !(false /* ConstantsALot TODO: PPC port*/)) { 1339 ___(or) mr(callers_sp, R1_SP); 1340 ___(std) std(return_pc, _abi(lr), R1_SP); 1341 ___(stdu) stdu(R1_SP, -offset, R1_SP); 1342 return; 1343 } 1344 1345 if (!method_is_frameless) { 1346 // Get callers sp. 1347 ___(or) mr(callers_sp, R1_SP); 1348 1349 // Push method's frame, modifies SP. 1350 assert(Assembler::is_uimm(framesize, 32U), "wrong type"); 1351 // The ABI is already accounted for in 'framesize' via the 1352 // 'out_preserve' area. 1353 Register tmp = push_frame_temp; 1354 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp). 1355 if (Assembler::is_simm(-offset, 16)) { 1356 ___(stdu) stdu(R1_SP, -offset, R1_SP); 1357 } else { 1358 long x = -offset; 1359 // Had to insert load_const(tmp, -offset). 1360 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16))); 1361 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff)); 1362 ___(rldicr) sldi(tmp, tmp, 32); 1363 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16); 1364 ___(ori) ori( tmp, tmp, (x & 0x0000ffff)); 1365 1366 ___(stdux) stdux(R1_SP, R1_SP, tmp); 1367 } 1368 } 1369#if 0 // TODO: PPC port 1370 // For testing large constant pools, emit a lot of constants to constant pool. 1371 // "Randomize" const_size. 1372 if (ConstantsALot) { 1373 const int num_consts = const_size(); 1374 for (int i = 0; i < num_consts; i++) { 1375 __ long_constant(0xB0B5B00BBABE); 1376 } 1377 } 1378#endif 1379 if (!method_is_frameless) { 1380 // Save return pc. 1381 ___(std) std(return_pc, _abi(lr), callers_sp); 1382 } 1383} 1384#undef ___ 1385#undef ___stop 1386#undef ___advance 1387 1388uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1389 // Variable size. determine dynamically. 1390 return MachNode::size(ra_); 1391} 1392 1393int MachPrologNode::reloc() const { 1394 // Return number of relocatable values contained in this instruction. 1395 return 1; // 1 reloc entry for load_const(toc). 1396} 1397 1398//============================================================================= 1399 1400#ifndef PRODUCT 1401void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1402 Compile* C = ra_->C; 1403 1404 st->print("EPILOG\n\t"); 1405 st->print("restore return pc\n\t"); 1406 st->print("pop frame\n\t"); 1407 1408 if (do_polling() && C->is_method_compilation()) { 1409 st->print("touch polling page\n\t"); 1410 } 1411} 1412#endif 1413 1414void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1415 Compile* C = ra_->C; 1416 MacroAssembler _masm(&cbuf); 1417 1418 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt; 1419 assert(framesize >= 0, "negative frame-size?"); 1420 1421 const bool method_needs_polling = do_polling() && C->is_method_compilation(); 1422 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; 1423 const Register return_pc = R11; 1424 const Register polling_page = R12; 1425 1426 if (!method_is_frameless) { 1427 // Restore return pc relative to callers' sp. 1428 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP); 1429 } 1430 1431 if (method_needs_polling) { 1432 if (LoadPollAddressFromThread) { 1433 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread); 1434 Unimplemented(); 1435 } else { 1436 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page() 1437 } 1438 } 1439 1440 if (!method_is_frameless) { 1441 // Move return pc to LR. 1442 __ mtlr(return_pc); 1443 // Pop frame (fixed frame-size). 1444 __ addi(R1_SP, R1_SP, (int)framesize); 1445 } 1446 1447 if (method_needs_polling) { 1448 // We need to mark the code position where the load from the safepoint 1449 // polling page was emitted as relocInfo::poll_return_type here. 1450 __ relocate(relocInfo::poll_return_type); 1451 __ load_from_polling_page(polling_page); 1452 } 1453} 1454 1455uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1456 // Variable size. Determine dynamically. 1457 return MachNode::size(ra_); 1458} 1459 1460int MachEpilogNode::reloc() const { 1461 // Return number of relocatable values contained in this instruction. 1462 return 1; // 1 for load_from_polling_page. 1463} 1464 1465const Pipeline * MachEpilogNode::pipeline() const { 1466 return MachNode::pipeline_class(); 1467} 1468 1469// This method seems to be obsolete. It is declared in machnode.hpp 1470// and defined in all *.ad files, but it is never called. Should we 1471// get rid of it? 1472int MachEpilogNode::safepoint_offset() const { 1473 assert(do_polling(), "no return for this epilog node"); 1474 return 0; 1475} 1476 1477#if 0 // TODO: PPC port 1478void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1479 MacroAssembler _masm(&cbuf); 1480 if (LoadPollAddressFromThread) { 1481 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread); 1482 } else { 1483 _masm.nop(); 1484 } 1485} 1486 1487uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const { 1488 if (LoadPollAddressFromThread) { 1489 return 4; 1490 } else { 1491 return 4; 1492 } 1493} 1494 1495#ifndef PRODUCT 1496void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1497 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread"); 1498} 1499#endif 1500 1501const RegMask &MachLoadPollAddrLateNode::out_RegMask() const { 1502 return RSCRATCH1_BITS64_REG_mask(); 1503} 1504#endif // PPC port 1505 1506// ============================================================================= 1507 1508// Figure out which register class each belongs in: rc_int, rc_float or 1509// rc_stack. 1510enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1511 1512static enum RC rc_class(OptoReg::Name reg) { 1513 // Return the register class for the given register. The given register 1514 // reg is a <register>_num value, which is an index into the MachRegisterNumbers 1515 // enumeration in adGlobals_ppc.hpp. 1516 1517 if (reg == OptoReg::Bad) return rc_bad; 1518 1519 // We have 64 integer register halves, starting at index 0. 1520 if (reg < 64) return rc_int; 1521 1522 // We have 64 floating-point register halves, starting at index 64. 1523 if (reg < 64+64) return rc_float; 1524 1525 // Between float regs & stack are the flags regs. 1526 assert(OptoReg::is_stack(reg), "blow up if spilling flags"); 1527 1528 return rc_stack; 1529} 1530 1531static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset, 1532 bool do_print, Compile* C, outputStream *st) { 1533 1534 assert(opcode == Assembler::LD_OPCODE || 1535 opcode == Assembler::STD_OPCODE || 1536 opcode == Assembler::LWZ_OPCODE || 1537 opcode == Assembler::STW_OPCODE || 1538 opcode == Assembler::LFD_OPCODE || 1539 opcode == Assembler::STFD_OPCODE || 1540 opcode == Assembler::LFS_OPCODE || 1541 opcode == Assembler::STFS_OPCODE, 1542 "opcode not supported"); 1543 1544 if (cbuf) { 1545 int d = 1546 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ? 1547 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/) 1548 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build. 1549 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP)); 1550 } 1551#ifndef PRODUCT 1552 else if (do_print) { 1553 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy", 1554 op_str, 1555 Matcher::regName[reg], 1556 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); 1557 } 1558#endif 1559 return 4; // size 1560} 1561 1562uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const { 1563 Compile* C = ra_->C; 1564 1565 // Get registers to move. 1566 OptoReg::Name src_hi = ra_->get_reg_second(in(1)); 1567 OptoReg::Name src_lo = ra_->get_reg_first(in(1)); 1568 OptoReg::Name dst_hi = ra_->get_reg_second(this); 1569 OptoReg::Name dst_lo = ra_->get_reg_first(this); 1570 1571 enum RC src_hi_rc = rc_class(src_hi); 1572 enum RC src_lo_rc = rc_class(src_lo); 1573 enum RC dst_hi_rc = rc_class(dst_hi); 1574 enum RC dst_lo_rc = rc_class(dst_lo); 1575 1576 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); 1577 if (src_hi != OptoReg::Bad) 1578 assert((src_lo&1)==0 && src_lo+1==src_hi && 1579 (dst_lo&1)==0 && dst_lo+1==dst_hi, 1580 "expected aligned-adjacent pairs"); 1581 // Generate spill code! 1582 int size = 0; 1583 1584 if (src_lo == dst_lo && src_hi == dst_hi) 1585 return size; // Self copy, no move. 1586 1587 // -------------------------------------- 1588 // Memory->Memory Spill. Use R0 to hold the value. 1589 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1590 int src_offset = ra_->reg2offset(src_lo); 1591 int dst_offset = ra_->reg2offset(dst_lo); 1592 if (src_hi != OptoReg::Bad) { 1593 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack, 1594 "expected same type of move for high parts"); 1595 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st); 1596 if (!cbuf && !do_size) st->print("\n\t"); 1597 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st); 1598 } else { 1599 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st); 1600 if (!cbuf && !do_size) st->print("\n\t"); 1601 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st); 1602 } 1603 return size; 1604 } 1605 1606 // -------------------------------------- 1607 // Check for float->int copy; requires a trip through memory. 1608 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1609 Unimplemented(); 1610 } 1611 1612 // -------------------------------------- 1613 // Check for integer reg-reg copy. 1614 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1615 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1616 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1617 size = (Rsrc != Rdst) ? 4 : 0; 1618 1619 if (cbuf) { 1620 MacroAssembler _masm(cbuf); 1621 if (size) { 1622 __ mr(Rdst, Rsrc); 1623 } 1624 } 1625#ifndef PRODUCT 1626 else if (!do_size) { 1627 if (size) { 1628 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1629 } else { 1630 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1631 } 1632 } 1633#endif 1634 return size; 1635 } 1636 1637 // Check for integer store. 1638 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1639 int dst_offset = ra_->reg2offset(dst_lo); 1640 if (src_hi != OptoReg::Bad) { 1641 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack, 1642 "expected same type of move for high parts"); 1643 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st); 1644 } else { 1645 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st); 1646 } 1647 return size; 1648 } 1649 1650 // Check for integer load. 1651 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1652 int src_offset = ra_->reg2offset(src_lo); 1653 if (src_hi != OptoReg::Bad) { 1654 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack, 1655 "expected same type of move for high parts"); 1656 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st); 1657 } else { 1658 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st); 1659 } 1660 return size; 1661 } 1662 1663 // Check for float reg-reg copy. 1664 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1665 if (cbuf) { 1666 MacroAssembler _masm(cbuf); 1667 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); 1668 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); 1669 __ fmr(Rdst, Rsrc); 1670 } 1671#ifndef PRODUCT 1672 else if (!do_size) { 1673 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1674 } 1675#endif 1676 return 4; 1677 } 1678 1679 // Check for float store. 1680 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1681 int dst_offset = ra_->reg2offset(dst_lo); 1682 if (src_hi != OptoReg::Bad) { 1683 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack, 1684 "expected same type of move for high parts"); 1685 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st); 1686 } else { 1687 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st); 1688 } 1689 return size; 1690 } 1691 1692 // Check for float load. 1693 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1694 int src_offset = ra_->reg2offset(src_lo); 1695 if (src_hi != OptoReg::Bad) { 1696 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack, 1697 "expected same type of move for high parts"); 1698 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st); 1699 } else { 1700 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st); 1701 } 1702 return size; 1703 } 1704 1705 // -------------------------------------------------------------------- 1706 // Check for hi bits still needing moving. Only happens for misaligned 1707 // arguments to native calls. 1708 if (src_hi == dst_hi) 1709 return size; // Self copy; no move. 1710 1711 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); 1712 ShouldNotReachHere(); // Unimplemented 1713 return 0; 1714} 1715 1716#ifndef PRODUCT 1717void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1718 if (!ra_) 1719 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx); 1720 else 1721 implementation(NULL, ra_, false, st); 1722} 1723#endif 1724 1725void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1726 implementation(&cbuf, ra_, false, NULL); 1727} 1728 1729uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1730 return implementation(NULL, ra_, true, NULL); 1731} 1732 1733#if 0 // TODO: PPC port 1734ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) { 1735#ifndef PRODUCT 1736 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined; 1737#endif 1738 assert(ra_->node_regs_max_index() != 0, ""); 1739 1740 // Get registers to move. 1741 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1)); 1742 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1)); 1743 OptoReg::Name dst_hi = ra_->get_reg_second(n); 1744 OptoReg::Name dst_lo = ra_->get_reg_first(n); 1745 1746 enum RC src_lo_rc = rc_class(src_lo); 1747 enum RC dst_lo_rc = rc_class(dst_lo); 1748 1749 if (src_lo == dst_lo && src_hi == dst_hi) 1750 return ppc64Opcode_none; // Self copy, no move. 1751 1752 // -------------------------------------- 1753 // Memory->Memory Spill. Use R0 to hold the value. 1754 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1755 return ppc64Opcode_compound; 1756 } 1757 1758 // -------------------------------------- 1759 // Check for float->int copy; requires a trip through memory. 1760 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1761 Unimplemented(); 1762 } 1763 1764 // -------------------------------------- 1765 // Check for integer reg-reg copy. 1766 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1767 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1768 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1769 if (Rsrc == Rdst) { 1770 return ppc64Opcode_none; 1771 } else { 1772 return ppc64Opcode_or; 1773 } 1774 } 1775 1776 // Check for integer store. 1777 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1778 if (src_hi != OptoReg::Bad) { 1779 return ppc64Opcode_std; 1780 } else { 1781 return ppc64Opcode_stw; 1782 } 1783 } 1784 1785 // Check for integer load. 1786 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1787 if (src_hi != OptoReg::Bad) { 1788 return ppc64Opcode_ld; 1789 } else { 1790 return ppc64Opcode_lwz; 1791 } 1792 } 1793 1794 // Check for float reg-reg copy. 1795 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1796 return ppc64Opcode_fmr; 1797 } 1798 1799 // Check for float store. 1800 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1801 if (src_hi != OptoReg::Bad) { 1802 return ppc64Opcode_stfd; 1803 } else { 1804 return ppc64Opcode_stfs; 1805 } 1806 } 1807 1808 // Check for float load. 1809 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1810 if (src_hi != OptoReg::Bad) { 1811 return ppc64Opcode_lfd; 1812 } else { 1813 return ppc64Opcode_lfs; 1814 } 1815 } 1816 1817 // -------------------------------------------------------------------- 1818 // Check for hi bits still needing moving. Only happens for misaligned 1819 // arguments to native calls. 1820 if (src_hi == dst_hi) { 1821 return ppc64Opcode_none; // Self copy; no move. 1822 } 1823 1824 ShouldNotReachHere(); 1825 return ppc64Opcode_undefined; 1826} 1827#endif // PPC port 1828 1829#ifndef PRODUCT 1830void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1831 st->print("NOP \t// %d nops to pad for loops.", _count); 1832} 1833#endif 1834 1835void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const { 1836 MacroAssembler _masm(&cbuf); 1837 // _count contains the number of nops needed for padding. 1838 for (int i = 0; i < _count; i++) { 1839 __ nop(); 1840 } 1841} 1842 1843uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1844 return _count * 4; 1845} 1846 1847#ifndef PRODUCT 1848void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1849 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1850 char reg_str[128]; 1851 ra_->dump_register(this, reg_str); 1852 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset); 1853} 1854#endif 1855 1856void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1857 MacroAssembler _masm(&cbuf); 1858 1859 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1860 int reg = ra_->get_encode(this); 1861 1862 if (Assembler::is_simm(offset, 16)) { 1863 __ addi(as_Register(reg), R1, offset); 1864 } else { 1865 ShouldNotReachHere(); 1866 } 1867} 1868 1869uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1870 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_). 1871 return 4; 1872} 1873 1874#ifndef PRODUCT 1875void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1876 st->print_cr("---- MachUEPNode ----"); 1877 st->print_cr("..."); 1878} 1879#endif 1880 1881void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1882 // This is the unverified entry point. 1883 MacroAssembler _masm(&cbuf); 1884 1885 // Inline_cache contains a klass. 1886 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); 1887 Register receiver_klass = R12_scratch2; // tmp 1888 1889 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1); 1890 assert(R11_scratch1 == R11, "need prologue scratch register"); 1891 1892 // Check for NULL argument if we don't have implicit null checks. 1893 if (!ImplicitNullChecks || !os::zero_page_read_protected()) { 1894 if (TrapBasedNullChecks) { 1895 __ trap_null_check(R3_ARG1); 1896 } else { 1897 Label valid; 1898 __ cmpdi(CCR0, R3_ARG1, 0); 1899 __ bne_predict_taken(CCR0, valid); 1900 // We have a null argument, branch to ic_miss_stub. 1901 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), 1902 relocInfo::runtime_call_type); 1903 __ bind(valid); 1904 } 1905 } 1906 // Assume argument is not NULL, load klass from receiver. 1907 __ load_klass(receiver_klass, R3_ARG1); 1908 1909 if (TrapBasedICMissChecks) { 1910 __ trap_ic_miss_check(receiver_klass, ic_klass); 1911 } else { 1912 Label valid; 1913 __ cmpd(CCR0, receiver_klass, ic_klass); 1914 __ beq_predict_taken(CCR0, valid); 1915 // We have an unexpected klass, branch to ic_miss_stub. 1916 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), 1917 relocInfo::runtime_call_type); 1918 __ bind(valid); 1919 } 1920 1921 // Argument is valid and klass is as expected, continue. 1922} 1923 1924#if 0 // TODO: PPC port 1925// Optimize UEP code on z (save a load_const() call in main path). 1926int MachUEPNode::ep_offset() { 1927 return 0; 1928} 1929#endif 1930 1931uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1932 // Variable size. Determine dynamically. 1933 return MachNode::size(ra_); 1934} 1935 1936//============================================================================= 1937 1938%} // interrupt source 1939 1940source_hpp %{ // Header information of the source block. 1941 1942class HandlerImpl { 1943 1944 public: 1945 1946 static int emit_exception_handler(CodeBuffer &cbuf); 1947 static int emit_deopt_handler(CodeBuffer& cbuf); 1948 1949 static uint size_exception_handler() { 1950 // The exception_handler is a b64_patchable. 1951 return MacroAssembler::b64_patchable_size; 1952 } 1953 1954 static uint size_deopt_handler() { 1955 // The deopt_handler is a bl64_patchable. 1956 return MacroAssembler::bl64_patchable_size; 1957 } 1958 1959}; 1960 1961%} // end source_hpp 1962 1963source %{ 1964 1965int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) { 1966 MacroAssembler _masm(&cbuf); 1967 1968 address base = __ start_a_stub(size_exception_handler()); 1969 if (base == NULL) return 0; // CodeBuffer::expand failed 1970 1971 int offset = __ offset(); 1972 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(), 1973 relocInfo::runtime_call_type); 1974 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size"); 1975 __ end_a_stub(); 1976 1977 return offset; 1978} 1979 1980// The deopt_handler is like the exception handler, but it calls to 1981// the deoptimization blob instead of jumping to the exception blob. 1982int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 1983 MacroAssembler _masm(&cbuf); 1984 1985 address base = __ start_a_stub(size_deopt_handler()); 1986 if (base == NULL) return 0; // CodeBuffer::expand failed 1987 1988 int offset = __ offset(); 1989 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(), 1990 relocInfo::runtime_call_type); 1991 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); 1992 __ end_a_stub(); 1993 1994 return offset; 1995} 1996 1997//============================================================================= 1998 1999// Use a frame slots bias for frameless methods if accessing the stack. 2000static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) { 2001 if (as_Register(reg_enc) == R1_SP) { 2002 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes(); 2003 } 2004 return 0; 2005} 2006 2007const bool Matcher::match_rule_supported(int opcode) { 2008 if (!has_match_rule(opcode)) 2009 return false; 2010 2011 switch (opcode) { 2012 case Op_SqrtD: 2013 return VM_Version::has_fsqrt(); 2014 case Op_CountLeadingZerosI: 2015 case Op_CountLeadingZerosL: 2016 case Op_CountTrailingZerosI: 2017 case Op_CountTrailingZerosL: 2018 if (!UseCountLeadingZerosInstructionsPPC64) 2019 return false; 2020 break; 2021 2022 case Op_PopCountI: 2023 case Op_PopCountL: 2024 return (UsePopCountInstruction && VM_Version::has_popcntw()); 2025 2026 case Op_StrComp: 2027 return SpecialStringCompareTo && !CompactStrings; 2028 case Op_StrEquals: 2029 return SpecialStringEquals && !CompactStrings; 2030 case Op_StrIndexOf: 2031 return SpecialStringIndexOf && !CompactStrings; 2032 case Op_StrIndexOfChar: 2033 return SpecialStringIndexOf && !CompactStrings; 2034 } 2035 2036 return true; // Per default match rules are supported. 2037} 2038 2039const bool Matcher::match_rule_supported_vector(int opcode, int vlen) { 2040 2041 // TODO 2042 // identify extra cases that we might want to provide match rules for 2043 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen 2044 bool ret_value = match_rule_supported(opcode); 2045 // Add rules here. 2046 2047 return ret_value; // Per default match rules are supported. 2048} 2049 2050const int Matcher::float_pressure(int default_pressure_threshold) { 2051 return default_pressure_threshold; 2052} 2053 2054int Matcher::regnum_to_fpu_offset(int regnum) { 2055 // No user for this method? 2056 Unimplemented(); 2057 return 999; 2058} 2059 2060const bool Matcher::convL2FSupported(void) { 2061 // fcfids can do the conversion (>= Power7). 2062 // fcfid + frsp showed rounding problem when result should be 0x3f800001. 2063 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call. 2064} 2065 2066// Vector width in bytes. 2067const int Matcher::vector_width_in_bytes(BasicType bt) { 2068 assert(MaxVectorSize == 8, ""); 2069 return 8; 2070} 2071 2072// Vector ideal reg. 2073const int Matcher::vector_ideal_reg(int size) { 2074 assert(MaxVectorSize == 8 && size == 8, ""); 2075 return Op_RegL; 2076} 2077 2078const int Matcher::vector_shift_count_ideal_reg(int size) { 2079 fatal("vector shift is not supported"); 2080 return Node::NotAMachineReg; 2081} 2082 2083// Limits on vector size (number of elements) loaded into vector. 2084const int Matcher::max_vector_size(const BasicType bt) { 2085 assert(is_java_primitive(bt), "only primitive type vectors"); 2086 return vector_width_in_bytes(bt)/type2aelembytes(bt); 2087} 2088 2089const int Matcher::min_vector_size(const BasicType bt) { 2090 return max_vector_size(bt); // Same as max. 2091} 2092 2093// PPC doesn't support misaligned vectors store/load. 2094const bool Matcher::misaligned_vectors_ok() { 2095 return false; 2096} 2097 2098// PPC AES support not yet implemented 2099const bool Matcher::pass_original_key_for_aes() { 2100 return false; 2101} 2102 2103// RETURNS: whether this branch offset is short enough that a short 2104// branch can be used. 2105// 2106// If the platform does not provide any short branch variants, then 2107// this method should return `false' for offset 0. 2108// 2109// `Compile::Fill_buffer' will decide on basis of this information 2110// whether to do the pass `Compile::Shorten_branches' at all. 2111// 2112// And `Compile::Shorten_branches' will decide on basis of this 2113// information whether to replace particular branch sites by short 2114// ones. 2115bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 2116 // Is the offset within the range of a ppc64 pc relative branch? 2117 bool b; 2118 2119 const int safety_zone = 3 * BytesPerInstWord; 2120 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone), 2121 29 - 16 + 1 + 2); 2122 return b; 2123} 2124 2125const bool Matcher::isSimpleConstant64(jlong value) { 2126 // Probably always true, even if a temp register is required. 2127 return true; 2128} 2129/* TODO: PPC port 2130// Make a new machine dependent decode node (with its operands). 2131MachTypeNode *Matcher::make_decode_node() { 2132 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0, 2133 "This method is only implemented for unscaled cOops mode so far"); 2134 MachTypeNode *decode = new decodeN_unscaledNode(); 2135 decode->set_opnd_array(0, new iRegPdstOper()); 2136 decode->set_opnd_array(1, new iRegNsrcOper()); 2137 return decode; 2138} 2139*/ 2140// Threshold size for cleararray. 2141const int Matcher::init_array_short_size = 8 * BytesPerLong; 2142 2143// false => size gets scaled to BytesPerLong, ok. 2144const bool Matcher::init_array_count_is_in_bytes = false; 2145 2146// Use conditional move (CMOVL) on Power7. 2147const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves 2148 2149// Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet. 2150// fsel doesn't accept a condition register as input, so this would be slightly different. 2151const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } 2152 2153// Power6 requires postalloc expand (see block.cpp for description of postalloc expand). 2154const bool Matcher::require_postalloc_expand = true; 2155 2156// Should the Matcher clone shifts on addressing modes, expecting them to 2157// be subsumed into complex addressing expressions or compute them into 2158// registers? True for Intel but false for most RISCs. 2159const bool Matcher::clone_shift_expressions = false; 2160 2161// Do we need to mask the count passed to shift instructions or does 2162// the cpu only look at the lower 5/6 bits anyway? 2163// PowerPC requires masked shift counts. 2164const bool Matcher::need_masked_shift_count = true; 2165 2166// This affects two different things: 2167// - how Decode nodes are matched 2168// - how ImplicitNullCheck opportunities are recognized 2169// If true, the matcher will try to remove all Decodes and match them 2170// (as operands) into nodes. NullChecks are not prepared to deal with 2171// Decodes by final_graph_reshaping(). 2172// If false, final_graph_reshaping() forces the decode behind the Cmp 2173// for a NullCheck. The matcher matches the Decode node into a register. 2174// Implicit_null_check optimization moves the Decode along with the 2175// memory operation back up before the NullCheck. 2176bool Matcher::narrow_oop_use_complex_address() { 2177 // TODO: PPC port if (MatchDecodeNodes) return true; 2178 return false; 2179} 2180 2181bool Matcher::narrow_klass_use_complex_address() { 2182 NOT_LP64(ShouldNotCallThis()); 2183 assert(UseCompressedClassPointers, "only for compressed klass code"); 2184 // TODO: PPC port if (MatchDecodeNodes) return true; 2185 return false; 2186} 2187 2188// Is it better to copy float constants, or load them directly from memory? 2189// Intel can load a float constant from a direct address, requiring no 2190// extra registers. Most RISCs will have to materialize an address into a 2191// register first, so they would do better to copy the constant from stack. 2192const bool Matcher::rematerialize_float_constants = false; 2193 2194// If CPU can load and store mis-aligned doubles directly then no fixup is 2195// needed. Else we split the double into 2 integer pieces and move it 2196// piece-by-piece. Only happens when passing doubles into C code as the 2197// Java calling convention forces doubles to be aligned. 2198const bool Matcher::misaligned_doubles_ok = true; 2199 2200void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 2201 Unimplemented(); 2202} 2203 2204// Advertise here if the CPU requires explicit rounding operations 2205// to implement the UseStrictFP mode. 2206const bool Matcher::strict_fp_requires_explicit_rounding = false; 2207 2208// Do floats take an entire double register or just half? 2209// 2210// A float occupies a ppc64 double register. For the allocator, a 2211// ppc64 double register appears as a pair of float registers. 2212bool Matcher::float_in_double() { return true; } 2213 2214// Do ints take an entire long register or just half? 2215// The relevant question is how the int is callee-saved: 2216// the whole long is written but de-opt'ing will have to extract 2217// the relevant 32 bits. 2218const bool Matcher::int_in_long = true; 2219 2220// Constants for c2c and c calling conventions. 2221 2222const MachRegisterNumbers iarg_reg[8] = { 2223 R3_num, R4_num, R5_num, R6_num, 2224 R7_num, R8_num, R9_num, R10_num 2225}; 2226 2227const MachRegisterNumbers farg_reg[13] = { 2228 F1_num, F2_num, F3_num, F4_num, 2229 F5_num, F6_num, F7_num, F8_num, 2230 F9_num, F10_num, F11_num, F12_num, 2231 F13_num 2232}; 2233 2234const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]); 2235 2236const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]); 2237 2238// Return whether or not this register is ever used as an argument. This 2239// function is used on startup to build the trampoline stubs in generateOptoStub. 2240// Registers not mentioned will be killed by the VM call in the trampoline, and 2241// arguments in those registers not be available to the callee. 2242bool Matcher::can_be_java_arg(int reg) { 2243 // We return true for all registers contained in iarg_reg[] and 2244 // farg_reg[] and their virtual halves. 2245 // We must include the virtual halves in order to get STDs and LDs 2246 // instead of STWs and LWs in the trampoline stubs. 2247 2248 if ( reg == R3_num || reg == R3_H_num 2249 || reg == R4_num || reg == R4_H_num 2250 || reg == R5_num || reg == R5_H_num 2251 || reg == R6_num || reg == R6_H_num 2252 || reg == R7_num || reg == R7_H_num 2253 || reg == R8_num || reg == R8_H_num 2254 || reg == R9_num || reg == R9_H_num 2255 || reg == R10_num || reg == R10_H_num) 2256 return true; 2257 2258 if ( reg == F1_num || reg == F1_H_num 2259 || reg == F2_num || reg == F2_H_num 2260 || reg == F3_num || reg == F3_H_num 2261 || reg == F4_num || reg == F4_H_num 2262 || reg == F5_num || reg == F5_H_num 2263 || reg == F6_num || reg == F6_H_num 2264 || reg == F7_num || reg == F7_H_num 2265 || reg == F8_num || reg == F8_H_num 2266 || reg == F9_num || reg == F9_H_num 2267 || reg == F10_num || reg == F10_H_num 2268 || reg == F11_num || reg == F11_H_num 2269 || reg == F12_num || reg == F12_H_num 2270 || reg == F13_num || reg == F13_H_num) 2271 return true; 2272 2273 return false; 2274} 2275 2276bool Matcher::is_spillable_arg(int reg) { 2277 return can_be_java_arg(reg); 2278} 2279 2280bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) { 2281 return false; 2282} 2283 2284// Register for DIVI projection of divmodI. 2285RegMask Matcher::divI_proj_mask() { 2286 ShouldNotReachHere(); 2287 return RegMask(); 2288} 2289 2290// Register for MODI projection of divmodI. 2291RegMask Matcher::modI_proj_mask() { 2292 ShouldNotReachHere(); 2293 return RegMask(); 2294} 2295 2296// Register for DIVL projection of divmodL. 2297RegMask Matcher::divL_proj_mask() { 2298 ShouldNotReachHere(); 2299 return RegMask(); 2300} 2301 2302// Register for MODL projection of divmodL. 2303RegMask Matcher::modL_proj_mask() { 2304 ShouldNotReachHere(); 2305 return RegMask(); 2306} 2307 2308const RegMask Matcher::method_handle_invoke_SP_save_mask() { 2309 return RegMask(); 2310} 2311 2312%} 2313 2314//----------ENCODING BLOCK----------------------------------------------------- 2315// This block specifies the encoding classes used by the compiler to output 2316// byte streams. Encoding classes are parameterized macros used by 2317// Machine Instruction Nodes in order to generate the bit encoding of the 2318// instruction. Operands specify their base encoding interface with the 2319// interface keyword. There are currently supported four interfaces, 2320// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 2321// operand to generate a function which returns its register number when 2322// queried. CONST_INTER causes an operand to generate a function which 2323// returns the value of the constant when queried. MEMORY_INTER causes an 2324// operand to generate four functions which return the Base Register, the 2325// Index Register, the Scale Value, and the Offset Value of the operand when 2326// queried. COND_INTER causes an operand to generate six functions which 2327// return the encoding code (ie - encoding bits for the instruction) 2328// associated with each basic boolean condition for a conditional instruction. 2329// 2330// Instructions specify two basic values for encoding. Again, a function 2331// is available to check if the constant displacement is an oop. They use the 2332// ins_encode keyword to specify their encoding classes (which must be 2333// a sequence of enc_class names, and their parameters, specified in 2334// the encoding block), and they use the 2335// opcode keyword to specify, in order, their primary, secondary, and 2336// tertiary opcode. Only the opcode sections which a particular instruction 2337// needs for encoding need to be specified. 2338encode %{ 2339 enc_class enc_unimplemented %{ 2340 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2341 MacroAssembler _masm(&cbuf); 2342 __ unimplemented("Unimplemented mach node encoding in AD file.", 13); 2343 %} 2344 2345 enc_class enc_untested %{ 2346#ifdef ASSERT 2347 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2348 MacroAssembler _masm(&cbuf); 2349 __ untested("Untested mach node encoding in AD file."); 2350#else 2351 // TODO: PPC port $archOpcode(ppc64Opcode_none); 2352#endif 2353 %} 2354 2355 enc_class enc_lbz(iRegIdst dst, memory mem) %{ 2356 // TODO: PPC port $archOpcode(ppc64Opcode_lbz); 2357 MacroAssembler _masm(&cbuf); 2358 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2359 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); 2360 %} 2361 2362 // Load acquire. 2363 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{ 2364 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2365 MacroAssembler _masm(&cbuf); 2366 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2367 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); 2368 __ twi_0($dst$$Register); 2369 __ isync(); 2370 %} 2371 2372 enc_class enc_lhz(iRegIdst dst, memory mem) %{ 2373 // TODO: PPC port $archOpcode(ppc64Opcode_lhz); 2374 2375 MacroAssembler _masm(&cbuf); 2376 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2377 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); 2378 %} 2379 2380 // Load acquire. 2381 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{ 2382 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2383 2384 MacroAssembler _masm(&cbuf); 2385 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2386 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); 2387 __ twi_0($dst$$Register); 2388 __ isync(); 2389 %} 2390 2391 enc_class enc_lwz(iRegIdst dst, memory mem) %{ 2392 // TODO: PPC port $archOpcode(ppc64Opcode_lwz); 2393 2394 MacroAssembler _masm(&cbuf); 2395 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2396 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); 2397 %} 2398 2399 // Load acquire. 2400 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{ 2401 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2402 2403 MacroAssembler _masm(&cbuf); 2404 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2405 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); 2406 __ twi_0($dst$$Register); 2407 __ isync(); 2408 %} 2409 2410 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{ 2411 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2412 MacroAssembler _masm(&cbuf); 2413 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2414 // Operand 'ds' requires 4-alignment. 2415 assert((Idisp & 0x3) == 0, "unaligned offset"); 2416 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 2417 %} 2418 2419 // Load acquire. 2420 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{ 2421 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2422 MacroAssembler _masm(&cbuf); 2423 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2424 // Operand 'ds' requires 4-alignment. 2425 assert((Idisp & 0x3) == 0, "unaligned offset"); 2426 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 2427 __ twi_0($dst$$Register); 2428 __ isync(); 2429 %} 2430 2431 enc_class enc_lfd(RegF dst, memory mem) %{ 2432 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); 2433 MacroAssembler _masm(&cbuf); 2434 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2435 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); 2436 %} 2437 2438 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{ 2439 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2440 2441 MacroAssembler _masm(&cbuf); 2442 int toc_offset = 0; 2443 2444 if (!ra_->C->in_scratch_emit_size()) { 2445 address const_toc_addr; 2446 // Create a non-oop constant, no relocation needed. 2447 // If it is an IC, it has a virtual_call_Relocation. 2448 const_toc_addr = __ long_constant((jlong)$src$$constant); 2449 if (const_toc_addr == NULL) { 2450 ciEnv::current()->record_out_of_memory_failure(); 2451 return; 2452 } 2453 2454 // Get the constant's TOC offset. 2455 toc_offset = __ offset_to_method_toc(const_toc_addr); 2456 2457 // Keep the current instruction offset in mind. 2458 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset(); 2459 } 2460 2461 __ ld($dst$$Register, toc_offset, $toc$$Register); 2462 %} 2463 2464 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{ 2465 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 2466 2467 MacroAssembler _masm(&cbuf); 2468 2469 if (!ra_->C->in_scratch_emit_size()) { 2470 address const_toc_addr; 2471 // Create a non-oop constant, no relocation needed. 2472 // If it is an IC, it has a virtual_call_Relocation. 2473 const_toc_addr = __ long_constant((jlong)$src$$constant); 2474 if (const_toc_addr == NULL) { 2475 ciEnv::current()->record_out_of_memory_failure(); 2476 return; 2477 } 2478 2479 // Get the constant's TOC offset. 2480 const int toc_offset = __ offset_to_method_toc(const_toc_addr); 2481 // Store the toc offset of the constant. 2482 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset; 2483 2484 // Also keep the current instruction offset in mind. 2485 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset(); 2486 } 2487 2488 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); 2489 %} 2490 2491%} // encode 2492 2493source %{ 2494 2495typedef struct { 2496 loadConL_hiNode *_large_hi; 2497 loadConL_loNode *_large_lo; 2498 loadConLNode *_small; 2499 MachNode *_last; 2500} loadConLNodesTuple; 2501 2502loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc, 2503 OptoReg::Name reg_second, OptoReg::Name reg_first) { 2504 loadConLNodesTuple nodes; 2505 2506 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2507 if (large_constant_pool) { 2508 // Create new nodes. 2509 loadConL_hiNode *m1 = new loadConL_hiNode(); 2510 loadConL_loNode *m2 = new loadConL_loNode(); 2511 2512 // inputs for new nodes 2513 m1->add_req(NULL, toc); 2514 m2->add_req(NULL, m1); 2515 2516 // operands for new nodes 2517 m1->_opnds[0] = new iRegLdstOper(); // dst 2518 m1->_opnds[1] = immSrc; // src 2519 m1->_opnds[2] = new iRegPdstOper(); // toc 2520 m2->_opnds[0] = new iRegLdstOper(); // dst 2521 m2->_opnds[1] = immSrc; // src 2522 m2->_opnds[2] = new iRegLdstOper(); // base 2523 2524 // Initialize ins_attrib TOC fields. 2525 m1->_const_toc_offset = -1; 2526 m2->_const_toc_offset_hi_node = m1; 2527 2528 // Initialize ins_attrib instruction offset. 2529 m1->_cbuf_insts_offset = -1; 2530 2531 // register allocation for new nodes 2532 ra_->set_pair(m1->_idx, reg_second, reg_first); 2533 ra_->set_pair(m2->_idx, reg_second, reg_first); 2534 2535 // Create result. 2536 nodes._large_hi = m1; 2537 nodes._large_lo = m2; 2538 nodes._small = NULL; 2539 nodes._last = nodes._large_lo; 2540 assert(m2->bottom_type()->isa_long(), "must be long"); 2541 } else { 2542 loadConLNode *m2 = new loadConLNode(); 2543 2544 // inputs for new nodes 2545 m2->add_req(NULL, toc); 2546 2547 // operands for new nodes 2548 m2->_opnds[0] = new iRegLdstOper(); // dst 2549 m2->_opnds[1] = immSrc; // src 2550 m2->_opnds[2] = new iRegPdstOper(); // toc 2551 2552 // Initialize ins_attrib instruction offset. 2553 m2->_cbuf_insts_offset = -1; 2554 2555 // register allocation for new nodes 2556 ra_->set_pair(m2->_idx, reg_second, reg_first); 2557 2558 // Create result. 2559 nodes._large_hi = NULL; 2560 nodes._large_lo = NULL; 2561 nodes._small = m2; 2562 nodes._last = nodes._small; 2563 assert(m2->bottom_type()->isa_long(), "must be long"); 2564 } 2565 2566 return nodes; 2567} 2568 2569%} // source 2570 2571encode %{ 2572 // Postalloc expand emitter for loading a long constant from the method's TOC. 2573 // Enc_class needed as consttanttablebase is not supported by postalloc 2574 // expand. 2575 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{ 2576 // Create new nodes. 2577 loadConLNodesTuple loadConLNodes = 2578 loadConLNodesTuple_create(ra_, n_toc, op_src, 2579 ra_->get_reg_second(this), ra_->get_reg_first(this)); 2580 2581 // Push new nodes. 2582 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); 2583 if (loadConLNodes._last) nodes->push(loadConLNodes._last); 2584 2585 // some asserts 2586 assert(nodes->length() >= 1, "must have created at least 1 node"); 2587 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); 2588 %} 2589 2590 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{ 2591 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2592 2593 MacroAssembler _masm(&cbuf); 2594 int toc_offset = 0; 2595 2596 if (!ra_->C->in_scratch_emit_size()) { 2597 intptr_t val = $src$$constant; 2598 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src 2599 address const_toc_addr; 2600 if (constant_reloc == relocInfo::oop_type) { 2601 // Create an oop constant and a corresponding relocation. 2602 AddressLiteral a = __ allocate_oop_address((jobject)val); 2603 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2604 __ relocate(a.rspec()); 2605 } else if (constant_reloc == relocInfo::metadata_type) { 2606 AddressLiteral a = __ constant_metadata_address((Metadata *)val); 2607 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2608 __ relocate(a.rspec()); 2609 } else { 2610 // Create a non-oop constant, no relocation needed. 2611 const_toc_addr = __ long_constant((jlong)$src$$constant); 2612 } 2613 2614 if (const_toc_addr == NULL) { 2615 ciEnv::current()->record_out_of_memory_failure(); 2616 return; 2617 } 2618 // Get the constant's TOC offset. 2619 toc_offset = __ offset_to_method_toc(const_toc_addr); 2620 } 2621 2622 __ ld($dst$$Register, toc_offset, $toc$$Register); 2623 %} 2624 2625 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{ 2626 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 2627 2628 MacroAssembler _masm(&cbuf); 2629 if (!ra_->C->in_scratch_emit_size()) { 2630 intptr_t val = $src$$constant; 2631 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src 2632 address const_toc_addr; 2633 if (constant_reloc == relocInfo::oop_type) { 2634 // Create an oop constant and a corresponding relocation. 2635 AddressLiteral a = __ allocate_oop_address((jobject)val); 2636 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2637 __ relocate(a.rspec()); 2638 } else if (constant_reloc == relocInfo::metadata_type) { 2639 AddressLiteral a = __ constant_metadata_address((Metadata *)val); 2640 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2641 __ relocate(a.rspec()); 2642 } else { // non-oop pointers, e.g. card mark base, heap top 2643 // Create a non-oop constant, no relocation needed. 2644 const_toc_addr = __ long_constant((jlong)$src$$constant); 2645 } 2646 2647 if (const_toc_addr == NULL) { 2648 ciEnv::current()->record_out_of_memory_failure(); 2649 return; 2650 } 2651 // Get the constant's TOC offset. 2652 const int toc_offset = __ offset_to_method_toc(const_toc_addr); 2653 // Store the toc offset of the constant. 2654 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset; 2655 } 2656 2657 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); 2658 %} 2659 2660 // Postalloc expand emitter for loading a ptr constant from the method's TOC. 2661 // Enc_class needed as consttanttablebase is not supported by postalloc 2662 // expand. 2663 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{ 2664 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2665 if (large_constant_pool) { 2666 // Create new nodes. 2667 loadConP_hiNode *m1 = new loadConP_hiNode(); 2668 loadConP_loNode *m2 = new loadConP_loNode(); 2669 2670 // inputs for new nodes 2671 m1->add_req(NULL, n_toc); 2672 m2->add_req(NULL, m1); 2673 2674 // operands for new nodes 2675 m1->_opnds[0] = new iRegPdstOper(); // dst 2676 m1->_opnds[1] = op_src; // src 2677 m1->_opnds[2] = new iRegPdstOper(); // toc 2678 m2->_opnds[0] = new iRegPdstOper(); // dst 2679 m2->_opnds[1] = op_src; // src 2680 m2->_opnds[2] = new iRegLdstOper(); // base 2681 2682 // Initialize ins_attrib TOC fields. 2683 m1->_const_toc_offset = -1; 2684 m2->_const_toc_offset_hi_node = m1; 2685 2686 // Register allocation for new nodes. 2687 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2688 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2689 2690 nodes->push(m1); 2691 nodes->push(m2); 2692 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 2693 } else { 2694 loadConPNode *m2 = new loadConPNode(); 2695 2696 // inputs for new nodes 2697 m2->add_req(NULL, n_toc); 2698 2699 // operands for new nodes 2700 m2->_opnds[0] = new iRegPdstOper(); // dst 2701 m2->_opnds[1] = op_src; // src 2702 m2->_opnds[2] = new iRegPdstOper(); // toc 2703 2704 // Register allocation for new nodes. 2705 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2706 2707 nodes->push(m2); 2708 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 2709 } 2710 %} 2711 2712 // Enc_class needed as consttanttablebase is not supported by postalloc 2713 // expand. 2714 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{ 2715 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2716 2717 MachNode *m2; 2718 if (large_constant_pool) { 2719 m2 = new loadConFCompNode(); 2720 } else { 2721 m2 = new loadConFNode(); 2722 } 2723 // inputs for new nodes 2724 m2->add_req(NULL, n_toc); 2725 2726 // operands for new nodes 2727 m2->_opnds[0] = op_dst; 2728 m2->_opnds[1] = op_src; 2729 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase 2730 2731 // register allocation for new nodes 2732 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2733 nodes->push(m2); 2734 %} 2735 2736 // Enc_class needed as consttanttablebase is not supported by postalloc 2737 // expand. 2738 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{ 2739 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2740 2741 MachNode *m2; 2742 if (large_constant_pool) { 2743 m2 = new loadConDCompNode(); 2744 } else { 2745 m2 = new loadConDNode(); 2746 } 2747 // inputs for new nodes 2748 m2->add_req(NULL, n_toc); 2749 2750 // operands for new nodes 2751 m2->_opnds[0] = op_dst; 2752 m2->_opnds[1] = op_src; 2753 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase 2754 2755 // register allocation for new nodes 2756 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2757 nodes->push(m2); 2758 %} 2759 2760 enc_class enc_stw(iRegIsrc src, memory mem) %{ 2761 // TODO: PPC port $archOpcode(ppc64Opcode_stw); 2762 MacroAssembler _masm(&cbuf); 2763 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2764 __ stw($src$$Register, Idisp, $mem$$base$$Register); 2765 %} 2766 2767 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{ 2768 // TODO: PPC port $archOpcode(ppc64Opcode_std); 2769 MacroAssembler _masm(&cbuf); 2770 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2771 // Operand 'ds' requires 4-alignment. 2772 assert((Idisp & 0x3) == 0, "unaligned offset"); 2773 __ std($src$$Register, Idisp, $mem$$base$$Register); 2774 %} 2775 2776 enc_class enc_stfs(RegF src, memory mem) %{ 2777 // TODO: PPC port $archOpcode(ppc64Opcode_stfs); 2778 MacroAssembler _masm(&cbuf); 2779 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2780 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register); 2781 %} 2782 2783 enc_class enc_stfd(RegF src, memory mem) %{ 2784 // TODO: PPC port $archOpcode(ppc64Opcode_stfd); 2785 MacroAssembler _masm(&cbuf); 2786 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2787 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register); 2788 %} 2789 2790 // Use release_store for card-marking to ensure that previous 2791 // oop-stores are visible before the card-mark change. 2792 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{ 2793 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2794 // FIXME: Implement this as a cmove and use a fixed condition code 2795 // register which is written on every transition to compiled code, 2796 // e.g. in call-stub and when returning from runtime stubs. 2797 // 2798 // Proposed code sequence for the cmove implementation: 2799 // 2800 // Label skip_release; 2801 // __ beq(CCRfixed, skip_release); 2802 // __ release(); 2803 // __ bind(skip_release); 2804 // __ stb(card mark); 2805 2806 MacroAssembler _masm(&cbuf); 2807 Label skip_storestore; 2808 2809#if 0 // TODO: PPC port 2810 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the 2811 // StoreStore barrier conditionally. 2812 __ lwz(R0, 0, $releaseFieldAddr$$Register); 2813 __ cmpwi($crx$$CondRegister, R0, 0); 2814 __ beq_predict_taken($crx$$CondRegister, skip_storestore); 2815#endif 2816 __ li(R0, 0); 2817 __ membar(Assembler::StoreStore); 2818#if 0 // TODO: PPC port 2819 __ bind(skip_storestore); 2820#endif 2821 2822 // Do the store. 2823 if ($mem$$index == 0) { 2824 __ stb(R0, $mem$$disp, $mem$$base$$Register); 2825 } else { 2826 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc"); 2827 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register); 2828 } 2829 %} 2830 2831 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{ 2832 2833 if (VM_Version::has_isel()) { 2834 // use isel instruction with Power 7 2835 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node(); 2836 encodeP_subNode *n_sub_base = new encodeP_subNode(); 2837 encodeP_shiftNode *n_shift = new encodeP_shiftNode(); 2838 cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode(); 2839 2840 n_compare->add_req(n_region, n_src); 2841 n_compare->_opnds[0] = op_crx; 2842 n_compare->_opnds[1] = op_src; 2843 n_compare->_opnds[2] = new immL16Oper(0); 2844 2845 n_sub_base->add_req(n_region, n_src); 2846 n_sub_base->_opnds[0] = op_dst; 2847 n_sub_base->_opnds[1] = op_src; 2848 n_sub_base->_bottom_type = _bottom_type; 2849 2850 n_shift->add_req(n_region, n_sub_base); 2851 n_shift->_opnds[0] = op_dst; 2852 n_shift->_opnds[1] = op_dst; 2853 n_shift->_bottom_type = _bottom_type; 2854 2855 n_cond_set->add_req(n_region, n_compare, n_shift); 2856 n_cond_set->_opnds[0] = op_dst; 2857 n_cond_set->_opnds[1] = op_crx; 2858 n_cond_set->_opnds[2] = op_dst; 2859 n_cond_set->_bottom_type = _bottom_type; 2860 2861 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2862 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2863 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2864 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2865 2866 nodes->push(n_compare); 2867 nodes->push(n_sub_base); 2868 nodes->push(n_shift); 2869 nodes->push(n_cond_set); 2870 2871 } else { 2872 // before Power 7 2873 moveRegNode *n_move = new moveRegNode(); 2874 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node(); 2875 encodeP_shiftNode *n_shift = new encodeP_shiftNode(); 2876 cond_sub_baseNode *n_sub_base = new cond_sub_baseNode(); 2877 2878 n_move->add_req(n_region, n_src); 2879 n_move->_opnds[0] = op_dst; 2880 n_move->_opnds[1] = op_src; 2881 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop. 2882 2883 n_compare->add_req(n_region, n_src); 2884 n_compare->add_prec(n_move); 2885 2886 n_compare->_opnds[0] = op_crx; 2887 n_compare->_opnds[1] = op_src; 2888 n_compare->_opnds[2] = new immL16Oper(0); 2889 2890 n_sub_base->add_req(n_region, n_compare, n_src); 2891 n_sub_base->_opnds[0] = op_dst; 2892 n_sub_base->_opnds[1] = op_crx; 2893 n_sub_base->_opnds[2] = op_src; 2894 n_sub_base->_bottom_type = _bottom_type; 2895 2896 n_shift->add_req(n_region, n_sub_base); 2897 n_shift->_opnds[0] = op_dst; 2898 n_shift->_opnds[1] = op_dst; 2899 n_shift->_bottom_type = _bottom_type; 2900 2901 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2902 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2903 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2904 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2905 2906 nodes->push(n_move); 2907 nodes->push(n_compare); 2908 nodes->push(n_sub_base); 2909 nodes->push(n_shift); 2910 } 2911 2912 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. 2913 %} 2914 2915 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{ 2916 2917 encodeP_subNode *n1 = new encodeP_subNode(); 2918 n1->add_req(n_region, n_src); 2919 n1->_opnds[0] = op_dst; 2920 n1->_opnds[1] = op_src; 2921 n1->_bottom_type = _bottom_type; 2922 2923 encodeP_shiftNode *n2 = new encodeP_shiftNode(); 2924 n2->add_req(n_region, n1); 2925 n2->_opnds[0] = op_dst; 2926 n2->_opnds[1] = op_dst; 2927 n2->_bottom_type = _bottom_type; 2928 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2929 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2930 2931 nodes->push(n1); 2932 nodes->push(n2); 2933 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. 2934 %} 2935 2936 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 2937 decodeN_shiftNode *n_shift = new decodeN_shiftNode(); 2938 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node(); 2939 2940 n_compare->add_req(n_region, n_src); 2941 n_compare->_opnds[0] = op_crx; 2942 n_compare->_opnds[1] = op_src; 2943 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR); 2944 2945 n_shift->add_req(n_region, n_src); 2946 n_shift->_opnds[0] = op_dst; 2947 n_shift->_opnds[1] = op_src; 2948 n_shift->_bottom_type = _bottom_type; 2949 2950 if (VM_Version::has_isel()) { 2951 // use isel instruction with Power 7 2952 2953 decodeN_addNode *n_add_base = new decodeN_addNode(); 2954 n_add_base->add_req(n_region, n_shift); 2955 n_add_base->_opnds[0] = op_dst; 2956 n_add_base->_opnds[1] = op_dst; 2957 n_add_base->_bottom_type = _bottom_type; 2958 2959 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode(); 2960 n_cond_set->add_req(n_region, n_compare, n_add_base); 2961 n_cond_set->_opnds[0] = op_dst; 2962 n_cond_set->_opnds[1] = op_crx; 2963 n_cond_set->_opnds[2] = op_dst; 2964 n_cond_set->_bottom_type = _bottom_type; 2965 2966 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 2967 ra_->set_oop(n_cond_set, true); 2968 2969 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2970 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2971 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2972 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2973 2974 nodes->push(n_compare); 2975 nodes->push(n_shift); 2976 nodes->push(n_add_base); 2977 nodes->push(n_cond_set); 2978 2979 } else { 2980 // before Power 7 2981 cond_add_baseNode *n_add_base = new cond_add_baseNode(); 2982 2983 n_add_base->add_req(n_region, n_compare, n_shift); 2984 n_add_base->_opnds[0] = op_dst; 2985 n_add_base->_opnds[1] = op_crx; 2986 n_add_base->_opnds[2] = op_dst; 2987 n_add_base->_bottom_type = _bottom_type; 2988 2989 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 2990 ra_->set_oop(n_add_base, true); 2991 2992 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2993 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2994 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2995 2996 nodes->push(n_compare); 2997 nodes->push(n_shift); 2998 nodes->push(n_add_base); 2999 } 3000 %} 3001 3002 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{ 3003 decodeN_shiftNode *n1 = new decodeN_shiftNode(); 3004 n1->add_req(n_region, n_src); 3005 n1->_opnds[0] = op_dst; 3006 n1->_opnds[1] = op_src; 3007 n1->_bottom_type = _bottom_type; 3008 3009 decodeN_addNode *n2 = new decodeN_addNode(); 3010 n2->add_req(n_region, n1); 3011 n2->_opnds[0] = op_dst; 3012 n2->_opnds[1] = op_dst; 3013 n2->_bottom_type = _bottom_type; 3014 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3015 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3016 3017 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 3018 ra_->set_oop(n2, true); 3019 3020 nodes->push(n1); 3021 nodes->push(n2); 3022 %} 3023 3024 enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{ 3025 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3026 3027 MacroAssembler _masm(&cbuf); 3028 int cc = $cmp$$cmpcode; 3029 int flags_reg = $crx$$reg; 3030 Label done; 3031 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3032 // Branch if not (cmp crx). 3033 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done); 3034 __ mr($dst$$Register, $src$$Register); 3035 // TODO PPC port __ endgroup_if_needed(_size == 12); 3036 __ bind(done); 3037 %} 3038 3039 enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{ 3040 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3041 3042 MacroAssembler _masm(&cbuf); 3043 Label done; 3044 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3045 // Branch if not (cmp crx). 3046 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 3047 __ li($dst$$Register, $src$$constant); 3048 // TODO PPC port __ endgroup_if_needed(_size == 12); 3049 __ bind(done); 3050 %} 3051 3052 // New atomics. 3053 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 3054 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3055 3056 MacroAssembler _masm(&cbuf); 3057 Register Rtmp = R0; 3058 Register Rres = $res$$Register; 3059 Register Rsrc = $src$$Register; 3060 Register Rptr = $mem_ptr$$Register; 3061 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3062 Register Rold = RegCollision ? Rtmp : Rres; 3063 3064 Label Lretry; 3065 __ bind(Lretry); 3066 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3067 __ add(Rtmp, Rsrc, Rold); 3068 __ stwcx_(Rtmp, Rptr); 3069 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3070 __ bne_predict_not_taken(CCR0, Lretry); 3071 } else { 3072 __ bne( CCR0, Lretry); 3073 } 3074 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); 3075 __ fence(); 3076 %} 3077 3078 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 3079 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3080 3081 MacroAssembler _masm(&cbuf); 3082 Register Rtmp = R0; 3083 Register Rres = $res$$Register; 3084 Register Rsrc = $src$$Register; 3085 Register Rptr = $mem_ptr$$Register; 3086 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3087 Register Rold = RegCollision ? Rtmp : Rres; 3088 3089 Label Lretry; 3090 __ bind(Lretry); 3091 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3092 __ add(Rtmp, Rsrc, Rold); 3093 __ stdcx_(Rtmp, Rptr); 3094 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3095 __ bne_predict_not_taken(CCR0, Lretry); 3096 } else { 3097 __ bne( CCR0, Lretry); 3098 } 3099 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); 3100 __ fence(); 3101 %} 3102 3103 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 3104 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3105 3106 MacroAssembler _masm(&cbuf); 3107 Register Rtmp = R0; 3108 Register Rres = $res$$Register; 3109 Register Rsrc = $src$$Register; 3110 Register Rptr = $mem_ptr$$Register; 3111 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3112 Register Rold = RegCollision ? Rtmp : Rres; 3113 3114 Label Lretry; 3115 __ bind(Lretry); 3116 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3117 __ stwcx_(Rsrc, Rptr); 3118 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3119 __ bne_predict_not_taken(CCR0, Lretry); 3120 } else { 3121 __ bne( CCR0, Lretry); 3122 } 3123 if (RegCollision) __ mr(Rres, Rtmp); 3124 __ fence(); 3125 %} 3126 3127 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 3128 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3129 3130 MacroAssembler _masm(&cbuf); 3131 Register Rtmp = R0; 3132 Register Rres = $res$$Register; 3133 Register Rsrc = $src$$Register; 3134 Register Rptr = $mem_ptr$$Register; 3135 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3136 Register Rold = RegCollision ? Rtmp : Rres; 3137 3138 Label Lretry; 3139 __ bind(Lretry); 3140 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3141 __ stdcx_(Rsrc, Rptr); 3142 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3143 __ bne_predict_not_taken(CCR0, Lretry); 3144 } else { 3145 __ bne( CCR0, Lretry); 3146 } 3147 if (RegCollision) __ mr(Rres, Rtmp); 3148 __ fence(); 3149 %} 3150 3151 // This enc_class is needed so that scheduler gets proper 3152 // input mapping for latency computation. 3153 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 3154 // TODO: PPC port $archOpcode(ppc64Opcode_andc); 3155 MacroAssembler _masm(&cbuf); 3156 __ andc($dst$$Register, $src1$$Register, $src2$$Register); 3157 %} 3158 3159 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ 3160 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3161 3162 MacroAssembler _masm(&cbuf); 3163 3164 Label done; 3165 __ cmpwi($crx$$CondRegister, $src$$Register, 0); 3166 __ li($dst$$Register, $zero$$constant); 3167 __ beq($crx$$CondRegister, done); 3168 __ li($dst$$Register, $notzero$$constant); 3169 __ bind(done); 3170 %} 3171 3172 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ 3173 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3174 3175 MacroAssembler _masm(&cbuf); 3176 3177 Label done; 3178 __ cmpdi($crx$$CondRegister, $src$$Register, 0); 3179 __ li($dst$$Register, $zero$$constant); 3180 __ beq($crx$$CondRegister, done); 3181 __ li($dst$$Register, $notzero$$constant); 3182 __ bind(done); 3183 %} 3184 3185 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{ 3186 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3187 3188 MacroAssembler _masm(&cbuf); 3189 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 3190 Label done; 3191 __ bso($crx$$CondRegister, done); 3192 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 3193 // TODO PPC port __ endgroup_if_needed(_size == 12); 3194 __ bind(done); 3195 %} 3196 3197 enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{ 3198 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3199 3200 MacroAssembler _masm(&cbuf); 3201 Label d; // dummy 3202 __ bind(d); 3203 Label* p = ($lbl$$label); 3204 // `p' is `NULL' when this encoding class is used only to 3205 // determine the size of the encoded instruction. 3206 Label& l = (NULL == p)? d : *(p); 3207 int cc = $cmp$$cmpcode; 3208 int flags_reg = $crx$$reg; 3209 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3210 int bhint = Assembler::bhintNoHint; 3211 3212 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3213 if (_prob <= PROB_NEVER) { 3214 bhint = Assembler::bhintIsNotTaken; 3215 } else if (_prob >= PROB_ALWAYS) { 3216 bhint = Assembler::bhintIsTaken; 3217 } 3218 } 3219 3220 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3221 cc_to_biint(cc, flags_reg), 3222 l); 3223 %} 3224 3225 enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{ 3226 // The scheduler doesn't know about branch shortening, so we set the opcode 3227 // to ppc64Opcode_bc in order to hide this detail from the scheduler. 3228 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3229 3230 MacroAssembler _masm(&cbuf); 3231 Label d; // dummy 3232 __ bind(d); 3233 Label* p = ($lbl$$label); 3234 // `p' is `NULL' when this encoding class is used only to 3235 // determine the size of the encoded instruction. 3236 Label& l = (NULL == p)? d : *(p); 3237 int cc = $cmp$$cmpcode; 3238 int flags_reg = $crx$$reg; 3239 int bhint = Assembler::bhintNoHint; 3240 3241 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3242 if (_prob <= PROB_NEVER) { 3243 bhint = Assembler::bhintIsNotTaken; 3244 } else if (_prob >= PROB_ALWAYS) { 3245 bhint = Assembler::bhintIsTaken; 3246 } 3247 } 3248 3249 // Tell the conditional far branch to optimize itself when being relocated. 3250 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3251 cc_to_biint(cc, flags_reg), 3252 l, 3253 MacroAssembler::bc_far_optimize_on_relocate); 3254 %} 3255 3256 // Branch used with Power6 scheduling (can be shortened without changing the node). 3257 enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{ 3258 // The scheduler doesn't know about branch shortening, so we set the opcode 3259 // to ppc64Opcode_bc in order to hide this detail from the scheduler. 3260 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3261 3262 MacroAssembler _masm(&cbuf); 3263 Label d; // dummy 3264 __ bind(d); 3265 Label* p = ($lbl$$label); 3266 // `p' is `NULL' when this encoding class is used only to 3267 // determine the size of the encoded instruction. 3268 Label& l = (NULL == p)? d : *(p); 3269 int cc = $cmp$$cmpcode; 3270 int flags_reg = $crx$$reg; 3271 int bhint = Assembler::bhintNoHint; 3272 3273 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3274 if (_prob <= PROB_NEVER) { 3275 bhint = Assembler::bhintIsNotTaken; 3276 } else if (_prob >= PROB_ALWAYS) { 3277 bhint = Assembler::bhintIsTaken; 3278 } 3279 } 3280 3281#if 0 // TODO: PPC port 3282 if (_size == 8) { 3283 // Tell the conditional far branch to optimize itself when being relocated. 3284 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3285 cc_to_biint(cc, flags_reg), 3286 l, 3287 MacroAssembler::bc_far_optimize_on_relocate); 3288 } else { 3289 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3290 cc_to_biint(cc, flags_reg), 3291 l); 3292 } 3293#endif 3294 Unimplemented(); 3295 %} 3296 3297 // Postalloc expand emitter for loading a replicatef float constant from 3298 // the method's TOC. 3299 // Enc_class needed as consttanttablebase is not supported by postalloc 3300 // expand. 3301 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{ 3302 // Create new nodes. 3303 3304 // Make an operand with the bit pattern to load as float. 3305 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF())); 3306 3307 loadConLNodesTuple loadConLNodes = 3308 loadConLNodesTuple_create(ra_, n_toc, op_repl, 3309 ra_->get_reg_second(this), ra_->get_reg_first(this)); 3310 3311 // Push new nodes. 3312 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); 3313 if (loadConLNodes._last) nodes->push(loadConLNodes._last); 3314 3315 assert(nodes->length() >= 1, "must have created at least 1 node"); 3316 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); 3317 %} 3318 3319 // This enc_class is needed so that scheduler gets proper 3320 // input mapping for latency computation. 3321 enc_class enc_poll(immI dst, iRegLdst poll) %{ 3322 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 3323 // Fake operand dst needed for PPC scheduler. 3324 assert($dst$$constant == 0x0, "dst must be 0x0"); 3325 3326 MacroAssembler _masm(&cbuf); 3327 // Mark the code position where the load from the safepoint 3328 // polling page was emitted as relocInfo::poll_type. 3329 __ relocate(relocInfo::poll_type); 3330 __ load_from_polling_page($poll$$Register); 3331 %} 3332 3333 // A Java static call or a runtime call. 3334 // 3335 // Branch-and-link relative to a trampoline. 3336 // The trampoline loads the target address and does a long branch to there. 3337 // In case we call java, the trampoline branches to a interpreter_stub 3338 // which loads the inline cache and the real call target from the constant pool. 3339 // 3340 // This basically looks like this: 3341 // 3342 // >>>> consts -+ -+ 3343 // | |- offset1 3344 // [call target1] | <-+ 3345 // [IC cache] |- offset2 3346 // [call target2] <--+ 3347 // 3348 // <<<< consts 3349 // >>>> insts 3350 // 3351 // bl offset16 -+ -+ ??? // How many bits available? 3352 // | | 3353 // <<<< insts | | 3354 // >>>> stubs | | 3355 // | |- trampoline_stub_Reloc 3356 // trampoline stub: | <-+ 3357 // r2 = toc | 3358 // r2 = [r2 + offset1] | // Load call target1 from const section 3359 // mtctr r2 | 3360 // bctr |- static_stub_Reloc 3361 // comp_to_interp_stub: <---+ 3362 // r1 = toc 3363 // ICreg = [r1 + IC_offset] // Load IC from const section 3364 // r1 = [r1 + offset2] // Load call target2 from const section 3365 // mtctr r1 3366 // bctr 3367 // 3368 // <<<< stubs 3369 // 3370 // The call instruction in the code either 3371 // - Branches directly to a compiled method if the offset is encodable in instruction. 3372 // - Branches to the trampoline stub if the offset to the compiled method is not encodable. 3373 // - Branches to the compiled_to_interp stub if the target is interpreted. 3374 // 3375 // Further there are three relocations from the loads to the constants in 3376 // the constant section. 3377 // 3378 // Usage of r1 and r2 in the stubs allows to distinguish them. 3379 enc_class enc_java_static_call(method meth) %{ 3380 // TODO: PPC port $archOpcode(ppc64Opcode_bl); 3381 3382 MacroAssembler _masm(&cbuf); 3383 address entry_point = (address)$meth$$method; 3384 3385 if (!_method) { 3386 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap. 3387 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type); 3388 } else { 3389 // Remember the offset not the address. 3390 const int start_offset = __ offset(); 3391 // The trampoline stub. 3392 if (!Compile::current()->in_scratch_emit_size()) { 3393 // No entry point given, use the current pc. 3394 // Make sure branch fits into 3395 if (entry_point == 0) entry_point = __ pc(); 3396 3397 // Put the entry point as a constant into the constant pool. 3398 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 3399 if (entry_point_toc_addr == NULL) { 3400 ciEnv::current()->record_out_of_memory_failure(); 3401 return; 3402 } 3403 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 3404 3405 3406 // Emit the trampoline stub which will be related to the branch-and-link below. 3407 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); 3408 if (ciEnv::current()->failing()) { return; } // Code cache may be full. 3409 int method_index = resolved_method_index(cbuf); 3410 __ relocate(_optimized_virtual ? opt_virtual_call_Relocation::spec(method_index) 3411 : static_call_Relocation::spec(method_index)); 3412 } 3413 3414 // The real call. 3415 // Note: At this point we do not have the address of the trampoline 3416 // stub, and the entry point might be too far away for bl, so __ pc() 3417 // serves as dummy and the bl will be patched later. 3418 cbuf.set_insts_mark(); 3419 __ bl(__ pc()); // Emits a relocation. 3420 3421 // The stub for call to interpreter. 3422 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 3423 if (stub == NULL) { 3424 ciEnv::current()->record_failure("CodeCache is full"); 3425 return; 3426 } 3427 } 3428 %} 3429 3430 // Second node of expanded dynamic call - the call. 3431 enc_class enc_java_dynamic_call_sched(method meth) %{ 3432 // TODO: PPC port $archOpcode(ppc64Opcode_bl); 3433 3434 MacroAssembler _masm(&cbuf); 3435 3436 if (!ra_->C->in_scratch_emit_size()) { 3437 // Create a call trampoline stub for the given method. 3438 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method; 3439 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none); 3440 if (entry_point_const == NULL) { 3441 ciEnv::current()->record_out_of_memory_failure(); 3442 return; 3443 } 3444 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const); 3445 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset()); 3446 if (ra_->C->env()->failing()) { return; } // Code cache may be full. 3447 3448 // Build relocation at call site with ic position as data. 3449 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) || 3450 (_load_ic_hi_node == NULL && _load_ic_node != NULL), 3451 "must have one, but can't have both"); 3452 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) || 3453 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1), 3454 "must contain instruction offset"); 3455 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL 3456 ? _load_ic_hi_node->_cbuf_insts_offset 3457 : _load_ic_node->_cbuf_insts_offset; 3458 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset); 3459 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr), 3460 "should be load from TOC"); 3461 int method_index = resolved_method_index(cbuf); 3462 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index)); 3463 } 3464 3465 // At this point I do not have the address of the trampoline stub, 3466 // and the entry point might be too far away for bl. Pc() serves 3467 // as dummy and bl will be patched later. 3468 __ bl((address) __ pc()); 3469 %} 3470 3471 // postalloc expand emitter for virtual calls. 3472 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{ 3473 3474 // Create the nodes for loading the IC from the TOC. 3475 loadConLNodesTuple loadConLNodes_IC = 3476 loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()), 3477 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num)); 3478 3479 // Create the call node. 3480 CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode(); 3481 call->_method_handle_invoke = _method_handle_invoke; 3482 call->_vtable_index = _vtable_index; 3483 call->_method = _method; 3484 call->_bci = _bci; 3485 call->_optimized_virtual = _optimized_virtual; 3486 call->_tf = _tf; 3487 call->_entry_point = _entry_point; 3488 call->_cnt = _cnt; 3489 call->_argsize = _argsize; 3490 call->_oop_map = _oop_map; 3491 call->_jvms = _jvms; 3492 call->_jvmadj = _jvmadj; 3493 call->_in_rms = _in_rms; 3494 call->_nesting = _nesting; 3495 call->_override_symbolic_info = _override_symbolic_info; 3496 3497 // New call needs all inputs of old call. 3498 // Req... 3499 for (uint i = 0; i < req(); ++i) { 3500 // The expanded node does not need toc any more. 3501 // Add the inline cache constant here instead. This expresses the 3502 // register of the inline cache must be live at the call. 3503 // Else we would have to adapt JVMState by -1. 3504 if (i == mach_constant_base_node_input()) { 3505 call->add_req(loadConLNodes_IC._last); 3506 } else { 3507 call->add_req(in(i)); 3508 } 3509 } 3510 // ...as well as prec 3511 for (uint i = req(); i < len(); ++i) { 3512 call->add_prec(in(i)); 3513 } 3514 3515 // Remember nodes loading the inline cache into r19. 3516 call->_load_ic_hi_node = loadConLNodes_IC._large_hi; 3517 call->_load_ic_node = loadConLNodes_IC._small; 3518 3519 // Operands for new nodes. 3520 call->_opnds[0] = _opnds[0]; 3521 call->_opnds[1] = _opnds[1]; 3522 3523 // Only the inline cache is associated with a register. 3524 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19"); 3525 3526 // Push new nodes. 3527 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi); 3528 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last); 3529 nodes->push(call); 3530 %} 3531 3532 // Compound version of call dynamic 3533 // Toc is only passed so that it can be used in ins_encode statement. 3534 // In the code we have to use $constanttablebase. 3535 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{ 3536 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3537 MacroAssembler _masm(&cbuf); 3538 int start_offset = __ offset(); 3539 3540 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC; 3541#if 0 3542 int vtable_index = this->_vtable_index; 3543 if (_vtable_index < 0) { 3544 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 3545 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 3546 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode()); 3547 3548 // Virtual call relocation will point to ic load. 3549 address virtual_call_meta_addr = __ pc(); 3550 // Load a clear inline cache. 3551 AddressLiteral empty_ic((address) Universe::non_oop_word()); 3552 bool success = __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc, /*fixed_size*/ true); 3553 if (!success) { 3554 ciEnv::current()->record_out_of_memory_failure(); 3555 return; 3556 } 3557 // CALL to fixup routine. Fixup routine uses ScopeDesc info 3558 // to determine who we intended to call. 3559 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr)); 3560 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none); 3561 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, 3562 "Fix constant in ret_addr_offset()"); 3563 } else { 3564 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 3565 // Go thru the vtable. Get receiver klass. Receiver already 3566 // checked for non-null. If we'll go thru a C2I adapter, the 3567 // interpreter expects method in R19_method. 3568 3569 __ load_klass(R11_scratch1, R3); 3570 3571 int entry_offset = InstanceKlass::vtable_start_offset() + _vtable_index * vtableEntry::size(); 3572 int v_off = entry_offset * wordSize + vtableEntry::method_offset_in_bytes(); 3573 __ li(R19_method, v_off); 3574 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/); 3575 // NOTE: for vtable dispatches, the vtable entry will never be 3576 // null. However it may very well end up in handle_wrong_method 3577 // if the method is abstract for the particular class. 3578 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method); 3579 // Call target. Either compiled code or C2I adapter. 3580 __ mtctr(R11_scratch1); 3581 __ bctrl(); 3582 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) { 3583 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset); 3584 } 3585 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, 3586 "Fix constant in ret_addr_offset()"); 3587 } 3588#endif 3589 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!). 3590 %} 3591 3592 // a runtime call 3593 enc_class enc_java_to_runtime_call (method meth) %{ 3594 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3595 3596 MacroAssembler _masm(&cbuf); 3597 const address start_pc = __ pc(); 3598 3599#if defined(ABI_ELFv2) 3600 address entry= !($meth$$method) ? NULL : (address)$meth$$method; 3601 __ call_c(entry, relocInfo::runtime_call_type); 3602#else 3603 // The function we're going to call. 3604 FunctionDescriptor fdtemp; 3605 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method; 3606 3607 Register Rtoc = R12_scratch2; 3608 // Calculate the method's TOC. 3609 __ calculate_address_from_global_toc(Rtoc, __ method_toc()); 3610 // Put entry, env, toc into the constant pool, this needs up to 3 constant 3611 // pool entries; call_c_using_toc will optimize the call. 3612 bool success = __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc); 3613 if (!success) { 3614 ciEnv::current()->record_out_of_memory_failure(); 3615 return; 3616 } 3617#endif 3618 3619 // Check the ret_addr_offset. 3620 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc, 3621 "Fix constant in ret_addr_offset()"); 3622 %} 3623 3624 // Move to ctr for leaf call. 3625 // This enc_class is needed so that scheduler gets proper 3626 // input mapping for latency computation. 3627 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{ 3628 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr); 3629 MacroAssembler _masm(&cbuf); 3630 __ mtctr($src$$Register); 3631 %} 3632 3633 // Postalloc expand emitter for runtime leaf calls. 3634 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{ 3635 loadConLNodesTuple loadConLNodes_Entry; 3636#if defined(ABI_ELFv2) 3637 jlong entry_address = (jlong) this->entry_point(); 3638 assert(entry_address, "need address here"); 3639 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address), 3640 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); 3641#else 3642 // Get the struct that describes the function we are about to call. 3643 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point(); 3644 assert(fd, "need fd here"); 3645 jlong entry_address = (jlong) fd->entry(); 3646 // new nodes 3647 loadConLNodesTuple loadConLNodes_Env; 3648 loadConLNodesTuple loadConLNodes_Toc; 3649 3650 // Create nodes and operands for loading the entry point. 3651 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address), 3652 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); 3653 3654 3655 // Create nodes and operands for loading the env pointer. 3656 if (fd->env() != NULL) { 3657 loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()), 3658 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); 3659 } else { 3660 loadConLNodes_Env._large_hi = NULL; 3661 loadConLNodes_Env._large_lo = NULL; 3662 loadConLNodes_Env._small = NULL; 3663 loadConLNodes_Env._last = new loadConL16Node(); 3664 loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper(); 3665 loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0); 3666 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); 3667 } 3668 3669 // Create nodes and operands for loading the Toc point. 3670 loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()), 3671 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num)); 3672#endif // ABI_ELFv2 3673 // mtctr node 3674 MachNode *mtctr = new CallLeafDirect_mtctrNode(); 3675 3676 assert(loadConLNodes_Entry._last != NULL, "entry must exist"); 3677 mtctr->add_req(0, loadConLNodes_Entry._last); 3678 3679 mtctr->_opnds[0] = new iRegLdstOper(); 3680 mtctr->_opnds[1] = new iRegLdstOper(); 3681 3682 // call node 3683 MachCallLeafNode *call = new CallLeafDirectNode(); 3684 3685 call->_opnds[0] = _opnds[0]; 3686 call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later. 3687 3688 // Make the new call node look like the old one. 3689 call->_name = _name; 3690 call->_tf = _tf; 3691 call->_entry_point = _entry_point; 3692 call->_cnt = _cnt; 3693 call->_argsize = _argsize; 3694 call->_oop_map = _oop_map; 3695 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms()."); 3696 call->_jvms = NULL; 3697 call->_jvmadj = _jvmadj; 3698 call->_in_rms = _in_rms; 3699 call->_nesting = _nesting; 3700 3701 3702 // New call needs all inputs of old call. 3703 // Req... 3704 for (uint i = 0; i < req(); ++i) { 3705 if (i != mach_constant_base_node_input()) { 3706 call->add_req(in(i)); 3707 } 3708 } 3709 3710 // These must be reqired edges, as the registers are live up to 3711 // the call. Else the constants are handled as kills. 3712 call->add_req(mtctr); 3713#if !defined(ABI_ELFv2) 3714 call->add_req(loadConLNodes_Env._last); 3715 call->add_req(loadConLNodes_Toc._last); 3716#endif 3717 3718 // ...as well as prec 3719 for (uint i = req(); i < len(); ++i) { 3720 call->add_prec(in(i)); 3721 } 3722 3723 // registers 3724 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num)); 3725 3726 // Insert the new nodes. 3727 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi); 3728 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last); 3729#if !defined(ABI_ELFv2) 3730 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi); 3731 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last); 3732 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi); 3733 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last); 3734#endif 3735 nodes->push(mtctr); 3736 nodes->push(call); 3737 %} 3738%} 3739 3740//----------FRAME-------------------------------------------------------------- 3741// Definition of frame structure and management information. 3742 3743frame %{ 3744 // What direction does stack grow in (assumed to be same for native & Java). 3745 stack_direction(TOWARDS_LOW); 3746 3747 // These two registers define part of the calling convention between 3748 // compiled code and the interpreter. 3749 3750 // Inline Cache Register or method for I2C. 3751 inline_cache_reg(R19); // R19_method 3752 3753 // Method Oop Register when calling interpreter. 3754 interpreter_method_oop_reg(R19); // R19_method 3755 3756 // Optional: name the operand used by cisc-spilling to access 3757 // [stack_pointer + offset]. 3758 cisc_spilling_operand_name(indOffset); 3759 3760 // Number of stack slots consumed by a Monitor enter. 3761 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size)); 3762 3763 // Compiled code's Frame Pointer. 3764 frame_pointer(R1); // R1_SP 3765 3766 // Interpreter stores its frame pointer in a register which is 3767 // stored to the stack by I2CAdaptors. I2CAdaptors convert from 3768 // interpreted java to compiled java. 3769 // 3770 // R14_state holds pointer to caller's cInterpreter. 3771 interpreter_frame_pointer(R14); // R14_state 3772 3773 stack_alignment(frame::alignment_in_bytes); 3774 3775 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size)); 3776 3777 // Number of outgoing stack slots killed above the 3778 // out_preserve_stack_slots for calls to C. Supports the var-args 3779 // backing area for register parms. 3780 // 3781 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size)); 3782 3783 // The after-PROLOG location of the return address. Location of 3784 // return address specifies a type (REG or STACK) and a number 3785 // representing the register number (i.e. - use a register name) or 3786 // stack slot. 3787 // 3788 // A: Link register is stored in stack slot ... 3789 // M: ... but it's in the caller's frame according to PPC-64 ABI. 3790 // J: Therefore, we make sure that the link register is also in R11_scratch1 3791 // at the end of the prolog. 3792 // B: We use R20, now. 3793 //return_addr(REG R20); 3794 3795 // G: After reading the comments made by all the luminaries on their 3796 // failure to tell the compiler where the return address really is, 3797 // I hardly dare to try myself. However, I'm convinced it's in slot 3798 // 4 what apparently works and saves us some spills. 3799 return_addr(STACK 4); 3800 3801 // This is the body of the function 3802 // 3803 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs 3804 // uint length, // length of array 3805 // bool is_outgoing) 3806 // 3807 // The `sig' array is to be updated. sig[j] represents the location 3808 // of the j-th argument, either a register or a stack slot. 3809 3810 // Comment taken from i486.ad: 3811 // Body of function which returns an integer array locating 3812 // arguments either in registers or in stack slots. Passed an array 3813 // of ideal registers called "sig" and a "length" count. Stack-slot 3814 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3815 // arguments for a CALLEE. Incoming stack arguments are 3816 // automatically biased by the preserve_stack_slots field above. 3817 calling_convention %{ 3818 // No difference between ingoing/outgoing. Just pass false. 3819 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 3820 %} 3821 3822 // Comment taken from i486.ad: 3823 // Body of function which returns an integer array locating 3824 // arguments either in registers or in stack slots. Passed an array 3825 // of ideal registers called "sig" and a "length" count. Stack-slot 3826 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3827 // arguments for a CALLEE. Incoming stack arguments are 3828 // automatically biased by the preserve_stack_slots field above. 3829 c_calling_convention %{ 3830 // This is obviously always outgoing. 3831 // C argument in register AND stack slot. 3832 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 3833 %} 3834 3835 // Location of native (C/C++) and interpreter return values. This 3836 // is specified to be the same as Java. In the 32-bit VM, long 3837 // values are actually returned from native calls in O0:O1 and 3838 // returned to the interpreter in I0:I1. The copying to and from 3839 // the register pairs is done by the appropriate call and epilog 3840 // opcodes. This simplifies the register allocator. 3841 c_return_value %{ 3842 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || 3843 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), 3844 "only return normal values"); 3845 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL 3846 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; 3847 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; 3848 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 3849 %} 3850 3851 // Location of compiled Java return values. Same as C 3852 return_value %{ 3853 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || 3854 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), 3855 "only return normal values"); 3856 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL 3857 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; 3858 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; 3859 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 3860 %} 3861%} 3862 3863 3864//----------ATTRIBUTES--------------------------------------------------------- 3865 3866//----------Operand Attributes------------------------------------------------- 3867op_attrib op_cost(1); // Required cost attribute. 3868 3869//----------Instruction Attributes--------------------------------------------- 3870 3871// Cost attribute. required. 3872ins_attrib ins_cost(DEFAULT_COST); 3873 3874// Is this instruction a non-matching short branch variant of some 3875// long branch? Not required. 3876ins_attrib ins_short_branch(0); 3877 3878ins_attrib ins_is_TrapBasedCheckNode(true); 3879 3880// Number of constants. 3881// This instruction uses the given number of constants 3882// (optional attribute). 3883// This is needed to determine in time whether the constant pool will 3884// exceed 4000 entries. Before postalloc_expand the overall number of constants 3885// is determined. It's also used to compute the constant pool size 3886// in Output(). 3887ins_attrib ins_num_consts(0); 3888 3889// Required alignment attribute (must be a power of 2) specifies the 3890// alignment that some part of the instruction (not necessarily the 3891// start) requires. If > 1, a compute_padding() function must be 3892// provided for the instruction. 3893ins_attrib ins_alignment(1); 3894 3895// Enforce/prohibit rematerializations. 3896// - If an instruction is attributed with 'ins_cannot_rematerialize(true)' 3897// then rematerialization of that instruction is prohibited and the 3898// instruction's value will be spilled if necessary. 3899// Causes that MachNode::rematerialize() returns false. 3900// - If an instruction is attributed with 'ins_should_rematerialize(true)' 3901// then rematerialization should be enforced and a copy of the instruction 3902// should be inserted if possible; rematerialization is not guaranteed. 3903// Note: this may result in rematerializations in front of every use. 3904// Causes that MachNode::rematerialize() can return true. 3905// (optional attribute) 3906ins_attrib ins_cannot_rematerialize(false); 3907ins_attrib ins_should_rematerialize(false); 3908 3909// Instruction has variable size depending on alignment. 3910ins_attrib ins_variable_size_depending_on_alignment(false); 3911 3912// Instruction is a nop. 3913ins_attrib ins_is_nop(false); 3914 3915// Instruction is mapped to a MachIfFastLock node (instead of MachFastLock). 3916ins_attrib ins_use_mach_if_fast_lock_node(false); 3917 3918// Field for the toc offset of a constant. 3919// 3920// This is needed if the toc offset is not encodable as an immediate in 3921// the PPC load instruction. If so, the upper (hi) bits of the offset are 3922// added to the toc, and from this a load with immediate is performed. 3923// With postalloc expand, we get two nodes that require the same offset 3924// but which don't know about each other. The offset is only known 3925// when the constant is added to the constant pool during emitting. 3926// It is generated in the 'hi'-node adding the upper bits, and saved 3927// in this node. The 'lo'-node has a link to the 'hi'-node and reads 3928// the offset from there when it gets encoded. 3929ins_attrib ins_field_const_toc_offset(0); 3930ins_attrib ins_field_const_toc_offset_hi_node(0); 3931 3932// A field that can hold the instructions offset in the code buffer. 3933// Set in the nodes emitter. 3934ins_attrib ins_field_cbuf_insts_offset(-1); 3935 3936// Fields for referencing a call's load-IC-node. 3937// If the toc offset can not be encoded as an immediate in a load, we 3938// use two nodes. 3939ins_attrib ins_field_load_ic_hi_node(0); 3940ins_attrib ins_field_load_ic_node(0); 3941 3942//----------OPERANDS----------------------------------------------------------- 3943// Operand definitions must precede instruction definitions for correct 3944// parsing in the ADLC because operands constitute user defined types 3945// which are used in instruction definitions. 3946// 3947// Formats are generated automatically for constants and base registers. 3948 3949//----------Simple Operands---------------------------------------------------- 3950// Immediate Operands 3951 3952// Integer Immediate: 32-bit 3953operand immI() %{ 3954 match(ConI); 3955 op_cost(40); 3956 format %{ %} 3957 interface(CONST_INTER); 3958%} 3959 3960operand immI8() %{ 3961 predicate(Assembler::is_simm(n->get_int(), 8)); 3962 op_cost(0); 3963 match(ConI); 3964 format %{ %} 3965 interface(CONST_INTER); 3966%} 3967 3968// Integer Immediate: 16-bit 3969operand immI16() %{ 3970 predicate(Assembler::is_simm(n->get_int(), 16)); 3971 op_cost(0); 3972 match(ConI); 3973 format %{ %} 3974 interface(CONST_INTER); 3975%} 3976 3977// Integer Immediate: 32-bit, where lowest 16 bits are 0x0000. 3978operand immIhi16() %{ 3979 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0)); 3980 match(ConI); 3981 op_cost(0); 3982 format %{ %} 3983 interface(CONST_INTER); 3984%} 3985 3986operand immInegpow2() %{ 3987 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int())))); 3988 match(ConI); 3989 op_cost(0); 3990 format %{ %} 3991 interface(CONST_INTER); 3992%} 3993 3994operand immIpow2minus1() %{ 3995 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1))); 3996 match(ConI); 3997 op_cost(0); 3998 format %{ %} 3999 interface(CONST_INTER); 4000%} 4001 4002operand immIpowerOf2() %{ 4003 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int()))))); 4004 match(ConI); 4005 op_cost(0); 4006 format %{ %} 4007 interface(CONST_INTER); 4008%} 4009 4010// Unsigned Integer Immediate: the values 0-31 4011operand uimmI5() %{ 4012 predicate(Assembler::is_uimm(n->get_int(), 5)); 4013 match(ConI); 4014 op_cost(0); 4015 format %{ %} 4016 interface(CONST_INTER); 4017%} 4018 4019// Unsigned Integer Immediate: 6-bit 4020operand uimmI6() %{ 4021 predicate(Assembler::is_uimm(n->get_int(), 6)); 4022 match(ConI); 4023 op_cost(0); 4024 format %{ %} 4025 interface(CONST_INTER); 4026%} 4027 4028// Unsigned Integer Immediate: 6-bit int, greater than 32 4029operand uimmI6_ge32() %{ 4030 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32); 4031 match(ConI); 4032 op_cost(0); 4033 format %{ %} 4034 interface(CONST_INTER); 4035%} 4036 4037// Unsigned Integer Immediate: 15-bit 4038operand uimmI15() %{ 4039 predicate(Assembler::is_uimm(n->get_int(), 15)); 4040 match(ConI); 4041 op_cost(0); 4042 format %{ %} 4043 interface(CONST_INTER); 4044%} 4045 4046// Unsigned Integer Immediate: 16-bit 4047operand uimmI16() %{ 4048 predicate(Assembler::is_uimm(n->get_int(), 16)); 4049 match(ConI); 4050 op_cost(0); 4051 format %{ %} 4052 interface(CONST_INTER); 4053%} 4054 4055// constant 'int 0'. 4056operand immI_0() %{ 4057 predicate(n->get_int() == 0); 4058 match(ConI); 4059 op_cost(0); 4060 format %{ %} 4061 interface(CONST_INTER); 4062%} 4063 4064// constant 'int 1'. 4065operand immI_1() %{ 4066 predicate(n->get_int() == 1); 4067 match(ConI); 4068 op_cost(0); 4069 format %{ %} 4070 interface(CONST_INTER); 4071%} 4072 4073// constant 'int -1'. 4074operand immI_minus1() %{ 4075 predicate(n->get_int() == -1); 4076 match(ConI); 4077 op_cost(0); 4078 format %{ %} 4079 interface(CONST_INTER); 4080%} 4081 4082// int value 16. 4083operand immI_16() %{ 4084 predicate(n->get_int() == 16); 4085 match(ConI); 4086 op_cost(0); 4087 format %{ %} 4088 interface(CONST_INTER); 4089%} 4090 4091// int value 24. 4092operand immI_24() %{ 4093 predicate(n->get_int() == 24); 4094 match(ConI); 4095 op_cost(0); 4096 format %{ %} 4097 interface(CONST_INTER); 4098%} 4099 4100// Compressed oops constants 4101// Pointer Immediate 4102operand immN() %{ 4103 match(ConN); 4104 4105 op_cost(10); 4106 format %{ %} 4107 interface(CONST_INTER); 4108%} 4109 4110// NULL Pointer Immediate 4111operand immN_0() %{ 4112 predicate(n->get_narrowcon() == 0); 4113 match(ConN); 4114 4115 op_cost(0); 4116 format %{ %} 4117 interface(CONST_INTER); 4118%} 4119 4120// Compressed klass constants 4121operand immNKlass() %{ 4122 match(ConNKlass); 4123 4124 op_cost(0); 4125 format %{ %} 4126 interface(CONST_INTER); 4127%} 4128 4129// This operand can be used to avoid matching of an instruct 4130// with chain rule. 4131operand immNKlass_NM() %{ 4132 match(ConNKlass); 4133 predicate(false); 4134 op_cost(0); 4135 format %{ %} 4136 interface(CONST_INTER); 4137%} 4138 4139// Pointer Immediate: 64-bit 4140operand immP() %{ 4141 match(ConP); 4142 op_cost(0); 4143 format %{ %} 4144 interface(CONST_INTER); 4145%} 4146 4147// Operand to avoid match of loadConP. 4148// This operand can be used to avoid matching of an instruct 4149// with chain rule. 4150operand immP_NM() %{ 4151 match(ConP); 4152 predicate(false); 4153 op_cost(0); 4154 format %{ %} 4155 interface(CONST_INTER); 4156%} 4157 4158// costant 'pointer 0'. 4159operand immP_0() %{ 4160 predicate(n->get_ptr() == 0); 4161 match(ConP); 4162 op_cost(0); 4163 format %{ %} 4164 interface(CONST_INTER); 4165%} 4166 4167// pointer 0x0 or 0x1 4168operand immP_0or1() %{ 4169 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1)); 4170 match(ConP); 4171 op_cost(0); 4172 format %{ %} 4173 interface(CONST_INTER); 4174%} 4175 4176operand immL() %{ 4177 match(ConL); 4178 op_cost(40); 4179 format %{ %} 4180 interface(CONST_INTER); 4181%} 4182 4183// Long Immediate: 16-bit 4184operand immL16() %{ 4185 predicate(Assembler::is_simm(n->get_long(), 16)); 4186 match(ConL); 4187 op_cost(0); 4188 format %{ %} 4189 interface(CONST_INTER); 4190%} 4191 4192// Long Immediate: 16-bit, 4-aligned 4193operand immL16Alg4() %{ 4194 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0)); 4195 match(ConL); 4196 op_cost(0); 4197 format %{ %} 4198 interface(CONST_INTER); 4199%} 4200 4201// Long Immediate: 32-bit, where lowest 16 bits are 0x0000. 4202operand immL32hi16() %{ 4203 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L)); 4204 match(ConL); 4205 op_cost(0); 4206 format %{ %} 4207 interface(CONST_INTER); 4208%} 4209 4210// Long Immediate: 32-bit 4211operand immL32() %{ 4212 predicate(Assembler::is_simm(n->get_long(), 32)); 4213 match(ConL); 4214 op_cost(0); 4215 format %{ %} 4216 interface(CONST_INTER); 4217%} 4218 4219// Long Immediate: 64-bit, where highest 16 bits are not 0x0000. 4220operand immLhighest16() %{ 4221 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L); 4222 match(ConL); 4223 op_cost(0); 4224 format %{ %} 4225 interface(CONST_INTER); 4226%} 4227 4228operand immLnegpow2() %{ 4229 predicate(is_power_of_2_long((jlong)-(n->get_long()))); 4230 match(ConL); 4231 op_cost(0); 4232 format %{ %} 4233 interface(CONST_INTER); 4234%} 4235 4236operand immLpow2minus1() %{ 4237 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) && 4238 (n->get_long() != (jlong)0xffffffffffffffffL)); 4239 match(ConL); 4240 op_cost(0); 4241 format %{ %} 4242 interface(CONST_INTER); 4243%} 4244 4245// constant 'long 0'. 4246operand immL_0() %{ 4247 predicate(n->get_long() == 0L); 4248 match(ConL); 4249 op_cost(0); 4250 format %{ %} 4251 interface(CONST_INTER); 4252%} 4253 4254// constat ' long -1'. 4255operand immL_minus1() %{ 4256 predicate(n->get_long() == -1L); 4257 match(ConL); 4258 op_cost(0); 4259 format %{ %} 4260 interface(CONST_INTER); 4261%} 4262 4263// Long Immediate: low 32-bit mask 4264operand immL_32bits() %{ 4265 predicate(n->get_long() == 0xFFFFFFFFL); 4266 match(ConL); 4267 op_cost(0); 4268 format %{ %} 4269 interface(CONST_INTER); 4270%} 4271 4272// Unsigned Long Immediate: 16-bit 4273operand uimmL16() %{ 4274 predicate(Assembler::is_uimm(n->get_long(), 16)); 4275 match(ConL); 4276 op_cost(0); 4277 format %{ %} 4278 interface(CONST_INTER); 4279%} 4280 4281// Float Immediate 4282operand immF() %{ 4283 match(ConF); 4284 op_cost(40); 4285 format %{ %} 4286 interface(CONST_INTER); 4287%} 4288 4289// Float Immediate: +0.0f. 4290operand immF_0() %{ 4291 predicate(jint_cast(n->getf()) == 0); 4292 match(ConF); 4293 4294 op_cost(0); 4295 format %{ %} 4296 interface(CONST_INTER); 4297%} 4298 4299// Double Immediate 4300operand immD() %{ 4301 match(ConD); 4302 op_cost(40); 4303 format %{ %} 4304 interface(CONST_INTER); 4305%} 4306 4307// Integer Register Operands 4308// Integer Destination Register 4309// See definition of reg_class bits32_reg_rw. 4310operand iRegIdst() %{ 4311 constraint(ALLOC_IN_RC(bits32_reg_rw)); 4312 match(RegI); 4313 match(rscratch1RegI); 4314 match(rscratch2RegI); 4315 match(rarg1RegI); 4316 match(rarg2RegI); 4317 match(rarg3RegI); 4318 match(rarg4RegI); 4319 format %{ %} 4320 interface(REG_INTER); 4321%} 4322 4323// Integer Source Register 4324// See definition of reg_class bits32_reg_ro. 4325operand iRegIsrc() %{ 4326 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4327 match(RegI); 4328 match(rscratch1RegI); 4329 match(rscratch2RegI); 4330 match(rarg1RegI); 4331 match(rarg2RegI); 4332 match(rarg3RegI); 4333 match(rarg4RegI); 4334 format %{ %} 4335 interface(REG_INTER); 4336%} 4337 4338operand rscratch1RegI() %{ 4339 constraint(ALLOC_IN_RC(rscratch1_bits32_reg)); 4340 match(iRegIdst); 4341 format %{ %} 4342 interface(REG_INTER); 4343%} 4344 4345operand rscratch2RegI() %{ 4346 constraint(ALLOC_IN_RC(rscratch2_bits32_reg)); 4347 match(iRegIdst); 4348 format %{ %} 4349 interface(REG_INTER); 4350%} 4351 4352operand rarg1RegI() %{ 4353 constraint(ALLOC_IN_RC(rarg1_bits32_reg)); 4354 match(iRegIdst); 4355 format %{ %} 4356 interface(REG_INTER); 4357%} 4358 4359operand rarg2RegI() %{ 4360 constraint(ALLOC_IN_RC(rarg2_bits32_reg)); 4361 match(iRegIdst); 4362 format %{ %} 4363 interface(REG_INTER); 4364%} 4365 4366operand rarg3RegI() %{ 4367 constraint(ALLOC_IN_RC(rarg3_bits32_reg)); 4368 match(iRegIdst); 4369 format %{ %} 4370 interface(REG_INTER); 4371%} 4372 4373operand rarg4RegI() %{ 4374 constraint(ALLOC_IN_RC(rarg4_bits32_reg)); 4375 match(iRegIdst); 4376 format %{ %} 4377 interface(REG_INTER); 4378%} 4379 4380operand rarg1RegL() %{ 4381 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); 4382 match(iRegLdst); 4383 format %{ %} 4384 interface(REG_INTER); 4385%} 4386 4387operand rarg2RegL() %{ 4388 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); 4389 match(iRegLdst); 4390 format %{ %} 4391 interface(REG_INTER); 4392%} 4393 4394operand rarg3RegL() %{ 4395 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); 4396 match(iRegLdst); 4397 format %{ %} 4398 interface(REG_INTER); 4399%} 4400 4401operand rarg4RegL() %{ 4402 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); 4403 match(iRegLdst); 4404 format %{ %} 4405 interface(REG_INTER); 4406%} 4407 4408// Pointer Destination Register 4409// See definition of reg_class bits64_reg_rw. 4410operand iRegPdst() %{ 4411 constraint(ALLOC_IN_RC(bits64_reg_rw)); 4412 match(RegP); 4413 match(rscratch1RegP); 4414 match(rscratch2RegP); 4415 match(rarg1RegP); 4416 match(rarg2RegP); 4417 match(rarg3RegP); 4418 match(rarg4RegP); 4419 format %{ %} 4420 interface(REG_INTER); 4421%} 4422 4423// Pointer Destination Register 4424// Operand not using r11 and r12 (killed in epilog). 4425operand iRegPdstNoScratch() %{ 4426 constraint(ALLOC_IN_RC(bits64_reg_leaf_call)); 4427 match(RegP); 4428 match(rarg1RegP); 4429 match(rarg2RegP); 4430 match(rarg3RegP); 4431 match(rarg4RegP); 4432 format %{ %} 4433 interface(REG_INTER); 4434%} 4435 4436// Pointer Source Register 4437// See definition of reg_class bits64_reg_ro. 4438operand iRegPsrc() %{ 4439 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4440 match(RegP); 4441 match(iRegPdst); 4442 match(rscratch1RegP); 4443 match(rscratch2RegP); 4444 match(rarg1RegP); 4445 match(rarg2RegP); 4446 match(rarg3RegP); 4447 match(rarg4RegP); 4448 match(threadRegP); 4449 format %{ %} 4450 interface(REG_INTER); 4451%} 4452 4453// Thread operand. 4454operand threadRegP() %{ 4455 constraint(ALLOC_IN_RC(thread_bits64_reg)); 4456 match(iRegPdst); 4457 format %{ "R16" %} 4458 interface(REG_INTER); 4459%} 4460 4461operand rscratch1RegP() %{ 4462 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); 4463 match(iRegPdst); 4464 format %{ "R11" %} 4465 interface(REG_INTER); 4466%} 4467 4468operand rscratch2RegP() %{ 4469 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); 4470 match(iRegPdst); 4471 format %{ %} 4472 interface(REG_INTER); 4473%} 4474 4475operand rarg1RegP() %{ 4476 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); 4477 match(iRegPdst); 4478 format %{ %} 4479 interface(REG_INTER); 4480%} 4481 4482operand rarg2RegP() %{ 4483 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); 4484 match(iRegPdst); 4485 format %{ %} 4486 interface(REG_INTER); 4487%} 4488 4489operand rarg3RegP() %{ 4490 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); 4491 match(iRegPdst); 4492 format %{ %} 4493 interface(REG_INTER); 4494%} 4495 4496operand rarg4RegP() %{ 4497 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); 4498 match(iRegPdst); 4499 format %{ %} 4500 interface(REG_INTER); 4501%} 4502 4503operand iRegNsrc() %{ 4504 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4505 match(RegN); 4506 match(iRegNdst); 4507 4508 format %{ %} 4509 interface(REG_INTER); 4510%} 4511 4512operand iRegNdst() %{ 4513 constraint(ALLOC_IN_RC(bits32_reg_rw)); 4514 match(RegN); 4515 4516 format %{ %} 4517 interface(REG_INTER); 4518%} 4519 4520// Long Destination Register 4521// See definition of reg_class bits64_reg_rw. 4522operand iRegLdst() %{ 4523 constraint(ALLOC_IN_RC(bits64_reg_rw)); 4524 match(RegL); 4525 match(rscratch1RegL); 4526 match(rscratch2RegL); 4527 format %{ %} 4528 interface(REG_INTER); 4529%} 4530 4531// Long Source Register 4532// See definition of reg_class bits64_reg_ro. 4533operand iRegLsrc() %{ 4534 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4535 match(RegL); 4536 match(iRegLdst); 4537 match(rscratch1RegL); 4538 match(rscratch2RegL); 4539 format %{ %} 4540 interface(REG_INTER); 4541%} 4542 4543// Special operand for ConvL2I. 4544operand iRegL2Isrc(iRegLsrc reg) %{ 4545 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4546 match(ConvL2I reg); 4547 format %{ "ConvL2I($reg)" %} 4548 interface(REG_INTER) 4549%} 4550 4551operand rscratch1RegL() %{ 4552 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); 4553 match(RegL); 4554 format %{ %} 4555 interface(REG_INTER); 4556%} 4557 4558operand rscratch2RegL() %{ 4559 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); 4560 match(RegL); 4561 format %{ %} 4562 interface(REG_INTER); 4563%} 4564 4565// Condition Code Flag Registers 4566operand flagsReg() %{ 4567 constraint(ALLOC_IN_RC(int_flags)); 4568 match(RegFlags); 4569 format %{ %} 4570 interface(REG_INTER); 4571%} 4572 4573operand flagsRegSrc() %{ 4574 constraint(ALLOC_IN_RC(int_flags_ro)); 4575 match(RegFlags); 4576 match(flagsReg); 4577 match(flagsRegCR0); 4578 format %{ %} 4579 interface(REG_INTER); 4580%} 4581 4582// Condition Code Flag Register CR0 4583operand flagsRegCR0() %{ 4584 constraint(ALLOC_IN_RC(int_flags_CR0)); 4585 match(RegFlags); 4586 format %{ "CR0" %} 4587 interface(REG_INTER); 4588%} 4589 4590operand flagsRegCR1() %{ 4591 constraint(ALLOC_IN_RC(int_flags_CR1)); 4592 match(RegFlags); 4593 format %{ "CR1" %} 4594 interface(REG_INTER); 4595%} 4596 4597operand flagsRegCR6() %{ 4598 constraint(ALLOC_IN_RC(int_flags_CR6)); 4599 match(RegFlags); 4600 format %{ "CR6" %} 4601 interface(REG_INTER); 4602%} 4603 4604operand regCTR() %{ 4605 constraint(ALLOC_IN_RC(ctr_reg)); 4606 // RegFlags should work. Introducing a RegSpecial type would cause a 4607 // lot of changes. 4608 match(RegFlags); 4609 format %{"SR_CTR" %} 4610 interface(REG_INTER); 4611%} 4612 4613operand regD() %{ 4614 constraint(ALLOC_IN_RC(dbl_reg)); 4615 match(RegD); 4616 format %{ %} 4617 interface(REG_INTER); 4618%} 4619 4620operand regF() %{ 4621 constraint(ALLOC_IN_RC(flt_reg)); 4622 match(RegF); 4623 format %{ %} 4624 interface(REG_INTER); 4625%} 4626 4627// Special Registers 4628 4629// Method Register 4630operand inline_cache_regP(iRegPdst reg) %{ 4631 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg 4632 match(reg); 4633 format %{ %} 4634 interface(REG_INTER); 4635%} 4636 4637operand compiler_method_oop_regP(iRegPdst reg) %{ 4638 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg 4639 match(reg); 4640 format %{ %} 4641 interface(REG_INTER); 4642%} 4643 4644operand interpreter_method_oop_regP(iRegPdst reg) %{ 4645 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg 4646 match(reg); 4647 format %{ %} 4648 interface(REG_INTER); 4649%} 4650 4651// Operands to remove register moves in unscaled mode. 4652// Match read/write registers with an EncodeP node if neither shift nor add are required. 4653operand iRegP2N(iRegPsrc reg) %{ 4654 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0); 4655 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4656 match(EncodeP reg); 4657 format %{ "$reg" %} 4658 interface(REG_INTER) 4659%} 4660 4661operand iRegN2P(iRegNsrc reg) %{ 4662 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4663 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4664 match(DecodeN reg); 4665 format %{ "$reg" %} 4666 interface(REG_INTER) 4667%} 4668 4669operand iRegN2P_klass(iRegNsrc reg) %{ 4670 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4671 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4672 match(DecodeNKlass reg); 4673 format %{ "$reg" %} 4674 interface(REG_INTER) 4675%} 4676 4677//----------Complex Operands--------------------------------------------------- 4678// Indirect Memory Reference 4679operand indirect(iRegPsrc reg) %{ 4680 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4681 match(reg); 4682 op_cost(100); 4683 format %{ "[$reg]" %} 4684 interface(MEMORY_INTER) %{ 4685 base($reg); 4686 index(0x0); 4687 scale(0x0); 4688 disp(0x0); 4689 %} 4690%} 4691 4692// Indirect with Offset 4693operand indOffset16(iRegPsrc reg, immL16 offset) %{ 4694 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4695 match(AddP reg offset); 4696 op_cost(100); 4697 format %{ "[$reg + $offset]" %} 4698 interface(MEMORY_INTER) %{ 4699 base($reg); 4700 index(0x0); 4701 scale(0x0); 4702 disp($offset); 4703 %} 4704%} 4705 4706// Indirect with 4-aligned Offset 4707operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{ 4708 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4709 match(AddP reg offset); 4710 op_cost(100); 4711 format %{ "[$reg + $offset]" %} 4712 interface(MEMORY_INTER) %{ 4713 base($reg); 4714 index(0x0); 4715 scale(0x0); 4716 disp($offset); 4717 %} 4718%} 4719 4720//----------Complex Operands for Compressed OOPs------------------------------- 4721// Compressed OOPs with narrow_oop_shift == 0. 4722 4723// Indirect Memory Reference, compressed OOP 4724operand indirectNarrow(iRegNsrc reg) %{ 4725 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4726 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4727 match(DecodeN reg); 4728 op_cost(100); 4729 format %{ "[$reg]" %} 4730 interface(MEMORY_INTER) %{ 4731 base($reg); 4732 index(0x0); 4733 scale(0x0); 4734 disp(0x0); 4735 %} 4736%} 4737 4738operand indirectNarrow_klass(iRegNsrc reg) %{ 4739 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4740 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4741 match(DecodeNKlass reg); 4742 op_cost(100); 4743 format %{ "[$reg]" %} 4744 interface(MEMORY_INTER) %{ 4745 base($reg); 4746 index(0x0); 4747 scale(0x0); 4748 disp(0x0); 4749 %} 4750%} 4751 4752// Indirect with Offset, compressed OOP 4753operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{ 4754 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4755 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4756 match(AddP (DecodeN reg) offset); 4757 op_cost(100); 4758 format %{ "[$reg + $offset]" %} 4759 interface(MEMORY_INTER) %{ 4760 base($reg); 4761 index(0x0); 4762 scale(0x0); 4763 disp($offset); 4764 %} 4765%} 4766 4767operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{ 4768 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4769 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4770 match(AddP (DecodeNKlass reg) offset); 4771 op_cost(100); 4772 format %{ "[$reg + $offset]" %} 4773 interface(MEMORY_INTER) %{ 4774 base($reg); 4775 index(0x0); 4776 scale(0x0); 4777 disp($offset); 4778 %} 4779%} 4780 4781// Indirect with 4-aligned Offset, compressed OOP 4782operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{ 4783 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4784 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4785 match(AddP (DecodeN reg) offset); 4786 op_cost(100); 4787 format %{ "[$reg + $offset]" %} 4788 interface(MEMORY_INTER) %{ 4789 base($reg); 4790 index(0x0); 4791 scale(0x0); 4792 disp($offset); 4793 %} 4794%} 4795 4796operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{ 4797 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4798 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4799 match(AddP (DecodeNKlass reg) offset); 4800 op_cost(100); 4801 format %{ "[$reg + $offset]" %} 4802 interface(MEMORY_INTER) %{ 4803 base($reg); 4804 index(0x0); 4805 scale(0x0); 4806 disp($offset); 4807 %} 4808%} 4809 4810//----------Special Memory Operands-------------------------------------------- 4811// Stack Slot Operand 4812// 4813// This operand is used for loading and storing temporary values on 4814// the stack where a match requires a value to flow through memory. 4815operand stackSlotI(sRegI reg) %{ 4816 constraint(ALLOC_IN_RC(stack_slots)); 4817 op_cost(100); 4818 //match(RegI); 4819 format %{ "[sp+$reg]" %} 4820 interface(MEMORY_INTER) %{ 4821 base(0x1); // R1_SP 4822 index(0x0); 4823 scale(0x0); 4824 disp($reg); // Stack Offset 4825 %} 4826%} 4827 4828operand stackSlotL(sRegL reg) %{ 4829 constraint(ALLOC_IN_RC(stack_slots)); 4830 op_cost(100); 4831 //match(RegL); 4832 format %{ "[sp+$reg]" %} 4833 interface(MEMORY_INTER) %{ 4834 base(0x1); // R1_SP 4835 index(0x0); 4836 scale(0x0); 4837 disp($reg); // Stack Offset 4838 %} 4839%} 4840 4841operand stackSlotP(sRegP reg) %{ 4842 constraint(ALLOC_IN_RC(stack_slots)); 4843 op_cost(100); 4844 //match(RegP); 4845 format %{ "[sp+$reg]" %} 4846 interface(MEMORY_INTER) %{ 4847 base(0x1); // R1_SP 4848 index(0x0); 4849 scale(0x0); 4850 disp($reg); // Stack Offset 4851 %} 4852%} 4853 4854operand stackSlotF(sRegF reg) %{ 4855 constraint(ALLOC_IN_RC(stack_slots)); 4856 op_cost(100); 4857 //match(RegF); 4858 format %{ "[sp+$reg]" %} 4859 interface(MEMORY_INTER) %{ 4860 base(0x1); // R1_SP 4861 index(0x0); 4862 scale(0x0); 4863 disp($reg); // Stack Offset 4864 %} 4865%} 4866 4867operand stackSlotD(sRegD reg) %{ 4868 constraint(ALLOC_IN_RC(stack_slots)); 4869 op_cost(100); 4870 //match(RegD); 4871 format %{ "[sp+$reg]" %} 4872 interface(MEMORY_INTER) %{ 4873 base(0x1); // R1_SP 4874 index(0x0); 4875 scale(0x0); 4876 disp($reg); // Stack Offset 4877 %} 4878%} 4879 4880// Operands for expressing Control Flow 4881// NOTE: Label is a predefined operand which should not be redefined in 4882// the AD file. It is generically handled within the ADLC. 4883 4884//----------Conditional Branch Operands---------------------------------------- 4885// Comparison Op 4886// 4887// This is the operation of the comparison, and is limited to the 4888// following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE 4889// (!=). 4890// 4891// Other attributes of the comparison, such as unsignedness, are specified 4892// by the comparison instruction that sets a condition code flags register. 4893// That result is represented by a flags operand whose subtype is appropriate 4894// to the unsignedness (etc.) of the comparison. 4895// 4896// Later, the instruction which matches both the Comparison Op (a Bool) and 4897// the flags (produced by the Cmp) specifies the coding of the comparison op 4898// by matching a specific subtype of Bool operand below. 4899 4900// When used for floating point comparisons: unordered same as less. 4901operand cmpOp() %{ 4902 match(Bool); 4903 format %{ "" %} 4904 interface(COND_INTER) %{ 4905 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'. 4906 // BO & BI 4907 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal 4908 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal 4909 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less 4910 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less 4911 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater 4912 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater 4913 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow 4914 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow 4915 %} 4916%} 4917 4918//----------OPERAND CLASSES---------------------------------------------------- 4919// Operand Classes are groups of operands that are used to simplify 4920// instruction definitions by not requiring the AD writer to specify 4921// seperate instructions for every form of operand when the 4922// instruction accepts multiple operand types with the same basic 4923// encoding and format. The classic case of this is memory operands. 4924// Indirect is not included since its use is limited to Compare & Swap. 4925 4926opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass); 4927// Memory operand where offsets are 4-aligned. Required for ld, std. 4928opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass); 4929opclass indirectMemory(indirect, indirectNarrow); 4930 4931// Special opclass for I and ConvL2I. 4932opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc); 4933 4934// Operand classes to match encode and decode. iRegN_P2N is only used 4935// for storeN. I have never seen an encode node elsewhere. 4936opclass iRegN_P2N(iRegNsrc, iRegP2N); 4937opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass); 4938 4939//----------PIPELINE----------------------------------------------------------- 4940 4941pipeline %{ 4942 4943// See J.M.Tendler et al. "Power4 system microarchitecture", IBM 4944// J. Res. & Dev., No. 1, Jan. 2002. 4945 4946//----------ATTRIBUTES--------------------------------------------------------- 4947attributes %{ 4948 4949 // Power4 instructions are of fixed length. 4950 fixed_size_instructions; 4951 4952 // TODO: if `bundle' means number of instructions fetched 4953 // per cycle, this is 8. If `bundle' means Power4 `group', that is 4954 // max instructions issued per cycle, this is 5. 4955 max_instructions_per_bundle = 8; 4956 4957 // A Power4 instruction is 4 bytes long. 4958 instruction_unit_size = 4; 4959 4960 // The Power4 processor fetches 64 bytes... 4961 instruction_fetch_unit_size = 64; 4962 4963 // ...in one line 4964 instruction_fetch_units = 1 4965 4966 // Unused, list one so that array generated by adlc is not empty. 4967 // Aix compiler chokes if _nop_count = 0. 4968 nops(fxNop); 4969%} 4970 4971//----------RESOURCES---------------------------------------------------------- 4972// Resources are the functional units available to the machine 4973resources( 4974 PPC_BR, // branch unit 4975 PPC_CR, // condition unit 4976 PPC_FX1, // integer arithmetic unit 1 4977 PPC_FX2, // integer arithmetic unit 2 4978 PPC_LDST1, // load/store unit 1 4979 PPC_LDST2, // load/store unit 2 4980 PPC_FP1, // float arithmetic unit 1 4981 PPC_FP2, // float arithmetic unit 2 4982 PPC_LDST = PPC_LDST1 | PPC_LDST2, 4983 PPC_FX = PPC_FX1 | PPC_FX2, 4984 PPC_FP = PPC_FP1 | PPC_FP2 4985 ); 4986 4987//----------PIPELINE DESCRIPTION----------------------------------------------- 4988// Pipeline Description specifies the stages in the machine's pipeline 4989pipe_desc( 4990 // Power4 longest pipeline path 4991 PPC_IF, // instruction fetch 4992 PPC_IC, 4993 //PPC_BP, // branch prediction 4994 PPC_D0, // decode 4995 PPC_D1, // decode 4996 PPC_D2, // decode 4997 PPC_D3, // decode 4998 PPC_Xfer1, 4999 PPC_GD, // group definition 5000 PPC_MP, // map 5001 PPC_ISS, // issue 5002 PPC_RF, // resource fetch 5003 PPC_EX1, // execute (all units) 5004 PPC_EX2, // execute (FP, LDST) 5005 PPC_EX3, // execute (FP, LDST) 5006 PPC_EX4, // execute (FP) 5007 PPC_EX5, // execute (FP) 5008 PPC_EX6, // execute (FP) 5009 PPC_WB, // write back 5010 PPC_Xfer2, 5011 PPC_CP 5012 ); 5013 5014//----------PIPELINE CLASSES--------------------------------------------------- 5015// Pipeline Classes describe the stages in which input and output are 5016// referenced by the hardware pipeline. 5017 5018// Simple pipeline classes. 5019 5020// Default pipeline class. 5021pipe_class pipe_class_default() %{ 5022 single_instruction; 5023 fixed_latency(2); 5024%} 5025 5026// Pipeline class for empty instructions. 5027pipe_class pipe_class_empty() %{ 5028 single_instruction; 5029 fixed_latency(0); 5030%} 5031 5032// Pipeline class for compares. 5033pipe_class pipe_class_compare() %{ 5034 single_instruction; 5035 fixed_latency(16); 5036%} 5037 5038// Pipeline class for traps. 5039pipe_class pipe_class_trap() %{ 5040 single_instruction; 5041 fixed_latency(100); 5042%} 5043 5044// Pipeline class for memory operations. 5045pipe_class pipe_class_memory() %{ 5046 single_instruction; 5047 fixed_latency(16); 5048%} 5049 5050// Pipeline class for call. 5051pipe_class pipe_class_call() %{ 5052 single_instruction; 5053 fixed_latency(100); 5054%} 5055 5056// Define the class for the Nop node. 5057define %{ 5058 MachNop = pipe_class_default; 5059%} 5060 5061%} 5062 5063//----------INSTRUCTIONS------------------------------------------------------- 5064 5065// Naming of instructions: 5066// opA_operB / opA_operB_operC: 5067// Operation 'op' with one or two source operands 'oper'. Result 5068// type is A, source operand types are B and C. 5069// Iff A == B == C, B and C are left out. 5070// 5071// The instructions are ordered according to the following scheme: 5072// - loads 5073// - load constants 5074// - prefetch 5075// - store 5076// - encode/decode 5077// - membar 5078// - conditional moves 5079// - compare & swap 5080// - arithmetic and logic operations 5081// * int: Add, Sub, Mul, Div, Mod 5082// * int: lShift, arShift, urShift, rot 5083// * float: Add, Sub, Mul, Div 5084// * and, or, xor ... 5085// - register moves: float <-> int, reg <-> stack, repl 5086// - cast (high level type cast, XtoP, castPP, castII, not_null etc. 5087// - conv (low level type cast requiring bit changes (sign extend etc) 5088// - compares, range & zero checks. 5089// - branches 5090// - complex operations, intrinsics, min, max, replicate 5091// - lock 5092// - Calls 5093// 5094// If there are similar instructions with different types they are sorted: 5095// int before float 5096// small before big 5097// signed before unsigned 5098// e.g., loadS before loadUS before loadI before loadF. 5099 5100 5101//----------Load/Store Instructions-------------------------------------------- 5102 5103//----------Load Instructions-------------------------------------------------- 5104 5105// Converts byte to int. 5106// As convB2I_reg, but without match rule. The match rule of convB2I_reg 5107// reuses the 'amount' operand, but adlc expects that operand specification 5108// and operands in match rule are equivalent. 5109instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{ 5110 effect(DEF dst, USE src); 5111 format %{ "EXTSB $dst, $src \t// byte->int" %} 5112 size(4); 5113 ins_encode %{ 5114 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); 5115 __ extsb($dst$$Register, $src$$Register); 5116 %} 5117 ins_pipe(pipe_class_default); 5118%} 5119 5120instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{ 5121 // match-rule, false predicate 5122 match(Set dst (LoadB mem)); 5123 predicate(false); 5124 5125 format %{ "LBZ $dst, $mem" %} 5126 size(4); 5127 ins_encode( enc_lbz(dst, mem) ); 5128 ins_pipe(pipe_class_memory); 5129%} 5130 5131instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{ 5132 // match-rule, false predicate 5133 match(Set dst (LoadB mem)); 5134 predicate(false); 5135 5136 format %{ "LBZ $dst, $mem\n\t" 5137 "TWI $dst\n\t" 5138 "ISYNC" %} 5139 size(12); 5140 ins_encode( enc_lbz_ac(dst, mem) ); 5141 ins_pipe(pipe_class_memory); 5142%} 5143 5144// Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. 5145instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{ 5146 match(Set dst (LoadB mem)); 5147 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5148 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5149 expand %{ 5150 iRegIdst tmp; 5151 loadUB_indirect(tmp, mem); 5152 convB2I_reg_2(dst, tmp); 5153 %} 5154%} 5155 5156instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{ 5157 match(Set dst (LoadB mem)); 5158 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); 5159 expand %{ 5160 iRegIdst tmp; 5161 loadUB_indirect_ac(tmp, mem); 5162 convB2I_reg_2(dst, tmp); 5163 %} 5164%} 5165 5166instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{ 5167 // match-rule, false predicate 5168 match(Set dst (LoadB mem)); 5169 predicate(false); 5170 5171 format %{ "LBZ $dst, $mem" %} 5172 size(4); 5173 ins_encode( enc_lbz(dst, mem) ); 5174 ins_pipe(pipe_class_memory); 5175%} 5176 5177instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{ 5178 // match-rule, false predicate 5179 match(Set dst (LoadB mem)); 5180 predicate(false); 5181 5182 format %{ "LBZ $dst, $mem\n\t" 5183 "TWI $dst\n\t" 5184 "ISYNC" %} 5185 size(12); 5186 ins_encode( enc_lbz_ac(dst, mem) ); 5187 ins_pipe(pipe_class_memory); 5188%} 5189 5190// Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. 5191instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{ 5192 match(Set dst (LoadB mem)); 5193 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5194 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5195 5196 expand %{ 5197 iRegIdst tmp; 5198 loadUB_indOffset16(tmp, mem); 5199 convB2I_reg_2(dst, tmp); 5200 %} 5201%} 5202 5203instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{ 5204 match(Set dst (LoadB mem)); 5205 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); 5206 5207 expand %{ 5208 iRegIdst tmp; 5209 loadUB_indOffset16_ac(tmp, mem); 5210 convB2I_reg_2(dst, tmp); 5211 %} 5212%} 5213 5214// Load Unsigned Byte (8bit UNsigned) into an int reg. 5215instruct loadUB(iRegIdst dst, memory mem) %{ 5216 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5217 match(Set dst (LoadUB mem)); 5218 ins_cost(MEMORY_REF_COST); 5219 5220 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %} 5221 size(4); 5222 ins_encode( enc_lbz(dst, mem) ); 5223 ins_pipe(pipe_class_memory); 5224%} 5225 5226// Load Unsigned Byte (8bit UNsigned) acquire. 5227instruct loadUB_ac(iRegIdst dst, memory mem) %{ 5228 match(Set dst (LoadUB mem)); 5229 ins_cost(3*MEMORY_REF_COST); 5230 5231 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t" 5232 "TWI $dst\n\t" 5233 "ISYNC" %} 5234 size(12); 5235 ins_encode( enc_lbz_ac(dst, mem) ); 5236 ins_pipe(pipe_class_memory); 5237%} 5238 5239// Load Unsigned Byte (8bit UNsigned) into a Long Register. 5240instruct loadUB2L(iRegLdst dst, memory mem) %{ 5241 match(Set dst (ConvI2L (LoadUB mem))); 5242 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); 5243 ins_cost(MEMORY_REF_COST); 5244 5245 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %} 5246 size(4); 5247 ins_encode( enc_lbz(dst, mem) ); 5248 ins_pipe(pipe_class_memory); 5249%} 5250 5251instruct loadUB2L_ac(iRegLdst dst, memory mem) %{ 5252 match(Set dst (ConvI2L (LoadUB mem))); 5253 ins_cost(3*MEMORY_REF_COST); 5254 5255 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t" 5256 "TWI $dst\n\t" 5257 "ISYNC" %} 5258 size(12); 5259 ins_encode( enc_lbz_ac(dst, mem) ); 5260 ins_pipe(pipe_class_memory); 5261%} 5262 5263// Load Short (16bit signed) 5264instruct loadS(iRegIdst dst, memory mem) %{ 5265 match(Set dst (LoadS mem)); 5266 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5267 ins_cost(MEMORY_REF_COST); 5268 5269 format %{ "LHA $dst, $mem" %} 5270 size(4); 5271 ins_encode %{ 5272 // TODO: PPC port $archOpcode(ppc64Opcode_lha); 5273 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5274 __ lha($dst$$Register, Idisp, $mem$$base$$Register); 5275 %} 5276 ins_pipe(pipe_class_memory); 5277%} 5278 5279// Load Short (16bit signed) acquire. 5280instruct loadS_ac(iRegIdst dst, memory mem) %{ 5281 match(Set dst (LoadS mem)); 5282 ins_cost(3*MEMORY_REF_COST); 5283 5284 format %{ "LHA $dst, $mem\t acquire\n\t" 5285 "TWI $dst\n\t" 5286 "ISYNC" %} 5287 size(12); 5288 ins_encode %{ 5289 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5290 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5291 __ lha($dst$$Register, Idisp, $mem$$base$$Register); 5292 __ twi_0($dst$$Register); 5293 __ isync(); 5294 %} 5295 ins_pipe(pipe_class_memory); 5296%} 5297 5298// Load Char (16bit unsigned) 5299instruct loadUS(iRegIdst dst, memory mem) %{ 5300 match(Set dst (LoadUS mem)); 5301 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5302 ins_cost(MEMORY_REF_COST); 5303 5304 format %{ "LHZ $dst, $mem" %} 5305 size(4); 5306 ins_encode( enc_lhz(dst, mem) ); 5307 ins_pipe(pipe_class_memory); 5308%} 5309 5310// Load Char (16bit unsigned) acquire. 5311instruct loadUS_ac(iRegIdst dst, memory mem) %{ 5312 match(Set dst (LoadUS mem)); 5313 ins_cost(3*MEMORY_REF_COST); 5314 5315 format %{ "LHZ $dst, $mem \t// acquire\n\t" 5316 "TWI $dst\n\t" 5317 "ISYNC" %} 5318 size(12); 5319 ins_encode( enc_lhz_ac(dst, mem) ); 5320 ins_pipe(pipe_class_memory); 5321%} 5322 5323// Load Unsigned Short/Char (16bit UNsigned) into a Long Register. 5324instruct loadUS2L(iRegLdst dst, memory mem) %{ 5325 match(Set dst (ConvI2L (LoadUS mem))); 5326 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); 5327 ins_cost(MEMORY_REF_COST); 5328 5329 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %} 5330 size(4); 5331 ins_encode( enc_lhz(dst, mem) ); 5332 ins_pipe(pipe_class_memory); 5333%} 5334 5335// Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire. 5336instruct loadUS2L_ac(iRegLdst dst, memory mem) %{ 5337 match(Set dst (ConvI2L (LoadUS mem))); 5338 ins_cost(3*MEMORY_REF_COST); 5339 5340 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t" 5341 "TWI $dst\n\t" 5342 "ISYNC" %} 5343 size(12); 5344 ins_encode( enc_lhz_ac(dst, mem) ); 5345 ins_pipe(pipe_class_memory); 5346%} 5347 5348// Load Integer. 5349instruct loadI(iRegIdst dst, memory mem) %{ 5350 match(Set dst (LoadI mem)); 5351 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5352 ins_cost(MEMORY_REF_COST); 5353 5354 format %{ "LWZ $dst, $mem" %} 5355 size(4); 5356 ins_encode( enc_lwz(dst, mem) ); 5357 ins_pipe(pipe_class_memory); 5358%} 5359 5360// Load Integer acquire. 5361instruct loadI_ac(iRegIdst dst, memory mem) %{ 5362 match(Set dst (LoadI mem)); 5363 ins_cost(3*MEMORY_REF_COST); 5364 5365 format %{ "LWZ $dst, $mem \t// load acquire\n\t" 5366 "TWI $dst\n\t" 5367 "ISYNC" %} 5368 size(12); 5369 ins_encode( enc_lwz_ac(dst, mem) ); 5370 ins_pipe(pipe_class_memory); 5371%} 5372 5373// Match loading integer and casting it to unsigned int in 5374// long register. 5375// LoadI + ConvI2L + AndL 0xffffffff. 5376instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{ 5377 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5378 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered()); 5379 ins_cost(MEMORY_REF_COST); 5380 5381 format %{ "LWZ $dst, $mem \t// zero-extend to long" %} 5382 size(4); 5383 ins_encode( enc_lwz(dst, mem) ); 5384 ins_pipe(pipe_class_memory); 5385%} 5386 5387// Match loading integer and casting it to long. 5388instruct loadI2L(iRegLdst dst, memory mem) %{ 5389 match(Set dst (ConvI2L (LoadI mem))); 5390 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); 5391 ins_cost(MEMORY_REF_COST); 5392 5393 format %{ "LWA $dst, $mem \t// loadI2L" %} 5394 size(4); 5395 ins_encode %{ 5396 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); 5397 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5398 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); 5399 %} 5400 ins_pipe(pipe_class_memory); 5401%} 5402 5403// Match loading integer and casting it to long - acquire. 5404instruct loadI2L_ac(iRegLdst dst, memory mem) %{ 5405 match(Set dst (ConvI2L (LoadI mem))); 5406 ins_cost(3*MEMORY_REF_COST); 5407 5408 format %{ "LWA $dst, $mem \t// loadI2L acquire" 5409 "TWI $dst\n\t" 5410 "ISYNC" %} 5411 size(12); 5412 ins_encode %{ 5413 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); 5414 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5415 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); 5416 __ twi_0($dst$$Register); 5417 __ isync(); 5418 %} 5419 ins_pipe(pipe_class_memory); 5420%} 5421 5422// Load Long - aligned 5423instruct loadL(iRegLdst dst, memoryAlg4 mem) %{ 5424 match(Set dst (LoadL mem)); 5425 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5426 ins_cost(MEMORY_REF_COST); 5427 5428 format %{ "LD $dst, $mem \t// long" %} 5429 size(4); 5430 ins_encode( enc_ld(dst, mem) ); 5431 ins_pipe(pipe_class_memory); 5432%} 5433 5434// Load Long - aligned acquire. 5435instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{ 5436 match(Set dst (LoadL mem)); 5437 ins_cost(3*MEMORY_REF_COST); 5438 5439 format %{ "LD $dst, $mem \t// long acquire\n\t" 5440 "TWI $dst\n\t" 5441 "ISYNC" %} 5442 size(12); 5443 ins_encode( enc_ld_ac(dst, mem) ); 5444 ins_pipe(pipe_class_memory); 5445%} 5446 5447// Load Long - UNaligned 5448instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{ 5449 match(Set dst (LoadL_unaligned mem)); 5450 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). 5451 ins_cost(MEMORY_REF_COST); 5452 5453 format %{ "LD $dst, $mem \t// unaligned long" %} 5454 size(4); 5455 ins_encode( enc_ld(dst, mem) ); 5456 ins_pipe(pipe_class_memory); 5457%} 5458 5459// Load nodes for superwords 5460 5461// Load Aligned Packed Byte 5462instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{ 5463 predicate(n->as_LoadVector()->memory_size() == 8); 5464 match(Set dst (LoadVector mem)); 5465 ins_cost(MEMORY_REF_COST); 5466 5467 format %{ "LD $dst, $mem \t// load 8-byte Vector" %} 5468 size(4); 5469 ins_encode( enc_ld(dst, mem) ); 5470 ins_pipe(pipe_class_memory); 5471%} 5472 5473// Load Range, range = array length (=jint) 5474instruct loadRange(iRegIdst dst, memory mem) %{ 5475 match(Set dst (LoadRange mem)); 5476 ins_cost(MEMORY_REF_COST); 5477 5478 format %{ "LWZ $dst, $mem \t// range" %} 5479 size(4); 5480 ins_encode( enc_lwz(dst, mem) ); 5481 ins_pipe(pipe_class_memory); 5482%} 5483 5484// Load Compressed Pointer 5485instruct loadN(iRegNdst dst, memory mem) %{ 5486 match(Set dst (LoadN mem)); 5487 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5488 ins_cost(MEMORY_REF_COST); 5489 5490 format %{ "LWZ $dst, $mem \t// load compressed ptr" %} 5491 size(4); 5492 ins_encode( enc_lwz(dst, mem) ); 5493 ins_pipe(pipe_class_memory); 5494%} 5495 5496// Load Compressed Pointer acquire. 5497instruct loadN_ac(iRegNdst dst, memory mem) %{ 5498 match(Set dst (LoadN mem)); 5499 ins_cost(3*MEMORY_REF_COST); 5500 5501 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t" 5502 "TWI $dst\n\t" 5503 "ISYNC" %} 5504 size(12); 5505 ins_encode( enc_lwz_ac(dst, mem) ); 5506 ins_pipe(pipe_class_memory); 5507%} 5508 5509// Load Compressed Pointer and decode it if narrow_oop_shift == 0. 5510instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{ 5511 match(Set dst (DecodeN (LoadN mem))); 5512 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0); 5513 ins_cost(MEMORY_REF_COST); 5514 5515 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %} 5516 size(4); 5517 ins_encode( enc_lwz(dst, mem) ); 5518 ins_pipe(pipe_class_memory); 5519%} 5520 5521instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{ 5522 match(Set dst (DecodeNKlass (LoadNKlass mem))); 5523 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 && 5524 _kids[0]->_leaf->as_Load()->is_unordered()); 5525 ins_cost(MEMORY_REF_COST); 5526 5527 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %} 5528 size(4); 5529 ins_encode( enc_lwz(dst, mem) ); 5530 ins_pipe(pipe_class_memory); 5531%} 5532 5533// Load Pointer 5534instruct loadP(iRegPdst dst, memoryAlg4 mem) %{ 5535 match(Set dst (LoadP mem)); 5536 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5537 ins_cost(MEMORY_REF_COST); 5538 5539 format %{ "LD $dst, $mem \t// ptr" %} 5540 size(4); 5541 ins_encode( enc_ld(dst, mem) ); 5542 ins_pipe(pipe_class_memory); 5543%} 5544 5545// Load Pointer acquire. 5546instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{ 5547 match(Set dst (LoadP mem)); 5548 ins_cost(3*MEMORY_REF_COST); 5549 5550 format %{ "LD $dst, $mem \t// ptr acquire\n\t" 5551 "TWI $dst\n\t" 5552 "ISYNC" %} 5553 size(12); 5554 ins_encode( enc_ld_ac(dst, mem) ); 5555 ins_pipe(pipe_class_memory); 5556%} 5557 5558// LoadP + CastP2L 5559instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{ 5560 match(Set dst (CastP2X (LoadP mem))); 5561 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); 5562 ins_cost(MEMORY_REF_COST); 5563 5564 format %{ "LD $dst, $mem \t// ptr + p2x" %} 5565 size(4); 5566 ins_encode( enc_ld(dst, mem) ); 5567 ins_pipe(pipe_class_memory); 5568%} 5569 5570// Load compressed klass pointer. 5571instruct loadNKlass(iRegNdst dst, memory mem) %{ 5572 match(Set dst (LoadNKlass mem)); 5573 ins_cost(MEMORY_REF_COST); 5574 5575 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %} 5576 size(4); 5577 ins_encode( enc_lwz(dst, mem) ); 5578 ins_pipe(pipe_class_memory); 5579%} 5580 5581// Load Klass Pointer 5582instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{ 5583 match(Set dst (LoadKlass mem)); 5584 ins_cost(MEMORY_REF_COST); 5585 5586 format %{ "LD $dst, $mem \t// klass ptr" %} 5587 size(4); 5588 ins_encode( enc_ld(dst, mem) ); 5589 ins_pipe(pipe_class_memory); 5590%} 5591 5592// Load Float 5593instruct loadF(regF dst, memory mem) %{ 5594 match(Set dst (LoadF mem)); 5595 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5596 ins_cost(MEMORY_REF_COST); 5597 5598 format %{ "LFS $dst, $mem" %} 5599 size(4); 5600 ins_encode %{ 5601 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 5602 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5603 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5604 %} 5605 ins_pipe(pipe_class_memory); 5606%} 5607 5608// Load Float acquire. 5609instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{ 5610 match(Set dst (LoadF mem)); 5611 effect(TEMP cr0); 5612 ins_cost(3*MEMORY_REF_COST); 5613 5614 format %{ "LFS $dst, $mem \t// acquire\n\t" 5615 "FCMPU cr0, $dst, $dst\n\t" 5616 "BNE cr0, next\n" 5617 "next:\n\t" 5618 "ISYNC" %} 5619 size(16); 5620 ins_encode %{ 5621 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5622 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5623 Label next; 5624 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5625 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); 5626 __ bne(CCR0, next); 5627 __ bind(next); 5628 __ isync(); 5629 %} 5630 ins_pipe(pipe_class_memory); 5631%} 5632 5633// Load Double - aligned 5634instruct loadD(regD dst, memory mem) %{ 5635 match(Set dst (LoadD mem)); 5636 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5637 ins_cost(MEMORY_REF_COST); 5638 5639 format %{ "LFD $dst, $mem" %} 5640 size(4); 5641 ins_encode( enc_lfd(dst, mem) ); 5642 ins_pipe(pipe_class_memory); 5643%} 5644 5645// Load Double - aligned acquire. 5646instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{ 5647 match(Set dst (LoadD mem)); 5648 effect(TEMP cr0); 5649 ins_cost(3*MEMORY_REF_COST); 5650 5651 format %{ "LFD $dst, $mem \t// acquire\n\t" 5652 "FCMPU cr0, $dst, $dst\n\t" 5653 "BNE cr0, next\n" 5654 "next:\n\t" 5655 "ISYNC" %} 5656 size(16); 5657 ins_encode %{ 5658 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5659 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5660 Label next; 5661 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5662 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); 5663 __ bne(CCR0, next); 5664 __ bind(next); 5665 __ isync(); 5666 %} 5667 ins_pipe(pipe_class_memory); 5668%} 5669 5670// Load Double - UNaligned 5671instruct loadD_unaligned(regD dst, memory mem) %{ 5672 match(Set dst (LoadD_unaligned mem)); 5673 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). 5674 ins_cost(MEMORY_REF_COST); 5675 5676 format %{ "LFD $dst, $mem" %} 5677 size(4); 5678 ins_encode( enc_lfd(dst, mem) ); 5679 ins_pipe(pipe_class_memory); 5680%} 5681 5682//----------Constants-------------------------------------------------------- 5683 5684// Load MachConstantTableBase: add hi offset to global toc. 5685// TODO: Handle hidden register r29 in bundler! 5686instruct loadToc_hi(iRegLdst dst) %{ 5687 effect(DEF dst); 5688 ins_cost(DEFAULT_COST); 5689 5690 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %} 5691 size(4); 5692 ins_encode %{ 5693 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5694 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc()); 5695 %} 5696 ins_pipe(pipe_class_default); 5697%} 5698 5699// Load MachConstantTableBase: add lo offset to global toc. 5700instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{ 5701 effect(DEF dst, USE src); 5702 ins_cost(DEFAULT_COST); 5703 5704 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %} 5705 size(4); 5706 ins_encode %{ 5707 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5708 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc()); 5709 %} 5710 ins_pipe(pipe_class_default); 5711%} 5712 5713// Load 16-bit integer constant 0xssss???? 5714instruct loadConI16(iRegIdst dst, immI16 src) %{ 5715 match(Set dst src); 5716 5717 format %{ "LI $dst, $src" %} 5718 size(4); 5719 ins_encode %{ 5720 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5721 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 5722 %} 5723 ins_pipe(pipe_class_default); 5724%} 5725 5726// Load integer constant 0x????0000 5727instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{ 5728 match(Set dst src); 5729 ins_cost(DEFAULT_COST); 5730 5731 format %{ "LIS $dst, $src.hi" %} 5732 size(4); 5733 ins_encode %{ 5734 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5735 // Lis sign extends 16-bit src then shifts it 16 bit to the left. 5736 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); 5737 %} 5738 ins_pipe(pipe_class_default); 5739%} 5740 5741// Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted 5742// and sign extended), this adds the low 16 bits. 5743instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 5744 // no match-rule, false predicate 5745 effect(DEF dst, USE src1, USE src2); 5746 predicate(false); 5747 5748 format %{ "ORI $dst, $src1.hi, $src2.lo" %} 5749 size(4); 5750 ins_encode %{ 5751 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5752 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 5753 %} 5754 ins_pipe(pipe_class_default); 5755%} 5756 5757instruct loadConI_Ex(iRegIdst dst, immI src) %{ 5758 match(Set dst src); 5759 ins_cost(DEFAULT_COST*2); 5760 5761 expand %{ 5762 // Would like to use $src$$constant. 5763 immI16 srcLo %{ _opnds[1]->constant() %} 5764 // srcHi can be 0000 if srcLo sign-extends to a negative number. 5765 immIhi16 srcHi %{ _opnds[1]->constant() %} 5766 iRegIdst tmpI; 5767 loadConIhi16(tmpI, srcHi); 5768 loadConI32_lo16(dst, tmpI, srcLo); 5769 %} 5770%} 5771 5772// No constant pool entries required. 5773instruct loadConL16(iRegLdst dst, immL16 src) %{ 5774 match(Set dst src); 5775 5776 format %{ "LI $dst, $src \t// long" %} 5777 size(4); 5778 ins_encode %{ 5779 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5780 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF))); 5781 %} 5782 ins_pipe(pipe_class_default); 5783%} 5784 5785// Load long constant 0xssssssss????0000 5786instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{ 5787 match(Set dst src); 5788 ins_cost(DEFAULT_COST); 5789 5790 format %{ "LIS $dst, $src.hi \t// long" %} 5791 size(4); 5792 ins_encode %{ 5793 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5794 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); 5795 %} 5796 ins_pipe(pipe_class_default); 5797%} 5798 5799// To load a 32 bit constant: merge lower 16 bits into already loaded 5800// high 16 bits. 5801instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 5802 // no match-rule, false predicate 5803 effect(DEF dst, USE src1, USE src2); 5804 predicate(false); 5805 5806 format %{ "ORI $dst, $src1, $src2.lo" %} 5807 size(4); 5808 ins_encode %{ 5809 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5810 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 5811 %} 5812 ins_pipe(pipe_class_default); 5813%} 5814 5815// Load 32-bit long constant 5816instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{ 5817 match(Set dst src); 5818 ins_cost(DEFAULT_COST*2); 5819 5820 expand %{ 5821 // Would like to use $src$$constant. 5822 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%} 5823 // srcHi can be 0000 if srcLo sign-extends to a negative number. 5824 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%} 5825 iRegLdst tmpL; 5826 loadConL32hi16(tmpL, srcHi); 5827 loadConL32_lo16(dst, tmpL, srcLo); 5828 %} 5829%} 5830 5831// Load long constant 0x????000000000000. 5832instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{ 5833 match(Set dst src); 5834 ins_cost(DEFAULT_COST); 5835 5836 expand %{ 5837 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%} 5838 immI shift32 %{ 32 %} 5839 iRegLdst tmpL; 5840 loadConL32hi16(tmpL, srcHi); 5841 lshiftL_regL_immI(dst, tmpL, shift32); 5842 %} 5843%} 5844 5845// Expand node for constant pool load: small offset. 5846instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{ 5847 effect(DEF dst, USE src, USE toc); 5848 ins_cost(MEMORY_REF_COST); 5849 5850 ins_num_consts(1); 5851 // Needed so that CallDynamicJavaDirect can compute the address of this 5852 // instruction for relocation. 5853 ins_field_cbuf_insts_offset(int); 5854 5855 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %} 5856 size(4); 5857 ins_encode( enc_load_long_constL(dst, src, toc) ); 5858 ins_pipe(pipe_class_memory); 5859%} 5860 5861// Expand node for constant pool load: large offset. 5862instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{ 5863 effect(DEF dst, USE src, USE toc); 5864 predicate(false); 5865 5866 ins_num_consts(1); 5867 ins_field_const_toc_offset(int); 5868 // Needed so that CallDynamicJavaDirect can compute the address of this 5869 // instruction for relocation. 5870 ins_field_cbuf_insts_offset(int); 5871 5872 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %} 5873 size(4); 5874 ins_encode( enc_load_long_constL_hi(dst, toc, src) ); 5875 ins_pipe(pipe_class_default); 5876%} 5877 5878// Expand node for constant pool load: large offset. 5879// No constant pool entries required. 5880instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{ 5881 effect(DEF dst, USE src, USE base); 5882 predicate(false); 5883 5884 ins_field_const_toc_offset_hi_node(loadConL_hiNode*); 5885 5886 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %} 5887 size(4); 5888 ins_encode %{ 5889 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 5890 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; 5891 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); 5892 %} 5893 ins_pipe(pipe_class_memory); 5894%} 5895 5896// Load long constant from constant table. Expand in case of 5897// offset > 16 bit is needed. 5898// Adlc adds toc node MachConstantTableBase. 5899instruct loadConL_Ex(iRegLdst dst, immL src) %{ 5900 match(Set dst src); 5901 ins_cost(MEMORY_REF_COST); 5902 5903 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %} 5904 // We can not inline the enc_class for the expand as that does not support constanttablebase. 5905 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) ); 5906%} 5907 5908// Load NULL as compressed oop. 5909instruct loadConN0(iRegNdst dst, immN_0 src) %{ 5910 match(Set dst src); 5911 ins_cost(DEFAULT_COST); 5912 5913 format %{ "LI $dst, $src \t// compressed ptr" %} 5914 size(4); 5915 ins_encode %{ 5916 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5917 __ li($dst$$Register, 0); 5918 %} 5919 ins_pipe(pipe_class_default); 5920%} 5921 5922// Load hi part of compressed oop constant. 5923instruct loadConN_hi(iRegNdst dst, immN src) %{ 5924 effect(DEF dst, USE src); 5925 ins_cost(DEFAULT_COST); 5926 5927 format %{ "LIS $dst, $src \t// narrow oop hi" %} 5928 size(4); 5929 ins_encode %{ 5930 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5931 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff)); 5932 %} 5933 ins_pipe(pipe_class_default); 5934%} 5935 5936// Add lo part of compressed oop constant to already loaded hi part. 5937instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{ 5938 effect(DEF dst, USE src1, USE src2); 5939 ins_cost(DEFAULT_COST); 5940 5941 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %} 5942 size(4); 5943 ins_encode %{ 5944 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5945 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 5946 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant); 5947 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5948 __ relocate(rspec, 1); 5949 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff); 5950 %} 5951 ins_pipe(pipe_class_default); 5952%} 5953 5954// Needed to postalloc expand loadConN: ConN is loaded as ConI 5955// leaving the upper 32 bits with sign-extension bits. 5956// This clears these bits: dst = src & 0xFFFFFFFF. 5957// TODO: Eventually call this maskN_regN_FFFFFFFF. 5958instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{ 5959 effect(DEF dst, USE src); 5960 predicate(false); 5961 5962 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask 5963 size(4); 5964 ins_encode %{ 5965 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 5966 __ clrldi($dst$$Register, $src$$Register, 0x20); 5967 %} 5968 ins_pipe(pipe_class_default); 5969%} 5970 5971// Optimize DecodeN for disjoint base. 5972// Load base of compressed oops into a register 5973instruct loadBase(iRegLdst dst) %{ 5974 effect(DEF dst); 5975 5976 format %{ "LoadConst $dst, heapbase" %} 5977 ins_encode %{ 5978 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5979 __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0); 5980 %} 5981 ins_pipe(pipe_class_default); 5982%} 5983 5984// Loading ConN must be postalloc expanded so that edges between 5985// the nodes are safe. They may not interfere with a safepoint. 5986// GL TODO: This needs three instructions: better put this into the constant pool. 5987instruct loadConN_Ex(iRegNdst dst, immN src) %{ 5988 match(Set dst src); 5989 ins_cost(DEFAULT_COST*2); 5990 5991 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask 5992 postalloc_expand %{ 5993 MachNode *m1 = new loadConN_hiNode(); 5994 MachNode *m2 = new loadConN_loNode(); 5995 MachNode *m3 = new clearMs32bNode(); 5996 m1->add_req(NULL); 5997 m2->add_req(NULL, m1); 5998 m3->add_req(NULL, m2); 5999 m1->_opnds[0] = op_dst; 6000 m1->_opnds[1] = op_src; 6001 m2->_opnds[0] = op_dst; 6002 m2->_opnds[1] = op_dst; 6003 m2->_opnds[2] = op_src; 6004 m3->_opnds[0] = op_dst; 6005 m3->_opnds[1] = op_dst; 6006 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6007 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6008 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6009 nodes->push(m1); 6010 nodes->push(m2); 6011 nodes->push(m3); 6012 %} 6013%} 6014 6015// We have seen a safepoint between the hi and lo parts, and this node was handled 6016// as an oop. Therefore this needs a match rule so that build_oop_map knows this is 6017// not a narrow oop. 6018instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{ 6019 match(Set dst src); 6020 effect(DEF dst, USE src); 6021 ins_cost(DEFAULT_COST); 6022 6023 format %{ "LIS $dst, $src \t// narrow klass hi" %} 6024 size(4); 6025 ins_encode %{ 6026 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 6027 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant); 6028 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff)); 6029 %} 6030 ins_pipe(pipe_class_default); 6031%} 6032 6033// As loadConNKlass_hi this must be recognized as narrow klass, not oop! 6034instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 6035 match(Set dst src1); 6036 effect(TEMP src2); 6037 ins_cost(DEFAULT_COST); 6038 6039 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask 6040 size(4); 6041 ins_encode %{ 6042 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6043 __ clrldi($dst$$Register, $src2$$Register, 0x20); 6044 %} 6045 ins_pipe(pipe_class_default); 6046%} 6047 6048// This needs a match rule so that build_oop_map knows this is 6049// not a narrow oop. 6050instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 6051 match(Set dst src1); 6052 effect(TEMP src2); 6053 ins_cost(DEFAULT_COST); 6054 6055 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %} 6056 size(4); 6057 ins_encode %{ 6058 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 6059 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant); 6060 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6061 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant); 6062 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6063 6064 __ relocate(rspec, 1); 6065 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff); 6066 %} 6067 ins_pipe(pipe_class_default); 6068%} 6069 6070// Loading ConNKlass must be postalloc expanded so that edges between 6071// the nodes are safe. They may not interfere with a safepoint. 6072instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{ 6073 match(Set dst src); 6074 ins_cost(DEFAULT_COST*2); 6075 6076 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask 6077 postalloc_expand %{ 6078 // Load high bits into register. Sign extended. 6079 MachNode *m1 = new loadConNKlass_hiNode(); 6080 m1->add_req(NULL); 6081 m1->_opnds[0] = op_dst; 6082 m1->_opnds[1] = op_src; 6083 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6084 nodes->push(m1); 6085 6086 MachNode *m2 = m1; 6087 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) { 6088 // Value might be 1-extended. Mask out these bits. 6089 m2 = new loadConNKlass_maskNode(); 6090 m2->add_req(NULL, m1); 6091 m2->_opnds[0] = op_dst; 6092 m2->_opnds[1] = op_src; 6093 m2->_opnds[2] = op_dst; 6094 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6095 nodes->push(m2); 6096 } 6097 6098 MachNode *m3 = new loadConNKlass_loNode(); 6099 m3->add_req(NULL, m2); 6100 m3->_opnds[0] = op_dst; 6101 m3->_opnds[1] = op_src; 6102 m3->_opnds[2] = op_dst; 6103 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6104 nodes->push(m3); 6105 %} 6106%} 6107 6108// 0x1 is used in object initialization (initial object header). 6109// No constant pool entries required. 6110instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{ 6111 match(Set dst src); 6112 6113 format %{ "LI $dst, $src \t// ptr" %} 6114 size(4); 6115 ins_encode %{ 6116 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 6117 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 6118 %} 6119 ins_pipe(pipe_class_default); 6120%} 6121 6122// Expand node for constant pool load: small offset. 6123// The match rule is needed to generate the correct bottom_type(), 6124// however this node should never match. The use of predicate is not 6125// possible since ADLC forbids predicates for chain rules. The higher 6126// costs do not prevent matching in this case. For that reason the 6127// operand immP_NM with predicate(false) is used. 6128instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{ 6129 match(Set dst src); 6130 effect(TEMP toc); 6131 6132 ins_num_consts(1); 6133 6134 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %} 6135 size(4); 6136 ins_encode( enc_load_long_constP(dst, src, toc) ); 6137 ins_pipe(pipe_class_memory); 6138%} 6139 6140// Expand node for constant pool load: large offset. 6141instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{ 6142 effect(DEF dst, USE src, USE toc); 6143 predicate(false); 6144 6145 ins_num_consts(1); 6146 ins_field_const_toc_offset(int); 6147 6148 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %} 6149 size(4); 6150 ins_encode( enc_load_long_constP_hi(dst, src, toc) ); 6151 ins_pipe(pipe_class_default); 6152%} 6153 6154// Expand node for constant pool load: large offset. 6155instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{ 6156 match(Set dst src); 6157 effect(TEMP base); 6158 6159 ins_field_const_toc_offset_hi_node(loadConP_hiNode*); 6160 6161 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %} 6162 size(4); 6163 ins_encode %{ 6164 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 6165 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; 6166 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); 6167 %} 6168 ins_pipe(pipe_class_memory); 6169%} 6170 6171// Load pointer constant from constant table. Expand in case an 6172// offset > 16 bit is needed. 6173// Adlc adds toc node MachConstantTableBase. 6174instruct loadConP_Ex(iRegPdst dst, immP src) %{ 6175 match(Set dst src); 6176 ins_cost(MEMORY_REF_COST); 6177 6178 // This rule does not use "expand" because then 6179 // the result type is not known to be an Oop. An ADLC 6180 // enhancement will be needed to make that work - not worth it! 6181 6182 // If this instruction rematerializes, it prolongs the live range 6183 // of the toc node, causing illegal graphs. 6184 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule(). 6185 ins_cannot_rematerialize(true); 6186 6187 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %} 6188 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) ); 6189%} 6190 6191// Expand node for constant pool load: small offset. 6192instruct loadConF(regF dst, immF src, iRegLdst toc) %{ 6193 effect(DEF dst, USE src, USE toc); 6194 ins_cost(MEMORY_REF_COST); 6195 6196 ins_num_consts(1); 6197 6198 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %} 6199 size(4); 6200 ins_encode %{ 6201 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 6202 address float_address = __ float_constant($src$$constant); 6203 if (float_address == NULL) { 6204 ciEnv::current()->record_out_of_memory_failure(); 6205 return; 6206 } 6207 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register); 6208 %} 6209 ins_pipe(pipe_class_memory); 6210%} 6211 6212// Expand node for constant pool load: large offset. 6213instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{ 6214 effect(DEF dst, USE src, USE toc); 6215 ins_cost(MEMORY_REF_COST); 6216 6217 ins_num_consts(1); 6218 6219 format %{ "ADDIS $toc, $toc, offset_hi\n\t" 6220 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t" 6221 "ADDIS $toc, $toc, -offset_hi"%} 6222 size(12); 6223 ins_encode %{ 6224 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6225 FloatRegister Rdst = $dst$$FloatRegister; 6226 Register Rtoc = $toc$$Register; 6227 address float_address = __ float_constant($src$$constant); 6228 if (float_address == NULL) { 6229 ciEnv::current()->record_out_of_memory_failure(); 6230 return; 6231 } 6232 int offset = __ offset_to_method_toc(float_address); 6233 int hi = (offset + (1<<15))>>16; 6234 int lo = offset - hi * (1<<16); 6235 6236 __ addis(Rtoc, Rtoc, hi); 6237 __ lfs(Rdst, lo, Rtoc); 6238 __ addis(Rtoc, Rtoc, -hi); 6239 %} 6240 ins_pipe(pipe_class_memory); 6241%} 6242 6243// Adlc adds toc node MachConstantTableBase. 6244instruct loadConF_Ex(regF dst, immF src) %{ 6245 match(Set dst src); 6246 ins_cost(MEMORY_REF_COST); 6247 6248 // See loadConP. 6249 ins_cannot_rematerialize(true); 6250 6251 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} 6252 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) ); 6253%} 6254 6255// Expand node for constant pool load: small offset. 6256instruct loadConD(regD dst, immD src, iRegLdst toc) %{ 6257 effect(DEF dst, USE src, USE toc); 6258 ins_cost(MEMORY_REF_COST); 6259 6260 ins_num_consts(1); 6261 6262 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %} 6263 size(4); 6264 ins_encode %{ 6265 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); 6266 address float_address = __ double_constant($src$$constant); 6267 if (float_address == NULL) { 6268 ciEnv::current()->record_out_of_memory_failure(); 6269 return; 6270 } 6271 int offset = __ offset_to_method_toc(float_address); 6272 __ lfd($dst$$FloatRegister, offset, $toc$$Register); 6273 %} 6274 ins_pipe(pipe_class_memory); 6275%} 6276 6277// Expand node for constant pool load: large offset. 6278instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{ 6279 effect(DEF dst, USE src, USE toc); 6280 ins_cost(MEMORY_REF_COST); 6281 6282 ins_num_consts(1); 6283 6284 format %{ "ADDIS $toc, $toc, offset_hi\n\t" 6285 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t" 6286 "ADDIS $toc, $toc, -offset_hi" %} 6287 size(12); 6288 ins_encode %{ 6289 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6290 FloatRegister Rdst = $dst$$FloatRegister; 6291 Register Rtoc = $toc$$Register; 6292 address float_address = __ double_constant($src$$constant); 6293 if (float_address == NULL) { 6294 ciEnv::current()->record_out_of_memory_failure(); 6295 return; 6296 } 6297 int offset = __ offset_to_method_toc(float_address); 6298 int hi = (offset + (1<<15))>>16; 6299 int lo = offset - hi * (1<<16); 6300 6301 __ addis(Rtoc, Rtoc, hi); 6302 __ lfd(Rdst, lo, Rtoc); 6303 __ addis(Rtoc, Rtoc, -hi); 6304 %} 6305 ins_pipe(pipe_class_memory); 6306%} 6307 6308// Adlc adds toc node MachConstantTableBase. 6309instruct loadConD_Ex(regD dst, immD src) %{ 6310 match(Set dst src); 6311 ins_cost(MEMORY_REF_COST); 6312 6313 // See loadConP. 6314 ins_cannot_rematerialize(true); 6315 6316 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} 6317 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) ); 6318%} 6319 6320// Prefetch instructions. 6321// Must be safe to execute with invalid address (cannot fault). 6322 6323// Special prefetch versions which use the dcbz instruction. 6324instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{ 6325 match(PrefetchAllocation (AddP mem src)); 6326 predicate(AllocatePrefetchStyle == 3); 6327 ins_cost(MEMORY_REF_COST); 6328 6329 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %} 6330 size(4); 6331 ins_encode %{ 6332 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6333 __ dcbz($src$$Register, $mem$$base$$Register); 6334 %} 6335 ins_pipe(pipe_class_memory); 6336%} 6337 6338instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{ 6339 match(PrefetchAllocation mem); 6340 predicate(AllocatePrefetchStyle == 3); 6341 ins_cost(MEMORY_REF_COST); 6342 6343 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %} 6344 size(4); 6345 ins_encode %{ 6346 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6347 __ dcbz($mem$$base$$Register); 6348 %} 6349 ins_pipe(pipe_class_memory); 6350%} 6351 6352instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{ 6353 match(PrefetchAllocation (AddP mem src)); 6354 predicate(AllocatePrefetchStyle != 3); 6355 ins_cost(MEMORY_REF_COST); 6356 6357 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %} 6358 size(4); 6359 ins_encode %{ 6360 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6361 __ dcbtst($src$$Register, $mem$$base$$Register); 6362 %} 6363 ins_pipe(pipe_class_memory); 6364%} 6365 6366instruct prefetch_alloc_no_offset(indirectMemory mem) %{ 6367 match(PrefetchAllocation mem); 6368 predicate(AllocatePrefetchStyle != 3); 6369 ins_cost(MEMORY_REF_COST); 6370 6371 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %} 6372 size(4); 6373 ins_encode %{ 6374 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6375 __ dcbtst($mem$$base$$Register); 6376 %} 6377 ins_pipe(pipe_class_memory); 6378%} 6379 6380//----------Store Instructions------------------------------------------------- 6381 6382// Store Byte 6383instruct storeB(memory mem, iRegIsrc src) %{ 6384 match(Set mem (StoreB mem src)); 6385 ins_cost(MEMORY_REF_COST); 6386 6387 format %{ "STB $src, $mem \t// byte" %} 6388 size(4); 6389 ins_encode %{ 6390 // TODO: PPC port $archOpcode(ppc64Opcode_stb); 6391 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 6392 __ stb($src$$Register, Idisp, $mem$$base$$Register); 6393 %} 6394 ins_pipe(pipe_class_memory); 6395%} 6396 6397// Store Char/Short 6398instruct storeC(memory mem, iRegIsrc src) %{ 6399 match(Set mem (StoreC mem src)); 6400 ins_cost(MEMORY_REF_COST); 6401 6402 format %{ "STH $src, $mem \t// short" %} 6403 size(4); 6404 ins_encode %{ 6405 // TODO: PPC port $archOpcode(ppc64Opcode_sth); 6406 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 6407 __ sth($src$$Register, Idisp, $mem$$base$$Register); 6408 %} 6409 ins_pipe(pipe_class_memory); 6410%} 6411 6412// Store Integer 6413instruct storeI(memory mem, iRegIsrc src) %{ 6414 match(Set mem (StoreI mem src)); 6415 ins_cost(MEMORY_REF_COST); 6416 6417 format %{ "STW $src, $mem" %} 6418 size(4); 6419 ins_encode( enc_stw(src, mem) ); 6420 ins_pipe(pipe_class_memory); 6421%} 6422 6423// ConvL2I + StoreI. 6424instruct storeI_convL2I(memory mem, iRegLsrc src) %{ 6425 match(Set mem (StoreI mem (ConvL2I src))); 6426 ins_cost(MEMORY_REF_COST); 6427 6428 format %{ "STW l2i($src), $mem" %} 6429 size(4); 6430 ins_encode( enc_stw(src, mem) ); 6431 ins_pipe(pipe_class_memory); 6432%} 6433 6434// Store Long 6435instruct storeL(memoryAlg4 mem, iRegLsrc src) %{ 6436 match(Set mem (StoreL mem src)); 6437 ins_cost(MEMORY_REF_COST); 6438 6439 format %{ "STD $src, $mem \t// long" %} 6440 size(4); 6441 ins_encode( enc_std(src, mem) ); 6442 ins_pipe(pipe_class_memory); 6443%} 6444 6445// Store super word nodes. 6446 6447// Store Aligned Packed Byte long register to memory 6448instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{ 6449 predicate(n->as_StoreVector()->memory_size() == 8); 6450 match(Set mem (StoreVector mem src)); 6451 ins_cost(MEMORY_REF_COST); 6452 6453 format %{ "STD $mem, $src \t// packed8B" %} 6454 size(4); 6455 ins_encode( enc_std(src, mem) ); 6456 ins_pipe(pipe_class_memory); 6457%} 6458 6459// Store Compressed Oop 6460instruct storeN(memory dst, iRegN_P2N src) %{ 6461 match(Set dst (StoreN dst src)); 6462 ins_cost(MEMORY_REF_COST); 6463 6464 format %{ "STW $src, $dst \t// compressed oop" %} 6465 size(4); 6466 ins_encode( enc_stw(src, dst) ); 6467 ins_pipe(pipe_class_memory); 6468%} 6469 6470// Store Compressed KLass 6471instruct storeNKlass(memory dst, iRegN_P2N src) %{ 6472 match(Set dst (StoreNKlass dst src)); 6473 ins_cost(MEMORY_REF_COST); 6474 6475 format %{ "STW $src, $dst \t// compressed klass" %} 6476 size(4); 6477 ins_encode( enc_stw(src, dst) ); 6478 ins_pipe(pipe_class_memory); 6479%} 6480 6481// Store Pointer 6482instruct storeP(memoryAlg4 dst, iRegPsrc src) %{ 6483 match(Set dst (StoreP dst src)); 6484 ins_cost(MEMORY_REF_COST); 6485 6486 format %{ "STD $src, $dst \t// ptr" %} 6487 size(4); 6488 ins_encode( enc_std(src, dst) ); 6489 ins_pipe(pipe_class_memory); 6490%} 6491 6492// Store Float 6493instruct storeF(memory mem, regF src) %{ 6494 match(Set mem (StoreF mem src)); 6495 ins_cost(MEMORY_REF_COST); 6496 6497 format %{ "STFS $src, $mem" %} 6498 size(4); 6499 ins_encode( enc_stfs(src, mem) ); 6500 ins_pipe(pipe_class_memory); 6501%} 6502 6503// Store Double 6504instruct storeD(memory mem, regD src) %{ 6505 match(Set mem (StoreD mem src)); 6506 ins_cost(MEMORY_REF_COST); 6507 6508 format %{ "STFD $src, $mem" %} 6509 size(4); 6510 ins_encode( enc_stfd(src, mem) ); 6511 ins_pipe(pipe_class_memory); 6512%} 6513 6514//----------Store Instructions With Zeros-------------------------------------- 6515 6516// Card-mark for CMS garbage collection. 6517// This cardmark does an optimization so that it must not always 6518// do a releasing store. For this, it gets the address of 6519// CMSCollectorCardTableModRefBSExt::_requires_release as input. 6520// (Using releaseFieldAddr in the match rule is a hack.) 6521instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{ 6522 match(Set mem (StoreCM mem releaseFieldAddr)); 6523 effect(TEMP crx); 6524 predicate(false); 6525 ins_cost(MEMORY_REF_COST); 6526 6527 // See loadConP. 6528 ins_cannot_rematerialize(true); 6529 6530 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %} 6531 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) ); 6532 ins_pipe(pipe_class_memory); 6533%} 6534 6535// Card-mark for CMS garbage collection. 6536// This cardmark does an optimization so that it must not always 6537// do a releasing store. For this, it needs the constant address of 6538// CMSCollectorCardTableModRefBSExt::_requires_release. 6539// This constant address is split off here by expand so we can use 6540// adlc / matcher functionality to load it from the constant section. 6541instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{ 6542 match(Set mem (StoreCM mem zero)); 6543 predicate(UseConcMarkSweepGC); 6544 6545 expand %{ 6546 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %} 6547 iRegLdst releaseFieldAddress; 6548 flagsReg crx; 6549 loadConL_Ex(releaseFieldAddress, baseImm); 6550 storeCM_CMS(mem, releaseFieldAddress, crx); 6551 %} 6552%} 6553 6554instruct storeCM_G1(memory mem, immI_0 zero) %{ 6555 match(Set mem (StoreCM mem zero)); 6556 predicate(UseG1GC); 6557 ins_cost(MEMORY_REF_COST); 6558 6559 ins_cannot_rematerialize(true); 6560 6561 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %} 6562 size(8); 6563 ins_encode %{ 6564 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6565 __ li(R0, 0); 6566 //__ release(); // G1: oops are allowed to get visible after dirty marking 6567 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias"); 6568 __ stb(R0, $mem$$disp, $mem$$base$$Register); 6569 %} 6570 ins_pipe(pipe_class_memory); 6571%} 6572 6573// Convert oop pointer into compressed form. 6574 6575// Nodes for postalloc expand. 6576 6577// Shift node for expand. 6578instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{ 6579 // The match rule is needed to make it a 'MachTypeNode'! 6580 match(Set dst (EncodeP src)); 6581 predicate(false); 6582 6583 format %{ "SRDI $dst, $src, 3 \t// encode" %} 6584 size(4); 6585 ins_encode %{ 6586 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6587 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); 6588 %} 6589 ins_pipe(pipe_class_default); 6590%} 6591 6592// Add node for expand. 6593instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{ 6594 // The match rule is needed to make it a 'MachTypeNode'! 6595 match(Set dst (EncodeP src)); 6596 predicate(false); 6597 6598 format %{ "SUB $dst, $src, oop_base \t// encode" %} 6599 ins_encode %{ 6600 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6601 __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0); 6602 %} 6603 ins_pipe(pipe_class_default); 6604%} 6605 6606// Conditional sub base. 6607instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{ 6608 // The match rule is needed to make it a 'MachTypeNode'! 6609 match(Set dst (EncodeP (Binary crx src1))); 6610 predicate(false); 6611 6612 format %{ "BEQ $crx, done\n\t" 6613 "SUB $dst, $src1, heapbase \t// encode: subtract base if != NULL\n" 6614 "done:" %} 6615 ins_encode %{ 6616 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6617 Label done; 6618 __ beq($crx$$CondRegister, done); 6619 __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0); 6620 __ bind(done); 6621 %} 6622 ins_pipe(pipe_class_default); 6623%} 6624 6625// Power 7 can use isel instruction 6626instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{ 6627 // The match rule is needed to make it a 'MachTypeNode'! 6628 match(Set dst (EncodeP (Binary crx src1))); 6629 predicate(false); 6630 6631 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %} 6632 size(4); 6633 ins_encode %{ 6634 // This is a Power7 instruction for which no machine description exists. 6635 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6636 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 6637 %} 6638 ins_pipe(pipe_class_default); 6639%} 6640 6641// Disjoint narrow oop base. 6642instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{ 6643 match(Set dst (EncodeP src)); 6644 predicate(Universe::narrow_oop_base_disjoint()); 6645 6646 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %} 6647 size(4); 6648 ins_encode %{ 6649 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6650 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); 6651 %} 6652 ins_pipe(pipe_class_default); 6653%} 6654 6655// shift != 0, base != 0 6656instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{ 6657 match(Set dst (EncodeP src)); 6658 effect(TEMP crx); 6659 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull && 6660 Universe::narrow_oop_shift() != 0 && 6661 Universe::narrow_oop_base_overlaps()); 6662 6663 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %} 6664 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx)); 6665%} 6666 6667// shift != 0, base != 0 6668instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{ 6669 match(Set dst (EncodeP src)); 6670 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull && 6671 Universe::narrow_oop_shift() != 0 && 6672 Universe::narrow_oop_base_overlaps()); 6673 6674 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %} 6675 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) ); 6676%} 6677 6678// shift != 0, base == 0 6679// TODO: This is the same as encodeP_shift. Merge! 6680instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{ 6681 match(Set dst (EncodeP src)); 6682 predicate(Universe::narrow_oop_shift() != 0 && 6683 Universe::narrow_oop_base() ==0); 6684 6685 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %} 6686 size(4); 6687 ins_encode %{ 6688 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6689 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); 6690 %} 6691 ins_pipe(pipe_class_default); 6692%} 6693 6694// Compressed OOPs with narrow_oop_shift == 0. 6695// shift == 0, base == 0 6696instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{ 6697 match(Set dst (EncodeP src)); 6698 predicate(Universe::narrow_oop_shift() == 0); 6699 6700 format %{ "MR $dst, $src \t// Ptr->Narrow" %} 6701 // variable size, 0 or 4. 6702 ins_encode %{ 6703 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6704 __ mr_if_needed($dst$$Register, $src$$Register); 6705 %} 6706 ins_pipe(pipe_class_default); 6707%} 6708 6709// Decode nodes. 6710 6711// Shift node for expand. 6712instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{ 6713 // The match rule is needed to make it a 'MachTypeNode'! 6714 match(Set dst (DecodeN src)); 6715 predicate(false); 6716 6717 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %} 6718 size(4); 6719 ins_encode %{ 6720 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 6721 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); 6722 %} 6723 ins_pipe(pipe_class_default); 6724%} 6725 6726// Add node for expand. 6727instruct decodeN_add(iRegPdst dst, iRegPdst src) %{ 6728 // The match rule is needed to make it a 'MachTypeNode'! 6729 match(Set dst (DecodeN src)); 6730 predicate(false); 6731 6732 format %{ "ADD $dst, $src, heapbase \t// DecodeN, add oop base" %} 6733 ins_encode %{ 6734 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6735 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0); 6736 %} 6737 ins_pipe(pipe_class_default); 6738%} 6739 6740// conditianal add base for expand 6741instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{ 6742 // The match rule is needed to make it a 'MachTypeNode'! 6743 // NOTICE that the rule is nonsense - we just have to make sure that: 6744 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) 6745 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. 6746 match(Set dst (DecodeN (Binary crx src))); 6747 predicate(false); 6748 6749 format %{ "BEQ $crx, done\n\t" 6750 "ADD $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n" 6751 "done:" %} 6752 ins_encode %{ 6753 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6754 Label done; 6755 __ beq($crx$$CondRegister, done); 6756 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0); 6757 __ bind(done); 6758 %} 6759 ins_pipe(pipe_class_default); 6760%} 6761 6762instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{ 6763 // The match rule is needed to make it a 'MachTypeNode'! 6764 // NOTICE that the rule is nonsense - we just have to make sure that: 6765 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) 6766 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. 6767 match(Set dst (DecodeN (Binary crx src1))); 6768 predicate(false); 6769 6770 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %} 6771 size(4); 6772 ins_encode %{ 6773 // This is a Power7 instruction for which no machine description exists. 6774 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6775 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 6776 %} 6777 ins_pipe(pipe_class_default); 6778%} 6779 6780// shift != 0, base != 0 6781instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 6782 match(Set dst (DecodeN src)); 6783 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6784 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && 6785 Universe::narrow_oop_shift() != 0 && 6786 Universe::narrow_oop_base() != 0); 6787 ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex. 6788 effect(TEMP crx); 6789 6790 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %} 6791 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) ); 6792%} 6793 6794// shift != 0, base == 0 6795instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{ 6796 match(Set dst (DecodeN src)); 6797 predicate(Universe::narrow_oop_shift() != 0 && 6798 Universe::narrow_oop_base() == 0); 6799 6800 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %} 6801 size(4); 6802 ins_encode %{ 6803 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 6804 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); 6805 %} 6806 ins_pipe(pipe_class_default); 6807%} 6808 6809// Optimize DecodeN for disjoint base. 6810// Shift narrow oop and or it into register that already contains the heap base. 6811// Base == dst must hold, and is assured by construction in postaloc_expand. 6812instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{ 6813 match(Set dst (DecodeN src)); 6814 effect(TEMP base); 6815 predicate(false); 6816 6817 format %{ "RLDIMI $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %} 6818 size(4); 6819 ins_encode %{ 6820 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 6821 __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift()); 6822 %} 6823 ins_pipe(pipe_class_default); 6824%} 6825 6826// Optimize DecodeN for disjoint base. 6827// This node requires only one cycle on the critical path. 6828// We must postalloc_expand as we can not express use_def effects where 6829// the used register is L and the def'ed register P. 6830instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{ 6831 match(Set dst (DecodeN src)); 6832 effect(TEMP_DEF dst); 6833 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6834 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 6835 Universe::narrow_oop_base_disjoint()); 6836 ins_cost(DEFAULT_COST); 6837 6838 format %{ "MOV $dst, heapbase \t\n" 6839 "RLDIMI $dst, $src, shift, 32-shift \t// decode with disjoint base" %} 6840 postalloc_expand %{ 6841 loadBaseNode *n1 = new loadBaseNode(); 6842 n1->add_req(NULL); 6843 n1->_opnds[0] = op_dst; 6844 6845 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode(); 6846 n2->add_req(n_region, n_src, n1); 6847 n2->_opnds[0] = op_dst; 6848 n2->_opnds[1] = op_src; 6849 n2->_opnds[2] = op_dst; 6850 n2->_bottom_type = _bottom_type; 6851 6852 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6853 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6854 6855 nodes->push(n1); 6856 nodes->push(n2); 6857 %} 6858%} 6859 6860instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 6861 match(Set dst (DecodeN src)); 6862 effect(TEMP_DEF dst, TEMP crx); 6863 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6864 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && 6865 Universe::narrow_oop_base_disjoint() && VM_Version::has_isel()); 6866 ins_cost(3 * DEFAULT_COST); 6867 6868 format %{ "DecodeN $dst, $src \t// decode with disjoint base using isel" %} 6869 postalloc_expand %{ 6870 loadBaseNode *n1 = new loadBaseNode(); 6871 n1->add_req(NULL); 6872 n1->_opnds[0] = op_dst; 6873 6874 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node(); 6875 n_compare->add_req(n_region, n_src); 6876 n_compare->_opnds[0] = op_crx; 6877 n_compare->_opnds[1] = op_src; 6878 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR); 6879 6880 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode(); 6881 n2->add_req(n_region, n_src, n1); 6882 n2->_opnds[0] = op_dst; 6883 n2->_opnds[1] = op_src; 6884 n2->_opnds[2] = op_dst; 6885 n2->_bottom_type = _bottom_type; 6886 6887 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode(); 6888 n_cond_set->add_req(n_region, n_compare, n2); 6889 n_cond_set->_opnds[0] = op_dst; 6890 n_cond_set->_opnds[1] = op_crx; 6891 n_cond_set->_opnds[2] = op_dst; 6892 n_cond_set->_bottom_type = _bottom_type; 6893 6894 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 6895 ra_->set_oop(n_cond_set, true); 6896 6897 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6898 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 6899 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6900 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6901 6902 nodes->push(n1); 6903 nodes->push(n_compare); 6904 nodes->push(n2); 6905 nodes->push(n_cond_set); 6906 %} 6907%} 6908 6909// src != 0, shift != 0, base != 0 6910instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{ 6911 match(Set dst (DecodeN src)); 6912 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6913 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 6914 Universe::narrow_oop_shift() != 0 && 6915 Universe::narrow_oop_base() != 0); 6916 ins_cost(2 * DEFAULT_COST); 6917 6918 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %} 6919 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src)); 6920%} 6921 6922// Compressed OOPs with narrow_oop_shift == 0. 6923instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{ 6924 match(Set dst (DecodeN src)); 6925 predicate(Universe::narrow_oop_shift() == 0); 6926 ins_cost(DEFAULT_COST); 6927 6928 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %} 6929 // variable size, 0 or 4. 6930 ins_encode %{ 6931 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6932 __ mr_if_needed($dst$$Register, $src$$Register); 6933 %} 6934 ins_pipe(pipe_class_default); 6935%} 6936 6937// Convert compressed oop into int for vectors alignment masking. 6938instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{ 6939 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); 6940 predicate(Universe::narrow_oop_shift() == 0); 6941 ins_cost(DEFAULT_COST); 6942 6943 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %} 6944 // variable size, 0 or 4. 6945 ins_encode %{ 6946 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6947 __ mr_if_needed($dst$$Register, $src$$Register); 6948 %} 6949 ins_pipe(pipe_class_default); 6950%} 6951 6952// Convert klass pointer into compressed form. 6953 6954// Nodes for postalloc expand. 6955 6956// Shift node for expand. 6957instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{ 6958 // The match rule is needed to make it a 'MachTypeNode'! 6959 match(Set dst (EncodePKlass src)); 6960 predicate(false); 6961 6962 format %{ "SRDI $dst, $src, 3 \t// encode" %} 6963 size(4); 6964 ins_encode %{ 6965 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6966 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); 6967 %} 6968 ins_pipe(pipe_class_default); 6969%} 6970 6971// Add node for expand. 6972instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ 6973 // The match rule is needed to make it a 'MachTypeNode'! 6974 match(Set dst (EncodePKlass (Binary base src))); 6975 predicate(false); 6976 6977 format %{ "SUB $dst, $base, $src \t// encode" %} 6978 size(4); 6979 ins_encode %{ 6980 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 6981 __ subf($dst$$Register, $base$$Register, $src$$Register); 6982 %} 6983 ins_pipe(pipe_class_default); 6984%} 6985 6986// Disjoint narrow oop base. 6987instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{ 6988 match(Set dst (EncodePKlass src)); 6989 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/); 6990 6991 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %} 6992 size(4); 6993 ins_encode %{ 6994 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6995 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32); 6996 %} 6997 ins_pipe(pipe_class_default); 6998%} 6999 7000// shift != 0, base != 0 7001instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{ 7002 match(Set dst (EncodePKlass (Binary base src))); 7003 predicate(false); 7004 7005 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} 7006 postalloc_expand %{ 7007 encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode(); 7008 n1->add_req(n_region, n_base, n_src); 7009 n1->_opnds[0] = op_dst; 7010 n1->_opnds[1] = op_base; 7011 n1->_opnds[2] = op_src; 7012 n1->_bottom_type = _bottom_type; 7013 7014 encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode(); 7015 n2->add_req(n_region, n1); 7016 n2->_opnds[0] = op_dst; 7017 n2->_opnds[1] = op_dst; 7018 n2->_bottom_type = _bottom_type; 7019 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7020 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7021 7022 nodes->push(n1); 7023 nodes->push(n2); 7024 %} 7025%} 7026 7027// shift != 0, base != 0 7028instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{ 7029 match(Set dst (EncodePKlass src)); 7030 //predicate(Universe::narrow_klass_shift() != 0 && 7031 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/); 7032 7033 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} 7034 ins_cost(DEFAULT_COST*2); // Don't count constant. 7035 expand %{ 7036 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %} 7037 iRegLdst base; 7038 loadConL_Ex(base, baseImm); 7039 encodePKlass_not_null_Ex(dst, base, src); 7040 %} 7041%} 7042 7043// Decode nodes. 7044 7045// Shift node for expand. 7046instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{ 7047 // The match rule is needed to make it a 'MachTypeNode'! 7048 match(Set dst (DecodeNKlass src)); 7049 predicate(false); 7050 7051 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %} 7052 size(4); 7053 ins_encode %{ 7054 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 7055 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); 7056 %} 7057 ins_pipe(pipe_class_default); 7058%} 7059 7060// Add node for expand. 7061 7062instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ 7063 // The match rule is needed to make it a 'MachTypeNode'! 7064 match(Set dst (DecodeNKlass (Binary base src))); 7065 predicate(false); 7066 7067 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %} 7068 size(4); 7069 ins_encode %{ 7070 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7071 __ add($dst$$Register, $base$$Register, $src$$Register); 7072 %} 7073 ins_pipe(pipe_class_default); 7074%} 7075 7076// src != 0, shift != 0, base != 0 7077instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{ 7078 match(Set dst (DecodeNKlass (Binary base src))); 7079 //effect(kill src); // We need a register for the immediate result after shifting. 7080 predicate(false); 7081 7082 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %} 7083 postalloc_expand %{ 7084 decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode(); 7085 n1->add_req(n_region, n_base, n_src); 7086 n1->_opnds[0] = op_dst; 7087 n1->_opnds[1] = op_base; 7088 n1->_opnds[2] = op_src; 7089 n1->_bottom_type = _bottom_type; 7090 7091 decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode(); 7092 n2->add_req(n_region, n1); 7093 n2->_opnds[0] = op_dst; 7094 n2->_opnds[1] = op_dst; 7095 n2->_bottom_type = _bottom_type; 7096 7097 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7098 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7099 7100 nodes->push(n1); 7101 nodes->push(n2); 7102 %} 7103%} 7104 7105// src != 0, shift != 0, base != 0 7106instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{ 7107 match(Set dst (DecodeNKlass src)); 7108 // predicate(Universe::narrow_klass_shift() != 0 && 7109 // Universe::narrow_klass_base() != 0); 7110 7111 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %} 7112 7113 ins_cost(DEFAULT_COST*2); // Don't count constant. 7114 expand %{ 7115 // We add first, then we shift. Like this, we can get along with one register less. 7116 // But we have to load the base pre-shifted. 7117 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %} 7118 iRegLdst base; 7119 loadConL_Ex(base, baseImm); 7120 decodeNKlass_notNull_addBase_Ex(dst, base, src); 7121 %} 7122%} 7123 7124//----------MemBar Instructions----------------------------------------------- 7125// Memory barrier flavors 7126 7127instruct membar_acquire() %{ 7128 match(LoadFence); 7129 ins_cost(4*MEMORY_REF_COST); 7130 7131 format %{ "MEMBAR-acquire" %} 7132 size(4); 7133 ins_encode %{ 7134 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7135 __ acquire(); 7136 %} 7137 ins_pipe(pipe_class_default); 7138%} 7139 7140instruct unnecessary_membar_acquire() %{ 7141 match(MemBarAcquire); 7142 ins_cost(0); 7143 7144 format %{ " -- \t// redundant MEMBAR-acquire - empty" %} 7145 size(0); 7146 ins_encode( /*empty*/ ); 7147 ins_pipe(pipe_class_default); 7148%} 7149 7150instruct membar_acquire_lock() %{ 7151 match(MemBarAcquireLock); 7152 ins_cost(0); 7153 7154 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %} 7155 size(0); 7156 ins_encode( /*empty*/ ); 7157 ins_pipe(pipe_class_default); 7158%} 7159 7160instruct membar_release() %{ 7161 match(MemBarRelease); 7162 match(StoreFence); 7163 ins_cost(4*MEMORY_REF_COST); 7164 7165 format %{ "MEMBAR-release" %} 7166 size(4); 7167 ins_encode %{ 7168 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7169 __ release(); 7170 %} 7171 ins_pipe(pipe_class_default); 7172%} 7173 7174instruct membar_storestore() %{ 7175 match(MemBarStoreStore); 7176 ins_cost(4*MEMORY_REF_COST); 7177 7178 format %{ "MEMBAR-store-store" %} 7179 size(4); 7180 ins_encode %{ 7181 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7182 __ membar(Assembler::StoreStore); 7183 %} 7184 ins_pipe(pipe_class_default); 7185%} 7186 7187instruct membar_release_lock() %{ 7188 match(MemBarReleaseLock); 7189 ins_cost(0); 7190 7191 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %} 7192 size(0); 7193 ins_encode( /*empty*/ ); 7194 ins_pipe(pipe_class_default); 7195%} 7196 7197instruct membar_volatile() %{ 7198 match(MemBarVolatile); 7199 ins_cost(4*MEMORY_REF_COST); 7200 7201 format %{ "MEMBAR-volatile" %} 7202 size(4); 7203 ins_encode %{ 7204 // TODO: PPC port $archOpcode(ppc64Opcode_sync); 7205 __ fence(); 7206 %} 7207 ins_pipe(pipe_class_default); 7208%} 7209 7210// This optimization is wrong on PPC. The following pattern is not supported: 7211// MemBarVolatile 7212// ^ ^ 7213// | | 7214// CtrlProj MemProj 7215// ^ ^ 7216// | | 7217// | Load 7218// | 7219// MemBarVolatile 7220// 7221// The first MemBarVolatile could get optimized out! According to 7222// Vladimir, this pattern can not occur on Oracle platforms. 7223// However, it does occur on PPC64 (because of membars in 7224// inline_unsafe_load_store). 7225// 7226// Add this node again if we found a good solution for inline_unsafe_load_store(). 7227// Don't forget to look at the implementation of post_store_load_barrier again, 7228// we did other fixes in that method. 7229//instruct unnecessary_membar_volatile() %{ 7230// match(MemBarVolatile); 7231// predicate(Matcher::post_store_load_barrier(n)); 7232// ins_cost(0); 7233// 7234// format %{ " -- \t// redundant MEMBAR-volatile - empty" %} 7235// size(0); 7236// ins_encode( /*empty*/ ); 7237// ins_pipe(pipe_class_default); 7238//%} 7239 7240instruct membar_CPUOrder() %{ 7241 match(MemBarCPUOrder); 7242 ins_cost(0); 7243 7244 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %} 7245 size(0); 7246 ins_encode( /*empty*/ ); 7247 ins_pipe(pipe_class_default); 7248%} 7249 7250//----------Conditional Move--------------------------------------------------- 7251 7252// Cmove using isel. 7253instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{ 7254 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7255 predicate(VM_Version::has_isel()); 7256 ins_cost(DEFAULT_COST); 7257 7258 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7259 size(4); 7260 ins_encode %{ 7261 // This is a Power7 instruction for which no machine description 7262 // exists. Anyways, the scheduler should be off on Power7. 7263 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7264 int cc = $cmp$$cmpcode; 7265 __ isel($dst$$Register, $crx$$CondRegister, 7266 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7267 %} 7268 ins_pipe(pipe_class_default); 7269%} 7270 7271instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{ 7272 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7273 predicate(!VM_Version::has_isel()); 7274 ins_cost(DEFAULT_COST+BRANCH_COST); 7275 7276 ins_variable_size_depending_on_alignment(true); 7277 7278 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7279 // Worst case is branch + move + stop, no stop without scheduler 7280 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7281 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7282 ins_pipe(pipe_class_default); 7283%} 7284 7285instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{ 7286 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7287 ins_cost(DEFAULT_COST+BRANCH_COST); 7288 7289 ins_variable_size_depending_on_alignment(true); 7290 7291 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7292 // Worst case is branch + move + stop, no stop without scheduler 7293 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7294 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7295 ins_pipe(pipe_class_default); 7296%} 7297 7298// Cmove using isel. 7299instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{ 7300 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7301 predicate(VM_Version::has_isel()); 7302 ins_cost(DEFAULT_COST); 7303 7304 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7305 size(4); 7306 ins_encode %{ 7307 // This is a Power7 instruction for which no machine description 7308 // exists. Anyways, the scheduler should be off on Power7. 7309 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7310 int cc = $cmp$$cmpcode; 7311 __ isel($dst$$Register, $crx$$CondRegister, 7312 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7313 %} 7314 ins_pipe(pipe_class_default); 7315%} 7316 7317instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{ 7318 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7319 predicate(!VM_Version::has_isel()); 7320 ins_cost(DEFAULT_COST+BRANCH_COST); 7321 7322 ins_variable_size_depending_on_alignment(true); 7323 7324 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7325 // Worst case is branch + move + stop, no stop without scheduler. 7326 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7327 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7328 ins_pipe(pipe_class_default); 7329%} 7330 7331instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{ 7332 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7333 ins_cost(DEFAULT_COST+BRANCH_COST); 7334 7335 ins_variable_size_depending_on_alignment(true); 7336 7337 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7338 // Worst case is branch + move + stop, no stop without scheduler. 7339 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7340 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7341 ins_pipe(pipe_class_default); 7342%} 7343 7344// Cmove using isel. 7345instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{ 7346 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7347 predicate(VM_Version::has_isel()); 7348 ins_cost(DEFAULT_COST); 7349 7350 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7351 size(4); 7352 ins_encode %{ 7353 // This is a Power7 instruction for which no machine description 7354 // exists. Anyways, the scheduler should be off on Power7. 7355 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7356 int cc = $cmp$$cmpcode; 7357 __ isel($dst$$Register, $crx$$CondRegister, 7358 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7359 %} 7360 ins_pipe(pipe_class_default); 7361%} 7362 7363// Conditional move for RegN. Only cmov(reg, reg). 7364instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{ 7365 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7366 predicate(!VM_Version::has_isel()); 7367 ins_cost(DEFAULT_COST+BRANCH_COST); 7368 7369 ins_variable_size_depending_on_alignment(true); 7370 7371 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7372 // Worst case is branch + move + stop, no stop without scheduler. 7373 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7374 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7375 ins_pipe(pipe_class_default); 7376%} 7377 7378instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{ 7379 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7380 ins_cost(DEFAULT_COST+BRANCH_COST); 7381 7382 ins_variable_size_depending_on_alignment(true); 7383 7384 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7385 // Worst case is branch + move + stop, no stop without scheduler. 7386 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7387 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7388 ins_pipe(pipe_class_default); 7389%} 7390 7391// Cmove using isel. 7392instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{ 7393 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7394 predicate(VM_Version::has_isel()); 7395 ins_cost(DEFAULT_COST); 7396 7397 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7398 size(4); 7399 ins_encode %{ 7400 // This is a Power7 instruction for which no machine description 7401 // exists. Anyways, the scheduler should be off on Power7. 7402 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7403 int cc = $cmp$$cmpcode; 7404 __ isel($dst$$Register, $crx$$CondRegister, 7405 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7406 %} 7407 ins_pipe(pipe_class_default); 7408%} 7409 7410instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{ 7411 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7412 predicate(!VM_Version::has_isel()); 7413 ins_cost(DEFAULT_COST+BRANCH_COST); 7414 7415 ins_variable_size_depending_on_alignment(true); 7416 7417 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7418 // Worst case is branch + move + stop, no stop without scheduler. 7419 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7420 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7421 ins_pipe(pipe_class_default); 7422%} 7423 7424instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{ 7425 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7426 ins_cost(DEFAULT_COST+BRANCH_COST); 7427 7428 ins_variable_size_depending_on_alignment(true); 7429 7430 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7431 // Worst case is branch + move + stop, no stop without scheduler. 7432 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7433 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7434 ins_pipe(pipe_class_default); 7435%} 7436 7437instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{ 7438 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src))); 7439 ins_cost(DEFAULT_COST+BRANCH_COST); 7440 7441 ins_variable_size_depending_on_alignment(true); 7442 7443 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} 7444 // Worst case is branch + move + stop, no stop without scheduler. 7445 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 7446 ins_encode %{ 7447 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); 7448 Label done; 7449 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 7450 // Branch if not (cmp crx). 7451 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 7452 __ fmr($dst$$FloatRegister, $src$$FloatRegister); 7453 // TODO PPC port __ endgroup_if_needed(_size == 12); 7454 __ bind(done); 7455 %} 7456 ins_pipe(pipe_class_default); 7457%} 7458 7459instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{ 7460 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src))); 7461 ins_cost(DEFAULT_COST+BRANCH_COST); 7462 7463 ins_variable_size_depending_on_alignment(true); 7464 7465 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} 7466 // Worst case is branch + move + stop, no stop without scheduler. 7467 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 7468 ins_encode %{ 7469 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); 7470 Label done; 7471 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 7472 // Branch if not (cmp crx). 7473 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 7474 __ fmr($dst$$FloatRegister, $src$$FloatRegister); 7475 // TODO PPC port __ endgroup_if_needed(_size == 12); 7476 __ bind(done); 7477 %} 7478 ins_pipe(pipe_class_default); 7479%} 7480 7481//----------Conditional_store-------------------------------------------------- 7482// Conditional-store of the updated heap-top. 7483// Used during allocation of the shared heap. 7484// Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7485 7486// As compareAndSwapL, but return flag register instead of boolean value in 7487// int register. 7488// Used by sun/misc/AtomicLongCSImpl.java. 7489// Mem_ptr must be a memory operand, else this node does not get 7490// Flag_needs_anti_dependence_check set by adlc. If this is not set this node 7491// can be rematerialized which leads to errors. 7492instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{ 7493 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal))); 7494 effect(TEMP cr0); 7495 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} 7496 ins_encode %{ 7497 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7498 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, 7499 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(), 7500 noreg, NULL, true); 7501 %} 7502 ins_pipe(pipe_class_default); 7503%} 7504 7505// As compareAndSwapP, but return flag register instead of boolean value in 7506// int register. 7507// This instruction is matched if UseTLAB is off. 7508// Mem_ptr must be a memory operand, else this node does not get 7509// Flag_needs_anti_dependence_check set by adlc. If this is not set this node 7510// can be rematerialized which leads to errors. 7511instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{ 7512 match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal))); 7513 ins_cost(2*MEMORY_REF_COST); 7514 7515 format %{ "STDCX_ if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} 7516 ins_encode %{ 7517 // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_); 7518 __ stdcx_($newVal$$Register, $mem_ptr$$Register); 7519 %} 7520 ins_pipe(pipe_class_memory); 7521%} 7522 7523// Implement LoadPLocked. Must be ordered against changes of the memory location 7524// by storePConditional. 7525// Don't know whether this is ever used. 7526instruct loadPLocked(iRegPdst dst, memory mem) %{ 7527 match(Set dst (LoadPLocked mem)); 7528 ins_cost(2*MEMORY_REF_COST); 7529 7530 format %{ "LDARX $dst, $mem \t// loadPLocked\n\t" %} 7531 size(4); 7532 ins_encode %{ 7533 // TODO: PPC port $archOpcode(ppc64Opcode_ldarx); 7534 __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update()); 7535 %} 7536 ins_pipe(pipe_class_memory); 7537%} 7538 7539//----------Compare-And-Swap--------------------------------------------------- 7540 7541// CompareAndSwap{P,I,L} have more than one output, therefore "CmpI 7542// (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be 7543// matched. 7544 7545instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{ 7546 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2))); 7547 effect(TEMP cr0); 7548 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} 7549 // Variable size: instruction count smaller if regs are disjoint. 7550 ins_encode %{ 7551 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7552 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7553 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7554 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7555 $res$$Register, true); 7556 %} 7557 ins_pipe(pipe_class_default); 7558%} 7559 7560instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{ 7561 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2))); 7562 effect(TEMP cr0); 7563 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} 7564 // Variable size: instruction count smaller if regs are disjoint. 7565 ins_encode %{ 7566 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7567 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7568 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7569 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7570 $res$$Register, true); 7571 %} 7572 ins_pipe(pipe_class_default); 7573%} 7574 7575instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{ 7576 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2))); 7577 effect(TEMP cr0); 7578 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %} 7579 // Variable size: instruction count smaller if regs are disjoint. 7580 ins_encode %{ 7581 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7582 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7583 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7584 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7585 $res$$Register, NULL, true); 7586 %} 7587 ins_pipe(pipe_class_default); 7588%} 7589 7590instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{ 7591 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2))); 7592 effect(TEMP cr0); 7593 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %} 7594 // Variable size: instruction count smaller if regs are disjoint. 7595 ins_encode %{ 7596 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7597 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7598 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7599 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7600 $res$$Register, NULL, true); 7601 %} 7602 ins_pipe(pipe_class_default); 7603%} 7604 7605instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{ 7606 match(Set res (GetAndAddI mem_ptr src)); 7607 effect(TEMP cr0); 7608 format %{ "GetAndAddI $res, $mem_ptr, $src" %} 7609 // Variable size: instruction count smaller if regs are disjoint. 7610 ins_encode( enc_GetAndAddI(res, mem_ptr, src) ); 7611 ins_pipe(pipe_class_default); 7612%} 7613 7614instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{ 7615 match(Set res (GetAndAddL mem_ptr src)); 7616 effect(TEMP cr0); 7617 format %{ "GetAndAddL $res, $mem_ptr, $src" %} 7618 // Variable size: instruction count smaller if regs are disjoint. 7619 ins_encode( enc_GetAndAddL(res, mem_ptr, src) ); 7620 ins_pipe(pipe_class_default); 7621%} 7622 7623instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{ 7624 match(Set res (GetAndSetI mem_ptr src)); 7625 effect(TEMP cr0); 7626 format %{ "GetAndSetI $res, $mem_ptr, $src" %} 7627 // Variable size: instruction count smaller if regs are disjoint. 7628 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); 7629 ins_pipe(pipe_class_default); 7630%} 7631 7632instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{ 7633 match(Set res (GetAndSetL mem_ptr src)); 7634 effect(TEMP cr0); 7635 format %{ "GetAndSetL $res, $mem_ptr, $src" %} 7636 // Variable size: instruction count smaller if regs are disjoint. 7637 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); 7638 ins_pipe(pipe_class_default); 7639%} 7640 7641instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{ 7642 match(Set res (GetAndSetP mem_ptr src)); 7643 effect(TEMP cr0); 7644 format %{ "GetAndSetP $res, $mem_ptr, $src" %} 7645 // Variable size: instruction count smaller if regs are disjoint. 7646 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); 7647 ins_pipe(pipe_class_default); 7648%} 7649 7650instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{ 7651 match(Set res (GetAndSetN mem_ptr src)); 7652 effect(TEMP cr0); 7653 format %{ "GetAndSetN $res, $mem_ptr, $src" %} 7654 // Variable size: instruction count smaller if regs are disjoint. 7655 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); 7656 ins_pipe(pipe_class_default); 7657%} 7658 7659//----------Arithmetic Instructions-------------------------------------------- 7660// Addition Instructions 7661 7662// Register Addition 7663instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{ 7664 match(Set dst (AddI src1 src2)); 7665 format %{ "ADD $dst, $src1, $src2" %} 7666 size(4); 7667 ins_encode %{ 7668 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7669 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7670 %} 7671 ins_pipe(pipe_class_default); 7672%} 7673 7674// Expand does not work with above instruct. (??) 7675instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7676 // no match-rule 7677 effect(DEF dst, USE src1, USE src2); 7678 format %{ "ADD $dst, $src1, $src2" %} 7679 size(4); 7680 ins_encode %{ 7681 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7682 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7683 %} 7684 ins_pipe(pipe_class_default); 7685%} 7686 7687instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 7688 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4)); 7689 ins_cost(DEFAULT_COST*3); 7690 7691 expand %{ 7692 // FIXME: we should do this in the ideal world. 7693 iRegIdst tmp1; 7694 iRegIdst tmp2; 7695 addI_reg_reg(tmp1, src1, src2); 7696 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg. 7697 addI_reg_reg(dst, tmp1, tmp2); 7698 %} 7699%} 7700 7701// Immediate Addition 7702instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 7703 match(Set dst (AddI src1 src2)); 7704 format %{ "ADDI $dst, $src1, $src2" %} 7705 size(4); 7706 ins_encode %{ 7707 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7708 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7709 %} 7710 ins_pipe(pipe_class_default); 7711%} 7712 7713// Immediate Addition with 16-bit shifted operand 7714instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{ 7715 match(Set dst (AddI src1 src2)); 7716 format %{ "ADDIS $dst, $src1, $src2" %} 7717 size(4); 7718 ins_encode %{ 7719 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7720 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7721 %} 7722 ins_pipe(pipe_class_default); 7723%} 7724 7725// Long Addition 7726instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7727 match(Set dst (AddL src1 src2)); 7728 format %{ "ADD $dst, $src1, $src2 \t// long" %} 7729 size(4); 7730 ins_encode %{ 7731 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7732 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7733 %} 7734 ins_pipe(pipe_class_default); 7735%} 7736 7737// Expand does not work with above instruct. (??) 7738instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7739 // no match-rule 7740 effect(DEF dst, USE src1, USE src2); 7741 format %{ "ADD $dst, $src1, $src2 \t// long" %} 7742 size(4); 7743 ins_encode %{ 7744 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7745 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7746 %} 7747 ins_pipe(pipe_class_default); 7748%} 7749 7750instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{ 7751 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4)); 7752 ins_cost(DEFAULT_COST*3); 7753 7754 expand %{ 7755 // FIXME: we should do this in the ideal world. 7756 iRegLdst tmp1; 7757 iRegLdst tmp2; 7758 addL_reg_reg(tmp1, src1, src2); 7759 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. 7760 addL_reg_reg(dst, tmp1, tmp2); 7761 %} 7762%} 7763 7764// AddL + ConvL2I. 7765instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7766 match(Set dst (ConvL2I (AddL src1 src2))); 7767 7768 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %} 7769 size(4); 7770 ins_encode %{ 7771 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7772 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7773 %} 7774 ins_pipe(pipe_class_default); 7775%} 7776 7777// No constant pool entries required. 7778instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 7779 match(Set dst (AddL src1 src2)); 7780 7781 format %{ "ADDI $dst, $src1, $src2" %} 7782 size(4); 7783 ins_encode %{ 7784 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7785 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7786 %} 7787 ins_pipe(pipe_class_default); 7788%} 7789 7790// Long Immediate Addition with 16-bit shifted operand. 7791// No constant pool entries required. 7792instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{ 7793 match(Set dst (AddL src1 src2)); 7794 7795 format %{ "ADDIS $dst, $src1, $src2" %} 7796 size(4); 7797 ins_encode %{ 7798 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7799 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7800 %} 7801 ins_pipe(pipe_class_default); 7802%} 7803 7804// Pointer Register Addition 7805instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{ 7806 match(Set dst (AddP src1 src2)); 7807 format %{ "ADD $dst, $src1, $src2" %} 7808 size(4); 7809 ins_encode %{ 7810 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7811 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7812 %} 7813 ins_pipe(pipe_class_default); 7814%} 7815 7816// Pointer Immediate Addition 7817// No constant pool entries required. 7818instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{ 7819 match(Set dst (AddP src1 src2)); 7820 7821 format %{ "ADDI $dst, $src1, $src2" %} 7822 size(4); 7823 ins_encode %{ 7824 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7825 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7826 %} 7827 ins_pipe(pipe_class_default); 7828%} 7829 7830// Pointer Immediate Addition with 16-bit shifted operand. 7831// No constant pool entries required. 7832instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{ 7833 match(Set dst (AddP src1 src2)); 7834 7835 format %{ "ADDIS $dst, $src1, $src2" %} 7836 size(4); 7837 ins_encode %{ 7838 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7839 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7840 %} 7841 ins_pipe(pipe_class_default); 7842%} 7843 7844//--------------------- 7845// Subtraction Instructions 7846 7847// Register Subtraction 7848instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7849 match(Set dst (SubI src1 src2)); 7850 format %{ "SUBF $dst, $src2, $src1" %} 7851 size(4); 7852 ins_encode %{ 7853 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7854 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7855 %} 7856 ins_pipe(pipe_class_default); 7857%} 7858 7859// Immediate Subtraction 7860// Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal), 7861// Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16. 7862 7863// SubI from constant (using subfic). 7864instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{ 7865 match(Set dst (SubI src1 src2)); 7866 format %{ "SUBI $dst, $src1, $src2" %} 7867 7868 size(4); 7869 ins_encode %{ 7870 // TODO: PPC port $archOpcode(ppc64Opcode_subfic); 7871 __ subfic($dst$$Register, $src2$$Register, $src1$$constant); 7872 %} 7873 ins_pipe(pipe_class_default); 7874%} 7875 7876// Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for 7877// positive integers and 0xF...F for negative ones. 7878instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{ 7879 // no match-rule, false predicate 7880 effect(DEF dst, USE src); 7881 predicate(false); 7882 7883 format %{ "SRAWI $dst, $src, #31" %} 7884 size(4); 7885 ins_encode %{ 7886 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 7887 __ srawi($dst$$Register, $src$$Register, 0x1f); 7888 %} 7889 ins_pipe(pipe_class_default); 7890%} 7891 7892instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{ 7893 match(Set dst (AbsI src)); 7894 ins_cost(DEFAULT_COST*3); 7895 7896 expand %{ 7897 iRegIdst tmp1; 7898 iRegIdst tmp2; 7899 signmask32I_regI(tmp1, src); 7900 xorI_reg_reg(tmp2, tmp1, src); 7901 subI_reg_reg(dst, tmp2, tmp1); 7902 %} 7903%} 7904 7905instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{ 7906 match(Set dst (SubI zero src2)); 7907 format %{ "NEG $dst, $src2" %} 7908 size(4); 7909 ins_encode %{ 7910 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7911 __ neg($dst$$Register, $src2$$Register); 7912 %} 7913 ins_pipe(pipe_class_default); 7914%} 7915 7916// Long subtraction 7917instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7918 match(Set dst (SubL src1 src2)); 7919 format %{ "SUBF $dst, $src2, $src1 \t// long" %} 7920 size(4); 7921 ins_encode %{ 7922 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7923 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7924 %} 7925 ins_pipe(pipe_class_default); 7926%} 7927 7928// SubL + convL2I. 7929instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7930 match(Set dst (ConvL2I (SubL src1 src2))); 7931 7932 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %} 7933 size(4); 7934 ins_encode %{ 7935 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7936 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7937 %} 7938 ins_pipe(pipe_class_default); 7939%} 7940 7941// Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 7942// positive longs and 0xF...F for negative ones. 7943instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{ 7944 // no match-rule, false predicate 7945 effect(DEF dst, USE src); 7946 predicate(false); 7947 7948 format %{ "SRADI $dst, $src, #63" %} 7949 size(4); 7950 ins_encode %{ 7951 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 7952 __ sradi($dst$$Register, $src$$Register, 0x3f); 7953 %} 7954 ins_pipe(pipe_class_default); 7955%} 7956 7957// Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 7958// positive longs and 0xF...F for negative ones. 7959instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{ 7960 // no match-rule, false predicate 7961 effect(DEF dst, USE src); 7962 predicate(false); 7963 7964 format %{ "SRADI $dst, $src, #63" %} 7965 size(4); 7966 ins_encode %{ 7967 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 7968 __ sradi($dst$$Register, $src$$Register, 0x3f); 7969 %} 7970 ins_pipe(pipe_class_default); 7971%} 7972 7973// Long negation 7974instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{ 7975 match(Set dst (SubL zero src2)); 7976 format %{ "NEG $dst, $src2 \t// long" %} 7977 size(4); 7978 ins_encode %{ 7979 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7980 __ neg($dst$$Register, $src2$$Register); 7981 %} 7982 ins_pipe(pipe_class_default); 7983%} 7984 7985// NegL + ConvL2I. 7986instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{ 7987 match(Set dst (ConvL2I (SubL zero src2))); 7988 7989 format %{ "NEG $dst, $src2 \t// long + l2i" %} 7990 size(4); 7991 ins_encode %{ 7992 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7993 __ neg($dst$$Register, $src2$$Register); 7994 %} 7995 ins_pipe(pipe_class_default); 7996%} 7997 7998// Multiplication Instructions 7999// Integer Multiplication 8000 8001// Register Multiplication 8002instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8003 match(Set dst (MulI src1 src2)); 8004 ins_cost(DEFAULT_COST); 8005 8006 format %{ "MULLW $dst, $src1, $src2" %} 8007 size(4); 8008 ins_encode %{ 8009 // TODO: PPC port $archOpcode(ppc64Opcode_mullw); 8010 __ mullw($dst$$Register, $src1$$Register, $src2$$Register); 8011 %} 8012 ins_pipe(pipe_class_default); 8013%} 8014 8015// Immediate Multiplication 8016instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 8017 match(Set dst (MulI src1 src2)); 8018 ins_cost(DEFAULT_COST); 8019 8020 format %{ "MULLI $dst, $src1, $src2" %} 8021 size(4); 8022 ins_encode %{ 8023 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); 8024 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); 8025 %} 8026 ins_pipe(pipe_class_default); 8027%} 8028 8029instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8030 match(Set dst (MulL src1 src2)); 8031 ins_cost(DEFAULT_COST); 8032 8033 format %{ "MULLD $dst $src1, $src2 \t// long" %} 8034 size(4); 8035 ins_encode %{ 8036 // TODO: PPC port $archOpcode(ppc64Opcode_mulld); 8037 __ mulld($dst$$Register, $src1$$Register, $src2$$Register); 8038 %} 8039 ins_pipe(pipe_class_default); 8040%} 8041 8042// Multiply high for optimized long division by constant. 8043instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8044 match(Set dst (MulHiL src1 src2)); 8045 ins_cost(DEFAULT_COST); 8046 8047 format %{ "MULHD $dst $src1, $src2 \t// long" %} 8048 size(4); 8049 ins_encode %{ 8050 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd); 8051 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register); 8052 %} 8053 ins_pipe(pipe_class_default); 8054%} 8055 8056// Immediate Multiplication 8057instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 8058 match(Set dst (MulL src1 src2)); 8059 ins_cost(DEFAULT_COST); 8060 8061 format %{ "MULLI $dst, $src1, $src2" %} 8062 size(4); 8063 ins_encode %{ 8064 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); 8065 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); 8066 %} 8067 ins_pipe(pipe_class_default); 8068%} 8069 8070// Integer Division with Immediate -1: Negate. 8071instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ 8072 match(Set dst (DivI src1 src2)); 8073 ins_cost(DEFAULT_COST); 8074 8075 format %{ "NEG $dst, $src1 \t// /-1" %} 8076 size(4); 8077 ins_encode %{ 8078 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8079 __ neg($dst$$Register, $src1$$Register); 8080 %} 8081 ins_pipe(pipe_class_default); 8082%} 8083 8084// Integer Division with constant, but not -1. 8085// We should be able to improve this by checking the type of src2. 8086// It might well be that src2 is known to be positive. 8087instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8088 match(Set dst (DivI src1 src2)); 8089 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1 8090 ins_cost(2*DEFAULT_COST); 8091 8092 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %} 8093 size(4); 8094 ins_encode %{ 8095 // TODO: PPC port $archOpcode(ppc64Opcode_divw); 8096 __ divw($dst$$Register, $src1$$Register, $src2$$Register); 8097 %} 8098 ins_pipe(pipe_class_default); 8099%} 8100 8101instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{ 8102 effect(USE_DEF dst, USE src1, USE crx); 8103 predicate(false); 8104 8105 ins_variable_size_depending_on_alignment(true); 8106 8107 format %{ "CMOVE $dst, neg($src1), $crx" %} 8108 // Worst case is branch + move + stop, no stop without scheduler. 8109 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 8110 ins_encode %{ 8111 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 8112 Label done; 8113 __ bne($crx$$CondRegister, done); 8114 __ neg($dst$$Register, $src1$$Register); 8115 // TODO PPC port __ endgroup_if_needed(_size == 12); 8116 __ bind(done); 8117 %} 8118 ins_pipe(pipe_class_default); 8119%} 8120 8121// Integer Division with Registers not containing constants. 8122instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8123 match(Set dst (DivI src1 src2)); 8124 ins_cost(10*DEFAULT_COST); 8125 8126 expand %{ 8127 immI16 imm %{ (int)-1 %} 8128 flagsReg tmp1; 8129 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 8130 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 8131 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 8132 %} 8133%} 8134 8135// Long Division with Immediate -1: Negate. 8136instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ 8137 match(Set dst (DivL src1 src2)); 8138 ins_cost(DEFAULT_COST); 8139 8140 format %{ "NEG $dst, $src1 \t// /-1, long" %} 8141 size(4); 8142 ins_encode %{ 8143 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8144 __ neg($dst$$Register, $src1$$Register); 8145 %} 8146 ins_pipe(pipe_class_default); 8147%} 8148 8149// Long Division with constant, but not -1. 8150instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8151 match(Set dst (DivL src1 src2)); 8152 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1. 8153 ins_cost(2*DEFAULT_COST); 8154 8155 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %} 8156 size(4); 8157 ins_encode %{ 8158 // TODO: PPC port $archOpcode(ppc64Opcode_divd); 8159 __ divd($dst$$Register, $src1$$Register, $src2$$Register); 8160 %} 8161 ins_pipe(pipe_class_default); 8162%} 8163 8164instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{ 8165 effect(USE_DEF dst, USE src1, USE crx); 8166 predicate(false); 8167 8168 ins_variable_size_depending_on_alignment(true); 8169 8170 format %{ "CMOVE $dst, neg($src1), $crx" %} 8171 // Worst case is branch + move + stop, no stop without scheduler. 8172 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 8173 ins_encode %{ 8174 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 8175 Label done; 8176 __ bne($crx$$CondRegister, done); 8177 __ neg($dst$$Register, $src1$$Register); 8178 // TODO PPC port __ endgroup_if_needed(_size == 12); 8179 __ bind(done); 8180 %} 8181 ins_pipe(pipe_class_default); 8182%} 8183 8184// Long Division with Registers not containing constants. 8185instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8186 match(Set dst (DivL src1 src2)); 8187 ins_cost(10*DEFAULT_COST); 8188 8189 expand %{ 8190 immL16 imm %{ (int)-1 %} 8191 flagsReg tmp1; 8192 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 8193 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 8194 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 8195 %} 8196%} 8197 8198// Integer Remainder with registers. 8199instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8200 match(Set dst (ModI src1 src2)); 8201 ins_cost(10*DEFAULT_COST); 8202 8203 expand %{ 8204 immI16 imm %{ (int)-1 %} 8205 flagsReg tmp1; 8206 iRegIdst tmp2; 8207 iRegIdst tmp3; 8208 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 8209 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 8210 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 8211 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 8212 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 8213 %} 8214%} 8215 8216// Long Remainder with registers 8217instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8218 match(Set dst (ModL src1 src2)); 8219 ins_cost(10*DEFAULT_COST); 8220 8221 expand %{ 8222 immL16 imm %{ (int)-1 %} 8223 flagsReg tmp1; 8224 iRegLdst tmp2; 8225 iRegLdst tmp3; 8226 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 8227 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 8228 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 8229 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 8230 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 8231 %} 8232%} 8233 8234// Integer Shift Instructions 8235 8236// Register Shift Left 8237 8238// Clear all but the lowest #mask bits. 8239// Used to normalize shift amounts in registers. 8240instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{ 8241 // no match-rule, false predicate 8242 effect(DEF dst, USE src, USE mask); 8243 predicate(false); 8244 8245 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %} 8246 size(4); 8247 ins_encode %{ 8248 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8249 __ clrldi($dst$$Register, $src$$Register, $mask$$constant); 8250 %} 8251 ins_pipe(pipe_class_default); 8252%} 8253 8254instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8255 // no match-rule, false predicate 8256 effect(DEF dst, USE src1, USE src2); 8257 predicate(false); 8258 8259 format %{ "SLW $dst, $src1, $src2" %} 8260 size(4); 8261 ins_encode %{ 8262 // TODO: PPC port $archOpcode(ppc64Opcode_slw); 8263 __ slw($dst$$Register, $src1$$Register, $src2$$Register); 8264 %} 8265 ins_pipe(pipe_class_default); 8266%} 8267 8268instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8269 match(Set dst (LShiftI src1 src2)); 8270 ins_cost(DEFAULT_COST*2); 8271 expand %{ 8272 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8273 iRegIdst tmpI; 8274 maskI_reg_imm(tmpI, src2, mask); 8275 lShiftI_reg_reg(dst, src1, tmpI); 8276 %} 8277%} 8278 8279// Register Shift Left Immediate 8280instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8281 match(Set dst (LShiftI src1 src2)); 8282 8283 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %} 8284 size(4); 8285 ins_encode %{ 8286 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8287 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8288 %} 8289 ins_pipe(pipe_class_default); 8290%} 8291 8292// AndI with negpow2-constant + LShiftI 8293instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ 8294 match(Set dst (LShiftI (AndI src1 src2) src3)); 8295 predicate(UseRotateAndMaskInstructionsPPC64); 8296 8297 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %} 8298 size(4); 8299 ins_encode %{ 8300 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi 8301 long src2 = $src2$$constant; 8302 long src3 = $src3$$constant; 8303 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); 8304 if (maskbits >= 32) { 8305 __ li($dst$$Register, 0); // addi 8306 } else { 8307 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f); 8308 } 8309 %} 8310 ins_pipe(pipe_class_default); 8311%} 8312 8313// RShiftI + AndI with negpow2-constant + LShiftI 8314instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ 8315 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3)); 8316 predicate(UseRotateAndMaskInstructionsPPC64); 8317 8318 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %} 8319 size(4); 8320 ins_encode %{ 8321 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi 8322 long src2 = $src2$$constant; 8323 long src3 = $src3$$constant; 8324 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); 8325 if (maskbits >= 32) { 8326 __ li($dst$$Register, 0); // addi 8327 } else { 8328 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f); 8329 } 8330 %} 8331 ins_pipe(pipe_class_default); 8332%} 8333 8334instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8335 // no match-rule, false predicate 8336 effect(DEF dst, USE src1, USE src2); 8337 predicate(false); 8338 8339 format %{ "SLD $dst, $src1, $src2" %} 8340 size(4); 8341 ins_encode %{ 8342 // TODO: PPC port $archOpcode(ppc64Opcode_sld); 8343 __ sld($dst$$Register, $src1$$Register, $src2$$Register); 8344 %} 8345 ins_pipe(pipe_class_default); 8346%} 8347 8348// Register Shift Left 8349instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8350 match(Set dst (LShiftL src1 src2)); 8351 ins_cost(DEFAULT_COST*2); 8352 expand %{ 8353 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8354 iRegIdst tmpI; 8355 maskI_reg_imm(tmpI, src2, mask); 8356 lShiftL_regL_regI(dst, src1, tmpI); 8357 %} 8358%} 8359 8360// Register Shift Left Immediate 8361instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8362 match(Set dst (LShiftL src1 src2)); 8363 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %} 8364 size(4); 8365 ins_encode %{ 8366 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8367 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8368 %} 8369 ins_pipe(pipe_class_default); 8370%} 8371 8372// If we shift more than 32 bits, we need not convert I2L. 8373instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{ 8374 match(Set dst (LShiftL (ConvI2L src1) src2)); 8375 ins_cost(DEFAULT_COST); 8376 8377 size(4); 8378 format %{ "SLDI $dst, i2l($src1), $src2" %} 8379 ins_encode %{ 8380 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8381 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8382 %} 8383 ins_pipe(pipe_class_default); 8384%} 8385 8386// Shift a postivie int to the left. 8387// Clrlsldi clears the upper 32 bits and shifts. 8388instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{ 8389 match(Set dst (LShiftL (ConvI2L src1) src2)); 8390 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int()); 8391 8392 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %} 8393 size(4); 8394 ins_encode %{ 8395 // TODO: PPC port $archOpcode(ppc64Opcode_rldic); 8396 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant); 8397 %} 8398 ins_pipe(pipe_class_default); 8399%} 8400 8401instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8402 // no match-rule, false predicate 8403 effect(DEF dst, USE src1, USE src2); 8404 predicate(false); 8405 8406 format %{ "SRAW $dst, $src1, $src2" %} 8407 size(4); 8408 ins_encode %{ 8409 // TODO: PPC port $archOpcode(ppc64Opcode_sraw); 8410 __ sraw($dst$$Register, $src1$$Register, $src2$$Register); 8411 %} 8412 ins_pipe(pipe_class_default); 8413%} 8414 8415// Register Arithmetic Shift Right 8416instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8417 match(Set dst (RShiftI src1 src2)); 8418 ins_cost(DEFAULT_COST*2); 8419 expand %{ 8420 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8421 iRegIdst tmpI; 8422 maskI_reg_imm(tmpI, src2, mask); 8423 arShiftI_reg_reg(dst, src1, tmpI); 8424 %} 8425%} 8426 8427// Register Arithmetic Shift Right Immediate 8428instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8429 match(Set dst (RShiftI src1 src2)); 8430 8431 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %} 8432 size(4); 8433 ins_encode %{ 8434 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 8435 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8436 %} 8437 ins_pipe(pipe_class_default); 8438%} 8439 8440instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8441 // no match-rule, false predicate 8442 effect(DEF dst, USE src1, USE src2); 8443 predicate(false); 8444 8445 format %{ "SRAD $dst, $src1, $src2" %} 8446 size(4); 8447 ins_encode %{ 8448 // TODO: PPC port $archOpcode(ppc64Opcode_srad); 8449 __ srad($dst$$Register, $src1$$Register, $src2$$Register); 8450 %} 8451 ins_pipe(pipe_class_default); 8452%} 8453 8454// Register Shift Right Arithmetic Long 8455instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8456 match(Set dst (RShiftL src1 src2)); 8457 ins_cost(DEFAULT_COST*2); 8458 8459 expand %{ 8460 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8461 iRegIdst tmpI; 8462 maskI_reg_imm(tmpI, src2, mask); 8463 arShiftL_regL_regI(dst, src1, tmpI); 8464 %} 8465%} 8466 8467// Register Shift Right Immediate 8468instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8469 match(Set dst (RShiftL src1 src2)); 8470 8471 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %} 8472 size(4); 8473 ins_encode %{ 8474 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8475 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8476 %} 8477 ins_pipe(pipe_class_default); 8478%} 8479 8480// RShiftL + ConvL2I 8481instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ 8482 match(Set dst (ConvL2I (RShiftL src1 src2))); 8483 8484 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} 8485 size(4); 8486 ins_encode %{ 8487 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8488 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8489 %} 8490 ins_pipe(pipe_class_default); 8491%} 8492 8493instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8494 // no match-rule, false predicate 8495 effect(DEF dst, USE src1, USE src2); 8496 predicate(false); 8497 8498 format %{ "SRW $dst, $src1, $src2" %} 8499 size(4); 8500 ins_encode %{ 8501 // TODO: PPC port $archOpcode(ppc64Opcode_srw); 8502 __ srw($dst$$Register, $src1$$Register, $src2$$Register); 8503 %} 8504 ins_pipe(pipe_class_default); 8505%} 8506 8507// Register Shift Right 8508instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8509 match(Set dst (URShiftI src1 src2)); 8510 ins_cost(DEFAULT_COST*2); 8511 8512 expand %{ 8513 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8514 iRegIdst tmpI; 8515 maskI_reg_imm(tmpI, src2, mask); 8516 urShiftI_reg_reg(dst, src1, tmpI); 8517 %} 8518%} 8519 8520// Register Shift Right Immediate 8521instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8522 match(Set dst (URShiftI src1 src2)); 8523 8524 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %} 8525 size(4); 8526 ins_encode %{ 8527 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8528 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8529 %} 8530 ins_pipe(pipe_class_default); 8531%} 8532 8533instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8534 // no match-rule, false predicate 8535 effect(DEF dst, USE src1, USE src2); 8536 predicate(false); 8537 8538 format %{ "SRD $dst, $src1, $src2" %} 8539 size(4); 8540 ins_encode %{ 8541 // TODO: PPC port $archOpcode(ppc64Opcode_srd); 8542 __ srd($dst$$Register, $src1$$Register, $src2$$Register); 8543 %} 8544 ins_pipe(pipe_class_default); 8545%} 8546 8547// Register Shift Right 8548instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8549 match(Set dst (URShiftL src1 src2)); 8550 ins_cost(DEFAULT_COST*2); 8551 8552 expand %{ 8553 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8554 iRegIdst tmpI; 8555 maskI_reg_imm(tmpI, src2, mask); 8556 urShiftL_regL_regI(dst, src1, tmpI); 8557 %} 8558%} 8559 8560// Register Shift Right Immediate 8561instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8562 match(Set dst (URShiftL src1 src2)); 8563 8564 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %} 8565 size(4); 8566 ins_encode %{ 8567 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8568 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8569 %} 8570 ins_pipe(pipe_class_default); 8571%} 8572 8573// URShiftL + ConvL2I. 8574instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ 8575 match(Set dst (ConvL2I (URShiftL src1 src2))); 8576 8577 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} 8578 size(4); 8579 ins_encode %{ 8580 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8581 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8582 %} 8583 ins_pipe(pipe_class_default); 8584%} 8585 8586// Register Shift Right Immediate with a CastP2X 8587instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{ 8588 match(Set dst (URShiftL (CastP2X src1) src2)); 8589 8590 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %} 8591 size(4); 8592 ins_encode %{ 8593 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8594 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8595 %} 8596 ins_pipe(pipe_class_default); 8597%} 8598 8599instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{ 8600 match(Set dst (ConvL2I (ConvI2L src))); 8601 8602 format %{ "EXTSW $dst, $src \t// int->int" %} 8603 size(4); 8604 ins_encode %{ 8605 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 8606 __ extsw($dst$$Register, $src$$Register); 8607 %} 8608 ins_pipe(pipe_class_default); 8609%} 8610 8611//----------Rotate Instructions------------------------------------------------ 8612 8613// Rotate Left by 8-bit immediate 8614instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{ 8615 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); 8616 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8617 8618 format %{ "ROTLWI $dst, $src, $lshift" %} 8619 size(4); 8620 ins_encode %{ 8621 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8622 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant); 8623 %} 8624 ins_pipe(pipe_class_default); 8625%} 8626 8627// Rotate Right by 8-bit immediate 8628instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{ 8629 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); 8630 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8631 8632 format %{ "ROTRWI $dst, $rshift" %} 8633 size(4); 8634 ins_encode %{ 8635 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8636 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant); 8637 %} 8638 ins_pipe(pipe_class_default); 8639%} 8640 8641//----------Floating Point Arithmetic Instructions----------------------------- 8642 8643// Add float single precision 8644instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 8645 match(Set dst (AddF src1 src2)); 8646 8647 format %{ "FADDS $dst, $src1, $src2" %} 8648 size(4); 8649 ins_encode %{ 8650 // TODO: PPC port $archOpcode(ppc64Opcode_fadds); 8651 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8652 %} 8653 ins_pipe(pipe_class_default); 8654%} 8655 8656// Add float double precision 8657instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 8658 match(Set dst (AddD src1 src2)); 8659 8660 format %{ "FADD $dst, $src1, $src2" %} 8661 size(4); 8662 ins_encode %{ 8663 // TODO: PPC port $archOpcode(ppc64Opcode_fadd); 8664 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8665 %} 8666 ins_pipe(pipe_class_default); 8667%} 8668 8669// Sub float single precision 8670instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 8671 match(Set dst (SubF src1 src2)); 8672 8673 format %{ "FSUBS $dst, $src1, $src2" %} 8674 size(4); 8675 ins_encode %{ 8676 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs); 8677 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8678 %} 8679 ins_pipe(pipe_class_default); 8680%} 8681 8682// Sub float double precision 8683instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 8684 match(Set dst (SubD src1 src2)); 8685 format %{ "FSUB $dst, $src1, $src2" %} 8686 size(4); 8687 ins_encode %{ 8688 // TODO: PPC port $archOpcode(ppc64Opcode_fsub); 8689 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8690 %} 8691 ins_pipe(pipe_class_default); 8692%} 8693 8694// Mul float single precision 8695instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 8696 match(Set dst (MulF src1 src2)); 8697 format %{ "FMULS $dst, $src1, $src2" %} 8698 size(4); 8699 ins_encode %{ 8700 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls); 8701 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8702 %} 8703 ins_pipe(pipe_class_default); 8704%} 8705 8706// Mul float double precision 8707instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 8708 match(Set dst (MulD src1 src2)); 8709 format %{ "FMUL $dst, $src1, $src2" %} 8710 size(4); 8711 ins_encode %{ 8712 // TODO: PPC port $archOpcode(ppc64Opcode_fmul); 8713 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8714 %} 8715 ins_pipe(pipe_class_default); 8716%} 8717 8718// Div float single precision 8719instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 8720 match(Set dst (DivF src1 src2)); 8721 format %{ "FDIVS $dst, $src1, $src2" %} 8722 size(4); 8723 ins_encode %{ 8724 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs); 8725 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8726 %} 8727 ins_pipe(pipe_class_default); 8728%} 8729 8730// Div float double precision 8731instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 8732 match(Set dst (DivD src1 src2)); 8733 format %{ "FDIV $dst, $src1, $src2" %} 8734 size(4); 8735 ins_encode %{ 8736 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv); 8737 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8738 %} 8739 ins_pipe(pipe_class_default); 8740%} 8741 8742// Absolute float single precision 8743instruct absF_reg(regF dst, regF src) %{ 8744 match(Set dst (AbsF src)); 8745 format %{ "FABS $dst, $src \t// float" %} 8746 size(4); 8747 ins_encode %{ 8748 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); 8749 __ fabs($dst$$FloatRegister, $src$$FloatRegister); 8750 %} 8751 ins_pipe(pipe_class_default); 8752%} 8753 8754// Absolute float double precision 8755instruct absD_reg(regD dst, regD src) %{ 8756 match(Set dst (AbsD src)); 8757 format %{ "FABS $dst, $src \t// double" %} 8758 size(4); 8759 ins_encode %{ 8760 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); 8761 __ fabs($dst$$FloatRegister, $src$$FloatRegister); 8762 %} 8763 ins_pipe(pipe_class_default); 8764%} 8765 8766instruct negF_reg(regF dst, regF src) %{ 8767 match(Set dst (NegF src)); 8768 format %{ "FNEG $dst, $src \t// float" %} 8769 size(4); 8770 ins_encode %{ 8771 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); 8772 __ fneg($dst$$FloatRegister, $src$$FloatRegister); 8773 %} 8774 ins_pipe(pipe_class_default); 8775%} 8776 8777instruct negD_reg(regD dst, regD src) %{ 8778 match(Set dst (NegD src)); 8779 format %{ "FNEG $dst, $src \t// double" %} 8780 size(4); 8781 ins_encode %{ 8782 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); 8783 __ fneg($dst$$FloatRegister, $src$$FloatRegister); 8784 %} 8785 ins_pipe(pipe_class_default); 8786%} 8787 8788// AbsF + NegF. 8789instruct negF_absF_reg(regF dst, regF src) %{ 8790 match(Set dst (NegF (AbsF src))); 8791 format %{ "FNABS $dst, $src \t// float" %} 8792 size(4); 8793 ins_encode %{ 8794 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); 8795 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); 8796 %} 8797 ins_pipe(pipe_class_default); 8798%} 8799 8800// AbsD + NegD. 8801instruct negD_absD_reg(regD dst, regD src) %{ 8802 match(Set dst (NegD (AbsD src))); 8803 format %{ "FNABS $dst, $src \t// double" %} 8804 size(4); 8805 ins_encode %{ 8806 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); 8807 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); 8808 %} 8809 ins_pipe(pipe_class_default); 8810%} 8811 8812// VM_Version::has_fsqrt() decides if this node will be used. 8813// Sqrt float double precision 8814instruct sqrtD_reg(regD dst, regD src) %{ 8815 match(Set dst (SqrtD src)); 8816 format %{ "FSQRT $dst, $src" %} 8817 size(4); 8818 ins_encode %{ 8819 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt); 8820 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister); 8821 %} 8822 ins_pipe(pipe_class_default); 8823%} 8824 8825// Single-precision sqrt. 8826instruct sqrtF_reg(regF dst, regF src) %{ 8827 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 8828 predicate(VM_Version::has_fsqrts()); 8829 ins_cost(DEFAULT_COST); 8830 8831 format %{ "FSQRTS $dst, $src" %} 8832 size(4); 8833 ins_encode %{ 8834 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts); 8835 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister); 8836 %} 8837 ins_pipe(pipe_class_default); 8838%} 8839 8840instruct roundDouble_nop(regD dst) %{ 8841 match(Set dst (RoundDouble dst)); 8842 ins_cost(0); 8843 8844 format %{ " -- \t// RoundDouble not needed - empty" %} 8845 size(0); 8846 // PPC results are already "rounded" (i.e., normal-format IEEE). 8847 ins_encode( /*empty*/ ); 8848 ins_pipe(pipe_class_default); 8849%} 8850 8851instruct roundFloat_nop(regF dst) %{ 8852 match(Set dst (RoundFloat dst)); 8853 ins_cost(0); 8854 8855 format %{ " -- \t// RoundFloat not needed - empty" %} 8856 size(0); 8857 // PPC results are already "rounded" (i.e., normal-format IEEE). 8858 ins_encode( /*empty*/ ); 8859 ins_pipe(pipe_class_default); 8860%} 8861 8862//----------Logical Instructions----------------------------------------------- 8863 8864// And Instructions 8865 8866// Register And 8867instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8868 match(Set dst (AndI src1 src2)); 8869 format %{ "AND $dst, $src1, $src2" %} 8870 size(4); 8871 ins_encode %{ 8872 // TODO: PPC port $archOpcode(ppc64Opcode_and); 8873 __ andr($dst$$Register, $src1$$Register, $src2$$Register); 8874 %} 8875 ins_pipe(pipe_class_default); 8876%} 8877 8878// Immediate And 8879instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{ 8880 match(Set dst (AndI src1 src2)); 8881 effect(KILL cr0); 8882 8883 format %{ "ANDI $dst, $src1, $src2" %} 8884 size(4); 8885 ins_encode %{ 8886 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 8887 // FIXME: avoid andi_ ? 8888 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); 8889 %} 8890 ins_pipe(pipe_class_default); 8891%} 8892 8893// Immediate And where the immediate is a negative power of 2. 8894instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{ 8895 match(Set dst (AndI src1 src2)); 8896 format %{ "ANDWI $dst, $src1, $src2" %} 8897 size(4); 8898 ins_encode %{ 8899 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8900 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant))); 8901 %} 8902 ins_pipe(pipe_class_default); 8903%} 8904 8905instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{ 8906 match(Set dst (AndI src1 src2)); 8907 format %{ "ANDWI $dst, $src1, $src2" %} 8908 size(4); 8909 ins_encode %{ 8910 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8911 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8912 %} 8913 ins_pipe(pipe_class_default); 8914%} 8915 8916instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{ 8917 match(Set dst (AndI src1 src2)); 8918 predicate(UseRotateAndMaskInstructionsPPC64); 8919 format %{ "ANDWI $dst, $src1, $src2" %} 8920 size(4); 8921 ins_encode %{ 8922 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8923 __ rlwinm($dst$$Register, $src1$$Register, 0, 8924 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f); 8925 %} 8926 ins_pipe(pipe_class_default); 8927%} 8928 8929// Register And Long 8930instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8931 match(Set dst (AndL src1 src2)); 8932 ins_cost(DEFAULT_COST); 8933 8934 format %{ "AND $dst, $src1, $src2 \t// long" %} 8935 size(4); 8936 ins_encode %{ 8937 // TODO: PPC port $archOpcode(ppc64Opcode_and); 8938 __ andr($dst$$Register, $src1$$Register, $src2$$Register); 8939 %} 8940 ins_pipe(pipe_class_default); 8941%} 8942 8943// Immediate And long 8944instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{ 8945 match(Set dst (AndL src1 src2)); 8946 effect(KILL cr0); 8947 8948 format %{ "ANDI $dst, $src1, $src2 \t// long" %} 8949 size(4); 8950 ins_encode %{ 8951 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 8952 // FIXME: avoid andi_ ? 8953 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); 8954 %} 8955 ins_pipe(pipe_class_default); 8956%} 8957 8958// Immediate And Long where the immediate is a negative power of 2. 8959instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{ 8960 match(Set dst (AndL src1 src2)); 8961 format %{ "ANDDI $dst, $src1, $src2" %} 8962 size(4); 8963 ins_encode %{ 8964 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8965 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant)); 8966 %} 8967 ins_pipe(pipe_class_default); 8968%} 8969 8970instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ 8971 match(Set dst (AndL src1 src2)); 8972 format %{ "ANDDI $dst, $src1, $src2" %} 8973 size(4); 8974 ins_encode %{ 8975 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8976 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8977 %} 8978 ins_pipe(pipe_class_default); 8979%} 8980 8981// AndL + ConvL2I. 8982instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ 8983 match(Set dst (ConvL2I (AndL src1 src2))); 8984 ins_cost(DEFAULT_COST); 8985 8986 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %} 8987 size(4); 8988 ins_encode %{ 8989 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8990 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8991 %} 8992 ins_pipe(pipe_class_default); 8993%} 8994 8995// Or Instructions 8996 8997// Register Or 8998instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8999 match(Set dst (OrI src1 src2)); 9000 format %{ "OR $dst, $src1, $src2" %} 9001 size(4); 9002 ins_encode %{ 9003 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9004 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9005 %} 9006 ins_pipe(pipe_class_default); 9007%} 9008 9009// Expand does not work with above instruct. (??) 9010instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9011 // no match-rule 9012 effect(DEF dst, USE src1, USE src2); 9013 format %{ "OR $dst, $src1, $src2" %} 9014 size(4); 9015 ins_encode %{ 9016 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9017 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9018 %} 9019 ins_pipe(pipe_class_default); 9020%} 9021 9022instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 9023 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4)); 9024 ins_cost(DEFAULT_COST*3); 9025 9026 expand %{ 9027 // FIXME: we should do this in the ideal world. 9028 iRegIdst tmp1; 9029 iRegIdst tmp2; 9030 orI_reg_reg(tmp1, src1, src2); 9031 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. 9032 orI_reg_reg(dst, tmp1, tmp2); 9033 %} 9034%} 9035 9036// Immediate Or 9037instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ 9038 match(Set dst (OrI src1 src2)); 9039 format %{ "ORI $dst, $src1, $src2" %} 9040 size(4); 9041 ins_encode %{ 9042 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 9043 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 9044 %} 9045 ins_pipe(pipe_class_default); 9046%} 9047 9048// Register Or Long 9049instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9050 match(Set dst (OrL src1 src2)); 9051 ins_cost(DEFAULT_COST); 9052 9053 size(4); 9054 format %{ "OR $dst, $src1, $src2 \t// long" %} 9055 ins_encode %{ 9056 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9057 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9058 %} 9059 ins_pipe(pipe_class_default); 9060%} 9061 9062// OrL + ConvL2I. 9063instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9064 match(Set dst (ConvL2I (OrL src1 src2))); 9065 ins_cost(DEFAULT_COST); 9066 9067 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %} 9068 size(4); 9069 ins_encode %{ 9070 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9071 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9072 %} 9073 ins_pipe(pipe_class_default); 9074%} 9075 9076// Immediate Or long 9077instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{ 9078 match(Set dst (OrL src1 con)); 9079 ins_cost(DEFAULT_COST); 9080 9081 format %{ "ORI $dst, $src1, $con \t// long" %} 9082 size(4); 9083 ins_encode %{ 9084 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 9085 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF); 9086 %} 9087 ins_pipe(pipe_class_default); 9088%} 9089 9090// Xor Instructions 9091 9092// Register Xor 9093instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9094 match(Set dst (XorI src1 src2)); 9095 format %{ "XOR $dst, $src1, $src2" %} 9096 size(4); 9097 ins_encode %{ 9098 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9099 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9100 %} 9101 ins_pipe(pipe_class_default); 9102%} 9103 9104// Expand does not work with above instruct. (??) 9105instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9106 // no match-rule 9107 effect(DEF dst, USE src1, USE src2); 9108 format %{ "XOR $dst, $src1, $src2" %} 9109 size(4); 9110 ins_encode %{ 9111 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9112 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9113 %} 9114 ins_pipe(pipe_class_default); 9115%} 9116 9117instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 9118 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4)); 9119 ins_cost(DEFAULT_COST*3); 9120 9121 expand %{ 9122 // FIXME: we should do this in the ideal world. 9123 iRegIdst tmp1; 9124 iRegIdst tmp2; 9125 xorI_reg_reg(tmp1, src1, src2); 9126 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg. 9127 xorI_reg_reg(dst, tmp1, tmp2); 9128 %} 9129%} 9130 9131// Immediate Xor 9132instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ 9133 match(Set dst (XorI src1 src2)); 9134 format %{ "XORI $dst, $src1, $src2" %} 9135 size(4); 9136 ins_encode %{ 9137 // TODO: PPC port $archOpcode(ppc64Opcode_xori); 9138 __ xori($dst$$Register, $src1$$Register, $src2$$constant); 9139 %} 9140 ins_pipe(pipe_class_default); 9141%} 9142 9143// Register Xor Long 9144instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9145 match(Set dst (XorL src1 src2)); 9146 ins_cost(DEFAULT_COST); 9147 9148 format %{ "XOR $dst, $src1, $src2 \t// long" %} 9149 size(4); 9150 ins_encode %{ 9151 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9152 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9153 %} 9154 ins_pipe(pipe_class_default); 9155%} 9156 9157// XorL + ConvL2I. 9158instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9159 match(Set dst (ConvL2I (XorL src1 src2))); 9160 ins_cost(DEFAULT_COST); 9161 9162 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %} 9163 size(4); 9164 ins_encode %{ 9165 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9166 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9167 %} 9168 ins_pipe(pipe_class_default); 9169%} 9170 9171// Immediate Xor Long 9172instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{ 9173 match(Set dst (XorL src1 src2)); 9174 ins_cost(DEFAULT_COST); 9175 9176 format %{ "XORI $dst, $src1, $src2 \t// long" %} 9177 size(4); 9178 ins_encode %{ 9179 // TODO: PPC port $archOpcode(ppc64Opcode_xori); 9180 __ xori($dst$$Register, $src1$$Register, $src2$$constant); 9181 %} 9182 ins_pipe(pipe_class_default); 9183%} 9184 9185instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ 9186 match(Set dst (XorI src1 src2)); 9187 ins_cost(DEFAULT_COST); 9188 9189 format %{ "NOT $dst, $src1 ($src2)" %} 9190 size(4); 9191 ins_encode %{ 9192 // TODO: PPC port $archOpcode(ppc64Opcode_nor); 9193 __ nor($dst$$Register, $src1$$Register, $src1$$Register); 9194 %} 9195 ins_pipe(pipe_class_default); 9196%} 9197 9198instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ 9199 match(Set dst (XorL src1 src2)); 9200 ins_cost(DEFAULT_COST); 9201 9202 format %{ "NOT $dst, $src1 ($src2) \t// long" %} 9203 size(4); 9204 ins_encode %{ 9205 // TODO: PPC port $archOpcode(ppc64Opcode_nor); 9206 __ nor($dst$$Register, $src1$$Register, $src1$$Register); 9207 %} 9208 ins_pipe(pipe_class_default); 9209%} 9210 9211// And-complement 9212instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{ 9213 match(Set dst (AndI (XorI src1 src2) src3)); 9214 ins_cost(DEFAULT_COST); 9215 9216 format %{ "ANDW $dst, xori($src1, $src2), $src3" %} 9217 size(4); 9218 ins_encode( enc_andc(dst, src3, src1) ); 9219 ins_pipe(pipe_class_default); 9220%} 9221 9222// And-complement 9223instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9224 // no match-rule, false predicate 9225 effect(DEF dst, USE src1, USE src2); 9226 predicate(false); 9227 9228 format %{ "ANDC $dst, $src1, $src2" %} 9229 size(4); 9230 ins_encode %{ 9231 // TODO: PPC port $archOpcode(ppc64Opcode_andc); 9232 __ andc($dst$$Register, $src1$$Register, $src2$$Register); 9233 %} 9234 ins_pipe(pipe_class_default); 9235%} 9236 9237//----------Moves between int/long and float/double---------------------------- 9238// 9239// The following rules move values from int/long registers/stack-locations 9240// to float/double registers/stack-locations and vice versa, without doing any 9241// conversions. These rules are used to implement the bit-conversion methods 9242// of java.lang.Float etc., e.g. 9243// int floatToIntBits(float value) 9244// float intBitsToFloat(int bits) 9245// 9246// Notes on the implementation on ppc64: 9247// We only provide rules which move between a register and a stack-location, 9248// because we always have to go through memory when moving between a float 9249// register and an integer register. 9250 9251//---------- Chain stack slots between similar types -------- 9252 9253// These are needed so that the rules below can match. 9254 9255// Load integer from stack slot 9256instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{ 9257 match(Set dst src); 9258 ins_cost(MEMORY_REF_COST); 9259 9260 format %{ "LWZ $dst, $src" %} 9261 size(4); 9262 ins_encode( enc_lwz(dst, src) ); 9263 ins_pipe(pipe_class_memory); 9264%} 9265 9266// Store integer to stack slot 9267instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{ 9268 match(Set dst src); 9269 ins_cost(MEMORY_REF_COST); 9270 9271 format %{ "STW $src, $dst \t// stk" %} 9272 size(4); 9273 ins_encode( enc_stw(src, dst) ); // rs=rt 9274 ins_pipe(pipe_class_memory); 9275%} 9276 9277// Load long from stack slot 9278instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{ 9279 match(Set dst src); 9280 ins_cost(MEMORY_REF_COST); 9281 9282 format %{ "LD $dst, $src \t// long" %} 9283 size(4); 9284 ins_encode( enc_ld(dst, src) ); 9285 ins_pipe(pipe_class_memory); 9286%} 9287 9288// Store long to stack slot 9289instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{ 9290 match(Set dst src); 9291 ins_cost(MEMORY_REF_COST); 9292 9293 format %{ "STD $src, $dst \t// long" %} 9294 size(4); 9295 ins_encode( enc_std(src, dst) ); // rs=rt 9296 ins_pipe(pipe_class_memory); 9297%} 9298 9299//----------Moves between int and float 9300 9301// Move float value from float stack-location to integer register. 9302instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{ 9303 match(Set dst (MoveF2I src)); 9304 ins_cost(MEMORY_REF_COST); 9305 9306 format %{ "LWZ $dst, $src \t// MoveF2I" %} 9307 size(4); 9308 ins_encode( enc_lwz(dst, src) ); 9309 ins_pipe(pipe_class_memory); 9310%} 9311 9312// Move float value from float register to integer stack-location. 9313instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{ 9314 match(Set dst (MoveF2I src)); 9315 ins_cost(MEMORY_REF_COST); 9316 9317 format %{ "STFS $src, $dst \t// MoveF2I" %} 9318 size(4); 9319 ins_encode( enc_stfs(src, dst) ); 9320 ins_pipe(pipe_class_memory); 9321%} 9322 9323// Move integer value from integer stack-location to float register. 9324instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{ 9325 match(Set dst (MoveI2F src)); 9326 ins_cost(MEMORY_REF_COST); 9327 9328 format %{ "LFS $dst, $src \t// MoveI2F" %} 9329 size(4); 9330 ins_encode %{ 9331 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 9332 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_); 9333 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register); 9334 %} 9335 ins_pipe(pipe_class_memory); 9336%} 9337 9338// Move integer value from integer register to float stack-location. 9339instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{ 9340 match(Set dst (MoveI2F src)); 9341 ins_cost(MEMORY_REF_COST); 9342 9343 format %{ "STW $src, $dst \t// MoveI2F" %} 9344 size(4); 9345 ins_encode( enc_stw(src, dst) ); 9346 ins_pipe(pipe_class_memory); 9347%} 9348 9349//----------Moves between long and float 9350 9351instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{ 9352 // no match-rule, false predicate 9353 effect(DEF dst, USE src); 9354 predicate(false); 9355 9356 format %{ "storeD $src, $dst \t// STACK" %} 9357 size(4); 9358 ins_encode( enc_stfd(src, dst) ); 9359 ins_pipe(pipe_class_default); 9360%} 9361 9362//----------Moves between long and double 9363 9364// Move double value from double stack-location to long register. 9365instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{ 9366 match(Set dst (MoveD2L src)); 9367 ins_cost(MEMORY_REF_COST); 9368 size(4); 9369 format %{ "LD $dst, $src \t// MoveD2L" %} 9370 ins_encode( enc_ld(dst, src) ); 9371 ins_pipe(pipe_class_memory); 9372%} 9373 9374// Move double value from double register to long stack-location. 9375instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{ 9376 match(Set dst (MoveD2L src)); 9377 effect(DEF dst, USE src); 9378 ins_cost(MEMORY_REF_COST); 9379 9380 format %{ "STFD $src, $dst \t// MoveD2L" %} 9381 size(4); 9382 ins_encode( enc_stfd(src, dst) ); 9383 ins_pipe(pipe_class_memory); 9384%} 9385 9386// Move long value from long stack-location to double register. 9387instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{ 9388 match(Set dst (MoveL2D src)); 9389 ins_cost(MEMORY_REF_COST); 9390 9391 format %{ "LFD $dst, $src \t// MoveL2D" %} 9392 size(4); 9393 ins_encode( enc_lfd(dst, src) ); 9394 ins_pipe(pipe_class_memory); 9395%} 9396 9397// Move long value from long register to double stack-location. 9398instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{ 9399 match(Set dst (MoveL2D src)); 9400 ins_cost(MEMORY_REF_COST); 9401 9402 format %{ "STD $src, $dst \t// MoveL2D" %} 9403 size(4); 9404 ins_encode( enc_std(src, dst) ); 9405 ins_pipe(pipe_class_memory); 9406%} 9407 9408//----------Register Move Instructions----------------------------------------- 9409 9410// Replicate for Superword 9411 9412instruct moveReg(iRegLdst dst, iRegIsrc src) %{ 9413 predicate(false); 9414 effect(DEF dst, USE src); 9415 9416 format %{ "MR $dst, $src \t// replicate " %} 9417 // variable size, 0 or 4. 9418 ins_encode %{ 9419 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9420 __ mr_if_needed($dst$$Register, $src$$Register); 9421 %} 9422 ins_pipe(pipe_class_default); 9423%} 9424 9425//----------Cast instructions (Java-level type cast)--------------------------- 9426 9427// Cast Long to Pointer for unsafe natives. 9428instruct castX2P(iRegPdst dst, iRegLsrc src) %{ 9429 match(Set dst (CastX2P src)); 9430 9431 format %{ "MR $dst, $src \t// Long->Ptr" %} 9432 // variable size, 0 or 4. 9433 ins_encode %{ 9434 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9435 __ mr_if_needed($dst$$Register, $src$$Register); 9436 %} 9437 ins_pipe(pipe_class_default); 9438%} 9439 9440// Cast Pointer to Long for unsafe natives. 9441instruct castP2X(iRegLdst dst, iRegP_N2P src) %{ 9442 match(Set dst (CastP2X src)); 9443 9444 format %{ "MR $dst, $src \t// Ptr->Long" %} 9445 // variable size, 0 or 4. 9446 ins_encode %{ 9447 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9448 __ mr_if_needed($dst$$Register, $src$$Register); 9449 %} 9450 ins_pipe(pipe_class_default); 9451%} 9452 9453instruct castPP(iRegPdst dst) %{ 9454 match(Set dst (CastPP dst)); 9455 format %{ " -- \t// castPP of $dst" %} 9456 size(0); 9457 ins_encode( /*empty*/ ); 9458 ins_pipe(pipe_class_default); 9459%} 9460 9461instruct castII(iRegIdst dst) %{ 9462 match(Set dst (CastII dst)); 9463 format %{ " -- \t// castII of $dst" %} 9464 size(0); 9465 ins_encode( /*empty*/ ); 9466 ins_pipe(pipe_class_default); 9467%} 9468 9469instruct checkCastPP(iRegPdst dst) %{ 9470 match(Set dst (CheckCastPP dst)); 9471 format %{ " -- \t// checkcastPP of $dst" %} 9472 size(0); 9473 ins_encode( /*empty*/ ); 9474 ins_pipe(pipe_class_default); 9475%} 9476 9477//----------Convert instructions----------------------------------------------- 9478 9479// Convert to boolean. 9480 9481// int_to_bool(src) : { 1 if src != 0 9482// { 0 else 9483// 9484// strategy: 9485// 1) Count leading zeros of 32 bit-value src, 9486// this returns 32 (0b10.0000) iff src == 0 and <32 otherwise. 9487// 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. 9488// 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. 9489 9490// convI2Bool 9491instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{ 9492 match(Set dst (Conv2B src)); 9493 predicate(UseCountLeadingZerosInstructionsPPC64); 9494 ins_cost(DEFAULT_COST); 9495 9496 expand %{ 9497 immI shiftAmount %{ 0x5 %} 9498 uimmI16 mask %{ 0x1 %} 9499 iRegIdst tmp1; 9500 iRegIdst tmp2; 9501 countLeadingZerosI(tmp1, src); 9502 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); 9503 xorI_reg_uimm16(dst, tmp2, mask); 9504 %} 9505%} 9506 9507instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{ 9508 match(Set dst (Conv2B src)); 9509 effect(TEMP crx); 9510 predicate(!UseCountLeadingZerosInstructionsPPC64); 9511 ins_cost(DEFAULT_COST); 9512 9513 format %{ "CMPWI $crx, $src, #0 \t// convI2B" 9514 "LI $dst, #0\n\t" 9515 "BEQ $crx, done\n\t" 9516 "LI $dst, #1\n" 9517 "done:" %} 9518 size(16); 9519 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) ); 9520 ins_pipe(pipe_class_compare); 9521%} 9522 9523// ConvI2B + XorI 9524instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{ 9525 match(Set dst (XorI (Conv2B src) mask)); 9526 predicate(UseCountLeadingZerosInstructionsPPC64); 9527 ins_cost(DEFAULT_COST); 9528 9529 expand %{ 9530 immI shiftAmount %{ 0x5 %} 9531 iRegIdst tmp1; 9532 countLeadingZerosI(tmp1, src); 9533 urShiftI_reg_imm(dst, tmp1, shiftAmount); 9534 %} 9535%} 9536 9537instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{ 9538 match(Set dst (XorI (Conv2B src) mask)); 9539 effect(TEMP crx); 9540 predicate(!UseCountLeadingZerosInstructionsPPC64); 9541 ins_cost(DEFAULT_COST); 9542 9543 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)" 9544 "LI $dst, #1\n\t" 9545 "BEQ $crx, done\n\t" 9546 "LI $dst, #0\n" 9547 "done:" %} 9548 size(16); 9549 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) ); 9550 ins_pipe(pipe_class_compare); 9551%} 9552 9553// AndI 0b0..010..0 + ConvI2B 9554instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{ 9555 match(Set dst (Conv2B (AndI src mask))); 9556 predicate(UseRotateAndMaskInstructionsPPC64); 9557 ins_cost(DEFAULT_COST); 9558 9559 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %} 9560 size(4); 9561 ins_encode %{ 9562 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 9563 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31); 9564 %} 9565 ins_pipe(pipe_class_default); 9566%} 9567 9568// Convert pointer to boolean. 9569// 9570// ptr_to_bool(src) : { 1 if src != 0 9571// { 0 else 9572// 9573// strategy: 9574// 1) Count leading zeros of 64 bit-value src, 9575// this returns 64 (0b100.0000) iff src == 0 and <64 otherwise. 9576// 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. 9577// 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. 9578 9579// ConvP2B 9580instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{ 9581 match(Set dst (Conv2B src)); 9582 predicate(UseCountLeadingZerosInstructionsPPC64); 9583 ins_cost(DEFAULT_COST); 9584 9585 expand %{ 9586 immI shiftAmount %{ 0x6 %} 9587 uimmI16 mask %{ 0x1 %} 9588 iRegIdst tmp1; 9589 iRegIdst tmp2; 9590 countLeadingZerosP(tmp1, src); 9591 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); 9592 xorI_reg_uimm16(dst, tmp2, mask); 9593 %} 9594%} 9595 9596instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{ 9597 match(Set dst (Conv2B src)); 9598 effect(TEMP crx); 9599 predicate(!UseCountLeadingZerosInstructionsPPC64); 9600 ins_cost(DEFAULT_COST); 9601 9602 format %{ "CMPDI $crx, $src, #0 \t// convP2B" 9603 "LI $dst, #0\n\t" 9604 "BEQ $crx, done\n\t" 9605 "LI $dst, #1\n" 9606 "done:" %} 9607 size(16); 9608 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) ); 9609 ins_pipe(pipe_class_compare); 9610%} 9611 9612// ConvP2B + XorI 9613instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{ 9614 match(Set dst (XorI (Conv2B src) mask)); 9615 predicate(UseCountLeadingZerosInstructionsPPC64); 9616 ins_cost(DEFAULT_COST); 9617 9618 expand %{ 9619 immI shiftAmount %{ 0x6 %} 9620 iRegIdst tmp1; 9621 countLeadingZerosP(tmp1, src); 9622 urShiftI_reg_imm(dst, tmp1, shiftAmount); 9623 %} 9624%} 9625 9626instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{ 9627 match(Set dst (XorI (Conv2B src) mask)); 9628 effect(TEMP crx); 9629 predicate(!UseCountLeadingZerosInstructionsPPC64); 9630 ins_cost(DEFAULT_COST); 9631 9632 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)" 9633 "LI $dst, #1\n\t" 9634 "BEQ $crx, done\n\t" 9635 "LI $dst, #0\n" 9636 "done:" %} 9637 size(16); 9638 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) ); 9639 ins_pipe(pipe_class_compare); 9640%} 9641 9642// if src1 < src2, return -1 else return 0 9643instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9644 match(Set dst (CmpLTMask src1 src2)); 9645 ins_cost(DEFAULT_COST*4); 9646 9647 expand %{ 9648 iRegLdst src1s; 9649 iRegLdst src2s; 9650 iRegLdst diff; 9651 convI2L_reg(src1s, src1); // Ensure proper sign extension. 9652 convI2L_reg(src2s, src2); // Ensure proper sign extension. 9653 subL_reg_reg(diff, src1s, src2s); 9654 // Need to consider >=33 bit result, therefore we need signmaskL. 9655 signmask64I_regL(dst, diff); 9656 %} 9657%} 9658 9659instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{ 9660 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0 9661 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %} 9662 size(4); 9663 ins_encode %{ 9664 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 9665 __ srawi($dst$$Register, $src1$$Register, 0x1f); 9666 %} 9667 ins_pipe(pipe_class_default); 9668%} 9669 9670//----------Arithmetic Conversion Instructions--------------------------------- 9671 9672// Convert to Byte -- nop 9673// Convert to Short -- nop 9674 9675// Convert to Int 9676 9677instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{ 9678 match(Set dst (RShiftI (LShiftI src amount) amount)); 9679 format %{ "EXTSB $dst, $src \t// byte->int" %} 9680 size(4); 9681 ins_encode %{ 9682 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); 9683 __ extsb($dst$$Register, $src$$Register); 9684 %} 9685 ins_pipe(pipe_class_default); 9686%} 9687 9688// LShiftI 16 + RShiftI 16 converts short to int. 9689instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{ 9690 match(Set dst (RShiftI (LShiftI src amount) amount)); 9691 format %{ "EXTSH $dst, $src \t// short->int" %} 9692 size(4); 9693 ins_encode %{ 9694 // TODO: PPC port $archOpcode(ppc64Opcode_extsh); 9695 __ extsh($dst$$Register, $src$$Register); 9696 %} 9697 ins_pipe(pipe_class_default); 9698%} 9699 9700// ConvL2I + ConvI2L: Sign extend int in long register. 9701instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{ 9702 match(Set dst (ConvI2L (ConvL2I src))); 9703 9704 format %{ "EXTSW $dst, $src \t// long->long" %} 9705 size(4); 9706 ins_encode %{ 9707 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 9708 __ extsw($dst$$Register, $src$$Register); 9709 %} 9710 ins_pipe(pipe_class_default); 9711%} 9712 9713instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{ 9714 match(Set dst (ConvL2I src)); 9715 format %{ "MR $dst, $src \t// long->int" %} 9716 // variable size, 0 or 4 9717 ins_encode %{ 9718 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9719 __ mr_if_needed($dst$$Register, $src$$Register); 9720 %} 9721 ins_pipe(pipe_class_default); 9722%} 9723 9724instruct convD2IRaw_regD(regD dst, regD src) %{ 9725 // no match-rule, false predicate 9726 effect(DEF dst, USE src); 9727 predicate(false); 9728 9729 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %} 9730 size(4); 9731 ins_encode %{ 9732 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);; 9733 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); 9734 %} 9735 ins_pipe(pipe_class_default); 9736%} 9737 9738instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{ 9739 // no match-rule, false predicate 9740 effect(DEF dst, USE crx, USE src); 9741 predicate(false); 9742 9743 ins_variable_size_depending_on_alignment(true); 9744 9745 format %{ "cmovI $crx, $dst, $src" %} 9746 // Worst case is branch + move + stop, no stop without scheduler. 9747 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 9748 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); 9749 ins_pipe(pipe_class_default); 9750%} 9751 9752instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{ 9753 // no match-rule, false predicate 9754 effect(DEF dst, USE crx, USE mem); 9755 predicate(false); 9756 9757 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %} 9758 postalloc_expand %{ 9759 // 9760 // replaces 9761 // 9762 // region dst crx mem 9763 // \ | | / 9764 // dst=cmovI_bso_stackSlotL_conLvalue0 9765 // 9766 // with 9767 // 9768 // region dst 9769 // \ / 9770 // dst=loadConI16(0) 9771 // | 9772 // ^ region dst crx mem 9773 // | \ | | / 9774 // dst=cmovI_bso_stackSlotL 9775 // 9776 9777 // Create new nodes. 9778 MachNode *m1 = new loadConI16Node(); 9779 MachNode *m2 = new cmovI_bso_stackSlotLNode(); 9780 9781 // inputs for new nodes 9782 m1->add_req(n_region); 9783 m2->add_req(n_region, n_crx, n_mem); 9784 9785 // precedences for new nodes 9786 m2->add_prec(m1); 9787 9788 // operands for new nodes 9789 m1->_opnds[0] = op_dst; 9790 m1->_opnds[1] = new immI16Oper(0); 9791 9792 m2->_opnds[0] = op_dst; 9793 m2->_opnds[1] = op_crx; 9794 m2->_opnds[2] = op_mem; 9795 9796 // registers for new nodes 9797 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9798 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9799 9800 // Insert new nodes. 9801 nodes->push(m1); 9802 nodes->push(m2); 9803 %} 9804%} 9805 9806// Double to Int conversion, NaN is mapped to 0. 9807instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{ 9808 match(Set dst (ConvD2I src)); 9809 ins_cost(DEFAULT_COST); 9810 9811 expand %{ 9812 regD tmpD; 9813 stackSlotL tmpS; 9814 flagsReg crx; 9815 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9816 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated). 9817 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). 9818 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9819 %} 9820%} 9821 9822instruct convF2IRaw_regF(regF dst, regF src) %{ 9823 // no match-rule, false predicate 9824 effect(DEF dst, USE src); 9825 predicate(false); 9826 9827 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %} 9828 size(4); 9829 ins_encode %{ 9830 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9831 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); 9832 %} 9833 ins_pipe(pipe_class_default); 9834%} 9835 9836// Float to Int conversion, NaN is mapped to 0. 9837instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{ 9838 match(Set dst (ConvF2I src)); 9839 ins_cost(DEFAULT_COST); 9840 9841 expand %{ 9842 regF tmpF; 9843 stackSlotL tmpS; 9844 flagsReg crx; 9845 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9846 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated). 9847 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). 9848 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9849 %} 9850%} 9851 9852// Convert to Long 9853 9854instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{ 9855 match(Set dst (ConvI2L src)); 9856 format %{ "EXTSW $dst, $src \t// int->long" %} 9857 size(4); 9858 ins_encode %{ 9859 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 9860 __ extsw($dst$$Register, $src$$Register); 9861 %} 9862 ins_pipe(pipe_class_default); 9863%} 9864 9865// Zero-extend: convert unsigned int to long (convUI2L). 9866instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{ 9867 match(Set dst (AndL (ConvI2L src) mask)); 9868 ins_cost(DEFAULT_COST); 9869 9870 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} 9871 size(4); 9872 ins_encode %{ 9873 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9874 __ clrldi($dst$$Register, $src$$Register, 32); 9875 %} 9876 ins_pipe(pipe_class_default); 9877%} 9878 9879// Zero-extend: convert unsigned int to long in long register. 9880instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{ 9881 match(Set dst (AndL src mask)); 9882 ins_cost(DEFAULT_COST); 9883 9884 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} 9885 size(4); 9886 ins_encode %{ 9887 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9888 __ clrldi($dst$$Register, $src$$Register, 32); 9889 %} 9890 ins_pipe(pipe_class_default); 9891%} 9892 9893instruct convF2LRaw_regF(regF dst, regF src) %{ 9894 // no match-rule, false predicate 9895 effect(DEF dst, USE src); 9896 predicate(false); 9897 9898 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %} 9899 size(4); 9900 ins_encode %{ 9901 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9902 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); 9903 %} 9904 ins_pipe(pipe_class_default); 9905%} 9906 9907instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{ 9908 // no match-rule, false predicate 9909 effect(DEF dst, USE crx, USE src); 9910 predicate(false); 9911 9912 ins_variable_size_depending_on_alignment(true); 9913 9914 format %{ "cmovL $crx, $dst, $src" %} 9915 // Worst case is branch + move + stop, no stop without scheduler. 9916 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 9917 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); 9918 ins_pipe(pipe_class_default); 9919%} 9920 9921instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{ 9922 // no match-rule, false predicate 9923 effect(DEF dst, USE crx, USE mem); 9924 predicate(false); 9925 9926 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %} 9927 postalloc_expand %{ 9928 // 9929 // replaces 9930 // 9931 // region dst crx mem 9932 // \ | | / 9933 // dst=cmovL_bso_stackSlotL_conLvalue0 9934 // 9935 // with 9936 // 9937 // region dst 9938 // \ / 9939 // dst=loadConL16(0) 9940 // | 9941 // ^ region dst crx mem 9942 // | \ | | / 9943 // dst=cmovL_bso_stackSlotL 9944 // 9945 9946 // Create new nodes. 9947 MachNode *m1 = new loadConL16Node(); 9948 MachNode *m2 = new cmovL_bso_stackSlotLNode(); 9949 9950 // inputs for new nodes 9951 m1->add_req(n_region); 9952 m2->add_req(n_region, n_crx, n_mem); 9953 m2->add_prec(m1); 9954 9955 // operands for new nodes 9956 m1->_opnds[0] = op_dst; 9957 m1->_opnds[1] = new immL16Oper(0); 9958 m2->_opnds[0] = op_dst; 9959 m2->_opnds[1] = op_crx; 9960 m2->_opnds[2] = op_mem; 9961 9962 // registers for new nodes 9963 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9964 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9965 9966 // Insert new nodes. 9967 nodes->push(m1); 9968 nodes->push(m2); 9969 %} 9970%} 9971 9972// Float to Long conversion, NaN is mapped to 0. 9973instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{ 9974 match(Set dst (ConvF2L src)); 9975 ins_cost(DEFAULT_COST); 9976 9977 expand %{ 9978 regF tmpF; 9979 stackSlotL tmpS; 9980 flagsReg crx; 9981 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9982 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated). 9983 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). 9984 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9985 %} 9986%} 9987 9988instruct convD2LRaw_regD(regD dst, regD src) %{ 9989 // no match-rule, false predicate 9990 effect(DEF dst, USE src); 9991 predicate(false); 9992 9993 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %} 9994 size(4); 9995 ins_encode %{ 9996 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9997 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); 9998 %} 9999 ins_pipe(pipe_class_default); 10000%} 10001 10002// Double to Long conversion, NaN is mapped to 0. 10003instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{ 10004 match(Set dst (ConvD2L src)); 10005 ins_cost(DEFAULT_COST); 10006 10007 expand %{ 10008 regD tmpD; 10009 stackSlotL tmpS; 10010 flagsReg crx; 10011 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 10012 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated). 10013 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). 10014 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 10015 %} 10016%} 10017 10018// Convert to Float 10019 10020// Placed here as needed in expand. 10021instruct convL2DRaw_regD(regD dst, regD src) %{ 10022 // no match-rule, false predicate 10023 effect(DEF dst, USE src); 10024 predicate(false); 10025 10026 format %{ "FCFID $dst, $src \t// convL2D" %} 10027 size(4); 10028 ins_encode %{ 10029 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); 10030 __ fcfid($dst$$FloatRegister, $src$$FloatRegister); 10031 %} 10032 ins_pipe(pipe_class_default); 10033%} 10034 10035// Placed here as needed in expand. 10036instruct convD2F_reg(regF dst, regD src) %{ 10037 match(Set dst (ConvD2F src)); 10038 format %{ "FRSP $dst, $src \t// convD2F" %} 10039 size(4); 10040 ins_encode %{ 10041 // TODO: PPC port $archOpcode(ppc64Opcode_frsp); 10042 __ frsp($dst$$FloatRegister, $src$$FloatRegister); 10043 %} 10044 ins_pipe(pipe_class_default); 10045%} 10046 10047// Integer to Float conversion. 10048instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{ 10049 match(Set dst (ConvI2F src)); 10050 predicate(!VM_Version::has_fcfids()); 10051 ins_cost(DEFAULT_COST); 10052 10053 expand %{ 10054 iRegLdst tmpL; 10055 stackSlotL tmpS; 10056 regD tmpD; 10057 regD tmpD2; 10058 convI2L_reg(tmpL, src); // Sign-extension int to long. 10059 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10060 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10061 convL2DRaw_regD(tmpD2, tmpD); // Convert to double. 10062 convD2F_reg(dst, tmpD2); // Convert double to float. 10063 %} 10064%} 10065 10066instruct convL2FRaw_regF(regF dst, regD src) %{ 10067 // no match-rule, false predicate 10068 effect(DEF dst, USE src); 10069 predicate(false); 10070 10071 format %{ "FCFIDS $dst, $src \t// convL2F" %} 10072 size(4); 10073 ins_encode %{ 10074 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); 10075 __ fcfids($dst$$FloatRegister, $src$$FloatRegister); 10076 %} 10077 ins_pipe(pipe_class_default); 10078%} 10079 10080// Integer to Float conversion. Special version for Power7. 10081instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{ 10082 match(Set dst (ConvI2F src)); 10083 predicate(VM_Version::has_fcfids()); 10084 ins_cost(DEFAULT_COST); 10085 10086 expand %{ 10087 iRegLdst tmpL; 10088 stackSlotL tmpS; 10089 regD tmpD; 10090 convI2L_reg(tmpL, src); // Sign-extension int to long. 10091 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10092 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10093 convL2FRaw_regF(dst, tmpD); // Convert to float. 10094 %} 10095%} 10096 10097// L2F to avoid runtime call. 10098instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{ 10099 match(Set dst (ConvL2F src)); 10100 predicate(VM_Version::has_fcfids()); 10101 ins_cost(DEFAULT_COST); 10102 10103 expand %{ 10104 stackSlotL tmpS; 10105 regD tmpD; 10106 regL_to_stkL(tmpS, src); // Store long to stack. 10107 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10108 convL2FRaw_regF(dst, tmpD); // Convert to float. 10109 %} 10110%} 10111 10112// Moved up as used in expand. 10113//instruct convD2F_reg(regF dst, regD src) %{%} 10114 10115// Convert to Double 10116 10117// Integer to Double conversion. 10118instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{ 10119 match(Set dst (ConvI2D src)); 10120 ins_cost(DEFAULT_COST); 10121 10122 expand %{ 10123 iRegLdst tmpL; 10124 stackSlotL tmpS; 10125 regD tmpD; 10126 convI2L_reg(tmpL, src); // Sign-extension int to long. 10127 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10128 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10129 convL2DRaw_regD(dst, tmpD); // Convert to double. 10130 %} 10131%} 10132 10133// Long to Double conversion 10134instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{ 10135 match(Set dst (ConvL2D src)); 10136 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10137 10138 expand %{ 10139 regD tmpD; 10140 moveL2D_stack_reg(tmpD, src); 10141 convL2DRaw_regD(dst, tmpD); 10142 %} 10143%} 10144 10145instruct convF2D_reg(regD dst, regF src) %{ 10146 match(Set dst (ConvF2D src)); 10147 format %{ "FMR $dst, $src \t// float->double" %} 10148 // variable size, 0 or 4 10149 ins_encode %{ 10150 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 10151 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister); 10152 %} 10153 ins_pipe(pipe_class_default); 10154%} 10155 10156//----------Control Flow Instructions------------------------------------------ 10157// Compare Instructions 10158 10159// Compare Integers 10160instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ 10161 match(Set crx (CmpI src1 src2)); 10162 size(4); 10163 format %{ "CMPW $crx, $src1, $src2" %} 10164 ins_encode %{ 10165 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); 10166 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10167 %} 10168 ins_pipe(pipe_class_compare); 10169%} 10170 10171instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{ 10172 match(Set crx (CmpI src1 src2)); 10173 format %{ "CMPWI $crx, $src1, $src2" %} 10174 size(4); 10175 ins_encode %{ 10176 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10177 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10178 %} 10179 ins_pipe(pipe_class_compare); 10180%} 10181 10182// (src1 & src2) == 0? 10183instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{ 10184 match(Set cr0 (CmpI (AndI src1 src2) zero)); 10185 // r0 is killed 10186 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %} 10187 size(4); 10188 ins_encode %{ 10189 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 10190 __ andi_(R0, $src1$$Register, $src2$$constant); 10191 %} 10192 ins_pipe(pipe_class_compare); 10193%} 10194 10195instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{ 10196 match(Set crx (CmpL src1 src2)); 10197 format %{ "CMPD $crx, $src1, $src2" %} 10198 size(4); 10199 ins_encode %{ 10200 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); 10201 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register); 10202 %} 10203 ins_pipe(pipe_class_compare); 10204%} 10205 10206instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{ 10207 match(Set crx (CmpL src1 src2)); 10208 format %{ "CMPDI $crx, $src1, $src2" %} 10209 size(4); 10210 ins_encode %{ 10211 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10212 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10213 %} 10214 ins_pipe(pipe_class_compare); 10215%} 10216 10217instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{ 10218 match(Set cr0 (CmpL (AndL src1 src2) zero)); 10219 // r0 is killed 10220 format %{ "AND R0, $src1, $src2 \t// BTST long" %} 10221 size(4); 10222 ins_encode %{ 10223 // TODO: PPC port $archOpcode(ppc64Opcode_and_); 10224 __ and_(R0, $src1$$Register, $src2$$Register); 10225 %} 10226 ins_pipe(pipe_class_compare); 10227%} 10228 10229instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{ 10230 match(Set cr0 (CmpL (AndL src1 src2) zero)); 10231 // r0 is killed 10232 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %} 10233 size(4); 10234 ins_encode %{ 10235 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 10236 __ andi_(R0, $src1$$Register, $src2$$constant); 10237 %} 10238 ins_pipe(pipe_class_compare); 10239%} 10240 10241instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{ 10242 // no match-rule, false predicate 10243 effect(DEF dst, USE crx); 10244 predicate(false); 10245 10246 ins_variable_size_depending_on_alignment(true); 10247 10248 format %{ "cmovI $crx, $dst, -1, 0, +1" %} 10249 // Worst case is branch + move + branch + move + stop, no stop without scheduler. 10250 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16); 10251 ins_encode %{ 10252 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 10253 Label done; 10254 // li(Rdst, 0); // equal -> 0 10255 __ beq($crx$$CondRegister, done); 10256 __ li($dst$$Register, 1); // greater -> +1 10257 __ bgt($crx$$CondRegister, done); 10258 __ li($dst$$Register, -1); // unordered or less -> -1 10259 // TODO: PPC port__ endgroup_if_needed(_size == 20); 10260 __ bind(done); 10261 %} 10262 ins_pipe(pipe_class_compare); 10263%} 10264 10265instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{ 10266 // no match-rule, false predicate 10267 effect(DEF dst, USE crx); 10268 predicate(false); 10269 10270 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %} 10271 postalloc_expand %{ 10272 // 10273 // replaces 10274 // 10275 // region crx 10276 // \ | 10277 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1 10278 // 10279 // with 10280 // 10281 // region 10282 // \ 10283 // dst=loadConI16(0) 10284 // | 10285 // ^ region crx 10286 // | \ | 10287 // dst=cmovI_conIvalueMinus1_conIvalue1 10288 // 10289 10290 // Create new nodes. 10291 MachNode *m1 = new loadConI16Node(); 10292 MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node(); 10293 10294 // inputs for new nodes 10295 m1->add_req(n_region); 10296 m2->add_req(n_region, n_crx); 10297 m2->add_prec(m1); 10298 10299 // operands for new nodes 10300 m1->_opnds[0] = op_dst; 10301 m1->_opnds[1] = new immI16Oper(0); 10302 m2->_opnds[0] = op_dst; 10303 m2->_opnds[1] = op_crx; 10304 10305 // registers for new nodes 10306 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10307 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10308 10309 // Insert new nodes. 10310 nodes->push(m1); 10311 nodes->push(m2); 10312 %} 10313%} 10314 10315// Manifest a CmpL3 result in an integer register. Very painful. 10316// This is the test to avoid. 10317// (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0) 10318instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 10319 match(Set dst (CmpL3 src1 src2)); 10320 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10321 10322 expand %{ 10323 flagsReg tmp1; 10324 cmpL_reg_reg(tmp1, src1, src2); 10325 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10326 %} 10327%} 10328 10329// Implicit range checks. 10330// A range check in the ideal world has one of the following shapes: 10331// - (If le (CmpU length index)), (IfTrue throw exception) 10332// - (If lt (CmpU index length)), (IfFalse throw exception) 10333// 10334// Match range check 'If le (CmpU length index)'. 10335instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{ 10336 match(If cmp (CmpU src_length index)); 10337 effect(USE labl); 10338 predicate(TrapBasedRangeChecks && 10339 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && 10340 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS && 10341 (Matcher::branches_to_uncommon_trap(_leaf))); 10342 10343 ins_is_TrapBasedCheckNode(true); 10344 10345 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %} 10346 size(4); 10347 ins_encode %{ 10348 // TODO: PPC port $archOpcode(ppc64Opcode_twi); 10349 if ($cmp$$cmpcode == 0x1 /* less_equal */) { 10350 __ trap_range_check_le($src_length$$Register, $index$$constant); 10351 } else { 10352 // Both successors are uncommon traps, probability is 0. 10353 // Node got flipped during fixup flow. 10354 assert($cmp$$cmpcode == 0x9, "must be greater"); 10355 __ trap_range_check_g($src_length$$Register, $index$$constant); 10356 } 10357 %} 10358 ins_pipe(pipe_class_trap); 10359%} 10360 10361// Match range check 'If lt (CmpU index length)'. 10362instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{ 10363 match(If cmp (CmpU src_index src_length)); 10364 effect(USE labl); 10365 predicate(TrapBasedRangeChecks && 10366 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 10367 _leaf->as_If()->_prob >= PROB_ALWAYS && 10368 (Matcher::branches_to_uncommon_trap(_leaf))); 10369 10370 ins_is_TrapBasedCheckNode(true); 10371 10372 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %} 10373 size(4); 10374 ins_encode %{ 10375 // TODO: PPC port $archOpcode(ppc64Opcode_tw); 10376 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { 10377 __ trap_range_check_ge($src_index$$Register, $src_length$$Register); 10378 } else { 10379 // Both successors are uncommon traps, probability is 0. 10380 // Node got flipped during fixup flow. 10381 assert($cmp$$cmpcode == 0x8, "must be less"); 10382 __ trap_range_check_l($src_index$$Register, $src_length$$Register); 10383 } 10384 %} 10385 ins_pipe(pipe_class_trap); 10386%} 10387 10388// Match range check 'If lt (CmpU index length)'. 10389instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{ 10390 match(If cmp (CmpU src_index length)); 10391 effect(USE labl); 10392 predicate(TrapBasedRangeChecks && 10393 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 10394 _leaf->as_If()->_prob >= PROB_ALWAYS && 10395 (Matcher::branches_to_uncommon_trap(_leaf))); 10396 10397 ins_is_TrapBasedCheckNode(true); 10398 10399 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %} 10400 size(4); 10401 ins_encode %{ 10402 // TODO: PPC port $archOpcode(ppc64Opcode_twi); 10403 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { 10404 __ trap_range_check_ge($src_index$$Register, $length$$constant); 10405 } else { 10406 // Both successors are uncommon traps, probability is 0. 10407 // Node got flipped during fixup flow. 10408 assert($cmp$$cmpcode == 0x8, "must be less"); 10409 __ trap_range_check_l($src_index$$Register, $length$$constant); 10410 } 10411 %} 10412 ins_pipe(pipe_class_trap); 10413%} 10414 10415instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ 10416 match(Set crx (CmpU src1 src2)); 10417 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %} 10418 size(4); 10419 ins_encode %{ 10420 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10421 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10422 %} 10423 ins_pipe(pipe_class_compare); 10424%} 10425 10426instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{ 10427 match(Set crx (CmpU src1 src2)); 10428 size(4); 10429 format %{ "CMPLWI $crx, $src1, $src2" %} 10430 ins_encode %{ 10431 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); 10432 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10433 %} 10434 ins_pipe(pipe_class_compare); 10435%} 10436 10437// Implicit zero checks (more implicit null checks). 10438// No constant pool entries required. 10439instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{ 10440 match(If cmp (CmpN value zero)); 10441 effect(USE labl); 10442 predicate(TrapBasedNullChecks && 10443 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 10444 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && 10445 Matcher::branches_to_uncommon_trap(_leaf)); 10446 ins_cost(1); 10447 10448 ins_is_TrapBasedCheckNode(true); 10449 10450 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %} 10451 size(4); 10452 ins_encode %{ 10453 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 10454 if ($cmp$$cmpcode == 0xA) { 10455 __ trap_null_check($value$$Register); 10456 } else { 10457 // Both successors are uncommon traps, probability is 0. 10458 // Node got flipped during fixup flow. 10459 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); 10460 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); 10461 } 10462 %} 10463 ins_pipe(pipe_class_trap); 10464%} 10465 10466// Compare narrow oops. 10467instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{ 10468 match(Set crx (CmpN src1 src2)); 10469 10470 size(4); 10471 ins_cost(2); 10472 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %} 10473 ins_encode %{ 10474 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10475 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10476 %} 10477 ins_pipe(pipe_class_compare); 10478%} 10479 10480instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{ 10481 match(Set crx (CmpN src1 src2)); 10482 // Make this more expensive than zeroCheckN_iReg_imm0. 10483 ins_cost(2); 10484 10485 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %} 10486 size(4); 10487 ins_encode %{ 10488 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); 10489 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10490 %} 10491 ins_pipe(pipe_class_compare); 10492%} 10493 10494// Implicit zero checks (more implicit null checks). 10495// No constant pool entries required. 10496instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{ 10497 match(If cmp (CmpP value zero)); 10498 effect(USE labl); 10499 predicate(TrapBasedNullChecks && 10500 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 10501 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && 10502 Matcher::branches_to_uncommon_trap(_leaf)); 10503 ins_cost(1); // Should not be cheaper than zeroCheckN. 10504 10505 ins_is_TrapBasedCheckNode(true); 10506 10507 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %} 10508 size(4); 10509 ins_encode %{ 10510 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 10511 if ($cmp$$cmpcode == 0xA) { 10512 __ trap_null_check($value$$Register); 10513 } else { 10514 // Both successors are uncommon traps, probability is 0. 10515 // Node got flipped during fixup flow. 10516 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); 10517 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); 10518 } 10519 %} 10520 ins_pipe(pipe_class_trap); 10521%} 10522 10523// Compare Pointers 10524instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{ 10525 match(Set crx (CmpP src1 src2)); 10526 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %} 10527 size(4); 10528 ins_encode %{ 10529 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10530 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register); 10531 %} 10532 ins_pipe(pipe_class_compare); 10533%} 10534 10535// Used in postalloc expand. 10536instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{ 10537 // This match rule prevents reordering of node before a safepoint. 10538 // This only makes sense if this instructions is used exclusively 10539 // for the expansion of EncodeP! 10540 match(Set crx (CmpP src1 src2)); 10541 predicate(false); 10542 10543 format %{ "CMPDI $crx, $src1, $src2" %} 10544 size(4); 10545 ins_encode %{ 10546 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10547 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10548 %} 10549 ins_pipe(pipe_class_compare); 10550%} 10551 10552//----------Float Compares---------------------------------------------------- 10553 10554instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{ 10555 // Needs matchrule, see cmpDUnordered. 10556 match(Set crx (CmpF src1 src2)); 10557 // no match-rule, false predicate 10558 predicate(false); 10559 10560 format %{ "cmpFUrd $crx, $src1, $src2" %} 10561 size(4); 10562 ins_encode %{ 10563 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); 10564 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); 10565 %} 10566 ins_pipe(pipe_class_default); 10567%} 10568 10569instruct cmov_bns_less(flagsReg crx) %{ 10570 // no match-rule, false predicate 10571 effect(DEF crx); 10572 predicate(false); 10573 10574 ins_variable_size_depending_on_alignment(true); 10575 10576 format %{ "cmov $crx" %} 10577 // Worst case is branch + move + stop, no stop without scheduler. 10578 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12); 10579 ins_encode %{ 10580 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr); 10581 Label done; 10582 __ bns($crx$$CondRegister, done); // not unordered -> keep crx 10583 __ li(R0, 0); 10584 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less' 10585 // TODO PPC port __ endgroup_if_needed(_size == 16); 10586 __ bind(done); 10587 %} 10588 ins_pipe(pipe_class_default); 10589%} 10590 10591// Compare floating, generate condition code. 10592instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{ 10593 // FIXME: should we match 'If cmp (CmpF src1 src2))' ?? 10594 // 10595 // The following code sequence occurs a lot in mpegaudio: 10596 // 10597 // block BXX: 10598 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0): 10599 // cmpFUrd CCR6, F11, F9 10600 // 4: instruct cmov_bns_less (cmpF_reg_reg-1): 10601 // cmov CCR6 10602 // 8: instruct branchConSched: 10603 // B_FARle CCR6, B56 P=0.500000 C=-1.000000 10604 match(Set crx (CmpF src1 src2)); 10605 ins_cost(DEFAULT_COST+BRANCH_COST); 10606 10607 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %} 10608 postalloc_expand %{ 10609 // 10610 // replaces 10611 // 10612 // region src1 src2 10613 // \ | | 10614 // crx=cmpF_reg_reg 10615 // 10616 // with 10617 // 10618 // region src1 src2 10619 // \ | | 10620 // crx=cmpFUnordered_reg_reg 10621 // | 10622 // ^ region 10623 // | \ 10624 // crx=cmov_bns_less 10625 // 10626 10627 // Create new nodes. 10628 MachNode *m1 = new cmpFUnordered_reg_regNode(); 10629 MachNode *m2 = new cmov_bns_lessNode(); 10630 10631 // inputs for new nodes 10632 m1->add_req(n_region, n_src1, n_src2); 10633 m2->add_req(n_region); 10634 m2->add_prec(m1); 10635 10636 // operands for new nodes 10637 m1->_opnds[0] = op_crx; 10638 m1->_opnds[1] = op_src1; 10639 m1->_opnds[2] = op_src2; 10640 m2->_opnds[0] = op_crx; 10641 10642 // registers for new nodes 10643 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10644 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10645 10646 // Insert new nodes. 10647 nodes->push(m1); 10648 nodes->push(m2); 10649 %} 10650%} 10651 10652// Compare float, generate -1,0,1 10653instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{ 10654 match(Set dst (CmpF3 src1 src2)); 10655 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10656 10657 expand %{ 10658 flagsReg tmp1; 10659 cmpFUnordered_reg_reg(tmp1, src1, src2); 10660 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10661 %} 10662%} 10663 10664instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{ 10665 // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the 10666 // node right before the conditional move using it. 10667 // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7, 10668 // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle 10669 // crashed in register allocation where the flags Reg between cmpDUnoredered and a 10670 // conditional move was supposed to be spilled. 10671 match(Set crx (CmpD src1 src2)); 10672 // False predicate, shall not be matched. 10673 predicate(false); 10674 10675 format %{ "cmpFUrd $crx, $src1, $src2" %} 10676 size(4); 10677 ins_encode %{ 10678 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); 10679 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); 10680 %} 10681 ins_pipe(pipe_class_default); 10682%} 10683 10684instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{ 10685 match(Set crx (CmpD src1 src2)); 10686 ins_cost(DEFAULT_COST+BRANCH_COST); 10687 10688 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %} 10689 postalloc_expand %{ 10690 // 10691 // replaces 10692 // 10693 // region src1 src2 10694 // \ | | 10695 // crx=cmpD_reg_reg 10696 // 10697 // with 10698 // 10699 // region src1 src2 10700 // \ | | 10701 // crx=cmpDUnordered_reg_reg 10702 // | 10703 // ^ region 10704 // | \ 10705 // crx=cmov_bns_less 10706 // 10707 10708 // create new nodes 10709 MachNode *m1 = new cmpDUnordered_reg_regNode(); 10710 MachNode *m2 = new cmov_bns_lessNode(); 10711 10712 // inputs for new nodes 10713 m1->add_req(n_region, n_src1, n_src2); 10714 m2->add_req(n_region); 10715 m2->add_prec(m1); 10716 10717 // operands for new nodes 10718 m1->_opnds[0] = op_crx; 10719 m1->_opnds[1] = op_src1; 10720 m1->_opnds[2] = op_src2; 10721 m2->_opnds[0] = op_crx; 10722 10723 // registers for new nodes 10724 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10725 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10726 10727 // Insert new nodes. 10728 nodes->push(m1); 10729 nodes->push(m2); 10730 %} 10731%} 10732 10733// Compare double, generate -1,0,1 10734instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{ 10735 match(Set dst (CmpD3 src1 src2)); 10736 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10737 10738 expand %{ 10739 flagsReg tmp1; 10740 cmpDUnordered_reg_reg(tmp1, src1, src2); 10741 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10742 %} 10743%} 10744 10745//----------Branches--------------------------------------------------------- 10746// Jump 10747 10748// Direct Branch. 10749instruct branch(label labl) %{ 10750 match(Goto); 10751 effect(USE labl); 10752 ins_cost(BRANCH_COST); 10753 10754 format %{ "B $labl" %} 10755 size(4); 10756 ins_encode %{ 10757 // TODO: PPC port $archOpcode(ppc64Opcode_b); 10758 Label d; // dummy 10759 __ bind(d); 10760 Label* p = $labl$$label; 10761 // `p' is `NULL' when this encoding class is used only to 10762 // determine the size of the encoded instruction. 10763 Label& l = (NULL == p)? d : *(p); 10764 __ b(l); 10765 %} 10766 ins_pipe(pipe_class_default); 10767%} 10768 10769// Conditional Near Branch 10770instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{ 10771 // Same match rule as `branchConFar'. 10772 match(If cmp crx); 10773 effect(USE lbl); 10774 ins_cost(BRANCH_COST); 10775 10776 // If set to 1 this indicates that the current instruction is a 10777 // short variant of a long branch. This avoids using this 10778 // instruction in first-pass matching. It will then only be used in 10779 // the `Shorten_branches' pass. 10780 ins_short_branch(1); 10781 10782 format %{ "B$cmp $crx, $lbl" %} 10783 size(4); 10784 ins_encode( enc_bc(crx, cmp, lbl) ); 10785 ins_pipe(pipe_class_default); 10786%} 10787 10788// This is for cases when the ppc64 `bc' instruction does not 10789// reach far enough. So we emit a far branch here, which is more 10790// expensive. 10791// 10792// Conditional Far Branch 10793instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{ 10794 // Same match rule as `branchCon'. 10795 match(If cmp crx); 10796 effect(USE crx, USE lbl); 10797 predicate(!false /* TODO: PPC port HB_Schedule*/); 10798 // Higher cost than `branchCon'. 10799 ins_cost(5*BRANCH_COST); 10800 10801 // This is not a short variant of a branch, but the long variant. 10802 ins_short_branch(0); 10803 10804 format %{ "B_FAR$cmp $crx, $lbl" %} 10805 size(8); 10806 ins_encode( enc_bc_far(crx, cmp, lbl) ); 10807 ins_pipe(pipe_class_default); 10808%} 10809 10810// Conditional Branch used with Power6 scheduler (can be far or short). 10811instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{ 10812 // Same match rule as `branchCon'. 10813 match(If cmp crx); 10814 effect(USE crx, USE lbl); 10815 predicate(false /* TODO: PPC port HB_Schedule*/); 10816 // Higher cost than `branchCon'. 10817 ins_cost(5*BRANCH_COST); 10818 10819 // Actually size doesn't depend on alignment but on shortening. 10820 ins_variable_size_depending_on_alignment(true); 10821 // long variant. 10822 ins_short_branch(0); 10823 10824 format %{ "B_FAR$cmp $crx, $lbl" %} 10825 size(8); // worst case 10826 ins_encode( enc_bc_short_far(crx, cmp, lbl) ); 10827 ins_pipe(pipe_class_default); 10828%} 10829 10830instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{ 10831 match(CountedLoopEnd cmp crx); 10832 effect(USE labl); 10833 ins_cost(BRANCH_COST); 10834 10835 // short variant. 10836 ins_short_branch(1); 10837 10838 format %{ "B$cmp $crx, $labl \t// counted loop end" %} 10839 size(4); 10840 ins_encode( enc_bc(crx, cmp, labl) ); 10841 ins_pipe(pipe_class_default); 10842%} 10843 10844instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{ 10845 match(CountedLoopEnd cmp crx); 10846 effect(USE labl); 10847 predicate(!false /* TODO: PPC port HB_Schedule */); 10848 ins_cost(BRANCH_COST); 10849 10850 // Long variant. 10851 ins_short_branch(0); 10852 10853 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} 10854 size(8); 10855 ins_encode( enc_bc_far(crx, cmp, labl) ); 10856 ins_pipe(pipe_class_default); 10857%} 10858 10859// Conditional Branch used with Power6 scheduler (can be far or short). 10860instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{ 10861 match(CountedLoopEnd cmp crx); 10862 effect(USE labl); 10863 predicate(false /* TODO: PPC port HB_Schedule */); 10864 // Higher cost than `branchCon'. 10865 ins_cost(5*BRANCH_COST); 10866 10867 // Actually size doesn't depend on alignment but on shortening. 10868 ins_variable_size_depending_on_alignment(true); 10869 // Long variant. 10870 ins_short_branch(0); 10871 10872 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} 10873 size(8); // worst case 10874 ins_encode( enc_bc_short_far(crx, cmp, labl) ); 10875 ins_pipe(pipe_class_default); 10876%} 10877 10878// ============================================================================ 10879// Java runtime operations, intrinsics and other complex operations. 10880 10881// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 10882// array for an instance of the superklass. Set a hidden internal cache on a 10883// hit (cache is checked with exposed code in gen_subtype_check()). Return 10884// not zero for a miss or zero for a hit. The encoding ALSO sets flags. 10885// 10886// GL TODO: Improve this. 10887// - result should not be a TEMP 10888// - Add match rule as on sparc avoiding additional Cmp. 10889instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass, 10890 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{ 10891 match(Set result (PartialSubtypeCheck subklass superklass)); 10892 effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr); 10893 ins_cost(DEFAULT_COST*10); 10894 10895 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %} 10896 ins_encode %{ 10897 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10898 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register, 10899 $tmp_klass$$Register, NULL, $result$$Register); 10900 %} 10901 ins_pipe(pipe_class_default); 10902%} 10903 10904// inlined locking and unlocking 10905 10906instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2) %{ 10907 match(Set crx (FastLock oop box)); 10908 effect(TEMP tmp1, TEMP tmp2); 10909 predicate(!Compile::current()->use_rtm()); 10910 10911 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2" %} 10912 ins_encode %{ 10913 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10914 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10915 $tmp1$$Register, $tmp2$$Register, /*tmp3*/ R0, 10916 UseBiasedLocking && !UseOptoBiasInlining); 10917 // If locking was successfull, crx should indicate 'EQ'. 10918 // The compiler generates a branch to the runtime call to 10919 // _complete_monitor_locking_Java for the case where crx is 'NE'. 10920 %} 10921 ins_pipe(pipe_class_compare); 10922%} 10923 10924// Separate version for TM. Use bound register for box to enable USE_KILL. 10925instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10926 match(Set crx (FastLock oop box)); 10927 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box); 10928 predicate(Compile::current()->use_rtm()); 10929 10930 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %} 10931 ins_encode %{ 10932 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10933 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10934 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, 10935 /*Biased Locking*/ false, 10936 _rtm_counters, _stack_rtm_counters, 10937 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(), 10938 /*TM*/ true, ra_->C->profile_rtm()); 10939 // If locking was successfull, crx should indicate 'EQ'. 10940 // The compiler generates a branch to the runtime call to 10941 // _complete_monitor_locking_Java for the case where crx is 'NE'. 10942 %} 10943 ins_pipe(pipe_class_compare); 10944%} 10945 10946instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10947 match(Set crx (FastUnlock oop box)); 10948 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 10949 predicate(!Compile::current()->use_rtm()); 10950 10951 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %} 10952 ins_encode %{ 10953 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10954 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10955 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, 10956 UseBiasedLocking && !UseOptoBiasInlining, 10957 false); 10958 // If unlocking was successfull, crx should indicate 'EQ'. 10959 // The compiler generates a branch to the runtime call to 10960 // _complete_monitor_unlocking_Java for the case where crx is 'NE'. 10961 %} 10962 ins_pipe(pipe_class_compare); 10963%} 10964 10965instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10966 match(Set crx (FastUnlock oop box)); 10967 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 10968 predicate(Compile::current()->use_rtm()); 10969 10970 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2 (TM)" %} 10971 ins_encode %{ 10972 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10973 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10974 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, 10975 /*Biased Locking*/ false, /*TM*/ true); 10976 // If unlocking was successfull, crx should indicate 'EQ'. 10977 // The compiler generates a branch to the runtime call to 10978 // _complete_monitor_unlocking_Java for the case where crx is 'NE'. 10979 %} 10980 ins_pipe(pipe_class_compare); 10981%} 10982 10983// Align address. 10984instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{ 10985 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 10986 10987 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %} 10988 size(4); 10989 ins_encode %{ 10990 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 10991 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant)); 10992 %} 10993 ins_pipe(pipe_class_default); 10994%} 10995 10996// Array size computation. 10997instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{ 10998 match(Set dst (SubL (CastP2X end) (CastP2X start))); 10999 11000 format %{ "SUB $dst, $end, $start \t// array size in bytes" %} 11001 size(4); 11002 ins_encode %{ 11003 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 11004 __ subf($dst$$Register, $start$$Register, $end$$Register); 11005 %} 11006 ins_pipe(pipe_class_default); 11007%} 11008 11009// Clear-array with dynamic array-size. 11010instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{ 11011 match(Set dummy (ClearArray cnt base)); 11012 effect(USE_KILL cnt, USE_KILL base, KILL ctr); 11013 ins_cost(MEMORY_REF_COST); 11014 11015 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11016 11017 format %{ "ClearArray $cnt, $base" %} 11018 ins_encode %{ 11019 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11020 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0 11021 %} 11022 ins_pipe(pipe_class_default); 11023%} 11024 11025// String_IndexOf for needle of length 1. 11026// 11027// Match needle into immediate operands: no loadConP node needed. Saves one 11028// register and two instructions over string_indexOf_imm1Node. 11029// 11030// Assumes register result differs from all input registers. 11031// 11032// Preserves registers haystack, haycnt 11033// Kills registers tmp1, tmp2 11034// Defines registers result 11035// 11036// Use dst register classes if register gets killed, as it is the case for tmp registers! 11037// 11038// Unfortunately this does not match too often. In many situations the AddP is used 11039// by several nodes, even several StrIndexOf nodes, breaking the match tree. 11040instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11041 immP needleImm, immL offsetImm, immI_1 needlecntImm, 11042 iRegIdst tmp1, iRegIdst tmp2, 11043 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{ 11044 predicate(SpecialStringIndexOf && !CompactStrings); // type check implicit by parameter type, See Matcher::match_rule_supported 11045 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm))); 11046 11047 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr); 11048 11049 ins_cost(150); 11050 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]" 11051 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} 11052 11053 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted 11054 ins_encode %{ 11055 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11056 immPOper *needleOper = (immPOper *)$needleImm; 11057 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 11058 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 11059 jchar chr; 11060 if (java_lang_String::has_coder_field()) { 11061 // New compact strings byte array strings 11062#ifdef VM_LITTLE_ENDIAN 11063 chr = (((jchar)needle_values->element_value(1).as_byte()) << 8) | 11064 (jchar)needle_values->element_value(0).as_byte(); 11065#else 11066 chr = (((jchar)needle_values->element_value(0).as_byte()) << 8) | 11067 (jchar)needle_values->element_value(1).as_byte(); 11068#endif 11069 } else { 11070 // Old char array strings 11071 chr = needle_values->char_at(0); 11072 } 11073 __ string_indexof_1($result$$Register, 11074 $haystack$$Register, $haycnt$$Register, 11075 R0, chr, 11076 $tmp1$$Register, $tmp2$$Register); 11077 %} 11078 ins_pipe(pipe_class_compare); 11079%} 11080 11081// String_IndexOf for needle of length 1. 11082// 11083// Special case requires less registers and emits less instructions. 11084// 11085// Assumes register result differs from all input registers. 11086// 11087// Preserves registers haystack, haycnt 11088// Kills registers tmp1, tmp2, needle 11089// Defines registers result 11090// 11091// Use dst register classes if register gets killed, as it is the case for tmp registers! 11092instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11093 rscratch2RegP needle, immI_1 needlecntImm, 11094 iRegIdst tmp1, iRegIdst tmp2, 11095 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{ 11096 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11097 effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result, 11098 TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr); 11099 // Required for EA: check if it is still a type_array. 11100 predicate(SpecialStringIndexOf && !CompactStrings && 11101 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11102 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11103 ins_cost(180); 11104 11105 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11106 11107 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11108 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %} 11109 ins_encode %{ 11110 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11111 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11112 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11113 guarantee(needle_values, "sanity"); 11114 jchar chr; 11115 if (java_lang_String::has_coder_field()) { 11116 // New compact strings byte array strings 11117#ifdef VM_LITTLE_ENDIAN 11118 chr = (((jchar)needle_values->element_value(1).as_byte()) << 8) | 11119 (jchar)needle_values->element_value(0).as_byte(); 11120#else 11121 chr = (((jchar)needle_values->element_value(0).as_byte()) << 8) | 11122 (jchar)needle_values->element_value(1).as_byte(); 11123#endif 11124 } else { 11125 // Old char array strings 11126 chr = needle_values->char_at(0); 11127 } 11128 __ string_indexof_1($result$$Register, 11129 $haystack$$Register, $haycnt$$Register, 11130 R0, chr, 11131 $tmp1$$Register, $tmp2$$Register); 11132 %} 11133 ins_pipe(pipe_class_compare); 11134%} 11135 11136// String_IndexOfChar 11137// 11138// Assumes register result differs from all input registers. 11139// 11140// Preserves registers haystack, haycnt 11141// Kills registers tmp1, tmp2 11142// Defines registers result 11143// 11144// Use dst register classes if register gets killed, as it is the case for tmp registers! 11145instruct string_indexOfChar(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11146 iRegIsrc ch, iRegIdst tmp1, iRegIdst tmp2, 11147 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{ 11148 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch)); 11149 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr); 11150 predicate(SpecialStringIndexOf && !CompactStrings); 11151 ins_cost(180); 11152 11153 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11154 11155 format %{ "String IndexOfChar $haystack[0..$haycnt], $ch" 11156 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} 11157 ins_encode %{ 11158 __ string_indexof_1($result$$Register, 11159 $haystack$$Register, $haycnt$$Register, 11160 $ch$$Register, 0 /* this is not used if the character is already in a register */, 11161 $tmp1$$Register, $tmp2$$Register); 11162 %} 11163 ins_pipe(pipe_class_compare); 11164%} 11165 11166// String_IndexOf. 11167// 11168// Length of needle as immediate. This saves instruction loading constant needle 11169// length. 11170// @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle 11171// completely or do it in vector instruction. This should save registers for 11172// needlecnt and needle. 11173// 11174// Assumes register result differs from all input registers. 11175// Overwrites haycnt, needlecnt. 11176// Use dst register classes if register gets killed, as it is the case for tmp registers! 11177instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, 11178 iRegPsrc needle, uimmI15 needlecntImm, 11179 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5, 11180 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11181 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11182 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result, 11183 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11184 // Required for EA: check if it is still a type_array. 11185 predicate(SpecialStringIndexOf && !CompactStrings && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11186 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11187 ins_cost(250); 11188 11189 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11190 11191 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11192 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %} 11193 ins_encode %{ 11194 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11195 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11196 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11197 11198 __ string_indexof($result$$Register, 11199 $haystack$$Register, $haycnt$$Register, 11200 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant, 11201 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); 11202 %} 11203 ins_pipe(pipe_class_compare); 11204%} 11205 11206// StrIndexOf node. 11207// 11208// Assumes register result differs from all input registers. 11209// Overwrites haycnt, needlecnt. 11210// Use dst register classes if register gets killed, as it is the case for tmp registers! 11211instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt, 11212 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, 11213 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11214 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 11215 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/ 11216 TEMP_DEF result, 11217 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11218 predicate(SpecialStringIndexOf && !CompactStrings); // See Matcher::match_rule_supported. 11219 ins_cost(300); 11220 11221 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11222 11223 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]" 11224 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %} 11225 ins_encode %{ 11226 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11227 __ string_indexof($result$$Register, 11228 $haystack$$Register, $haycnt$$Register, 11229 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant. 11230 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); 11231 %} 11232 ins_pipe(pipe_class_compare); 11233%} 11234 11235// String equals with immediate. 11236instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result, 11237 iRegPdst tmp1, iRegPdst tmp2, 11238 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{ 11239 match(Set result (StrEquals (Binary str1 str2) cntImm)); 11240 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, 11241 KILL cr0, KILL cr6, KILL ctr); 11242 predicate(SpecialStringEquals && !CompactStrings); // See Matcher::match_rule_supported. 11243 ins_cost(250); 11244 11245 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11246 11247 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)" 11248 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %} 11249 ins_encode %{ 11250 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11251 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant, 11252 $result$$Register, $tmp1$$Register, $tmp2$$Register); 11253 %} 11254 ins_pipe(pipe_class_compare); 11255%} 11256 11257// String equals. 11258// Use dst register classes if register gets killed, as it is the case for TEMP operands! 11259instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result, 11260 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5, 11261 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11262 match(Set result (StrEquals (Binary str1 str2) cnt)); 11263 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, 11264 KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11265 predicate(SpecialStringEquals && !CompactStrings); // See Matcher::match_rule_supported. 11266 ins_cost(300); 11267 11268 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11269 11270 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result" 11271 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %} 11272 ins_encode %{ 11273 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11274 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register, 11275 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register); 11276 %} 11277 ins_pipe(pipe_class_compare); 11278%} 11279 11280// String compare. 11281// Char[] pointers are passed in. 11282// Use dst register classes if register gets killed, as it is the case for TEMP operands! 11283instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result, 11284 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{ 11285 predicate(!CompactStrings); 11286 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11287 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr); 11288 ins_cost(300); 11289 11290 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11291 11292 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result" 11293 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %} 11294 ins_encode %{ 11295 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11296 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register, 11297 $result$$Register, $tmp$$Register); 11298 %} 11299 ins_pipe(pipe_class_compare); 11300%} 11301 11302//---------- Min/Max Instructions --------------------------------------------- 11303 11304instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 11305 match(Set dst (MinI src1 src2)); 11306 ins_cost(DEFAULT_COST*6); 11307 11308 expand %{ 11309 iRegLdst src1s; 11310 iRegLdst src2s; 11311 iRegLdst diff; 11312 iRegLdst sm; 11313 iRegLdst doz; // difference or zero 11314 convI2L_reg(src1s, src1); // Ensure proper sign extension. 11315 convI2L_reg(src2s, src2); // Ensure proper sign extension. 11316 subL_reg_reg(diff, src2s, src1s); 11317 // Need to consider >=33 bit result, therefore we need signmaskL. 11318 signmask64L_regL(sm, diff); 11319 andL_reg_reg(doz, diff, sm); // <=0 11320 addI_regL_regL(dst, doz, src1s); 11321 %} 11322%} 11323 11324instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 11325 match(Set dst (MaxI src1 src2)); 11326 ins_cost(DEFAULT_COST*6); 11327 11328 expand %{ 11329 iRegLdst src1s; 11330 iRegLdst src2s; 11331 iRegLdst diff; 11332 iRegLdst sm; 11333 iRegLdst doz; // difference or zero 11334 convI2L_reg(src1s, src1); // Ensure proper sign extension. 11335 convI2L_reg(src2s, src2); // Ensure proper sign extension. 11336 subL_reg_reg(diff, src2s, src1s); 11337 // Need to consider >=33 bit result, therefore we need signmaskL. 11338 signmask64L_regL(sm, diff); 11339 andcL_reg_reg(doz, diff, sm); // >=0 11340 addI_regL_regL(dst, doz, src1s); 11341 %} 11342%} 11343 11344//---------- Population Count Instructions ------------------------------------ 11345 11346// Popcnt for Power7. 11347instruct popCountI(iRegIdst dst, iRegIsrc src) %{ 11348 match(Set dst (PopCountI src)); 11349 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); 11350 ins_cost(DEFAULT_COST); 11351 11352 format %{ "POPCNTW $dst, $src" %} 11353 size(4); 11354 ins_encode %{ 11355 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); 11356 __ popcntw($dst$$Register, $src$$Register); 11357 %} 11358 ins_pipe(pipe_class_default); 11359%} 11360 11361// Popcnt for Power7. 11362instruct popCountL(iRegIdst dst, iRegLsrc src) %{ 11363 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); 11364 match(Set dst (PopCountL src)); 11365 ins_cost(DEFAULT_COST); 11366 11367 format %{ "POPCNTD $dst, $src" %} 11368 size(4); 11369 ins_encode %{ 11370 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); 11371 __ popcntd($dst$$Register, $src$$Register); 11372 %} 11373 ins_pipe(pipe_class_default); 11374%} 11375 11376instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{ 11377 match(Set dst (CountLeadingZerosI src)); 11378 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. 11379 ins_cost(DEFAULT_COST); 11380 11381 format %{ "CNTLZW $dst, $src" %} 11382 size(4); 11383 ins_encode %{ 11384 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw); 11385 __ cntlzw($dst$$Register, $src$$Register); 11386 %} 11387 ins_pipe(pipe_class_default); 11388%} 11389 11390instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{ 11391 match(Set dst (CountLeadingZerosL src)); 11392 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. 11393 ins_cost(DEFAULT_COST); 11394 11395 format %{ "CNTLZD $dst, $src" %} 11396 size(4); 11397 ins_encode %{ 11398 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); 11399 __ cntlzd($dst$$Register, $src$$Register); 11400 %} 11401 ins_pipe(pipe_class_default); 11402%} 11403 11404instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{ 11405 // no match-rule, false predicate 11406 effect(DEF dst, USE src); 11407 predicate(false); 11408 11409 format %{ "CNTLZD $dst, $src" %} 11410 size(4); 11411 ins_encode %{ 11412 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); 11413 __ cntlzd($dst$$Register, $src$$Register); 11414 %} 11415 ins_pipe(pipe_class_default); 11416%} 11417 11418instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{ 11419 match(Set dst (CountTrailingZerosI src)); 11420 predicate(UseCountLeadingZerosInstructionsPPC64); 11421 ins_cost(DEFAULT_COST); 11422 11423 expand %{ 11424 immI16 imm1 %{ (int)-1 %} 11425 immI16 imm2 %{ (int)32 %} 11426 immI_minus1 m1 %{ -1 %} 11427 iRegIdst tmpI1; 11428 iRegIdst tmpI2; 11429 iRegIdst tmpI3; 11430 addI_reg_imm16(tmpI1, src, imm1); 11431 andcI_reg_reg(tmpI2, src, m1, tmpI1); 11432 countLeadingZerosI(tmpI3, tmpI2); 11433 subI_imm16_reg(dst, imm2, tmpI3); 11434 %} 11435%} 11436 11437instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{ 11438 match(Set dst (CountTrailingZerosL src)); 11439 predicate(UseCountLeadingZerosInstructionsPPC64); 11440 ins_cost(DEFAULT_COST); 11441 11442 expand %{ 11443 immL16 imm1 %{ (long)-1 %} 11444 immI16 imm2 %{ (int)64 %} 11445 iRegLdst tmpL1; 11446 iRegLdst tmpL2; 11447 iRegIdst tmpL3; 11448 addL_reg_imm16(tmpL1, src, imm1); 11449 andcL_reg_reg(tmpL2, tmpL1, src); 11450 countLeadingZerosL(tmpL3, tmpL2); 11451 subI_imm16_reg(dst, imm2, tmpL3); 11452 %} 11453%} 11454 11455// Expand nodes for byte_reverse_int. 11456instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ 11457 effect(DEF dst, USE src, USE pos, USE shift); 11458 predicate(false); 11459 11460 format %{ "INSRWI $dst, $src, $pos, $shift" %} 11461 size(4); 11462 ins_encode %{ 11463 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); 11464 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); 11465 %} 11466 ins_pipe(pipe_class_default); 11467%} 11468 11469// As insrwi_a, but with USE_DEF. 11470instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ 11471 effect(USE_DEF dst, USE src, USE pos, USE shift); 11472 predicate(false); 11473 11474 format %{ "INSRWI $dst, $src, $pos, $shift" %} 11475 size(4); 11476 ins_encode %{ 11477 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); 11478 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); 11479 %} 11480 ins_pipe(pipe_class_default); 11481%} 11482 11483// Just slightly faster than java implementation. 11484instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{ 11485 match(Set dst (ReverseBytesI src)); 11486 predicate(UseCountLeadingZerosInstructionsPPC64); 11487 ins_cost(DEFAULT_COST); 11488 11489 expand %{ 11490 immI16 imm24 %{ (int) 24 %} 11491 immI16 imm16 %{ (int) 16 %} 11492 immI16 imm8 %{ (int) 8 %} 11493 immI16 imm4 %{ (int) 4 %} 11494 immI16 imm0 %{ (int) 0 %} 11495 iRegLdst tmpI1; 11496 iRegLdst tmpI2; 11497 iRegLdst tmpI3; 11498 11499 urShiftI_reg_imm(tmpI1, src, imm24); 11500 insrwi_a(dst, tmpI1, imm24, imm8); 11501 urShiftI_reg_imm(tmpI2, src, imm16); 11502 insrwi(dst, tmpI2, imm8, imm16); 11503 urShiftI_reg_imm(tmpI3, src, imm8); 11504 insrwi(dst, tmpI3, imm8, imm8); 11505 insrwi(dst, src, imm0, imm8); 11506 %} 11507%} 11508 11509//---------- Replicate Vector Instructions ------------------------------------ 11510 11511// Insrdi does replicate if src == dst. 11512instruct repl32(iRegLdst dst) %{ 11513 predicate(false); 11514 effect(USE_DEF dst); 11515 11516 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %} 11517 size(4); 11518 ins_encode %{ 11519 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11520 __ insrdi($dst$$Register, $dst$$Register, 32, 0); 11521 %} 11522 ins_pipe(pipe_class_default); 11523%} 11524 11525// Insrdi does replicate if src == dst. 11526instruct repl48(iRegLdst dst) %{ 11527 predicate(false); 11528 effect(USE_DEF dst); 11529 11530 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %} 11531 size(4); 11532 ins_encode %{ 11533 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11534 __ insrdi($dst$$Register, $dst$$Register, 48, 0); 11535 %} 11536 ins_pipe(pipe_class_default); 11537%} 11538 11539// Insrdi does replicate if src == dst. 11540instruct repl56(iRegLdst dst) %{ 11541 predicate(false); 11542 effect(USE_DEF dst); 11543 11544 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %} 11545 size(4); 11546 ins_encode %{ 11547 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 11548 __ insrdi($dst$$Register, $dst$$Register, 56, 0); 11549 %} 11550 ins_pipe(pipe_class_default); 11551%} 11552 11553instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11554 match(Set dst (ReplicateB src)); 11555 predicate(n->as_Vector()->length() == 8); 11556 expand %{ 11557 moveReg(dst, src); 11558 repl56(dst); 11559 repl48(dst); 11560 repl32(dst); 11561 %} 11562%} 11563 11564instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{ 11565 match(Set dst (ReplicateB zero)); 11566 predicate(n->as_Vector()->length() == 8); 11567 format %{ "LI $dst, #0 \t// replicate8B" %} 11568 size(4); 11569 ins_encode %{ 11570 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11571 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11572 %} 11573 ins_pipe(pipe_class_default); 11574%} 11575 11576instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11577 match(Set dst (ReplicateB src)); 11578 predicate(n->as_Vector()->length() == 8); 11579 format %{ "LI $dst, #-1 \t// replicate8B" %} 11580 size(4); 11581 ins_encode %{ 11582 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11583 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11584 %} 11585 ins_pipe(pipe_class_default); 11586%} 11587 11588instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11589 match(Set dst (ReplicateS src)); 11590 predicate(n->as_Vector()->length() == 4); 11591 expand %{ 11592 moveReg(dst, src); 11593 repl48(dst); 11594 repl32(dst); 11595 %} 11596%} 11597 11598instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{ 11599 match(Set dst (ReplicateS zero)); 11600 predicate(n->as_Vector()->length() == 4); 11601 format %{ "LI $dst, #0 \t// replicate4C" %} 11602 size(4); 11603 ins_encode %{ 11604 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11605 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11606 %} 11607 ins_pipe(pipe_class_default); 11608%} 11609 11610instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11611 match(Set dst (ReplicateS src)); 11612 predicate(n->as_Vector()->length() == 4); 11613 format %{ "LI $dst, -1 \t// replicate4C" %} 11614 size(4); 11615 ins_encode %{ 11616 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11617 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11618 %} 11619 ins_pipe(pipe_class_default); 11620%} 11621 11622instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 11623 match(Set dst (ReplicateI src)); 11624 predicate(n->as_Vector()->length() == 2); 11625 ins_cost(2 * DEFAULT_COST); 11626 expand %{ 11627 moveReg(dst, src); 11628 repl32(dst); 11629 %} 11630%} 11631 11632instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{ 11633 match(Set dst (ReplicateI zero)); 11634 predicate(n->as_Vector()->length() == 2); 11635 format %{ "LI $dst, #0 \t// replicate4C" %} 11636 size(4); 11637 ins_encode %{ 11638 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11639 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 11640 %} 11641 ins_pipe(pipe_class_default); 11642%} 11643 11644instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{ 11645 match(Set dst (ReplicateI src)); 11646 predicate(n->as_Vector()->length() == 2); 11647 format %{ "LI $dst, -1 \t// replicate4C" %} 11648 size(4); 11649 ins_encode %{ 11650 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11651 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 11652 %} 11653 ins_pipe(pipe_class_default); 11654%} 11655 11656// Move float to int register via stack, replicate. 11657instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{ 11658 match(Set dst (ReplicateF src)); 11659 predicate(n->as_Vector()->length() == 2); 11660 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST); 11661 expand %{ 11662 stackSlotL tmpS; 11663 iRegIdst tmpI; 11664 moveF2I_reg_stack(tmpS, src); // Move float to stack. 11665 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg. 11666 moveReg(dst, tmpI); // Move int to long reg. 11667 repl32(dst); // Replicate bitpattern. 11668 %} 11669%} 11670 11671// Replicate scalar constant to packed float values in Double register 11672instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{ 11673 match(Set dst (ReplicateF src)); 11674 predicate(n->as_Vector()->length() == 2); 11675 ins_cost(5 * DEFAULT_COST); 11676 11677 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %} 11678 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) ); 11679%} 11680 11681// Replicate scalar zero constant to packed float values in Double register 11682instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{ 11683 match(Set dst (ReplicateF zero)); 11684 predicate(n->as_Vector()->length() == 2); 11685 11686 format %{ "LI $dst, #0 \t// replicate2F" %} 11687 ins_encode %{ 11688 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 11689 __ li($dst$$Register, 0x0); 11690 %} 11691 ins_pipe(pipe_class_default); 11692%} 11693 11694 11695//----------Overflow Math Instructions----------------------------------------- 11696 11697// Note that we have to make sure that XER.SO is reset before using overflow instructions. 11698// Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc). 11699// Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.) 11700 11701instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{ 11702 match(Set cr0 (OverflowAddL op1 op2)); 11703 11704 format %{ "add_ $op1, $op2\t# overflow check long" %} 11705 ins_encode %{ 11706 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11707 __ li(R0, 0); 11708 __ mtxer(R0); // clear XER.SO 11709 __ addo_(R0, $op1$$Register, $op2$$Register); 11710 %} 11711 ins_pipe(pipe_class_default); 11712%} 11713 11714instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{ 11715 match(Set cr0 (OverflowSubL op1 op2)); 11716 11717 format %{ "subfo_ R0, $op2, $op1\t# overflow check long" %} 11718 ins_encode %{ 11719 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11720 __ li(R0, 0); 11721 __ mtxer(R0); // clear XER.SO 11722 __ subfo_(R0, $op2$$Register, $op1$$Register); 11723 %} 11724 ins_pipe(pipe_class_default); 11725%} 11726 11727instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{ 11728 match(Set cr0 (OverflowSubL zero op2)); 11729 11730 format %{ "nego_ R0, $op2\t# overflow check long" %} 11731 ins_encode %{ 11732 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11733 __ li(R0, 0); 11734 __ mtxer(R0); // clear XER.SO 11735 __ nego_(R0, $op2$$Register); 11736 %} 11737 ins_pipe(pipe_class_default); 11738%} 11739 11740instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{ 11741 match(Set cr0 (OverflowMulL op1 op2)); 11742 11743 format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %} 11744 ins_encode %{ 11745 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11746 __ li(R0, 0); 11747 __ mtxer(R0); // clear XER.SO 11748 __ mulldo_(R0, $op1$$Register, $op2$$Register); 11749 %} 11750 ins_pipe(pipe_class_default); 11751%} 11752 11753 11754// ============================================================================ 11755// Safepoint Instruction 11756 11757instruct safePoint_poll(iRegPdst poll) %{ 11758 match(SafePoint poll); 11759 predicate(LoadPollAddressFromThread); 11760 11761 // It caused problems to add the effect that r0 is killed, but this 11762 // effect no longer needs to be mentioned, since r0 is not contained 11763 // in a reg_class. 11764 11765 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %} 11766 size(4); 11767 ins_encode( enc_poll(0x0, poll) ); 11768 ins_pipe(pipe_class_default); 11769%} 11770 11771// Safepoint without per-thread support. Load address of page to poll 11772// as constant. 11773// Rscratch2RegP is R12. 11774// LoadConPollAddr node is added in pd_post_matching_hook(). It must be 11775// a seperate node so that the oop map is at the right location. 11776instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{ 11777 match(SafePoint poll); 11778 predicate(!LoadPollAddressFromThread); 11779 11780 // It caused problems to add the effect that r0 is killed, but this 11781 // effect no longer needs to be mentioned, since r0 is not contained 11782 // in a reg_class. 11783 11784 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %} 11785 ins_encode( enc_poll(0x0, poll) ); 11786 ins_pipe(pipe_class_default); 11787%} 11788 11789// ============================================================================ 11790// Call Instructions 11791 11792// Call Java Static Instruction 11793 11794// Schedulable version of call static node. 11795instruct CallStaticJavaDirect(method meth) %{ 11796 match(CallStaticJava); 11797 effect(USE meth); 11798 ins_cost(CALL_COST); 11799 11800 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); 11801 11802 format %{ "CALL,static $meth \t// ==> " %} 11803 size(4); 11804 ins_encode( enc_java_static_call(meth) ); 11805 ins_pipe(pipe_class_call); 11806%} 11807 11808// Call Java Dynamic Instruction 11809 11810// Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call). 11811// Loading of IC was postalloc expanded. The nodes loading the IC are reachable 11812// via fields ins_field_load_ic_hi_node and ins_field_load_ic_node. 11813// The call destination must still be placed in the constant pool. 11814instruct CallDynamicJavaDirectSched(method meth) %{ 11815 match(CallDynamicJava); // To get all the data fields we need ... 11816 effect(USE meth); 11817 predicate(false); // ... but never match. 11818 11819 ins_field_load_ic_hi_node(loadConL_hiNode*); 11820 ins_field_load_ic_node(loadConLNode*); 11821 ins_num_consts(1 /* 1 patchable constant: call destination */); 11822 11823 format %{ "BL \t// dynamic $meth ==> " %} 11824 size(4); 11825 ins_encode( enc_java_dynamic_call_sched(meth) ); 11826 ins_pipe(pipe_class_call); 11827%} 11828 11829// Schedulable (i.e. postalloc expanded) version of call dynamic java. 11830// We use postalloc expanded calls if we use inline caches 11831// and do not update method data. 11832// 11833// This instruction has two constants: inline cache (IC) and call destination. 11834// Loading the inline cache will be postalloc expanded, thus leaving a call with 11835// one constant. 11836instruct CallDynamicJavaDirectSched_Ex(method meth) %{ 11837 match(CallDynamicJava); 11838 effect(USE meth); 11839 predicate(UseInlineCaches); 11840 ins_cost(CALL_COST); 11841 11842 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */); 11843 11844 format %{ "CALL,dynamic $meth \t// postalloc expanded" %} 11845 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) ); 11846%} 11847 11848// Compound version of call dynamic java 11849// We use postalloc expanded calls if we use inline caches 11850// and do not update method data. 11851instruct CallDynamicJavaDirect(method meth) %{ 11852 match(CallDynamicJava); 11853 effect(USE meth); 11854 predicate(!UseInlineCaches); 11855 ins_cost(CALL_COST); 11856 11857 // Enc_java_to_runtime_call needs up to 4 constants (method data oop). 11858 ins_num_consts(4); 11859 11860 format %{ "CALL,dynamic $meth \t// ==> " %} 11861 ins_encode( enc_java_dynamic_call(meth, constanttablebase) ); 11862 ins_pipe(pipe_class_call); 11863%} 11864 11865// Call Runtime Instruction 11866 11867instruct CallRuntimeDirect(method meth) %{ 11868 match(CallRuntime); 11869 effect(USE meth); 11870 ins_cost(CALL_COST); 11871 11872 // Enc_java_to_runtime_call needs up to 3 constants: call target, 11873 // env for callee, C-toc. 11874 ins_num_consts(3); 11875 11876 format %{ "CALL,runtime" %} 11877 ins_encode( enc_java_to_runtime_call(meth) ); 11878 ins_pipe(pipe_class_call); 11879%} 11880 11881// Call Leaf 11882 11883// Used by postalloc expand of CallLeafDirect_Ex (mtctr). 11884instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{ 11885 effect(DEF dst, USE src); 11886 11887 ins_num_consts(1); 11888 11889 format %{ "MTCTR $src" %} 11890 size(4); 11891 ins_encode( enc_leaf_call_mtctr(src) ); 11892 ins_pipe(pipe_class_default); 11893%} 11894 11895// Used by postalloc expand of CallLeafDirect_Ex (actual call). 11896instruct CallLeafDirect(method meth) %{ 11897 match(CallLeaf); // To get the data all the data fields we need ... 11898 effect(USE meth); 11899 predicate(false); // but never match. 11900 11901 format %{ "BCTRL \t// leaf call $meth ==> " %} 11902 size(4); 11903 ins_encode %{ 11904 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl); 11905 __ bctrl(); 11906 %} 11907 ins_pipe(pipe_class_call); 11908%} 11909 11910// postalloc expand of CallLeafDirect. 11911// Load adress to call from TOC, then bl to it. 11912instruct CallLeafDirect_Ex(method meth) %{ 11913 match(CallLeaf); 11914 effect(USE meth); 11915 ins_cost(CALL_COST); 11916 11917 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target, 11918 // env for callee, C-toc. 11919 ins_num_consts(3); 11920 11921 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %} 11922 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); 11923%} 11924 11925// Call runtime without safepoint - same as CallLeaf. 11926// postalloc expand of CallLeafNoFPDirect. 11927// Load adress to call from TOC, then bl to it. 11928instruct CallLeafNoFPDirect_Ex(method meth) %{ 11929 match(CallLeafNoFP); 11930 effect(USE meth); 11931 ins_cost(CALL_COST); 11932 11933 // Enc_java_to_runtime_call needs up to 3 constants: call target, 11934 // env for callee, C-toc. 11935 ins_num_consts(3); 11936 11937 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %} 11938 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); 11939%} 11940 11941// Tail Call; Jump from runtime stub to Java code. 11942// Also known as an 'interprocedural jump'. 11943// Target of jump will eventually return to caller. 11944// TailJump below removes the return address. 11945instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{ 11946 match(TailCall jump_target method_oop); 11947 ins_cost(CALL_COST); 11948 11949 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t" 11950 "BCTR \t// tail call" %} 11951 size(8); 11952 ins_encode %{ 11953 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11954 __ mtctr($jump_target$$Register); 11955 __ bctr(); 11956 %} 11957 ins_pipe(pipe_class_call); 11958%} 11959 11960// Return Instruction 11961instruct Ret() %{ 11962 match(Return); 11963 format %{ "BLR \t// branch to link register" %} 11964 size(4); 11965 ins_encode %{ 11966 // TODO: PPC port $archOpcode(ppc64Opcode_blr); 11967 // LR is restored in MachEpilogNode. Just do the RET here. 11968 __ blr(); 11969 %} 11970 ins_pipe(pipe_class_default); 11971%} 11972 11973// Tail Jump; remove the return address; jump to target. 11974// TailCall above leaves the return address around. 11975// TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 11976// ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 11977// "restore" before this instruction (in Epilogue), we need to materialize it 11978// in %i0. 11979instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{ 11980 match(TailJump jump_target ex_oop); 11981 ins_cost(CALL_COST); 11982 11983 format %{ "LD R4_ARG2 = LR\n\t" 11984 "MTCTR $jump_target\n\t" 11985 "BCTR \t// TailJump, exception oop: $ex_oop" %} 11986 size(12); 11987 ins_encode %{ 11988 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11989 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP); 11990 __ mtctr($jump_target$$Register); 11991 __ bctr(); 11992 %} 11993 ins_pipe(pipe_class_call); 11994%} 11995 11996// Create exception oop: created by stack-crawling runtime code. 11997// Created exception is now available to this handler, and is setup 11998// just prior to jumping to this handler. No code emitted. 11999instruct CreateException(rarg1RegP ex_oop) %{ 12000 match(Set ex_oop (CreateEx)); 12001 ins_cost(0); 12002 12003 format %{ " -- \t// exception oop; no code emitted" %} 12004 size(0); 12005 ins_encode( /*empty*/ ); 12006 ins_pipe(pipe_class_default); 12007%} 12008 12009// Rethrow exception: The exception oop will come in the first 12010// argument position. Then JUMP (not call) to the rethrow stub code. 12011instruct RethrowException() %{ 12012 match(Rethrow); 12013 ins_cost(CALL_COST); 12014 12015 format %{ "Jmp rethrow_stub" %} 12016 ins_encode %{ 12017 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 12018 cbuf.set_insts_mark(); 12019 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type); 12020 %} 12021 ins_pipe(pipe_class_call); 12022%} 12023 12024// Die now. 12025instruct ShouldNotReachHere() %{ 12026 match(Halt); 12027 ins_cost(CALL_COST); 12028 12029 format %{ "ShouldNotReachHere" %} 12030 size(4); 12031 ins_encode %{ 12032 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 12033 __ trap_should_not_reach_here(); 12034 %} 12035 ins_pipe(pipe_class_default); 12036%} 12037 12038// This name is KNOWN by the ADLC and cannot be changed. The ADLC 12039// forces a 'TypeRawPtr::BOTTOM' output type for this guy. 12040// Get a DEF on threadRegP, no costs, no encoding, use 12041// 'ins_should_rematerialize(true)' to avoid spilling. 12042instruct tlsLoadP(threadRegP dst) %{ 12043 match(Set dst (ThreadLocal)); 12044 ins_cost(0); 12045 12046 ins_should_rematerialize(true); 12047 12048 format %{ " -- \t// $dst=Thread::current(), empty" %} 12049 size(0); 12050 ins_encode( /*empty*/ ); 12051 ins_pipe(pipe_class_empty); 12052%} 12053 12054//---Some PPC specific nodes--------------------------------------------------- 12055 12056// Stop a group. 12057instruct endGroup() %{ 12058 ins_cost(0); 12059 12060 ins_is_nop(true); 12061 12062 format %{ "End Bundle (ori r1, r1, 0)" %} 12063 size(4); 12064 ins_encode %{ 12065 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup); 12066 __ endgroup(); 12067 %} 12068 ins_pipe(pipe_class_default); 12069%} 12070 12071// Nop instructions 12072 12073instruct fxNop() %{ 12074 ins_cost(0); 12075 12076 ins_is_nop(true); 12077 12078 format %{ "fxNop" %} 12079 size(4); 12080 ins_encode %{ 12081 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12082 __ nop(); 12083 %} 12084 ins_pipe(pipe_class_default); 12085%} 12086 12087instruct fpNop0() %{ 12088 ins_cost(0); 12089 12090 ins_is_nop(true); 12091 12092 format %{ "fpNop0" %} 12093 size(4); 12094 ins_encode %{ 12095 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12096 __ fpnop0(); 12097 %} 12098 ins_pipe(pipe_class_default); 12099%} 12100 12101instruct fpNop1() %{ 12102 ins_cost(0); 12103 12104 ins_is_nop(true); 12105 12106 format %{ "fpNop1" %} 12107 size(4); 12108 ins_encode %{ 12109 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12110 __ fpnop1(); 12111 %} 12112 ins_pipe(pipe_class_default); 12113%} 12114 12115instruct brNop0() %{ 12116 ins_cost(0); 12117 size(4); 12118 format %{ "brNop0" %} 12119 ins_encode %{ 12120 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12121 __ brnop0(); 12122 %} 12123 ins_is_nop(true); 12124 ins_pipe(pipe_class_default); 12125%} 12126 12127instruct brNop1() %{ 12128 ins_cost(0); 12129 12130 ins_is_nop(true); 12131 12132 format %{ "brNop1" %} 12133 size(4); 12134 ins_encode %{ 12135 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12136 __ brnop1(); 12137 %} 12138 ins_pipe(pipe_class_default); 12139%} 12140 12141instruct brNop2() %{ 12142 ins_cost(0); 12143 12144 ins_is_nop(true); 12145 12146 format %{ "brNop2" %} 12147 size(4); 12148 ins_encode %{ 12149 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12150 __ brnop2(); 12151 %} 12152 ins_pipe(pipe_class_default); 12153%} 12154 12155//----------PEEPHOLE RULES----------------------------------------------------- 12156// These must follow all instruction definitions as they use the names 12157// defined in the instructions definitions. 12158// 12159// peepmatch ( root_instr_name [preceeding_instruction]* ); 12160// 12161// peepconstraint %{ 12162// (instruction_number.operand_name relational_op instruction_number.operand_name 12163// [, ...] ); 12164// // instruction numbers are zero-based using left to right order in peepmatch 12165// 12166// peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 12167// // provide an instruction_number.operand_name for each operand that appears 12168// // in the replacement instruction's match rule 12169// 12170// ---------VM FLAGS--------------------------------------------------------- 12171// 12172// All peephole optimizations can be turned off using -XX:-OptoPeephole 12173// 12174// Each peephole rule is given an identifying number starting with zero and 12175// increasing by one in the order seen by the parser. An individual peephole 12176// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 12177// on the command-line. 12178// 12179// ---------CURRENT LIMITATIONS---------------------------------------------- 12180// 12181// Only match adjacent instructions in same basic block 12182// Only equality constraints 12183// Only constraints between operands, not (0.dest_reg == EAX_enc) 12184// Only one replacement instruction 12185// 12186// ---------EXAMPLE---------------------------------------------------------- 12187// 12188// // pertinent parts of existing instructions in architecture description 12189// instruct movI(eRegI dst, eRegI src) %{ 12190// match(Set dst (CopyI src)); 12191// %} 12192// 12193// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 12194// match(Set dst (AddI dst src)); 12195// effect(KILL cr); 12196// %} 12197// 12198// // Change (inc mov) to lea 12199// peephole %{ 12200// // increment preceeded by register-register move 12201// peepmatch ( incI_eReg movI ); 12202// // require that the destination register of the increment 12203// // match the destination register of the move 12204// peepconstraint ( 0.dst == 1.dst ); 12205// // construct a replacement instruction that sets 12206// // the destination to ( move's source register + one ) 12207// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12208// %} 12209// 12210// Implementation no longer uses movX instructions since 12211// machine-independent system no longer uses CopyX nodes. 12212// 12213// peephole %{ 12214// peepmatch ( incI_eReg movI ); 12215// peepconstraint ( 0.dst == 1.dst ); 12216// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12217// %} 12218// 12219// peephole %{ 12220// peepmatch ( decI_eReg movI ); 12221// peepconstraint ( 0.dst == 1.dst ); 12222// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12223// %} 12224// 12225// peephole %{ 12226// peepmatch ( addI_eReg_imm movI ); 12227// peepconstraint ( 0.dst == 1.dst ); 12228// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12229// %} 12230// 12231// peephole %{ 12232// peepmatch ( addP_eReg_imm movP ); 12233// peepconstraint ( 0.dst == 1.dst ); 12234// peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); 12235// %} 12236 12237// // Change load of spilled value to only a spill 12238// instruct storeI(memory mem, eRegI src) %{ 12239// match(Set mem (StoreI mem src)); 12240// %} 12241// 12242// instruct loadI(eRegI dst, memory mem) %{ 12243// match(Set dst (LoadI mem)); 12244// %} 12245// 12246peephole %{ 12247 peepmatch ( loadI storeI ); 12248 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12249 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 12250%} 12251 12252peephole %{ 12253 peepmatch ( loadL storeL ); 12254 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12255 peepreplace ( storeL( 1.mem 1.mem 1.src ) ); 12256%} 12257 12258peephole %{ 12259 peepmatch ( loadP storeP ); 12260 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem ); 12261 peepreplace ( storeP( 1.dst 1.dst 1.src ) ); 12262%} 12263 12264//----------SMARTSPILL RULES--------------------------------------------------- 12265// These must follow all instruction definitions as they use the names 12266// defined in the instructions definitions. 12267