reg_split.cpp revision 3602:da91efe96a93
160107Sobrien/* 22786Ssos * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. 32786Ssos * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 42786Ssos * 52786Ssos * This code is free software; you can redistribute it and/or modify it 62786Ssos * under the terms of the GNU General Public License version 2 only, as 72786Ssos * published by the Free Software Foundation. 82786Ssos * 92786Ssos * This code is distributed in the hope that it will be useful, but WITHOUT 102786Ssos * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 112786Ssos * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 122786Ssos * version 2 for more details (a copy is included in the LICENSE file that 132786Ssos * accompanied this code). 142786Ssos * 152786Ssos * You should have received a copy of the GNU General Public License version 162786Ssos * 2 along with this work; if not, write to the Free Software Foundation, 172786Ssos * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 1838140Syokota * 192786Ssos * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 206867Sache * or visit www.oracle.com if you need additional information or have any 214686Sache * questions. 222786Ssos * 232786Ssos */ 242786Ssos 252786Ssos#include "precompiled.hpp" 262786Ssos#include "libadt/vectset.hpp" 272786Ssos#include "memory/allocation.inline.hpp" 282786Ssos#include "opto/addnode.hpp" 292786Ssos#include "opto/c2compiler.hpp" 302786Ssos#include "opto/callnode.hpp" 312786Ssos#include "opto/cfgnode.hpp" 322786Ssos#include "opto/chaitin.hpp" 332786Ssos#include "opto/loopnode.hpp" 342786Ssos#include "opto/machnode.hpp" 352786Ssos 362786Ssos//------------------------------Split-------------------------------------- 372786Ssos// Walk the graph in RPO and for each lrg which spills, propagate reaching 382786Ssos// definitions. During propagation, split the live range around regions of 392786Ssos// High Register Pressure (HRP). If a Def is in a region of Low Register 402786Ssos// Pressure (LRP), it will not get spilled until we encounter a region of 412786Ssos// HRP between it and one of its uses. We will spill at the transition 422786Ssos// point between LRP and HRP. Uses in the HRP region will use the spilled 432786Ssos// Def. The first Use outside the HRP region will generate a SpillCopy to 442786Ssos// hoist the live range back up into a register, and all subsequent uses 452786Ssos// will use that new Def until another HRP region is encountered. Defs in 462786Ssos// HRP regions will get trailing SpillCopies to push the LRG down into the 472786Ssos// stack immediately. 482786Ssos// 492786Ssos// As a side effect, unlink from (hence make dead) coalesced copies. 502786Ssos// 512786Ssos 522786Ssosstatic const char out_of_nodes[] = "out of nodes during split"; 532786Ssos 542786Ssos//------------------------------get_spillcopy_wide----------------------------- 552786Ssos// Get a SpillCopy node with wide-enough masks. Use the 'wide-mask', the 562786Ssos// wide ideal-register spill-mask if possible. If the 'wide-mask' does 572786Ssos// not cover the input (or output), use the input (or output) mask instead. 582786SsosNode *PhaseChaitin::get_spillcopy_wide( Node *def, Node *use, uint uidx ) { 592786Ssos // If ideal reg doesn't exist we've got a bad schedule happening 602786Ssos // that is forcing us to spill something that isn't spillable. 612786Ssos // Bail rather than abort 622786Ssos int ireg = def->ideal_reg(); 6332848Syokota if( ireg == 0 || ireg == Op_RegFlags ) { 642786Ssos assert(false, "attempted to spill a non-spillable item"); 652786Ssos C->record_method_not_compilable("attempted to spill a non-spillable item"); 662786Ssos return NULL; 672786Ssos } 682786Ssos if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { 692786Ssos return NULL; 702786Ssos } 712786Ssos const RegMask *i_mask = &def->out_RegMask(); 722786Ssos const RegMask *w_mask = C->matcher()->idealreg2spillmask[ireg]; 732786Ssos const RegMask *o_mask = use ? &use->in_RegMask(uidx) : w_mask; 742786Ssos const RegMask *w_i_mask = w_mask->overlap( *i_mask ) ? w_mask : i_mask; 752786Ssos const RegMask *w_o_mask; 762786Ssos 772786Ssos int num_regs = RegMask::num_registers(ireg); 782786Ssos bool is_vect = RegMask::is_vector(ireg); 792786Ssos if( w_mask->overlap( *o_mask ) && // Overlap AND 802786Ssos ((num_regs == 1) // Single use or aligned 812786Ssos || is_vect // or vector 825994Ssos || !is_vect && o_mask->is_aligned_pairs()) ) { 832786Ssos assert(!is_vect || o_mask->is_aligned_sets(num_regs), "vectors are aligned"); 842786Ssos // Don't come here for mis-aligned doubles 852786Ssos w_o_mask = w_mask; 862786Ssos } else { // wide ideal mask does not overlap with o_mask 872786Ssos // Mis-aligned doubles come here and XMM->FPR moves on x86. 882786Ssos w_o_mask = o_mask; // Must target desired registers 896869Sache // Does the ideal-reg-mask overlap with o_mask? I.e., can I use 902786Ssos // a reg-reg move or do I need a trip across register classes 912786Ssos // (and thus through memory)? 922786Ssos if( !C->matcher()->idealreg2regmask[ireg]->overlap( *o_mask) && o_mask->is_UP() ) 932786Ssos // Here we assume a trip through memory is required. 942786Ssos w_i_mask = &C->FIRST_STACK_mask(); 952786Ssos } 962786Ssos return new (C) MachSpillCopyNode( def, *w_i_mask, *w_o_mask ); 972786Ssos} 9874119Sache 992786Ssos//------------------------------insert_proj------------------------------------ 1002786Ssos// Insert the spill at chosen location. Skip over any intervening Proj's or 1012786Ssos// Phis. Skip over a CatchNode and projs, inserting in the fall-through block 1022786Ssos// instead. Update high-pressure indices. Create a new live range. 1032786Ssosvoid PhaseChaitin::insert_proj( Block *b, uint i, Node *spill, uint maxlrg ) { 1042786Ssos // Skip intervening ProjNodes. Do not insert between a ProjNode and 1052786Ssos // its definer. 1062786Ssos while( i < b->_nodes.size() && 1072786Ssos (b->_nodes[i]->is_Proj() || 10874119Sache b->_nodes[i]->is_Phi() ) ) 10975339Ssobomax i++; 11043334Syokota 11175339Ssobomax // Do not insert between a call and his Catch 11275339Ssobomax if( b->_nodes[i]->is_Catch() ) { 11375339Ssobomax // Put the instruction at the top of the fall-thru block. 1142786Ssos // Find the fall-thru projection 1152786Ssos while( 1 ) { 1162786Ssos const CatchProjNode *cp = b->_nodes[++i]->as_CatchProj(); 1172786Ssos if( cp->_con == CatchProjNode::fall_through_index ) 1182786Ssos break; 1192786Ssos } 1202786Ssos int sidx = i - b->end_idx()-1; 1212786Ssos b = b->_succs[sidx]; // Switch to successor block 1222786Ssos i = 1; // Right at start of block 1232786Ssos } 1242786Ssos 1252786Ssos b->_nodes.insert(i,spill); // Insert node in block 1262786Ssos _cfg._bbs.map(spill->_idx,b); // Update node->block mapping to reflect 1272786Ssos // Adjust the point where we go hi-pressure 1282786Ssos if( i <= b->_ihrp_index ) b->_ihrp_index++; 1292786Ssos if( i <= b->_fhrp_index ) b->_fhrp_index++; 1302786Ssos 1312786Ssos // Assign a new Live Range Number to the SpillCopy and grow 1322786Ssos // the node->live range mapping. 1332786Ssos new_lrg(spill,maxlrg); 1342786Ssos} 1352786Ssos 1362786Ssos//------------------------------split_DEF-------------------------------------- 1372786Ssos// There are four categories of Split; UP/DOWN x DEF/USE 1382786Ssos// Only three of these really occur as DOWN/USE will always color 13913631Sache// Any Split with a DEF cannot CISC-Spill now. Thus we need 1402786Ssos// two helper routines, one for Split DEFS (insert after instruction), 1412786Ssos// one for Split USES (insert before instruction). DEF insertion 1422786Ssos// happens inside Split, where the Leaveblock array is updated. 14313631Sacheuint PhaseChaitin::split_DEF( Node *def, Block *b, int loc, uint maxlrg, Node **Reachblock, Node **debug_defs, GrowableArray<uint> splits, int slidx ) { 1442786Ssos#ifdef ASSERT 1452786Ssos // Increment the counter for this lrg 14638140Syokota splits.at_put(slidx, splits.at(slidx)+1); 1472786Ssos#endif 1486867Sache // If we are spilling the memory op for an implicit null check, at the 1494686Sache // null check location (ie - null check is in HRP block) we need to do 1502786Ssos // the null-check first, then spill-down in the following block. 1512786Ssos // (The implicit_null_check function ensures the use is also dominated 1522786Ssos // by the branch-not-taken block.) 1532786Ssos Node *be = b->end(); 1542786Ssos if( be->is_MachNullCheck() && be->in(1) == def && def == b->_nodes[loc] ) { 1552786Ssos // Spill goes in the branch-not-taken block 1562786Ssos b = b->_succs[b->_nodes[b->end_idx()+1]->Opcode() == Op_IfTrue]; 1572786Ssos loc = 0; // Just past the Region 1582786Ssos } 1592786Ssos assert( loc >= 0, "must insert past block head" ); 1602786Ssos 1612786Ssos // Get a def-side SpillCopy 1622786Ssos Node *spill = get_spillcopy_wide(def,NULL,0); 1632786Ssos // Did we fail to split?, then bail 1642786Ssos if (!spill) { 1652786Ssos return 0; 1662786Ssos } 1672786Ssos 1682786Ssos // Insert the spill at chosen location 1692786Ssos insert_proj( b, loc+1, spill, maxlrg++); 1702786Ssos 1712786Ssos // Insert new node into Reaches array 1722786Ssos Reachblock[slidx] = spill; 1732786Ssos // Update debug list of reaching down definitions by adding this one 1742786Ssos debug_defs[slidx] = spill; 1752786Ssos 1762786Ssos // return updated count of live ranges 1772786Ssos return maxlrg; 1782786Ssos} 1792786Ssos 1802786Ssos//------------------------------split_USE-------------------------------------- 1812786Ssos// Splits at uses can involve redeffing the LRG, so no CISC Spilling there. 1822786Ssos// Debug uses want to know if def is already stack enabled. 1832786Ssosuint PhaseChaitin::split_USE( Node *def, Block *b, Node *use, uint useidx, uint maxlrg, bool def_down, bool cisc_sp, GrowableArray<uint> splits, int slidx ) { 1842786Ssos#ifdef ASSERT 1852786Ssos // Increment the counter for this lrg 1862786Ssos splits.at_put(slidx, splits.at(slidx)+1); 1872786Ssos#endif 1882786Ssos 1892786Ssos // Some setup stuff for handling debug node uses 1902786Ssos JVMState* jvms = use->jvms(); 1916851Ssos uint debug_start = jvms ? jvms->debug_start() : 999999; 1922786Ssos uint debug_end = jvms ? jvms->debug_end() : 999999; 1932786Ssos 1942786Ssos //------------------------------------------- 1952786Ssos // Check for use of debug info 1962786Ssos if (useidx >= debug_start && useidx < debug_end) { 1972786Ssos // Actually it's perfectly legal for constant debug info to appear 1982786Ssos // just unlikely. In this case the optimizer left a ConI of a 4 1992786Ssos // as both inputs to a Phi with only a debug use. It's a single-def 2002786Ssos // live range of a rematerializable value. The live range spills, 2012786Ssos // rematerializes and now the ConI directly feeds into the debug info. 2022786Ssos // assert(!def->is_Con(), "constant debug info already constructed directly"); 2032786Ssos 2042786Ssos // Special split handling for Debug Info 2052786Ssos // If DEF is DOWN, just hook the edge and return 2062786Ssos // If DEF is UP, Split it DOWN for this USE. 2072786Ssos if( def->is_Mach() ) { 2082786Ssos if( def_down ) { 2092786Ssos // DEF is DOWN, so connect USE directly to the DEF 2105994Ssos use->set_req(useidx, def); 2112786Ssos } else { 2122786Ssos // Block and index where the use occurs. 2132786Ssos Block *b = _cfg._bbs[use->_idx]; 2142786Ssos // Put the clone just prior to use 2152786Ssos int bindex = b->find_node(use); 2162786Ssos // DEF is UP, so must copy it DOWN and hook in USE 2176869Sache // Insert SpillCopy before the USE, which uses DEF as its input, 2182786Ssos // and defs a new live range, which is used by this node. 2192786Ssos Node *spill = get_spillcopy_wide(def,use,useidx); 2202786Ssos // did we fail to split? 2212786Ssos if (!spill) { 2222786Ssos // Bail 2232786Ssos return 0; 2242786Ssos } 2252786Ssos // insert into basic block 22674119Sache insert_proj( b, bindex, spill, maxlrg++ ); 2272786Ssos // Use the new split 2282786Ssos use->set_req(useidx,spill); 2292786Ssos } 2302786Ssos // No further split handling needed for this use 2312786Ssos return maxlrg; 2322786Ssos } // End special splitting for debug info live range 2332786Ssos } // If debug info 2342786Ssos 2352786Ssos // CISC-SPILLING 23674119Sache // Finally, check to see if USE is CISC-Spillable, and if so, 23775339Ssobomax // gather_lrg_masks will add the flags bit to its mask, and 23843334Syokota // no use side copy is needed. This frees up the live range 23975339Ssobomax // register choices without causing copy coalescing, etc. 24075339Ssobomax if( UseCISCSpill && cisc_sp ) { 24175339Ssobomax int inp = use->cisc_operand(); 24243334Syokota if( inp != AdlcVMDeps::Not_cisc_spillable ) 243 // Convert operand number to edge index number 244 inp = use->as_Mach()->operand_index(inp); 245 if( inp == (int)useidx ) { 246 use->set_req(useidx, def); 247#ifndef PRODUCT 248 if( TraceCISCSpill ) { 249 tty->print(" set_split: "); 250 use->dump(); 251 } 252#endif 253 return maxlrg; 254 } 255 } 256 257 //------------------------------------------- 258 // Insert a Copy before the use 259 260 // Block and index where the use occurs. 261 int bindex; 262 // Phi input spill-copys belong at the end of the prior block 263 if( use->is_Phi() ) { 264 b = _cfg._bbs[b->pred(useidx)->_idx]; 265 bindex = b->end_idx(); 266 } else { 267 // Put the clone just prior to use 268 bindex = b->find_node(use); 269 } 270 271 Node *spill = get_spillcopy_wide( def, use, useidx ); 272 if( !spill ) return 0; // Bailed out 273 // Insert SpillCopy before the USE, which uses the reaching DEF as 274 // its input, and defs a new live range, which is used by this node. 275 insert_proj( b, bindex, spill, maxlrg++ ); 276 // Use the spill/clone 277 use->set_req(useidx,spill); 278 279 // return updated live range count 280 return maxlrg; 281} 282 283//------------------------------clone_node---------------------------- 284// Clone node with anti dependence check. 285Node* clone_node(Node* def, Block *b, Compile* C) { 286 if (def->needs_anti_dependence_check()) { 287#ifdef ASSERT 288 if (Verbose) { 289 tty->print_cr("RA attempts to clone node with anti_dependence:"); 290 def->dump(-1); tty->cr(); 291 tty->print_cr("into block:"); 292 b->dump(); 293 } 294#endif 295 if (C->subsume_loads() == true && !C->failing()) { 296 // Retry with subsume_loads == false 297 // If this is the first failure, the sentinel string will "stick" 298 // to the Compile object, and the C2Compiler will see it and retry. 299 C->record_failure(C2Compiler::retry_no_subsuming_loads()); 300 } else { 301 // Bailout without retry 302 C->record_method_not_compilable("RA Split failed: attempt to clone node with anti_dependence"); 303 } 304 return 0; 305 } 306 return def->clone(); 307} 308 309//------------------------------split_Rematerialize---------------------------- 310// Clone a local copy of the def. 311Node *PhaseChaitin::split_Rematerialize( Node *def, Block *b, uint insidx, uint &maxlrg, GrowableArray<uint> splits, int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru ) { 312 // The input live ranges will be stretched to the site of the new 313 // instruction. They might be stretched past a def and will thus 314 // have the old and new values of the same live range alive at the 315 // same time - a definite no-no. Split out private copies of 316 // the inputs. 317 if( def->req() > 1 ) { 318 for( uint i = 1; i < def->req(); i++ ) { 319 Node *in = def->in(i); 320 // Check for single-def (LRG cannot redefined) 321 uint lidx = n2lidx(in); 322 if( lidx >= _maxlrg ) continue; // Value is a recent spill-copy 323 if (lrgs(lidx).is_singledef()) continue; 324 325 Block *b_def = _cfg._bbs[def->_idx]; 326 int idx_def = b_def->find_node(def); 327 Node *in_spill = get_spillcopy_wide( in, def, i ); 328 if( !in_spill ) return 0; // Bailed out 329 insert_proj(b_def,idx_def,in_spill,maxlrg++); 330 if( b_def == b ) 331 insidx++; 332 def->set_req(i,in_spill); 333 } 334 } 335 336 Node *spill = clone_node(def, b, C); 337 if (spill == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { 338 // Check when generating nodes 339 return 0; 340 } 341 342 // See if any inputs are currently being spilled, and take the 343 // latest copy of spilled inputs. 344 if( spill->req() > 1 ) { 345 for( uint i = 1; i < spill->req(); i++ ) { 346 Node *in = spill->in(i); 347 uint lidx = Find_id(in); 348 349 // Walk backwards thru spill copy node intermediates 350 if (walkThru) { 351 while ( in->is_SpillCopy() && lidx >= _maxlrg ) { 352 in = in->in(1); 353 lidx = Find_id(in); 354 } 355 356 if (lidx < _maxlrg && lrgs(lidx).is_multidef()) { 357 // walkThru found a multidef LRG, which is unsafe to use, so 358 // just keep the original def used in the clone. 359 in = spill->in(i); 360 lidx = Find_id(in); 361 } 362 } 363 364 if( lidx < _maxlrg && lrgs(lidx).reg() >= LRG::SPILL_REG ) { 365 Node *rdef = Reachblock[lrg2reach[lidx]]; 366 if( rdef ) spill->set_req(i,rdef); 367 } 368 } 369 } 370 371 372 assert( spill->out_RegMask().is_UP(), "rematerialize to a reg" ); 373 // Rematerialized op is def->spilled+1 374 set_was_spilled(spill); 375 if( _spilled_once.test(def->_idx) ) 376 set_was_spilled(spill); 377 378 insert_proj( b, insidx, spill, maxlrg++ ); 379#ifdef ASSERT 380 // Increment the counter for this lrg 381 splits.at_put(slidx, splits.at(slidx)+1); 382#endif 383 // See if the cloned def kills any flags, and copy those kills as well 384 uint i = insidx+1; 385 if( clone_projs( b, i, def, spill, maxlrg ) ) { 386 // Adjust the point where we go hi-pressure 387 if( i <= b->_ihrp_index ) b->_ihrp_index++; 388 if( i <= b->_fhrp_index ) b->_fhrp_index++; 389 } 390 391 return spill; 392} 393 394//------------------------------is_high_pressure------------------------------- 395// Function to compute whether or not this live range is "high pressure" 396// in this block - whether it spills eagerly or not. 397bool PhaseChaitin::is_high_pressure( Block *b, LRG *lrg, uint insidx ) { 398 if( lrg->_was_spilled1 ) return true; 399 // Forced spilling due to conflict? Then split only at binding uses 400 // or defs, not for supposed capacity problems. 401 // CNC - Turned off 7/8/99, causes too much spilling 402 // if( lrg->_is_bound ) return false; 403 404 // Use float pressure numbers for vectors. 405 bool is_float_or_vector = lrg->_is_float || lrg->_is_vector; 406 // Not yet reached the high-pressure cutoff point, so low pressure 407 uint hrp_idx = is_float_or_vector ? b->_fhrp_index : b->_ihrp_index; 408 if( insidx < hrp_idx ) return false; 409 // Register pressure for the block as a whole depends on reg class 410 int block_pres = is_float_or_vector ? b->_freg_pressure : b->_reg_pressure; 411 // Bound live ranges will split at the binding points first; 412 // Intermediate splits should assume the live range's register set 413 // got "freed up" and that num_regs will become INT_PRESSURE. 414 int bound_pres = is_float_or_vector ? FLOATPRESSURE : INTPRESSURE; 415 // Effective register pressure limit. 416 int lrg_pres = (lrg->get_invalid_mask_size() > lrg->num_regs()) 417 ? (lrg->get_invalid_mask_size() >> (lrg->num_regs()-1)) : bound_pres; 418 // High pressure if block pressure requires more register freedom 419 // than live range has. 420 return block_pres >= lrg_pres; 421} 422 423 424//------------------------------prompt_use--------------------------------- 425// True if lidx is used before any real register is def'd in the block 426bool PhaseChaitin::prompt_use( Block *b, uint lidx ) { 427 if( lrgs(lidx)._was_spilled2 ) return false; 428 429 // Scan block for 1st use. 430 for( uint i = 1; i <= b->end_idx(); i++ ) { 431 Node *n = b->_nodes[i]; 432 // Ignore PHI use, these can be up or down 433 if( n->is_Phi() ) continue; 434 for( uint j = 1; j < n->req(); j++ ) 435 if( Find_id(n->in(j)) == lidx ) 436 return true; // Found 1st use! 437 if( n->out_RegMask().is_NotEmpty() ) return false; 438 } 439 return false; 440} 441 442//------------------------------Split-------------------------------------- 443//----------Split Routine---------- 444// ***** NEW SPLITTING HEURISTIC ***** 445// DEFS: If the DEF is in a High Register Pressure(HRP) Block, split there. 446// Else, no split unless there is a HRP block between a DEF and 447// one of its uses, and then split at the HRP block. 448// 449// USES: If USE is in HRP, split at use to leave main LRG on stack. 450// Else, hoist LRG back up to register only (ie - split is also DEF) 451// We will compute a new maxlrg as we go 452uint PhaseChaitin::Split(uint maxlrg, ResourceArea* split_arena) { 453 NOT_PRODUCT( Compile::TracePhase t3("regAllocSplit", &_t_regAllocSplit, TimeCompiler); ) 454 455 // Free thread local resources used by this method on exit. 456 ResourceMark rm(split_arena); 457 458 uint bidx, pidx, slidx, insidx, inpidx, twoidx; 459 uint non_phi = 1, spill_cnt = 0; 460 Node **Reachblock; 461 Node *n1, *n2, *n3; 462 Node_List *defs,*phis; 463 bool *UPblock; 464 bool u1, u2, u3; 465 Block *b, *pred; 466 PhiNode *phi; 467 GrowableArray<uint> lidxs(split_arena, _maxlrg, 0, 0); 468 469 // Array of counters to count splits per live range 470 GrowableArray<uint> splits(split_arena, _maxlrg, 0, 0); 471 472#define NEW_SPLIT_ARRAY(type, size)\ 473 (type*) split_arena->allocate_bytes((size) * sizeof(type)) 474 475 //----------Setup Code---------- 476 // Create a convenient mapping from lrg numbers to reaches/leaves indices 477 uint *lrg2reach = NEW_SPLIT_ARRAY( uint, _maxlrg ); 478 // Keep track of DEFS & Phis for later passes 479 defs = new Node_List(); 480 phis = new Node_List(); 481 // Gather info on which LRG's are spilling, and build maps 482 for( bidx = 1; bidx < _maxlrg; bidx++ ) { 483 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) { 484 assert(!lrgs(bidx).mask().is_AllStack(),"AllStack should color"); 485 lrg2reach[bidx] = spill_cnt; 486 spill_cnt++; 487 lidxs.append(bidx); 488#ifdef ASSERT 489 // Initialize the split counts to zero 490 splits.append(0); 491#endif 492#ifndef PRODUCT 493 if( PrintOpto && WizardMode && lrgs(bidx)._was_spilled1 ) 494 tty->print_cr("Warning, 2nd spill of L%d",bidx); 495#endif 496 } 497 } 498 499 // Create side arrays for propagating reaching defs info. 500 // Each block needs a node pointer for each spilling live range for the 501 // Def which is live into the block. Phi nodes handle multiple input 502 // Defs by querying the output of their predecessor blocks and resolving 503 // them to a single Def at the phi. The pointer is updated for each 504 // Def in the block, and then becomes the output for the block when 505 // processing of the block is complete. We also need to track whether 506 // a Def is UP or DOWN. UP means that it should get a register (ie - 507 // it is always in LRP regions), and DOWN means that it is probably 508 // on the stack (ie - it crosses HRP regions). 509 Node ***Reaches = NEW_SPLIT_ARRAY( Node**, _cfg._num_blocks+1 ); 510 bool **UP = NEW_SPLIT_ARRAY( bool*, _cfg._num_blocks+1 ); 511 Node **debug_defs = NEW_SPLIT_ARRAY( Node*, spill_cnt ); 512 VectorSet **UP_entry= NEW_SPLIT_ARRAY( VectorSet*, spill_cnt ); 513 514 // Initialize Reaches & UP 515 for( bidx = 0; bidx < _cfg._num_blocks+1; bidx++ ) { 516 Reaches[bidx] = NEW_SPLIT_ARRAY( Node*, spill_cnt ); 517 UP[bidx] = NEW_SPLIT_ARRAY( bool, spill_cnt ); 518 Node **Reachblock = Reaches[bidx]; 519 bool *UPblock = UP[bidx]; 520 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 521 UPblock[slidx] = true; // Assume they start in registers 522 Reachblock[slidx] = NULL; // Assume that no def is present 523 } 524 } 525 526#undef NEW_SPLIT_ARRAY 527 528 // Initialize to array of empty vectorsets 529 for( slidx = 0; slidx < spill_cnt; slidx++ ) 530 UP_entry[slidx] = new VectorSet(split_arena); 531 532 //----------PASS 1---------- 533 //----------Propagation & Node Insertion Code---------- 534 // Walk the Blocks in RPO for DEF & USE info 535 for( bidx = 0; bidx < _cfg._num_blocks; bidx++ ) { 536 537 if (C->check_node_count(spill_cnt, out_of_nodes)) { 538 return 0; 539 } 540 541 b = _cfg._blocks[bidx]; 542 // Reaches & UP arrays for this block 543 Reachblock = Reaches[b->_pre_order]; 544 UPblock = UP[b->_pre_order]; 545 // Reset counter of start of non-Phi nodes in block 546 non_phi = 1; 547 //----------Block Entry Handling---------- 548 // Check for need to insert a new phi 549 // Cycle through this block's predecessors, collecting Reaches 550 // info for each spilled LRG. If they are identical, no phi is 551 // needed. If they differ, check for a phi, and insert if missing, 552 // or update edges if present. Set current block's Reaches set to 553 // be either the phi's or the reaching def, as appropriate. 554 // If no Phi is needed, check if the LRG needs to spill on entry 555 // to the block due to HRP. 556 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 557 // Grab the live range number 558 uint lidx = lidxs.at(slidx); 559 // Do not bother splitting or putting in Phis for single-def 560 // rematerialized live ranges. This happens alot to constants 561 // with long live ranges. 562 if( lrgs(lidx).is_singledef() && 563 lrgs(lidx)._def->rematerialize() ) { 564 // reset the Reaches & UP entries 565 Reachblock[slidx] = lrgs(lidx)._def; 566 UPblock[slidx] = true; 567 // Record following instruction in case 'n' rematerializes and 568 // kills flags 569 Block *pred1 = _cfg._bbs[b->pred(1)->_idx]; 570 continue; 571 } 572 573 // Initialize needs_phi and needs_split 574 bool needs_phi = false; 575 bool needs_split = false; 576 bool has_phi = false; 577 // Walk the predecessor blocks to check inputs for that live range 578 // Grab predecessor block header 579 n1 = b->pred(1); 580 // Grab the appropriate reaching def info for inpidx 581 pred = _cfg._bbs[n1->_idx]; 582 pidx = pred->_pre_order; 583 Node **Ltmp = Reaches[pidx]; 584 bool *Utmp = UP[pidx]; 585 n1 = Ltmp[slidx]; 586 u1 = Utmp[slidx]; 587 // Initialize node for saving type info 588 n3 = n1; 589 u3 = u1; 590 591 // Compare inputs to see if a Phi is needed 592 for( inpidx = 2; inpidx < b->num_preds(); inpidx++ ) { 593 // Grab predecessor block headers 594 n2 = b->pred(inpidx); 595 // Grab the appropriate reaching def info for inpidx 596 pred = _cfg._bbs[n2->_idx]; 597 pidx = pred->_pre_order; 598 Ltmp = Reaches[pidx]; 599 Utmp = UP[pidx]; 600 n2 = Ltmp[slidx]; 601 u2 = Utmp[slidx]; 602 // For each LRG, decide if a phi is necessary 603 if( n1 != n2 ) { 604 needs_phi = true; 605 } 606 // See if the phi has mismatched inputs, UP vs. DOWN 607 if( n1 && n2 && (u1 != u2) ) { 608 needs_split = true; 609 } 610 // Move n2/u2 to n1/u1 for next iteration 611 n1 = n2; 612 u1 = u2; 613 // Preserve a non-NULL predecessor for later type referencing 614 if( (n3 == NULL) && (n2 != NULL) ){ 615 n3 = n2; 616 u3 = u2; 617 } 618 } // End for all potential Phi inputs 619 620 // check block for appropriate phinode & update edges 621 for( insidx = 1; insidx <= b->end_idx(); insidx++ ) { 622 n1 = b->_nodes[insidx]; 623 // bail if this is not a phi 624 phi = n1->is_Phi() ? n1->as_Phi() : NULL; 625 if( phi == NULL ) { 626 // Keep track of index of first non-PhiNode instruction in block 627 non_phi = insidx; 628 // break out of the for loop as we have handled all phi nodes 629 break; 630 } 631 // must be looking at a phi 632 if( Find_id(n1) == lidxs.at(slidx) ) { 633 // found the necessary phi 634 needs_phi = false; 635 has_phi = true; 636 // initialize the Reaches entry for this LRG 637 Reachblock[slidx] = phi; 638 break; 639 } // end if found correct phi 640 } // end for all phi's 641 642 // If a phi is needed or exist, check for it 643 if( needs_phi || has_phi ) { 644 // add new phinode if one not already found 645 if( needs_phi ) { 646 // create a new phi node and insert it into the block 647 // type is taken from left over pointer to a predecessor 648 assert(n3,"No non-NULL reaching DEF for a Phi"); 649 phi = new (C, b->num_preds()) PhiNode(b->head(), n3->bottom_type()); 650 // initialize the Reaches entry for this LRG 651 Reachblock[slidx] = phi; 652 653 // add node to block & node_to_block mapping 654 insert_proj( b, insidx++, phi, maxlrg++ ); 655 non_phi++; 656 // Reset new phi's mapping to be the spilling live range 657 _names.map(phi->_idx, lidx); 658 assert(Find_id(phi) == lidx,"Bad update on Union-Find mapping"); 659 } // end if not found correct phi 660 // Here you have either found or created the Phi, so record it 661 assert(phi != NULL,"Must have a Phi Node here"); 662 phis->push(phi); 663 // PhiNodes should either force the LRG UP or DOWN depending 664 // on its inputs and the register pressure in the Phi's block. 665 UPblock[slidx] = true; // Assume new DEF is UP 666 // If entering a high-pressure area with no immediate use, 667 // assume Phi is DOWN 668 if( is_high_pressure( b, &lrgs(lidx), b->end_idx()) && !prompt_use(b,lidx) ) 669 UPblock[slidx] = false; 670 // If we are not split up/down and all inputs are down, then we 671 // are down 672 if( !needs_split && !u3 ) 673 UPblock[slidx] = false; 674 } // end if phi is needed 675 676 // Do not need a phi, so grab the reaching DEF 677 else { 678 // Grab predecessor block header 679 n1 = b->pred(1); 680 // Grab the appropriate reaching def info for k 681 pred = _cfg._bbs[n1->_idx]; 682 pidx = pred->_pre_order; 683 Node **Ltmp = Reaches[pidx]; 684 bool *Utmp = UP[pidx]; 685 // reset the Reaches & UP entries 686 Reachblock[slidx] = Ltmp[slidx]; 687 UPblock[slidx] = Utmp[slidx]; 688 } // end else no Phi is needed 689 } // end for all spilling live ranges 690 // DEBUG 691#ifndef PRODUCT 692 if(trace_spilling()) { 693 tty->print("/`\nBlock %d: ", b->_pre_order); 694 tty->print("Reaching Definitions after Phi handling\n"); 695 for( uint x = 0; x < spill_cnt; x++ ) { 696 tty->print("Spill Idx %d: UP %d: Node\n",x,UPblock[x]); 697 if( Reachblock[x] ) 698 Reachblock[x]->dump(); 699 else 700 tty->print("Undefined\n"); 701 } 702 } 703#endif 704 705 //----------Non-Phi Node Splitting---------- 706 // Since phi-nodes have now been handled, the Reachblock array for this 707 // block is initialized with the correct starting value for the defs which 708 // reach non-phi instructions in this block. Thus, process non-phi 709 // instructions normally, inserting SpillCopy nodes for all spill 710 // locations. 711 712 // Memoize any DOWN reaching definitions for use as DEBUG info 713 for( insidx = 0; insidx < spill_cnt; insidx++ ) { 714 debug_defs[insidx] = (UPblock[insidx]) ? NULL : Reachblock[insidx]; 715 if( UPblock[insidx] ) // Memoize UP decision at block start 716 UP_entry[insidx]->set( b->_pre_order ); 717 } 718 719 //----------Walk Instructions in the Block and Split---------- 720 // For all non-phi instructions in the block 721 for( insidx = 1; insidx <= b->end_idx(); insidx++ ) { 722 Node *n = b->_nodes[insidx]; 723 // Find the defining Node's live range index 724 uint defidx = Find_id(n); 725 uint cnt = n->req(); 726 727 if( n->is_Phi() ) { 728 // Skip phi nodes after removing dead copies. 729 if( defidx < _maxlrg ) { 730 // Check for useless Phis. These appear if we spill, then 731 // coalesce away copies. Dont touch Phis in spilling live 732 // ranges; they are busy getting modifed in this pass. 733 if( lrgs(defidx).reg() < LRG::SPILL_REG ) { 734 uint i; 735 Node *u = NULL; 736 // Look for the Phi merging 2 unique inputs 737 for( i = 1; i < cnt; i++ ) { 738 // Ignore repeats and self 739 if( n->in(i) != u && n->in(i) != n ) { 740 // Found a unique input 741 if( u != NULL ) // If it's the 2nd, bail out 742 break; 743 u = n->in(i); // Else record it 744 } 745 } 746 assert( u, "at least 1 valid input expected" ); 747 if( i >= cnt ) { // Found one unique input 748 assert(Find_id(n) == Find_id(u), "should be the same lrg"); 749 n->replace_by(u); // Then replace with unique input 750 n->disconnect_inputs(NULL); 751 b->_nodes.remove(insidx); 752 insidx--; 753 b->_ihrp_index--; 754 b->_fhrp_index--; 755 } 756 } 757 } 758 continue; 759 } 760 assert( insidx > b->_ihrp_index || 761 (b->_reg_pressure < (uint)INTPRESSURE) || 762 b->_ihrp_index > 4000000 || 763 b->_ihrp_index >= b->end_idx() || 764 !b->_nodes[b->_ihrp_index]->is_Proj(), "" ); 765 assert( insidx > b->_fhrp_index || 766 (b->_freg_pressure < (uint)FLOATPRESSURE) || 767 b->_fhrp_index > 4000000 || 768 b->_fhrp_index >= b->end_idx() || 769 !b->_nodes[b->_fhrp_index]->is_Proj(), "" ); 770 771 // ********** Handle Crossing HRP Boundry ********** 772 if( (insidx == b->_ihrp_index) || (insidx == b->_fhrp_index) ) { 773 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 774 // Check for need to split at HRP boundary - split if UP 775 n1 = Reachblock[slidx]; 776 // bail out if no reaching DEF 777 if( n1 == NULL ) continue; 778 // bail out if live range is 'isolated' around inner loop 779 uint lidx = lidxs.at(slidx); 780 // If live range is currently UP 781 if( UPblock[slidx] ) { 782 // set location to insert spills at 783 // SPLIT DOWN HERE - NO CISC SPILL 784 if( is_high_pressure( b, &lrgs(lidx), insidx ) && 785 !n1->rematerialize() ) { 786 // If there is already a valid stack definition available, use it 787 if( debug_defs[slidx] != NULL ) { 788 Reachblock[slidx] = debug_defs[slidx]; 789 } 790 else { 791 // Insert point is just past last use or def in the block 792 int insert_point = insidx-1; 793 while( insert_point > 0 ) { 794 Node *n = b->_nodes[insert_point]; 795 // Hit top of block? Quit going backwards 796 if( n->is_Phi() ) break; 797 // Found a def? Better split after it. 798 if( n2lidx(n) == lidx ) break; 799 // Look for a use 800 uint i; 801 for( i = 1; i < n->req(); i++ ) 802 if( n2lidx(n->in(i)) == lidx ) 803 break; 804 // Found a use? Better split after it. 805 if( i < n->req() ) break; 806 insert_point--; 807 } 808 uint orig_eidx = b->end_idx(); 809 maxlrg = split_DEF( n1, b, insert_point, maxlrg, Reachblock, debug_defs, splits, slidx); 810 // If it wasn't split bail 811 if (!maxlrg) { 812 return 0; 813 } 814 // Spill of NULL check mem op goes into the following block. 815 if (b->end_idx() > orig_eidx) 816 insidx++; 817 } 818 // This is a new DEF, so update UP 819 UPblock[slidx] = false; 820#ifndef PRODUCT 821 // DEBUG 822 if( trace_spilling() ) { 823 tty->print("\nNew Split DOWN DEF of Spill Idx "); 824 tty->print("%d, UP %d:\n",slidx,false); 825 n1->dump(); 826 } 827#endif 828 } 829 } // end if LRG is UP 830 } // end for all spilling live ranges 831 assert( b->_nodes[insidx] == n, "got insidx set incorrectly" ); 832 } // end if crossing HRP Boundry 833 834 // If the LRG index is oob, then this is a new spillcopy, skip it. 835 if( defidx >= _maxlrg ) { 836 continue; 837 } 838 LRG &deflrg = lrgs(defidx); 839 uint copyidx = n->is_Copy(); 840 // Remove coalesced copy from CFG 841 if( copyidx && defidx == n2lidx(n->in(copyidx)) ) { 842 n->replace_by( n->in(copyidx) ); 843 n->set_req( copyidx, NULL ); 844 b->_nodes.remove(insidx--); 845 b->_ihrp_index--; // Adjust the point where we go hi-pressure 846 b->_fhrp_index--; 847 continue; 848 } 849 850#define DERIVED 0 851 852 // ********** Handle USES ********** 853 bool nullcheck = false; 854 // Implicit null checks never use the spilled value 855 if( n->is_MachNullCheck() ) 856 nullcheck = true; 857 if( !nullcheck ) { 858 // Search all inputs for a Spill-USE 859 JVMState* jvms = n->jvms(); 860 uint oopoff = jvms ? jvms->oopoff() : cnt; 861 uint old_last = cnt - 1; 862 for( inpidx = 1; inpidx < cnt; inpidx++ ) { 863 // Derived/base pairs may be added to our inputs during this loop. 864 // If inpidx > old_last, then one of these new inputs is being 865 // handled. Skip the derived part of the pair, but process 866 // the base like any other input. 867 if( inpidx > old_last && ((inpidx - oopoff) & 1) == DERIVED ) { 868 continue; // skip derived_debug added below 869 } 870 // Get lidx of input 871 uint useidx = Find_id(n->in(inpidx)); 872 // Not a brand-new split, and it is a spill use 873 if( useidx < _maxlrg && lrgs(useidx).reg() >= LRG::SPILL_REG ) { 874 // Check for valid reaching DEF 875 slidx = lrg2reach[useidx]; 876 Node *def = Reachblock[slidx]; 877 assert( def != NULL, "Using Undefined Value in Split()\n"); 878 879 // (+++) %%%% remove this in favor of pre-pass in matcher.cpp 880 // monitor references do not care where they live, so just hook 881 if ( jvms && jvms->is_monitor_use(inpidx) ) { 882 // The effect of this clone is to drop the node out of the block, 883 // so that the allocator does not see it anymore, and therefore 884 // does not attempt to assign it a register. 885 def = clone_node(def, b, C); 886 if (def == NULL || C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { 887 return 0; 888 } 889 _names.extend(def->_idx,0); 890 _cfg._bbs.map(def->_idx,b); 891 n->set_req(inpidx, def); 892 continue; 893 } 894 895 // Rematerializable? Then clone def at use site instead 896 // of store/load 897 if( def->rematerialize() ) { 898 int old_size = b->_nodes.size(); 899 def = split_Rematerialize( def, b, insidx, maxlrg, splits, slidx, lrg2reach, Reachblock, true ); 900 if( !def ) return 0; // Bail out 901 insidx += b->_nodes.size()-old_size; 902 } 903 904 MachNode *mach = n->is_Mach() ? n->as_Mach() : NULL; 905 // Base pointers and oopmap references do not care where they live. 906 if ((inpidx >= oopoff) || 907 (mach && mach->ideal_Opcode() == Op_AddP && inpidx == AddPNode::Base)) { 908 if (def->rematerialize() && lrgs(useidx)._was_spilled2) { 909 // This def has been rematerialized a couple of times without 910 // progress. It doesn't care if it lives UP or DOWN, so 911 // spill it down now. 912 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false,splits,slidx); 913 // If it wasn't split bail 914 if (!maxlrg) { 915 return 0; 916 } 917 insidx++; // Reset iterator to skip USE side split 918 } else { 919 // Just hook the def edge 920 n->set_req(inpidx, def); 921 } 922 923 if (inpidx >= oopoff) { 924 // After oopoff, we have derived/base pairs. We must mention all 925 // derived pointers here as derived/base pairs for GC. If the 926 // derived value is spilling and we have a copy both in Reachblock 927 // (called here 'def') and debug_defs[slidx] we need to mention 928 // both in derived/base pairs or kill one. 929 Node *derived_debug = debug_defs[slidx]; 930 if( ((inpidx - oopoff) & 1) == DERIVED && // derived vs base? 931 mach && mach->ideal_Opcode() != Op_Halt && 932 derived_debug != NULL && 933 derived_debug != def ) { // Actual 2nd value appears 934 // We have already set 'def' as a derived value. 935 // Also set debug_defs[slidx] as a derived value. 936 uint k; 937 for( k = oopoff; k < cnt; k += 2 ) 938 if( n->in(k) == derived_debug ) 939 break; // Found an instance of debug derived 940 if( k == cnt ) {// No instance of debug_defs[slidx] 941 // Add a derived/base pair to cover the debug info. 942 // We have to process the added base later since it is not 943 // handled yet at this point but skip derived part. 944 assert(((n->req() - oopoff) & 1) == DERIVED, 945 "must match skip condition above"); 946 n->add_req( derived_debug ); // this will be skipped above 947 n->add_req( n->in(inpidx+1) ); // this will be processed 948 // Increment cnt to handle added input edges on 949 // subsequent iterations. 950 cnt += 2; 951 } 952 } 953 } 954 continue; 955 } 956 // Special logic for DEBUG info 957 if( jvms && b->_freq > BLOCK_FREQUENCY(0.5) ) { 958 uint debug_start = jvms->debug_start(); 959 // If this is debug info use & there is a reaching DOWN def 960 if ((debug_start <= inpidx) && (debug_defs[slidx] != NULL)) { 961 assert(inpidx < oopoff, "handle only debug info here"); 962 // Just hook it in & move on 963 n->set_req(inpidx, debug_defs[slidx]); 964 // (Note that this can make two sides of a split live at the 965 // same time: The debug def on stack, and another def in a 966 // register. The GC needs to know about both of them, but any 967 // derived pointers after oopoff will refer to only one of the 968 // two defs and the GC would therefore miss the other. Thus 969 // this hack is only allowed for debug info which is Java state 970 // and therefore never a derived pointer.) 971 continue; 972 } 973 } 974 // Grab register mask info 975 const RegMask &dmask = def->out_RegMask(); 976 const RegMask &umask = n->in_RegMask(inpidx); 977 bool is_vect = RegMask::is_vector(def->ideal_reg()); 978 assert(inpidx < oopoff, "cannot use-split oop map info"); 979 980 bool dup = UPblock[slidx]; 981 bool uup = umask.is_UP(); 982 983 // Need special logic to handle bound USES. Insert a split at this 984 // bound use if we can't rematerialize the def, or if we need the 985 // split to form a misaligned pair. 986 if( !umask.is_AllStack() && 987 (int)umask.Size() <= lrgs(useidx).num_regs() && 988 (!def->rematerialize() || 989 !is_vect && umask.is_misaligned_pair())) { 990 // These need a Split regardless of overlap or pressure 991 // SPLIT - NO DEF - NO CISC SPILL 992 maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx); 993 // If it wasn't split bail 994 if (!maxlrg) { 995 return 0; 996 } 997 insidx++; // Reset iterator to skip USE side split 998 continue; 999 } 1000 1001 if (UseFPUForSpilling && n->is_MachCall() && !uup && !dup ) { 1002 // The use at the call can force the def down so insert 1003 // a split before the use to allow the def more freedom. 1004 maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx); 1005 // If it wasn't split bail 1006 if (!maxlrg) { 1007 return 0; 1008 } 1009 insidx++; // Reset iterator to skip USE side split 1010 continue; 1011 } 1012 1013 // Here is the logic chart which describes USE Splitting: 1014 // 0 = false or DOWN, 1 = true or UP 1015 // 1016 // Overlap | DEF | USE | Action 1017 //------------------------------------------------------- 1018 // 0 | 0 | 0 | Copy - mem -> mem 1019 // 0 | 0 | 1 | Split-UP - Check HRP 1020 // 0 | 1 | 0 | Split-DOWN - Debug Info? 1021 // 0 | 1 | 1 | Copy - reg -> reg 1022 // 1 | 0 | 0 | Reset Input Edge (no Split) 1023 // 1 | 0 | 1 | Split-UP - Check HRP 1024 // 1 | 1 | 0 | Split-DOWN - Debug Info? 1025 // 1 | 1 | 1 | Reset Input Edge (no Split) 1026 // 1027 // So, if (dup == uup), then overlap test determines action, 1028 // with true being no split, and false being copy. Else, 1029 // if DEF is DOWN, Split-UP, and check HRP to decide on 1030 // resetting DEF. Finally if DEF is UP, Split-DOWN, with 1031 // special handling for Debug Info. 1032 if( dup == uup ) { 1033 if( dmask.overlap(umask) ) { 1034 // Both are either up or down, and there is overlap, No Split 1035 n->set_req(inpidx, def); 1036 } 1037 else { // Both are either up or down, and there is no overlap 1038 if( dup ) { // If UP, reg->reg copy 1039 // COPY ACROSS HERE - NO DEF - NO CISC SPILL 1040 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx); 1041 // If it wasn't split bail 1042 if (!maxlrg) { 1043 return 0; 1044 } 1045 insidx++; // Reset iterator to skip USE side split 1046 } 1047 else { // DOWN, mem->mem copy 1048 // COPY UP & DOWN HERE - NO DEF - NO CISC SPILL 1049 // First Split-UP to move value into Register 1050 uint def_ideal = def->ideal_reg(); 1051 const RegMask* tmp_rm = Matcher::idealreg2regmask[def_ideal]; 1052 Node *spill = new (C) MachSpillCopyNode(def, dmask, *tmp_rm); 1053 insert_proj( b, insidx, spill, maxlrg ); 1054 // Then Split-DOWN as if previous Split was DEF 1055 maxlrg = split_USE(spill,b,n,inpidx,maxlrg,false,false, splits,slidx); 1056 // If it wasn't split bail 1057 if (!maxlrg) { 1058 return 0; 1059 } 1060 insidx += 2; // Reset iterator to skip USE side splits 1061 } 1062 } // End else no overlap 1063 } // End if dup == uup 1064 // dup != uup, so check dup for direction of Split 1065 else { 1066 if( dup ) { // If UP, Split-DOWN and check Debug Info 1067 // If this node is already a SpillCopy, just patch the edge 1068 // except the case of spilling to stack. 1069 if( n->is_SpillCopy() ) { 1070 RegMask tmp_rm(umask); 1071 tmp_rm.SUBTRACT(Matcher::STACK_ONLY_mask); 1072 if( dmask.overlap(tmp_rm) ) { 1073 if( def != n->in(inpidx) ) { 1074 n->set_req(inpidx, def); 1075 } 1076 continue; 1077 } 1078 } 1079 // COPY DOWN HERE - NO DEF - NO CISC SPILL 1080 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx); 1081 // If it wasn't split bail 1082 if (!maxlrg) { 1083 return 0; 1084 } 1085 insidx++; // Reset iterator to skip USE side split 1086 // Check for debug-info split. Capture it for later 1087 // debug splits of the same value 1088 if (jvms && jvms->debug_start() <= inpidx && inpidx < oopoff) 1089 debug_defs[slidx] = n->in(inpidx); 1090 1091 } 1092 else { // DOWN, Split-UP and check register pressure 1093 if( is_high_pressure( b, &lrgs(useidx), insidx ) ) { 1094 // COPY UP HERE - NO DEF - CISC SPILL 1095 maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,true, splits,slidx); 1096 // If it wasn't split bail 1097 if (!maxlrg) { 1098 return 0; 1099 } 1100 insidx++; // Reset iterator to skip USE side split 1101 } else { // LRP 1102 // COPY UP HERE - WITH DEF - NO CISC SPILL 1103 maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,false, splits,slidx); 1104 // If it wasn't split bail 1105 if (!maxlrg) { 1106 return 0; 1107 } 1108 // Flag this lift-up in a low-pressure block as 1109 // already-spilled, so if it spills again it will 1110 // spill hard (instead of not spilling hard and 1111 // coalescing away). 1112 set_was_spilled(n->in(inpidx)); 1113 // Since this is a new DEF, update Reachblock & UP 1114 Reachblock[slidx] = n->in(inpidx); 1115 UPblock[slidx] = true; 1116 insidx++; // Reset iterator to skip USE side split 1117 } 1118 } // End else DOWN 1119 } // End dup != uup 1120 } // End if Spill USE 1121 } // End For All Inputs 1122 } // End If not nullcheck 1123 1124 // ********** Handle DEFS ********** 1125 // DEFS either Split DOWN in HRP regions or when the LRG is bound, or 1126 // just reset the Reaches info in LRP regions. DEFS must always update 1127 // UP info. 1128 if( deflrg.reg() >= LRG::SPILL_REG ) { // Spilled? 1129 uint slidx = lrg2reach[defidx]; 1130 // Add to defs list for later assignment of new live range number 1131 defs->push(n); 1132 // Set a flag on the Node indicating it has already spilled. 1133 // Only do it for capacity spills not conflict spills. 1134 if( !deflrg._direct_conflict ) 1135 set_was_spilled(n); 1136 assert(!n->is_Phi(),"Cannot insert Phi into DEFS list"); 1137 // Grab UP info for DEF 1138 const RegMask &dmask = n->out_RegMask(); 1139 bool defup = dmask.is_UP(); 1140 int ireg = n->ideal_reg(); 1141 bool is_vect = RegMask::is_vector(ireg); 1142 // Only split at Def if this is a HRP block or bound (and spilled once) 1143 if( !n->rematerialize() && 1144 (((dmask.is_bound(ireg) || !is_vect && dmask.is_misaligned_pair()) && 1145 (deflrg._direct_conflict || deflrg._must_spill)) || 1146 // Check for LRG being up in a register and we are inside a high 1147 // pressure area. Spill it down immediately. 1148 (defup && is_high_pressure(b,&deflrg,insidx))) ) { 1149 assert( !n->rematerialize(), "" ); 1150 assert( !n->is_SpillCopy(), "" ); 1151 // Do a split at the def site. 1152 maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx ); 1153 // If it wasn't split bail 1154 if (!maxlrg) { 1155 return 0; 1156 } 1157 // Split DEF's Down 1158 UPblock[slidx] = 0; 1159#ifndef PRODUCT 1160 // DEBUG 1161 if( trace_spilling() ) { 1162 tty->print("\nNew Split DOWN DEF of Spill Idx "); 1163 tty->print("%d, UP %d:\n",slidx,false); 1164 n->dump(); 1165 } 1166#endif 1167 } 1168 else { // Neither bound nor HRP, must be LRP 1169 // otherwise, just record the def 1170 Reachblock[slidx] = n; 1171 // UP should come from the outRegmask() of the DEF 1172 UPblock[slidx] = defup; 1173 // Update debug list of reaching down definitions, kill if DEF is UP 1174 debug_defs[slidx] = defup ? NULL : n; 1175#ifndef PRODUCT 1176 // DEBUG 1177 if( trace_spilling() ) { 1178 tty->print("\nNew DEF of Spill Idx "); 1179 tty->print("%d, UP %d:\n",slidx,defup); 1180 n->dump(); 1181 } 1182#endif 1183 } // End else LRP 1184 } // End if spill def 1185 1186 // ********** Split Left Over Mem-Mem Moves ********** 1187 // Check for mem-mem copies and split them now. Do not do this 1188 // to copies about to be spilled; they will be Split shortly. 1189 if( copyidx ) { 1190 Node *use = n->in(copyidx); 1191 uint useidx = Find_id(use); 1192 if( useidx < _maxlrg && // This is not a new split 1193 OptoReg::is_stack(deflrg.reg()) && 1194 deflrg.reg() < LRG::SPILL_REG ) { // And DEF is from stack 1195 LRG &uselrg = lrgs(useidx); 1196 if( OptoReg::is_stack(uselrg.reg()) && 1197 uselrg.reg() < LRG::SPILL_REG && // USE is from stack 1198 deflrg.reg() != uselrg.reg() ) { // Not trivially removed 1199 uint def_ideal_reg = n->bottom_type()->ideal_reg(); 1200 const RegMask &def_rm = *Matcher::idealreg2regmask[def_ideal_reg]; 1201 const RegMask &use_rm = n->in_RegMask(copyidx); 1202 if( def_rm.overlap(use_rm) && n->is_SpillCopy() ) { // Bug 4707800, 'n' may be a storeSSL 1203 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { // Check when generating nodes 1204 return 0; 1205 } 1206 Node *spill = new (C) MachSpillCopyNode(use,use_rm,def_rm); 1207 n->set_req(copyidx,spill); 1208 n->as_MachSpillCopy()->set_in_RegMask(def_rm); 1209 // Put the spill just before the copy 1210 insert_proj( b, insidx++, spill, maxlrg++ ); 1211 } 1212 } 1213 } 1214 } 1215 } // End For All Instructions in Block - Non-PHI Pass 1216 1217 // Check if each LRG is live out of this block so as not to propagate 1218 // beyond the last use of a LRG. 1219 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 1220 uint defidx = lidxs.at(slidx); 1221 IndexSet *liveout = _live->live(b); 1222 if( !liveout->member(defidx) ) { 1223#ifdef ASSERT 1224 // The index defidx is not live. Check the liveout array to ensure that 1225 // it contains no members which compress to defidx. Finding such an 1226 // instance may be a case to add liveout adjustment in compress_uf_map(). 1227 // See 5063219. 1228 uint member; 1229 IndexSetIterator isi(liveout); 1230 while ((member = isi.next()) != 0) { 1231 assert(defidx != Find_const(member), "Live out member has not been compressed"); 1232 } 1233#endif 1234 Reachblock[slidx] = NULL; 1235 } else { 1236 assert(Reachblock[slidx] != NULL,"No reaching definition for liveout value"); 1237 } 1238 } 1239#ifndef PRODUCT 1240 if( trace_spilling() ) 1241 b->dump(); 1242#endif 1243 } // End For All Blocks 1244 1245 //----------PASS 2---------- 1246 // Reset all DEF live range numbers here 1247 for( insidx = 0; insidx < defs->size(); insidx++ ) { 1248 // Grab the def 1249 n1 = defs->at(insidx); 1250 // Set new lidx for DEF 1251 new_lrg(n1, maxlrg++); 1252 } 1253 //----------Phi Node Splitting---------- 1254 // Clean up a phi here, and assign a new live range number 1255 // Cycle through this block's predecessors, collecting Reaches 1256 // info for each spilled LRG and update edges. 1257 // Walk the phis list to patch inputs, split phis, and name phis 1258 uint lrgs_before_phi_split = maxlrg; 1259 for( insidx = 0; insidx < phis->size(); insidx++ ) { 1260 Node *phi = phis->at(insidx); 1261 assert(phi->is_Phi(),"This list must only contain Phi Nodes"); 1262 Block *b = _cfg._bbs[phi->_idx]; 1263 // Grab the live range number 1264 uint lidx = Find_id(phi); 1265 uint slidx = lrg2reach[lidx]; 1266 // Update node to lidx map 1267 new_lrg(phi, maxlrg++); 1268 // Get PASS1's up/down decision for the block. 1269 int phi_up = !!UP_entry[slidx]->test(b->_pre_order); 1270 1271 // Force down if double-spilling live range 1272 if( lrgs(lidx)._was_spilled1 ) 1273 phi_up = false; 1274 1275 // When splitting a Phi we an split it normal or "inverted". 1276 // An inverted split makes the splits target the Phi's UP/DOWN 1277 // sense inverted; then the Phi is followed by a final def-side 1278 // split to invert back. It changes which blocks the spill code 1279 // goes in. 1280 1281 // Walk the predecessor blocks and assign the reaching def to the Phi. 1282 // Split Phi nodes by placing USE side splits wherever the reaching 1283 // DEF has the wrong UP/DOWN value. 1284 for( uint i = 1; i < b->num_preds(); i++ ) { 1285 // Get predecessor block pre-order number 1286 Block *pred = _cfg._bbs[b->pred(i)->_idx]; 1287 pidx = pred->_pre_order; 1288 // Grab reaching def 1289 Node *def = Reaches[pidx][slidx]; 1290 assert( def, "must have reaching def" ); 1291 // If input up/down sense and reg-pressure DISagree 1292 if( def->rematerialize() ) { 1293 // Place the rematerialized node above any MSCs created during 1294 // phi node splitting. end_idx points at the insertion point 1295 // so look at the node before it. 1296 int insert = pred->end_idx(); 1297 while (insert >= 1 && 1298 pred->_nodes[insert - 1]->is_SpillCopy() && 1299 Find(pred->_nodes[insert - 1]) >= lrgs_before_phi_split) { 1300 insert--; 1301 } 1302 def = split_Rematerialize( def, pred, insert, maxlrg, splits, slidx, lrg2reach, Reachblock, false ); 1303 if( !def ) return 0; // Bail out 1304 } 1305 // Update the Phi's input edge array 1306 phi->set_req(i,def); 1307 // Grab the UP/DOWN sense for the input 1308 u1 = UP[pidx][slidx]; 1309 if( u1 != (phi_up != 0)) { 1310 maxlrg = split_USE(def, b, phi, i, maxlrg, !u1, false, splits,slidx); 1311 // If it wasn't split bail 1312 if (!maxlrg) { 1313 return 0; 1314 } 1315 } 1316 } // End for all inputs to the Phi 1317 } // End for all Phi Nodes 1318 // Update _maxlrg to save Union asserts 1319 _maxlrg = maxlrg; 1320 1321 1322 //----------PASS 3---------- 1323 // Pass over all Phi's to union the live ranges 1324 for( insidx = 0; insidx < phis->size(); insidx++ ) { 1325 Node *phi = phis->at(insidx); 1326 assert(phi->is_Phi(),"This list must only contain Phi Nodes"); 1327 // Walk all inputs to Phi and Union input live range with Phi live range 1328 for( uint i = 1; i < phi->req(); i++ ) { 1329 // Grab the input node 1330 Node *n = phi->in(i); 1331 assert( n, "" ); 1332 uint lidx = Find(n); 1333 uint pidx = Find(phi); 1334 if( lidx < pidx ) 1335 Union(n, phi); 1336 else if( lidx > pidx ) 1337 Union(phi, n); 1338 } // End for all inputs to the Phi Node 1339 } // End for all Phi Nodes 1340 // Now union all two address instructions 1341 for( insidx = 0; insidx < defs->size(); insidx++ ) { 1342 // Grab the def 1343 n1 = defs->at(insidx); 1344 // Set new lidx for DEF & handle 2-addr instructions 1345 if( n1->is_Mach() && ((twoidx = n1->as_Mach()->two_adr()) != 0) ) { 1346 assert( Find(n1->in(twoidx)) < maxlrg,"Assigning bad live range index"); 1347 // Union the input and output live ranges 1348 uint lr1 = Find(n1); 1349 uint lr2 = Find(n1->in(twoidx)); 1350 if( lr1 < lr2 ) 1351 Union(n1, n1->in(twoidx)); 1352 else if( lr1 > lr2 ) 1353 Union(n1->in(twoidx), n1); 1354 } // End if two address 1355 } // End for all defs 1356 // DEBUG 1357#ifdef ASSERT 1358 // Validate all live range index assignments 1359 for( bidx = 0; bidx < _cfg._num_blocks; bidx++ ) { 1360 b = _cfg._blocks[bidx]; 1361 for( insidx = 0; insidx <= b->end_idx(); insidx++ ) { 1362 Node *n = b->_nodes[insidx]; 1363 uint defidx = Find(n); 1364 assert(defidx < _maxlrg,"Bad live range index in Split"); 1365 assert(defidx < maxlrg,"Bad live range index in Split"); 1366 } 1367 } 1368 // Issue a warning if splitting made no progress 1369 int noprogress = 0; 1370 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 1371 if( PrintOpto && WizardMode && splits.at(slidx) == 0 ) { 1372 tty->print_cr("Failed to split live range %d", lidxs.at(slidx)); 1373 //BREAKPOINT; 1374 } 1375 else { 1376 noprogress++; 1377 } 1378 } 1379 if(!noprogress) { 1380 tty->print_cr("Failed to make progress in Split"); 1381 //BREAKPOINT; 1382 } 1383#endif 1384 // Return updated count of live ranges 1385 return maxlrg; 1386} 1387