reg_split.cpp revision 0:a61af66fc99e
1/* 2 * Copyright 2000-2006 Sun Microsystems, Inc. All Rights Reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 * CA 95054 USA or visit www.sun.com if you need additional information or 21 * have any questions. 22 * 23 */ 24 25#include "incls/_precompiled.incl" 26#include "incls/_reg_split.cpp.incl" 27 28//------------------------------Split-------------------------------------- 29// Walk the graph in RPO and for each lrg which spills, propogate reaching 30// definitions. During propogation, split the live range around regions of 31// High Register Pressure (HRP). If a Def is in a region of Low Register 32// Pressure (LRP), it will not get spilled until we encounter a region of 33// HRP between it and one of its uses. We will spill at the transition 34// point between LRP and HRP. Uses in the HRP region will use the spilled 35// Def. The first Use outside the HRP region will generate a SpillCopy to 36// hoist the live range back up into a register, and all subsequent uses 37// will use that new Def until another HRP region is encountered. Defs in 38// HRP regions will get trailing SpillCopies to push the LRG down into the 39// stack immediately. 40// 41// As a side effect, unlink from (hence make dead) coalesced copies. 42// 43 44static const char out_of_nodes[] = "out of nodes during split"; 45 46//------------------------------get_spillcopy_wide----------------------------- 47// Get a SpillCopy node with wide-enough masks. Use the 'wide-mask', the 48// wide ideal-register spill-mask if possible. If the 'wide-mask' does 49// not cover the input (or output), use the input (or output) mask instead. 50Node *PhaseChaitin::get_spillcopy_wide( Node *def, Node *use, uint uidx ) { 51 // If ideal reg doesn't exist we've got a bad schedule happening 52 // that is forcing us to spill something that isn't spillable. 53 // Bail rather than abort 54 int ireg = def->ideal_reg(); 55 if( ireg == 0 || ireg == Op_RegFlags ) { 56 C->record_method_not_compilable("attempted to spill a non-spillable item"); 57 return NULL; 58 } 59 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { 60 return NULL; 61 } 62 const RegMask *i_mask = &def->out_RegMask(); 63 const RegMask *w_mask = C->matcher()->idealreg2spillmask[ireg]; 64 const RegMask *o_mask = use ? &use->in_RegMask(uidx) : w_mask; 65 const RegMask *w_i_mask = w_mask->overlap( *i_mask ) ? w_mask : i_mask; 66 const RegMask *w_o_mask; 67 68 if( w_mask->overlap( *o_mask ) && // Overlap AND 69 ((ireg != Op_RegL && ireg != Op_RegD // Single use or aligned 70#ifdef _LP64 71 && ireg != Op_RegP 72#endif 73 ) || o_mask->is_aligned_Pairs()) ) { 74 // Don't come here for mis-aligned doubles 75 w_o_mask = w_mask; 76 } else { // wide ideal mask does not overlap with o_mask 77 // Mis-aligned doubles come here and XMM->FPR moves on x86. 78 w_o_mask = o_mask; // Must target desired registers 79 // Does the ideal-reg-mask overlap with o_mask? I.e., can I use 80 // a reg-reg move or do I need a trip across register classes 81 // (and thus through memory)? 82 if( !C->matcher()->idealreg2regmask[ireg]->overlap( *o_mask) && o_mask->is_UP() ) 83 // Here we assume a trip through memory is required. 84 w_i_mask = &C->FIRST_STACK_mask(); 85 } 86 return new (C) MachSpillCopyNode( def, *w_i_mask, *w_o_mask ); 87} 88 89//------------------------------insert_proj------------------------------------ 90// Insert the spill at chosen location. Skip over any interveneing Proj's or 91// Phis. Skip over a CatchNode and projs, inserting in the fall-through block 92// instead. Update high-pressure indices. Create a new live range. 93void PhaseChaitin::insert_proj( Block *b, uint i, Node *spill, uint maxlrg ) { 94 // Skip intervening ProjNodes. Do not insert between a ProjNode and 95 // its definer. 96 while( i < b->_nodes.size() && 97 (b->_nodes[i]->is_Proj() || 98 b->_nodes[i]->is_Phi() ) ) 99 i++; 100 101 // Do not insert between a call and his Catch 102 if( b->_nodes[i]->is_Catch() ) { 103 // Put the instruction at the top of the fall-thru block. 104 // Find the fall-thru projection 105 while( 1 ) { 106 const CatchProjNode *cp = b->_nodes[++i]->as_CatchProj(); 107 if( cp->_con == CatchProjNode::fall_through_index ) 108 break; 109 } 110 int sidx = i - b->end_idx()-1; 111 b = b->_succs[sidx]; // Switch to successor block 112 i = 1; // Right at start of block 113 } 114 115 b->_nodes.insert(i,spill); // Insert node in block 116 _cfg._bbs.map(spill->_idx,b); // Update node->block mapping to reflect 117 // Adjust the point where we go hi-pressure 118 if( i <= b->_ihrp_index ) b->_ihrp_index++; 119 if( i <= b->_fhrp_index ) b->_fhrp_index++; 120 121 // Assign a new Live Range Number to the SpillCopy and grow 122 // the node->live range mapping. 123 new_lrg(spill,maxlrg); 124} 125 126//------------------------------split_DEF-------------------------------------- 127// There are four catagories of Split; UP/DOWN x DEF/USE 128// Only three of these really occur as DOWN/USE will always color 129// Any Split with a DEF cannot CISC-Spill now. Thus we need 130// two helper routines, one for Split DEFS (insert after instruction), 131// one for Split USES (insert before instruction). DEF insertion 132// happens inside Split, where the Leaveblock array is updated. 133uint PhaseChaitin::split_DEF( Node *def, Block *b, int loc, uint maxlrg, Node **Reachblock, Node **debug_defs, GrowableArray<uint> splits, int slidx ) { 134#ifdef ASSERT 135 // Increment the counter for this lrg 136 splits.at_put(slidx, splits.at(slidx)+1); 137#endif 138 // If we are spilling the memory op for an implicit null check, at the 139 // null check location (ie - null check is in HRP block) we need to do 140 // the null-check first, then spill-down in the following block. 141 // (The implicit_null_check function ensures the use is also dominated 142 // by the branch-not-taken block.) 143 Node *be = b->end(); 144 if( be->is_MachNullCheck() && be->in(1) == def && def == b->_nodes[loc] ) { 145 // Spill goes in the branch-not-taken block 146 b = b->_succs[b->_nodes[b->end_idx()+1]->Opcode() == Op_IfTrue]; 147 loc = 0; // Just past the Region 148 } 149 assert( loc >= 0, "must insert past block head" ); 150 151 // Get a def-side SpillCopy 152 Node *spill = get_spillcopy_wide(def,NULL,0); 153 // Did we fail to split?, then bail 154 if (!spill) { 155 return 0; 156 } 157 158 // Insert the spill at chosen location 159 insert_proj( b, loc+1, spill, maxlrg++); 160 161 // Insert new node into Reaches array 162 Reachblock[slidx] = spill; 163 // Update debug list of reaching down definitions by adding this one 164 debug_defs[slidx] = spill; 165 166 // return updated count of live ranges 167 return maxlrg; 168} 169 170//------------------------------split_USE-------------------------------------- 171// Splits at uses can involve redeffing the LRG, so no CISC Spilling there. 172// Debug uses want to know if def is already stack enabled. 173uint PhaseChaitin::split_USE( Node *def, Block *b, Node *use, uint useidx, uint maxlrg, bool def_down, bool cisc_sp, GrowableArray<uint> splits, int slidx ) { 174#ifdef ASSERT 175 // Increment the counter for this lrg 176 splits.at_put(slidx, splits.at(slidx)+1); 177#endif 178 179 // Some setup stuff for handling debug node uses 180 JVMState* jvms = use->jvms(); 181 uint debug_start = jvms ? jvms->debug_start() : 999999; 182 uint debug_end = jvms ? jvms->debug_end() : 999999; 183 184 //------------------------------------------- 185 // Check for use of debug info 186 if (useidx >= debug_start && useidx < debug_end) { 187 // Actually it's perfectly legal for constant debug info to appear 188 // just unlikely. In this case the optimizer left a ConI of a 4 189 // as both inputs to a Phi with only a debug use. It's a single-def 190 // live range of a rematerializable value. The live range spills, 191 // rematerializes and now the ConI directly feeds into the debug info. 192 // assert(!def->is_Con(), "constant debug info already constructed directly"); 193 194 // Special split handling for Debug Info 195 // If DEF is DOWN, just hook the edge and return 196 // If DEF is UP, Split it DOWN for this USE. 197 if( def->is_Mach() ) { 198 if( def_down ) { 199 // DEF is DOWN, so connect USE directly to the DEF 200 use->set_req(useidx, def); 201 } else { 202 // Block and index where the use occurs. 203 Block *b = _cfg._bbs[use->_idx]; 204 // Put the clone just prior to use 205 int bindex = b->find_node(use); 206 // DEF is UP, so must copy it DOWN and hook in USE 207 // Insert SpillCopy before the USE, which uses DEF as its input, 208 // and defs a new live range, which is used by this node. 209 Node *spill = get_spillcopy_wide(def,use,useidx); 210 // did we fail to split? 211 if (!spill) { 212 // Bail 213 return 0; 214 } 215 // insert into basic block 216 insert_proj( b, bindex, spill, maxlrg++ ); 217 // Use the new split 218 use->set_req(useidx,spill); 219 } 220 // No further split handling needed for this use 221 return maxlrg; 222 } // End special splitting for debug info live range 223 } // If debug info 224 225 // CISC-SPILLING 226 // Finally, check to see if USE is CISC-Spillable, and if so, 227 // gather_lrg_masks will add the flags bit to its mask, and 228 // no use side copy is needed. This frees up the live range 229 // register choices without causing copy coalescing, etc. 230 if( UseCISCSpill && cisc_sp ) { 231 int inp = use->cisc_operand(); 232 if( inp != AdlcVMDeps::Not_cisc_spillable ) 233 // Convert operand number to edge index number 234 inp = use->as_Mach()->operand_index(inp); 235 if( inp == (int)useidx ) { 236 use->set_req(useidx, def); 237#ifndef PRODUCT 238 if( TraceCISCSpill ) { 239 tty->print(" set_split: "); 240 use->dump(); 241 } 242#endif 243 return maxlrg; 244 } 245 } 246 247 //------------------------------------------- 248 // Insert a Copy before the use 249 250 // Block and index where the use occurs. 251 int bindex; 252 // Phi input spill-copys belong at the end of the prior block 253 if( use->is_Phi() ) { 254 b = _cfg._bbs[b->pred(useidx)->_idx]; 255 bindex = b->end_idx(); 256 } else { 257 // Put the clone just prior to use 258 bindex = b->find_node(use); 259 } 260 261 Node *spill = get_spillcopy_wide( def, use, useidx ); 262 if( !spill ) return 0; // Bailed out 263 // Insert SpillCopy before the USE, which uses the reaching DEF as 264 // its input, and defs a new live range, which is used by this node. 265 insert_proj( b, bindex, spill, maxlrg++ ); 266 // Use the spill/clone 267 use->set_req(useidx,spill); 268 269 // return updated live range count 270 return maxlrg; 271} 272 273//------------------------------split_Rematerialize---------------------------- 274// Clone a local copy of the def. 275Node *PhaseChaitin::split_Rematerialize( Node *def, Block *b, uint insidx, uint &maxlrg, GrowableArray<uint> splits, int slidx, uint *lrg2reach, Node **Reachblock, bool walkThru ) { 276 // The input live ranges will be stretched to the site of the new 277 // instruction. They might be stretched past a def and will thus 278 // have the old and new values of the same live range alive at the 279 // same time - a definite no-no. Split out private copies of 280 // the inputs. 281 if( def->req() > 1 ) { 282 for( uint i = 1; i < def->req(); i++ ) { 283 Node *in = def->in(i); 284 // Check for single-def (LRG cannot redefined) 285 uint lidx = n2lidx(in); 286 if( lidx >= _maxlrg ) continue; // Value is a recent spill-copy 287 if( lrgs(lidx)._def != NodeSentinel ) continue; 288 289 Block *b_def = _cfg._bbs[def->_idx]; 290 int idx_def = b_def->find_node(def); 291 Node *in_spill = get_spillcopy_wide( in, def, i ); 292 if( !in_spill ) return 0; // Bailed out 293 insert_proj(b_def,idx_def,in_spill,maxlrg++); 294 if( b_def == b ) 295 insidx++; 296 def->set_req(i,in_spill); 297 } 298 } 299 300 Node *spill = def->clone(); 301 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { 302 // Check when generating nodes 303 return 0; 304 } 305 306 // See if any inputs are currently being spilled, and take the 307 // latest copy of spilled inputs. 308 if( spill->req() > 1 ) { 309 for( uint i = 1; i < spill->req(); i++ ) { 310 Node *in = spill->in(i); 311 uint lidx = Find_id(in); 312 313 // Walk backwards thru spill copy node intermediates 314 if( walkThru ) 315 while ( in->is_SpillCopy() && lidx >= _maxlrg ) { 316 in = in->in(1); 317 lidx = Find_id(in); 318 } 319 320 if( lidx < _maxlrg && lrgs(lidx).reg() >= LRG::SPILL_REG ) { 321 Node *rdef = Reachblock[lrg2reach[lidx]]; 322 if( rdef ) spill->set_req(i,rdef); 323 } 324 } 325 } 326 327 328 assert( spill->out_RegMask().is_UP(), "rematerialize to a reg" ); 329 // Rematerialized op is def->spilled+1 330 set_was_spilled(spill); 331 if( _spilled_once.test(def->_idx) ) 332 set_was_spilled(spill); 333 334 insert_proj( b, insidx, spill, maxlrg++ ); 335#ifdef ASSERT 336 // Increment the counter for this lrg 337 splits.at_put(slidx, splits.at(slidx)+1); 338#endif 339 // See if the cloned def kills any flags, and copy those kills as well 340 uint i = insidx+1; 341 if( clone_projs( b, i, def, spill, maxlrg ) ) { 342 // Adjust the point where we go hi-pressure 343 if( i <= b->_ihrp_index ) b->_ihrp_index++; 344 if( i <= b->_fhrp_index ) b->_fhrp_index++; 345 } 346 347 return spill; 348} 349 350//------------------------------is_high_pressure------------------------------- 351// Function to compute whether or not this live range is "high pressure" 352// in this block - whether it spills eagerly or not. 353bool PhaseChaitin::is_high_pressure( Block *b, LRG *lrg, uint insidx ) { 354 if( lrg->_was_spilled1 ) return true; 355 // Forced spilling due to conflict? Then split only at binding uses 356 // or defs, not for supposed capacity problems. 357 // CNC - Turned off 7/8/99, causes too much spilling 358 // if( lrg->_is_bound ) return false; 359 360 // Not yet reached the high-pressure cutoff point, so low pressure 361 uint hrp_idx = lrg->_is_float ? b->_fhrp_index : b->_ihrp_index; 362 if( insidx < hrp_idx ) return false; 363 // Register pressure for the block as a whole depends on reg class 364 int block_pres = lrg->_is_float ? b->_freg_pressure : b->_reg_pressure; 365 // Bound live ranges will split at the binding points first; 366 // Intermediate splits should assume the live range's register set 367 // got "freed up" and that num_regs will become INT_PRESSURE. 368 int bound_pres = lrg->_is_float ? FLOATPRESSURE : INTPRESSURE; 369 // Effective register pressure limit. 370 int lrg_pres = (lrg->get_invalid_mask_size() > lrg->num_regs()) 371 ? (lrg->get_invalid_mask_size() >> (lrg->num_regs()-1)) : bound_pres; 372 // High pressure if block pressure requires more register freedom 373 // than live range has. 374 return block_pres >= lrg_pres; 375} 376 377 378//------------------------------prompt_use--------------------------------- 379// True if lidx is used before any real register is def'd in the block 380bool PhaseChaitin::prompt_use( Block *b, uint lidx ) { 381 if( lrgs(lidx)._was_spilled2 ) return false; 382 383 // Scan block for 1st use. 384 for( uint i = 1; i <= b->end_idx(); i++ ) { 385 Node *n = b->_nodes[i]; 386 // Ignore PHI use, these can be up or down 387 if( n->is_Phi() ) continue; 388 for( uint j = 1; j < n->req(); j++ ) 389 if( Find_id(n->in(j)) == lidx ) 390 return true; // Found 1st use! 391 if( n->out_RegMask().is_NotEmpty() ) return false; 392 } 393 return false; 394} 395 396//------------------------------Split-------------------------------------- 397//----------Split Routine---------- 398// ***** NEW SPLITTING HEURISTIC ***** 399// DEFS: If the DEF is in a High Register Pressure(HRP) Block, split there. 400// Else, no split unless there is a HRP block between a DEF and 401// one of its uses, and then split at the HRP block. 402// 403// USES: If USE is in HRP, split at use to leave main LRG on stack. 404// Else, hoist LRG back up to register only (ie - split is also DEF) 405// We will compute a new maxlrg as we go 406uint PhaseChaitin::Split( uint maxlrg ) { 407 NOT_PRODUCT( Compile::TracePhase t3("regAllocSplit", &_t_regAllocSplit, TimeCompiler); ) 408 409 uint bidx, pidx, slidx, insidx, inpidx, twoidx; 410 uint non_phi = 1, spill_cnt = 0; 411 Node **Reachblock; 412 Node *n1, *n2, *n3; 413 Node_List *defs,*phis; 414 bool *UPblock; 415 bool u1, u2, u3; 416 Block *b, *pred; 417 PhiNode *phi; 418 GrowableArray<uint> lidxs; 419 420 // Array of counters to count splits per live range 421 GrowableArray<uint> splits; 422 423 //----------Setup Code---------- 424 // Create a convenient mapping from lrg numbers to reaches/leaves indices 425 uint *lrg2reach = NEW_RESOURCE_ARRAY( uint, _maxlrg ); 426 // Keep track of DEFS & Phis for later passes 427 defs = new Node_List(); 428 phis = new Node_List(); 429 // Gather info on which LRG's are spilling, and build maps 430 for( bidx = 1; bidx < _maxlrg; bidx++ ) { 431 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) { 432 assert(!lrgs(bidx).mask().is_AllStack(),"AllStack should color"); 433 lrg2reach[bidx] = spill_cnt; 434 spill_cnt++; 435 lidxs.append(bidx); 436#ifdef ASSERT 437 // Initialize the split counts to zero 438 splits.append(0); 439#endif 440#ifndef PRODUCT 441 if( PrintOpto && WizardMode && lrgs(bidx)._was_spilled1 ) 442 tty->print_cr("Warning, 2nd spill of L%d",bidx); 443#endif 444 } 445 } 446 447 // Create side arrays for propagating reaching defs info. 448 // Each block needs a node pointer for each spilling live range for the 449 // Def which is live into the block. Phi nodes handle multiple input 450 // Defs by querying the output of their predecessor blocks and resolving 451 // them to a single Def at the phi. The pointer is updated for each 452 // Def in the block, and then becomes the output for the block when 453 // processing of the block is complete. We also need to track whether 454 // a Def is UP or DOWN. UP means that it should get a register (ie - 455 // it is always in LRP regions), and DOWN means that it is probably 456 // on the stack (ie - it crosses HRP regions). 457 Node ***Reaches = NEW_RESOURCE_ARRAY( Node**, _cfg._num_blocks+1 ); 458 bool **UP = NEW_RESOURCE_ARRAY( bool*, _cfg._num_blocks+1 ); 459 Node **debug_defs = NEW_RESOURCE_ARRAY( Node*, spill_cnt ); 460 VectorSet **UP_entry= NEW_RESOURCE_ARRAY( VectorSet*, spill_cnt ); 461 462 // Initialize Reaches & UP 463 for( bidx = 0; bidx < _cfg._num_blocks+1; bidx++ ) { 464 Reaches[bidx] = NEW_RESOURCE_ARRAY( Node*, spill_cnt ); 465 UP[bidx] = NEW_RESOURCE_ARRAY( bool, spill_cnt ); 466 Node **Reachblock = Reaches[bidx]; 467 bool *UPblock = UP[bidx]; 468 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 469 UPblock[slidx] = true; // Assume they start in registers 470 Reachblock[slidx] = NULL; // Assume that no def is present 471 } 472 } 473 474 // Initialize to array of empty vectorsets 475 for( slidx = 0; slidx < spill_cnt; slidx++ ) 476 UP_entry[slidx] = new VectorSet(Thread::current()->resource_area()); 477 478 //----------PASS 1---------- 479 //----------Propagation & Node Insertion Code---------- 480 // Walk the Blocks in RPO for DEF & USE info 481 for( bidx = 0; bidx < _cfg._num_blocks; bidx++ ) { 482 483 if (C->check_node_count(spill_cnt, out_of_nodes)) { 484 return 0; 485 } 486 487 b = _cfg._blocks[bidx]; 488 // Reaches & UP arrays for this block 489 Reachblock = Reaches[b->_pre_order]; 490 UPblock = UP[b->_pre_order]; 491 // Reset counter of start of non-Phi nodes in block 492 non_phi = 1; 493 //----------Block Entry Handling---------- 494 // Check for need to insert a new phi 495 // Cycle through this block's predecessors, collecting Reaches 496 // info for each spilled LRG. If they are identical, no phi is 497 // needed. If they differ, check for a phi, and insert if missing, 498 // or update edges if present. Set current block's Reaches set to 499 // be either the phi's or the reaching def, as appropriate. 500 // If no Phi is needed, check if the LRG needs to spill on entry 501 // to the block due to HRP. 502 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 503 // Grab the live range number 504 uint lidx = lidxs.at(slidx); 505 // Do not bother splitting or putting in Phis for single-def 506 // rematerialized live ranges. This happens alot to constants 507 // with long live ranges. 508 if( lrgs(lidx)._def != NodeSentinel && 509 lrgs(lidx)._def->rematerialize() ) { 510 // reset the Reaches & UP entries 511 Reachblock[slidx] = lrgs(lidx)._def; 512 UPblock[slidx] = true; 513 // Record following instruction in case 'n' rematerializes and 514 // kills flags 515 Block *pred1 = _cfg._bbs[b->pred(1)->_idx]; 516 continue; 517 } 518 519 // Initialize needs_phi and needs_split 520 bool needs_phi = false; 521 bool needs_split = false; 522 // Walk the predecessor blocks to check inputs for that live range 523 // Grab predecessor block header 524 n1 = b->pred(1); 525 // Grab the appropriate reaching def info for inpidx 526 pred = _cfg._bbs[n1->_idx]; 527 pidx = pred->_pre_order; 528 Node **Ltmp = Reaches[pidx]; 529 bool *Utmp = UP[pidx]; 530 n1 = Ltmp[slidx]; 531 u1 = Utmp[slidx]; 532 // Initialize node for saving type info 533 n3 = n1; 534 u3 = u1; 535 536 // Compare inputs to see if a Phi is needed 537 for( inpidx = 2; inpidx < b->num_preds(); inpidx++ ) { 538 // Grab predecessor block headers 539 n2 = b->pred(inpidx); 540 // Grab the appropriate reaching def info for inpidx 541 pred = _cfg._bbs[n2->_idx]; 542 pidx = pred->_pre_order; 543 Ltmp = Reaches[pidx]; 544 Utmp = UP[pidx]; 545 n2 = Ltmp[slidx]; 546 u2 = Utmp[slidx]; 547 // For each LRG, decide if a phi is necessary 548 if( n1 != n2 ) { 549 needs_phi = true; 550 } 551 // See if the phi has mismatched inputs, UP vs. DOWN 552 if( n1 && n2 && (u1 != u2) ) { 553 needs_split = true; 554 } 555 // Move n2/u2 to n1/u1 for next iteration 556 n1 = n2; 557 u1 = u2; 558 // Preserve a non-NULL predecessor for later type referencing 559 if( (n3 == NULL) && (n2 != NULL) ){ 560 n3 = n2; 561 u3 = u2; 562 } 563 } // End for all potential Phi inputs 564 565 // If a phi is needed, check for it 566 if( needs_phi ) { 567 // check block for appropriate phinode & update edges 568 for( insidx = 1; insidx <= b->end_idx(); insidx++ ) { 569 n1 = b->_nodes[insidx]; 570 // bail if this is not a phi 571 phi = n1->is_Phi() ? n1->as_Phi() : NULL; 572 if( phi == NULL ) { 573 // Keep track of index of first non-PhiNode instruction in block 574 non_phi = insidx; 575 // break out of the for loop as we have handled all phi nodes 576 break; 577 } 578 // must be looking at a phi 579 if( Find_id(n1) == lidxs.at(slidx) ) { 580 // found the necessary phi 581 needs_phi = false; 582 // initialize the Reaches entry for this LRG 583 Reachblock[slidx] = phi; 584 break; 585 } // end if found correct phi 586 } // end for all phi's 587 // add new phinode if one not already found 588 if( needs_phi ) { 589 // create a new phi node and insert it into the block 590 // type is taken from left over pointer to a predecessor 591 assert(n3,"No non-NULL reaching DEF for a Phi"); 592 phi = new (C, b->num_preds()) PhiNode(b->head(), n3->bottom_type()); 593 // initialize the Reaches entry for this LRG 594 Reachblock[slidx] = phi; 595 596 // add node to block & node_to_block mapping 597 insert_proj( b, insidx++, phi, maxlrg++ ); 598 non_phi++; 599 // Reset new phi's mapping to be the spilling live range 600 _names.map(phi->_idx, lidx); 601 assert(Find_id(phi) == lidx,"Bad update on Union-Find mapping"); 602 } // end if not found correct phi 603 // Here you have either found or created the Phi, so record it 604 assert(phi != NULL,"Must have a Phi Node here"); 605 phis->push(phi); 606 // PhiNodes should either force the LRG UP or DOWN depending 607 // on its inputs and the register pressure in the Phi's block. 608 UPblock[slidx] = true; // Assume new DEF is UP 609 // If entering a high-pressure area with no immediate use, 610 // assume Phi is DOWN 611 if( is_high_pressure( b, &lrgs(lidx), b->end_idx()) && !prompt_use(b,lidx) ) 612 UPblock[slidx] = false; 613 // If we are not split up/down and all inputs are down, then we 614 // are down 615 if( !needs_split && !u3 ) 616 UPblock[slidx] = false; 617 } // end if phi is needed 618 619 // Do not need a phi, so grab the reaching DEF 620 else { 621 // Grab predecessor block header 622 n1 = b->pred(1); 623 // Grab the appropriate reaching def info for k 624 pred = _cfg._bbs[n1->_idx]; 625 pidx = pred->_pre_order; 626 Node **Ltmp = Reaches[pidx]; 627 bool *Utmp = UP[pidx]; 628 // reset the Reaches & UP entries 629 Reachblock[slidx] = Ltmp[slidx]; 630 UPblock[slidx] = Utmp[slidx]; 631 } // end else no Phi is needed 632 } // end for all spilling live ranges 633 // DEBUG 634#ifndef PRODUCT 635 if(trace_spilling()) { 636 tty->print("/`\nBlock %d: ", b->_pre_order); 637 tty->print("Reaching Definitions after Phi handling\n"); 638 for( uint x = 0; x < spill_cnt; x++ ) { 639 tty->print("Spill Idx %d: UP %d: Node\n",x,UPblock[x]); 640 if( Reachblock[x] ) 641 Reachblock[x]->dump(); 642 else 643 tty->print("Undefined\n"); 644 } 645 } 646#endif 647 648 //----------Non-Phi Node Splitting---------- 649 // Since phi-nodes have now been handled, the Reachblock array for this 650 // block is initialized with the correct starting value for the defs which 651 // reach non-phi instructions in this block. Thus, process non-phi 652 // instructions normally, inserting SpillCopy nodes for all spill 653 // locations. 654 655 // Memoize any DOWN reaching definitions for use as DEBUG info 656 for( insidx = 0; insidx < spill_cnt; insidx++ ) { 657 debug_defs[insidx] = (UPblock[insidx]) ? NULL : Reachblock[insidx]; 658 if( UPblock[insidx] ) // Memoize UP decision at block start 659 UP_entry[insidx]->set( b->_pre_order ); 660 } 661 662 //----------Walk Instructions in the Block and Split---------- 663 // For all non-phi instructions in the block 664 for( insidx = 1; insidx <= b->end_idx(); insidx++ ) { 665 Node *n = b->_nodes[insidx]; 666 // Find the defining Node's live range index 667 uint defidx = Find_id(n); 668 uint cnt = n->req(); 669 670 if( n->is_Phi() ) { 671 // Skip phi nodes after removing dead copies. 672 if( defidx < _maxlrg ) { 673 // Check for useless Phis. These appear if we spill, then 674 // coalesce away copies. Dont touch Phis in spilling live 675 // ranges; they are busy getting modifed in this pass. 676 if( lrgs(defidx).reg() < LRG::SPILL_REG ) { 677 uint i; 678 Node *u = NULL; 679 // Look for the Phi merging 2 unique inputs 680 for( i = 1; i < cnt; i++ ) { 681 // Ignore repeats and self 682 if( n->in(i) != u && n->in(i) != n ) { 683 // Found a unique input 684 if( u != NULL ) // If it's the 2nd, bail out 685 break; 686 u = n->in(i); // Else record it 687 } 688 } 689 assert( u, "at least 1 valid input expected" ); 690 if( i >= cnt ) { // Didn't find 2+ unique inputs? 691 n->replace_by(u); // Then replace with unique input 692 n->disconnect_inputs(NULL); 693 b->_nodes.remove(insidx); 694 insidx--; 695 b->_ihrp_index--; 696 b->_fhrp_index--; 697 } 698 } 699 } 700 continue; 701 } 702 assert( insidx > b->_ihrp_index || 703 (b->_reg_pressure < (uint)INTPRESSURE) || 704 b->_ihrp_index > 4000000 || 705 b->_ihrp_index >= b->end_idx() || 706 !b->_nodes[b->_ihrp_index]->is_Proj(), "" ); 707 assert( insidx > b->_fhrp_index || 708 (b->_freg_pressure < (uint)FLOATPRESSURE) || 709 b->_fhrp_index > 4000000 || 710 b->_fhrp_index >= b->end_idx() || 711 !b->_nodes[b->_fhrp_index]->is_Proj(), "" ); 712 713 // ********** Handle Crossing HRP Boundry ********** 714 if( (insidx == b->_ihrp_index) || (insidx == b->_fhrp_index) ) { 715 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 716 // Check for need to split at HRP boundry - split if UP 717 n1 = Reachblock[slidx]; 718 // bail out if no reaching DEF 719 if( n1 == NULL ) continue; 720 // bail out if live range is 'isolated' around inner loop 721 uint lidx = lidxs.at(slidx); 722 // If live range is currently UP 723 if( UPblock[slidx] ) { 724 // set location to insert spills at 725 // SPLIT DOWN HERE - NO CISC SPILL 726 if( is_high_pressure( b, &lrgs(lidx), insidx ) && 727 !n1->rematerialize() ) { 728 // If there is already a valid stack definition available, use it 729 if( debug_defs[slidx] != NULL ) { 730 Reachblock[slidx] = debug_defs[slidx]; 731 } 732 else { 733 // Insert point is just past last use or def in the block 734 int insert_point = insidx-1; 735 while( insert_point > 0 ) { 736 Node *n = b->_nodes[insert_point]; 737 // Hit top of block? Quit going backwards 738 if( n->is_Phi() ) break; 739 // Found a def? Better split after it. 740 if( n2lidx(n) == lidx ) break; 741 // Look for a use 742 uint i; 743 for( i = 1; i < n->req(); i++ ) 744 if( n2lidx(n->in(i)) == lidx ) 745 break; 746 // Found a use? Better split after it. 747 if( i < n->req() ) break; 748 insert_point--; 749 } 750 maxlrg = split_DEF( n1, b, insert_point, maxlrg, Reachblock, debug_defs, splits, slidx); 751 // If it wasn't split bail 752 if (!maxlrg) { 753 return 0; 754 } 755 insidx++; 756 } 757 // This is a new DEF, so update UP 758 UPblock[slidx] = false; 759#ifndef PRODUCT 760 // DEBUG 761 if( trace_spilling() ) { 762 tty->print("\nNew Split DOWN DEF of Spill Idx "); 763 tty->print("%d, UP %d:\n",slidx,false); 764 n1->dump(); 765 } 766#endif 767 } 768 } // end if LRG is UP 769 } // end for all spilling live ranges 770 assert( b->_nodes[insidx] == n, "got insidx set incorrectly" ); 771 } // end if crossing HRP Boundry 772 773 // If the LRG index is oob, then this is a new spillcopy, skip it. 774 if( defidx >= _maxlrg ) { 775 continue; 776 } 777 LRG &deflrg = lrgs(defidx); 778 uint copyidx = n->is_Copy(); 779 // Remove coalesced copy from CFG 780 if( copyidx && defidx == n2lidx(n->in(copyidx)) ) { 781 n->replace_by( n->in(copyidx) ); 782 n->set_req( copyidx, NULL ); 783 b->_nodes.remove(insidx--); 784 b->_ihrp_index--; // Adjust the point where we go hi-pressure 785 b->_fhrp_index--; 786 continue; 787 } 788 789#define DERIVED 0 790 791 // ********** Handle USES ********** 792 bool nullcheck = false; 793 // Implicit null checks never use the spilled value 794 if( n->is_MachNullCheck() ) 795 nullcheck = true; 796 if( !nullcheck ) { 797 // Search all inputs for a Spill-USE 798 JVMState* jvms = n->jvms(); 799 uint oopoff = jvms ? jvms->oopoff() : cnt; 800 uint old_last = cnt - 1; 801 for( inpidx = 1; inpidx < cnt; inpidx++ ) { 802 // Derived/base pairs may be added to our inputs during this loop. 803 // If inpidx > old_last, then one of these new inputs is being 804 // handled. Skip the derived part of the pair, but process 805 // the base like any other input. 806 if( inpidx > old_last && ((inpidx - oopoff) & 1) == DERIVED ) { 807 continue; // skip derived_debug added below 808 } 809 // Get lidx of input 810 uint useidx = Find_id(n->in(inpidx)); 811 // Not a brand-new split, and it is a spill use 812 if( useidx < _maxlrg && lrgs(useidx).reg() >= LRG::SPILL_REG ) { 813 // Check for valid reaching DEF 814 slidx = lrg2reach[useidx]; 815 Node *def = Reachblock[slidx]; 816 assert( def != NULL, "Using Undefined Value in Split()\n"); 817 818 // (+++) %%%% remove this in favor of pre-pass in matcher.cpp 819 // monitor references do not care where they live, so just hook 820 if ( jvms && jvms->is_monitor_use(inpidx) ) { 821 // The effect of this clone is to drop the node out of the block, 822 // so that the allocator does not see it anymore, and therefore 823 // does not attempt to assign it a register. 824 def = def->clone(); 825 _names.extend(def->_idx,0); 826 _cfg._bbs.map(def->_idx,b); 827 n->set_req(inpidx, def); 828 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { 829 return 0; 830 } 831 continue; 832 } 833 834 // Rematerializable? Then clone def at use site instead 835 // of store/load 836 if( def->rematerialize() ) { 837 int old_size = b->_nodes.size(); 838 def = split_Rematerialize( def, b, insidx, maxlrg, splits, slidx, lrg2reach, Reachblock, true ); 839 if( !def ) return 0; // Bail out 840 insidx += b->_nodes.size()-old_size; 841 } 842 843 MachNode *mach = n->is_Mach() ? n->as_Mach() : NULL; 844 // Base pointers and oopmap references do not care where they live. 845 if ((inpidx >= oopoff) || 846 (mach && mach->ideal_Opcode() == Op_AddP && inpidx == AddPNode::Base)) { 847 if (def->rematerialize() && lrgs(useidx)._was_spilled2) { 848 // This def has been rematerialized a couple of times without 849 // progress. It doesn't care if it lives UP or DOWN, so 850 // spill it down now. 851 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false,splits,slidx); 852 // If it wasn't split bail 853 if (!maxlrg) { 854 return 0; 855 } 856 insidx++; // Reset iterator to skip USE side split 857 } else { 858 // Just hook the def edge 859 n->set_req(inpidx, def); 860 } 861 862 if (inpidx >= oopoff) { 863 // After oopoff, we have derived/base pairs. We must mention all 864 // derived pointers here as derived/base pairs for GC. If the 865 // derived value is spilling and we have a copy both in Reachblock 866 // (called here 'def') and debug_defs[slidx] we need to mention 867 // both in derived/base pairs or kill one. 868 Node *derived_debug = debug_defs[slidx]; 869 if( ((inpidx - oopoff) & 1) == DERIVED && // derived vs base? 870 mach && mach->ideal_Opcode() != Op_Halt && 871 derived_debug != NULL && 872 derived_debug != def ) { // Actual 2nd value appears 873 // We have already set 'def' as a derived value. 874 // Also set debug_defs[slidx] as a derived value. 875 uint k; 876 for( k = oopoff; k < cnt; k += 2 ) 877 if( n->in(k) == derived_debug ) 878 break; // Found an instance of debug derived 879 if( k == cnt ) {// No instance of debug_defs[slidx] 880 // Add a derived/base pair to cover the debug info. 881 // We have to process the added base later since it is not 882 // handled yet at this point but skip derived part. 883 assert(((n->req() - oopoff) & 1) == DERIVED, 884 "must match skip condition above"); 885 n->add_req( derived_debug ); // this will be skipped above 886 n->add_req( n->in(inpidx+1) ); // this will be processed 887 // Increment cnt to handle added input edges on 888 // subsequent iterations. 889 cnt += 2; 890 } 891 } 892 } 893 continue; 894 } 895 // Special logic for DEBUG info 896 if( jvms && b->_freq > BLOCK_FREQUENCY(0.5) ) { 897 uint debug_start = jvms->debug_start(); 898 // If this is debug info use & there is a reaching DOWN def 899 if ((debug_start <= inpidx) && (debug_defs[slidx] != NULL)) { 900 assert(inpidx < oopoff, "handle only debug info here"); 901 // Just hook it in & move on 902 n->set_req(inpidx, debug_defs[slidx]); 903 // (Note that this can make two sides of a split live at the 904 // same time: The debug def on stack, and another def in a 905 // register. The GC needs to know about both of them, but any 906 // derived pointers after oopoff will refer to only one of the 907 // two defs and the GC would therefore miss the other. Thus 908 // this hack is only allowed for debug info which is Java state 909 // and therefore never a derived pointer.) 910 continue; 911 } 912 } 913 // Grab register mask info 914 const RegMask &dmask = def->out_RegMask(); 915 const RegMask &umask = n->in_RegMask(inpidx); 916 917 assert(inpidx < oopoff, "cannot use-split oop map info"); 918 919 bool dup = UPblock[slidx]; 920 bool uup = umask.is_UP(); 921 922 // Need special logic to handle bound USES. Insert a split at this 923 // bound use if we can't rematerialize the def, or if we need the 924 // split to form a misaligned pair. 925 if( !umask.is_AllStack() && 926 (int)umask.Size() <= lrgs(useidx).num_regs() && 927 (!def->rematerialize() || 928 umask.is_misaligned_Pair())) { 929 // These need a Split regardless of overlap or pressure 930 // SPLIT - NO DEF - NO CISC SPILL 931 maxlrg = split_USE(def,b,n,inpidx,maxlrg,dup,false, splits,slidx); 932 // If it wasn't split bail 933 if (!maxlrg) { 934 return 0; 935 } 936 insidx++; // Reset iterator to skip USE side split 937 continue; 938 } 939 // Here is the logic chart which describes USE Splitting: 940 // 0 = false or DOWN, 1 = true or UP 941 // 942 // Overlap | DEF | USE | Action 943 //------------------------------------------------------- 944 // 0 | 0 | 0 | Copy - mem -> mem 945 // 0 | 0 | 1 | Split-UP - Check HRP 946 // 0 | 1 | 0 | Split-DOWN - Debug Info? 947 // 0 | 1 | 1 | Copy - reg -> reg 948 // 1 | 0 | 0 | Reset Input Edge (no Split) 949 // 1 | 0 | 1 | Split-UP - Check HRP 950 // 1 | 1 | 0 | Split-DOWN - Debug Info? 951 // 1 | 1 | 1 | Reset Input Edge (no Split) 952 // 953 // So, if (dup == uup), then overlap test determines action, 954 // with true being no split, and false being copy. Else, 955 // if DEF is DOWN, Split-UP, and check HRP to decide on 956 // resetting DEF. Finally if DEF is UP, Split-DOWN, with 957 // special handling for Debug Info. 958 if( dup == uup ) { 959 if( dmask.overlap(umask) ) { 960 // Both are either up or down, and there is overlap, No Split 961 n->set_req(inpidx, def); 962 } 963 else { // Both are either up or down, and there is no overlap 964 if( dup ) { // If UP, reg->reg copy 965 // COPY ACROSS HERE - NO DEF - NO CISC SPILL 966 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx); 967 // If it wasn't split bail 968 if (!maxlrg) { 969 return 0; 970 } 971 insidx++; // Reset iterator to skip USE side split 972 } 973 else { // DOWN, mem->mem copy 974 // COPY UP & DOWN HERE - NO DEF - NO CISC SPILL 975 // First Split-UP to move value into Register 976 uint def_ideal = def->ideal_reg(); 977 const RegMask* tmp_rm = Matcher::idealreg2regmask[def_ideal]; 978 Node *spill = new (C) MachSpillCopyNode(def, dmask, *tmp_rm); 979 insert_proj( b, insidx, spill, maxlrg ); 980 // Then Split-DOWN as if previous Split was DEF 981 maxlrg = split_USE(spill,b,n,inpidx,maxlrg,false,false, splits,slidx); 982 // If it wasn't split bail 983 if (!maxlrg) { 984 return 0; 985 } 986 insidx += 2; // Reset iterator to skip USE side splits 987 } 988 } // End else no overlap 989 } // End if dup == uup 990 // dup != uup, so check dup for direction of Split 991 else { 992 if( dup ) { // If UP, Split-DOWN and check Debug Info 993 // If this node is already a SpillCopy, just patch the edge 994 // except the case of spilling to stack. 995 if( n->is_SpillCopy() ) { 996 RegMask tmp_rm(umask); 997 tmp_rm.SUBTRACT(Matcher::STACK_ONLY_mask); 998 if( dmask.overlap(tmp_rm) ) { 999 if( def != n->in(inpidx) ) { 1000 n->set_req(inpidx, def); 1001 } 1002 continue; 1003 } 1004 } 1005 // COPY DOWN HERE - NO DEF - NO CISC SPILL 1006 maxlrg = split_USE(def,b,n,inpidx,maxlrg,false,false, splits,slidx); 1007 // If it wasn't split bail 1008 if (!maxlrg) { 1009 return 0; 1010 } 1011 insidx++; // Reset iterator to skip USE side split 1012 // Check for debug-info split. Capture it for later 1013 // debug splits of the same value 1014 if (jvms && jvms->debug_start() <= inpidx && inpidx < oopoff) 1015 debug_defs[slidx] = n->in(inpidx); 1016 1017 } 1018 else { // DOWN, Split-UP and check register pressure 1019 if( is_high_pressure( b, &lrgs(useidx), insidx ) ) { 1020 // COPY UP HERE - NO DEF - CISC SPILL 1021 maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,true, splits,slidx); 1022 // If it wasn't split bail 1023 if (!maxlrg) { 1024 return 0; 1025 } 1026 insidx++; // Reset iterator to skip USE side split 1027 } else { // LRP 1028 // COPY UP HERE - WITH DEF - NO CISC SPILL 1029 maxlrg = split_USE(def,b,n,inpidx,maxlrg,true,false, splits,slidx); 1030 // If it wasn't split bail 1031 if (!maxlrg) { 1032 return 0; 1033 } 1034 // Flag this lift-up in a low-pressure block as 1035 // already-spilled, so if it spills again it will 1036 // spill hard (instead of not spilling hard and 1037 // coalescing away). 1038 set_was_spilled(n->in(inpidx)); 1039 // Since this is a new DEF, update Reachblock & UP 1040 Reachblock[slidx] = n->in(inpidx); 1041 UPblock[slidx] = true; 1042 insidx++; // Reset iterator to skip USE side split 1043 } 1044 } // End else DOWN 1045 } // End dup != uup 1046 } // End if Spill USE 1047 } // End For All Inputs 1048 } // End If not nullcheck 1049 1050 // ********** Handle DEFS ********** 1051 // DEFS either Split DOWN in HRP regions or when the LRG is bound, or 1052 // just reset the Reaches info in LRP regions. DEFS must always update 1053 // UP info. 1054 if( deflrg.reg() >= LRG::SPILL_REG ) { // Spilled? 1055 uint slidx = lrg2reach[defidx]; 1056 // Add to defs list for later assignment of new live range number 1057 defs->push(n); 1058 // Set a flag on the Node indicating it has already spilled. 1059 // Only do it for capacity spills not conflict spills. 1060 if( !deflrg._direct_conflict ) 1061 set_was_spilled(n); 1062 assert(!n->is_Phi(),"Cannot insert Phi into DEFS list"); 1063 // Grab UP info for DEF 1064 const RegMask &dmask = n->out_RegMask(); 1065 bool defup = dmask.is_UP(); 1066 // Only split at Def if this is a HRP block or bound (and spilled once) 1067 if( !n->rematerialize() && 1068 (((dmask.is_bound1() || dmask.is_bound2() || dmask.is_misaligned_Pair()) && 1069 (deflrg._direct_conflict || deflrg._must_spill)) || 1070 // Check for LRG being up in a register and we are inside a high 1071 // pressure area. Spill it down immediately. 1072 (defup && is_high_pressure(b,&deflrg,insidx))) ) { 1073 assert( !n->rematerialize(), "" ); 1074 assert( !n->is_SpillCopy(), "" ); 1075 // Do a split at the def site. 1076 maxlrg = split_DEF( n, b, insidx, maxlrg, Reachblock, debug_defs, splits, slidx ); 1077 // If it wasn't split bail 1078 if (!maxlrg) { 1079 return 0; 1080 } 1081 // Split DEF's Down 1082 UPblock[slidx] = 0; 1083#ifndef PRODUCT 1084 // DEBUG 1085 if( trace_spilling() ) { 1086 tty->print("\nNew Split DOWN DEF of Spill Idx "); 1087 tty->print("%d, UP %d:\n",slidx,false); 1088 n->dump(); 1089 } 1090#endif 1091 } 1092 else { // Neither bound nor HRP, must be LRP 1093 // otherwise, just record the def 1094 Reachblock[slidx] = n; 1095 // UP should come from the outRegmask() of the DEF 1096 UPblock[slidx] = defup; 1097 // Update debug list of reaching down definitions, kill if DEF is UP 1098 debug_defs[slidx] = defup ? NULL : n; 1099#ifndef PRODUCT 1100 // DEBUG 1101 if( trace_spilling() ) { 1102 tty->print("\nNew DEF of Spill Idx "); 1103 tty->print("%d, UP %d:\n",slidx,defup); 1104 n->dump(); 1105 } 1106#endif 1107 } // End else LRP 1108 } // End if spill def 1109 1110 // ********** Split Left Over Mem-Mem Moves ********** 1111 // Check for mem-mem copies and split them now. Do not do this 1112 // to copies about to be spilled; they will be Split shortly. 1113 if( copyidx ) { 1114 Node *use = n->in(copyidx); 1115 uint useidx = Find_id(use); 1116 if( useidx < _maxlrg && // This is not a new split 1117 OptoReg::is_stack(deflrg.reg()) && 1118 deflrg.reg() < LRG::SPILL_REG ) { // And DEF is from stack 1119 LRG &uselrg = lrgs(useidx); 1120 if( OptoReg::is_stack(uselrg.reg()) && 1121 uselrg.reg() < LRG::SPILL_REG && // USE is from stack 1122 deflrg.reg() != uselrg.reg() ) { // Not trivially removed 1123 uint def_ideal_reg = Matcher::base2reg[n->bottom_type()->base()]; 1124 const RegMask &def_rm = *Matcher::idealreg2regmask[def_ideal_reg]; 1125 const RegMask &use_rm = n->in_RegMask(copyidx); 1126 if( def_rm.overlap(use_rm) && n->is_SpillCopy() ) { // Bug 4707800, 'n' may be a storeSSL 1127 if (C->check_node_count(NodeLimitFudgeFactor, out_of_nodes)) { // Check when generating nodes 1128 return 0; 1129 } 1130 Node *spill = new (C) MachSpillCopyNode(use,use_rm,def_rm); 1131 n->set_req(copyidx,spill); 1132 n->as_MachSpillCopy()->set_in_RegMask(def_rm); 1133 // Put the spill just before the copy 1134 insert_proj( b, insidx++, spill, maxlrg++ ); 1135 } 1136 } 1137 } 1138 } 1139 } // End For All Instructions in Block - Non-PHI Pass 1140 1141 // Check if each LRG is live out of this block so as not to propagate 1142 // beyond the last use of a LRG. 1143 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 1144 uint defidx = lidxs.at(slidx); 1145 IndexSet *liveout = _live->live(b); 1146 if( !liveout->member(defidx) ) { 1147#ifdef ASSERT 1148 // The index defidx is not live. Check the liveout array to ensure that 1149 // it contains no members which compress to defidx. Finding such an 1150 // instance may be a case to add liveout adjustment in compress_uf_map(). 1151 // See 5063219. 1152 uint member; 1153 IndexSetIterator isi(liveout); 1154 while ((member = isi.next()) != 0) { 1155 assert(defidx != Find_const(member), "Live out member has not been compressed"); 1156 } 1157#endif 1158 Reachblock[slidx] = NULL; 1159 } else { 1160 assert(Reachblock[slidx] != NULL,"No reaching definition for liveout value"); 1161 } 1162 } 1163#ifndef PRODUCT 1164 if( trace_spilling() ) 1165 b->dump(); 1166#endif 1167 } // End For All Blocks 1168 1169 //----------PASS 2---------- 1170 // Reset all DEF live range numbers here 1171 for( insidx = 0; insidx < defs->size(); insidx++ ) { 1172 // Grab the def 1173 n1 = defs->at(insidx); 1174 // Set new lidx for DEF 1175 new_lrg(n1, maxlrg++); 1176 } 1177 //----------Phi Node Splitting---------- 1178 // Clean up a phi here, and assign a new live range number 1179 // Cycle through this block's predecessors, collecting Reaches 1180 // info for each spilled LRG and update edges. 1181 // Walk the phis list to patch inputs, split phis, and name phis 1182 for( insidx = 0; insidx < phis->size(); insidx++ ) { 1183 Node *phi = phis->at(insidx); 1184 assert(phi->is_Phi(),"This list must only contain Phi Nodes"); 1185 Block *b = _cfg._bbs[phi->_idx]; 1186 // Grab the live range number 1187 uint lidx = Find_id(phi); 1188 uint slidx = lrg2reach[lidx]; 1189 // Update node to lidx map 1190 new_lrg(phi, maxlrg++); 1191 // Get PASS1's up/down decision for the block. 1192 int phi_up = !!UP_entry[slidx]->test(b->_pre_order); 1193 1194 // Force down if double-spilling live range 1195 if( lrgs(lidx)._was_spilled1 ) 1196 phi_up = false; 1197 1198 // When splitting a Phi we an split it normal or "inverted". 1199 // An inverted split makes the splits target the Phi's UP/DOWN 1200 // sense inverted; then the Phi is followed by a final def-side 1201 // split to invert back. It changes which blocks the spill code 1202 // goes in. 1203 1204 // Walk the predecessor blocks and assign the reaching def to the Phi. 1205 // Split Phi nodes by placing USE side splits wherever the reaching 1206 // DEF has the wrong UP/DOWN value. 1207 for( uint i = 1; i < b->num_preds(); i++ ) { 1208 // Get predecessor block pre-order number 1209 Block *pred = _cfg._bbs[b->pred(i)->_idx]; 1210 pidx = pred->_pre_order; 1211 // Grab reaching def 1212 Node *def = Reaches[pidx][slidx]; 1213 assert( def, "must have reaching def" ); 1214 // If input up/down sense and reg-pressure DISagree 1215 if( def->rematerialize() ) { 1216 def = split_Rematerialize( def, pred, pred->end_idx(), maxlrg, splits, slidx, lrg2reach, Reachblock, false ); 1217 if( !def ) return 0; // Bail out 1218 } 1219 // Update the Phi's input edge array 1220 phi->set_req(i,def); 1221 // Grab the UP/DOWN sense for the input 1222 u1 = UP[pidx][slidx]; 1223 if( u1 != (phi_up != 0)) { 1224 maxlrg = split_USE(def, b, phi, i, maxlrg, !u1, false, splits,slidx); 1225 // If it wasn't split bail 1226 if (!maxlrg) { 1227 return 0; 1228 } 1229 } 1230 } // End for all inputs to the Phi 1231 } // End for all Phi Nodes 1232 // Update _maxlrg to save Union asserts 1233 _maxlrg = maxlrg; 1234 1235 1236 //----------PASS 3---------- 1237 // Pass over all Phi's to union the live ranges 1238 for( insidx = 0; insidx < phis->size(); insidx++ ) { 1239 Node *phi = phis->at(insidx); 1240 assert(phi->is_Phi(),"This list must only contain Phi Nodes"); 1241 // Walk all inputs to Phi and Union input live range with Phi live range 1242 for( uint i = 1; i < phi->req(); i++ ) { 1243 // Grab the input node 1244 Node *n = phi->in(i); 1245 assert( n, "" ); 1246 uint lidx = Find(n); 1247 uint pidx = Find(phi); 1248 if( lidx < pidx ) 1249 Union(n, phi); 1250 else if( lidx > pidx ) 1251 Union(phi, n); 1252 } // End for all inputs to the Phi Node 1253 } // End for all Phi Nodes 1254 // Now union all two address instructions 1255 for( insidx = 0; insidx < defs->size(); insidx++ ) { 1256 // Grab the def 1257 n1 = defs->at(insidx); 1258 // Set new lidx for DEF & handle 2-addr instructions 1259 if( n1->is_Mach() && ((twoidx = n1->as_Mach()->two_adr()) != 0) ) { 1260 assert( Find(n1->in(twoidx)) < maxlrg,"Assigning bad live range index"); 1261 // Union the input and output live ranges 1262 uint lr1 = Find(n1); 1263 uint lr2 = Find(n1->in(twoidx)); 1264 if( lr1 < lr2 ) 1265 Union(n1, n1->in(twoidx)); 1266 else if( lr1 > lr2 ) 1267 Union(n1->in(twoidx), n1); 1268 } // End if two address 1269 } // End for all defs 1270 // DEBUG 1271#ifdef ASSERT 1272 // Validate all live range index assignments 1273 for( bidx = 0; bidx < _cfg._num_blocks; bidx++ ) { 1274 b = _cfg._blocks[bidx]; 1275 for( insidx = 0; insidx <= b->end_idx(); insidx++ ) { 1276 Node *n = b->_nodes[insidx]; 1277 uint defidx = Find(n); 1278 assert(defidx < _maxlrg,"Bad live range index in Split"); 1279 assert(defidx < maxlrg,"Bad live range index in Split"); 1280 } 1281 } 1282 // Issue a warning if splitting made no progress 1283 int noprogress = 0; 1284 for( slidx = 0; slidx < spill_cnt; slidx++ ) { 1285 if( PrintOpto && WizardMode && splits.at(slidx) == 0 ) { 1286 tty->print_cr("Failed to split live range %d", lidxs.at(slidx)); 1287 //BREAKPOINT; 1288 } 1289 else { 1290 noprogress++; 1291 } 1292 } 1293 if(!noprogress) { 1294 tty->print_cr("Failed to make progress in Split"); 1295 //BREAKPOINT; 1296 } 1297#endif 1298 // Return updated count of live ranges 1299 return maxlrg; 1300} 1301