matcher.cpp revision 3602:da91efe96a93
1/* 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25#include "precompiled.hpp" 26#include "memory/allocation.inline.hpp" 27#include "opto/addnode.hpp" 28#include "opto/callnode.hpp" 29#include "opto/connode.hpp" 30#include "opto/idealGraphPrinter.hpp" 31#include "opto/matcher.hpp" 32#include "opto/memnode.hpp" 33#include "opto/opcodes.hpp" 34#include "opto/regmask.hpp" 35#include "opto/rootnode.hpp" 36#include "opto/runtime.hpp" 37#include "opto/type.hpp" 38#include "opto/vectornode.hpp" 39#include "runtime/atomic.hpp" 40#include "runtime/os.hpp" 41#ifdef TARGET_ARCH_MODEL_x86_32 42# include "adfiles/ad_x86_32.hpp" 43#endif 44#ifdef TARGET_ARCH_MODEL_x86_64 45# include "adfiles/ad_x86_64.hpp" 46#endif 47#ifdef TARGET_ARCH_MODEL_sparc 48# include "adfiles/ad_sparc.hpp" 49#endif 50#ifdef TARGET_ARCH_MODEL_zero 51# include "adfiles/ad_zero.hpp" 52#endif 53#ifdef TARGET_ARCH_MODEL_arm 54# include "adfiles/ad_arm.hpp" 55#endif 56#ifdef TARGET_ARCH_MODEL_ppc 57# include "adfiles/ad_ppc.hpp" 58#endif 59 60OptoReg::Name OptoReg::c_frame_pointer; 61 62const RegMask *Matcher::idealreg2regmask[_last_machine_leaf]; 63RegMask Matcher::mreg2regmask[_last_Mach_Reg]; 64RegMask Matcher::STACK_ONLY_mask; 65RegMask Matcher::c_frame_ptr_mask; 66const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE; 67const uint Matcher::_end_rematerialize = _END_REMATERIALIZE; 68 69//---------------------------Matcher------------------------------------------- 70Matcher::Matcher( Node_List &proj_list ) : 71 PhaseTransform( Phase::Ins_Select ), 72#ifdef ASSERT 73 _old2new_map(C->comp_arena()), 74 _new2old_map(C->comp_arena()), 75#endif 76 _shared_nodes(C->comp_arena()), 77 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp), 78 _swallowed(swallowed), 79 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE), 80 _end_inst_chain_rule(_END_INST_CHAIN_RULE), 81 _must_clone(must_clone), _proj_list(proj_list), 82 _register_save_policy(register_save_policy), 83 _c_reg_save_policy(c_reg_save_policy), 84 _register_save_type(register_save_type), 85 _ruleName(ruleName), 86 _allocation_started(false), 87 _states_arena(Chunk::medium_size), 88 _visited(&_states_arena), 89 _shared(&_states_arena), 90 _dontcare(&_states_arena) { 91 C->set_matcher(this); 92 93 idealreg2spillmask [Op_RegI] = NULL; 94 idealreg2spillmask [Op_RegN] = NULL; 95 idealreg2spillmask [Op_RegL] = NULL; 96 idealreg2spillmask [Op_RegF] = NULL; 97 idealreg2spillmask [Op_RegD] = NULL; 98 idealreg2spillmask [Op_RegP] = NULL; 99 idealreg2spillmask [Op_VecS] = NULL; 100 idealreg2spillmask [Op_VecD] = NULL; 101 idealreg2spillmask [Op_VecX] = NULL; 102 idealreg2spillmask [Op_VecY] = NULL; 103 104 idealreg2debugmask [Op_RegI] = NULL; 105 idealreg2debugmask [Op_RegN] = NULL; 106 idealreg2debugmask [Op_RegL] = NULL; 107 idealreg2debugmask [Op_RegF] = NULL; 108 idealreg2debugmask [Op_RegD] = NULL; 109 idealreg2debugmask [Op_RegP] = NULL; 110 idealreg2debugmask [Op_VecS] = NULL; 111 idealreg2debugmask [Op_VecD] = NULL; 112 idealreg2debugmask [Op_VecX] = NULL; 113 idealreg2debugmask [Op_VecY] = NULL; 114 115 idealreg2mhdebugmask[Op_RegI] = NULL; 116 idealreg2mhdebugmask[Op_RegN] = NULL; 117 idealreg2mhdebugmask[Op_RegL] = NULL; 118 idealreg2mhdebugmask[Op_RegF] = NULL; 119 idealreg2mhdebugmask[Op_RegD] = NULL; 120 idealreg2mhdebugmask[Op_RegP] = NULL; 121 idealreg2mhdebugmask[Op_VecS] = NULL; 122 idealreg2mhdebugmask[Op_VecD] = NULL; 123 idealreg2mhdebugmask[Op_VecX] = NULL; 124 idealreg2mhdebugmask[Op_VecY] = NULL; 125 126 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node 127} 128 129//------------------------------warp_incoming_stk_arg------------------------ 130// This warps a VMReg into an OptoReg::Name 131OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) { 132 OptoReg::Name warped; 133 if( reg->is_stack() ) { // Stack slot argument? 134 warped = OptoReg::add(_old_SP, reg->reg2stack() ); 135 warped = OptoReg::add(warped, C->out_preserve_stack_slots()); 136 if( warped >= _in_arg_limit ) 137 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen 138 if (!RegMask::can_represent_arg(warped)) { 139 // the compiler cannot represent this method's calling sequence 140 C->record_method_not_compilable_all_tiers("unsupported incoming calling sequence"); 141 return OptoReg::Bad; 142 } 143 return warped; 144 } 145 return OptoReg::as_OptoReg(reg); 146} 147 148//---------------------------compute_old_SP------------------------------------ 149OptoReg::Name Compile::compute_old_SP() { 150 int fixed = fixed_slots(); 151 int preserve = in_preserve_stack_slots(); 152 return OptoReg::stack2reg(round_to(fixed + preserve, Matcher::stack_alignment_in_slots())); 153} 154 155 156 157#ifdef ASSERT 158void Matcher::verify_new_nodes_only(Node* xroot) { 159 // Make sure that the new graph only references new nodes 160 ResourceMark rm; 161 Unique_Node_List worklist; 162 VectorSet visited(Thread::current()->resource_area()); 163 worklist.push(xroot); 164 while (worklist.size() > 0) { 165 Node* n = worklist.pop(); 166 visited <<= n->_idx; 167 assert(C->node_arena()->contains(n), "dead node"); 168 for (uint j = 0; j < n->req(); j++) { 169 Node* in = n->in(j); 170 if (in != NULL) { 171 assert(C->node_arena()->contains(in), "dead node"); 172 if (!visited.test(in->_idx)) { 173 worklist.push(in); 174 } 175 } 176 } 177 } 178} 179#endif 180 181 182//---------------------------match--------------------------------------------- 183void Matcher::match( ) { 184 if( MaxLabelRootDepth < 100 ) { // Too small? 185 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum"); 186 MaxLabelRootDepth = 100; 187 } 188 // One-time initialization of some register masks. 189 init_spill_mask( C->root()->in(1) ); 190 _return_addr_mask = return_addr(); 191#ifdef _LP64 192 // Pointers take 2 slots in 64-bit land 193 _return_addr_mask.Insert(OptoReg::add(return_addr(),1)); 194#endif 195 196 // Map a Java-signature return type into return register-value 197 // machine registers for 0, 1 and 2 returned values. 198 const TypeTuple *range = C->tf()->range(); 199 if( range->cnt() > TypeFunc::Parms ) { // If not a void function 200 // Get ideal-register return type 201 int ireg = range->field_at(TypeFunc::Parms)->ideal_reg(); 202 // Get machine return register 203 uint sop = C->start()->Opcode(); 204 OptoRegPair regs = return_value(ireg, false); 205 206 // And mask for same 207 _return_value_mask = RegMask(regs.first()); 208 if( OptoReg::is_valid(regs.second()) ) 209 _return_value_mask.Insert(regs.second()); 210 } 211 212 // --------------- 213 // Frame Layout 214 215 // Need the method signature to determine the incoming argument types, 216 // because the types determine which registers the incoming arguments are 217 // in, and this affects the matched code. 218 const TypeTuple *domain = C->tf()->domain(); 219 uint argcnt = domain->cnt() - TypeFunc::Parms; 220 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 221 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 222 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt ); 223 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt ); 224 uint i; 225 for( i = 0; i<argcnt; i++ ) { 226 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 227 } 228 229 // Pass array of ideal registers and length to USER code (from the AD file) 230 // that will convert this to an array of register numbers. 231 const StartNode *start = C->start(); 232 start->calling_convention( sig_bt, vm_parm_regs, argcnt ); 233#ifdef ASSERT 234 // Sanity check users' calling convention. Real handy while trying to 235 // get the initial port correct. 236 { for (uint i = 0; i<argcnt; i++) { 237 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 238 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" ); 239 _parm_regs[i].set_bad(); 240 continue; 241 } 242 VMReg parm_reg = vm_parm_regs[i].first(); 243 assert(parm_reg->is_valid(), "invalid arg?"); 244 if (parm_reg->is_reg()) { 245 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg); 246 assert(can_be_java_arg(opto_parm_reg) || 247 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) || 248 opto_parm_reg == inline_cache_reg(), 249 "parameters in register must be preserved by runtime stubs"); 250 } 251 for (uint j = 0; j < i; j++) { 252 assert(parm_reg != vm_parm_regs[j].first(), 253 "calling conv. must produce distinct regs"); 254 } 255 } 256 } 257#endif 258 259 // Do some initial frame layout. 260 261 // Compute the old incoming SP (may be called FP) as 262 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2. 263 _old_SP = C->compute_old_SP(); 264 assert( is_even(_old_SP), "must be even" ); 265 266 // Compute highest incoming stack argument as 267 // _old_SP + out_preserve_stack_slots + incoming argument size. 268 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 269 assert( is_even(_in_arg_limit), "out_preserve must be even" ); 270 for( i = 0; i < argcnt; i++ ) { 271 // Permit args to have no register 272 _calling_convention_mask[i].Clear(); 273 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 274 continue; 275 } 276 // calling_convention returns stack arguments as a count of 277 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to 278 // the allocators point of view, taking into account all the 279 // preserve area, locks & pad2. 280 281 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first()); 282 if( OptoReg::is_valid(reg1)) 283 _calling_convention_mask[i].Insert(reg1); 284 285 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second()); 286 if( OptoReg::is_valid(reg2)) 287 _calling_convention_mask[i].Insert(reg2); 288 289 // Saved biased stack-slot register number 290 _parm_regs[i].set_pair(reg2, reg1); 291 } 292 293 // Finally, make sure the incoming arguments take up an even number of 294 // words, in case the arguments or locals need to contain doubleword stack 295 // slots. The rest of the system assumes that stack slot pairs (in 296 // particular, in the spill area) which look aligned will in fact be 297 // aligned relative to the stack pointer in the target machine. Double 298 // stack slots will always be allocated aligned. 299 _new_SP = OptoReg::Name(round_to(_in_arg_limit, RegMask::SlotsPerLong)); 300 301 // Compute highest outgoing stack argument as 302 // _new_SP + out_preserve_stack_slots + max(outgoing argument size). 303 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 304 assert( is_even(_out_arg_limit), "out_preserve must be even" ); 305 306 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) { 307 // the compiler cannot represent this method's calling sequence 308 C->record_method_not_compilable("must be able to represent all call arguments in reg mask"); 309 } 310 311 if (C->failing()) return; // bailed out on incoming arg failure 312 313 // --------------- 314 // Collect roots of matcher trees. Every node for which 315 // _shared[_idx] is cleared is guaranteed to not be shared, and thus 316 // can be a valid interior of some tree. 317 find_shared( C->root() ); 318 find_shared( C->top() ); 319 320 C->print_method("Before Matching"); 321 322 // Create new ideal node ConP #NULL even if it does exist in old space 323 // to avoid false sharing if the corresponding mach node is not used. 324 // The corresponding mach node is only used in rare cases for derived 325 // pointers. 326 Node* new_ideal_null = ConNode::make(C, TypePtr::NULL_PTR); 327 328 // Swap out to old-space; emptying new-space 329 Arena *old = C->node_arena()->move_contents(C->old_arena()); 330 331 // Save debug and profile information for nodes in old space: 332 _old_node_note_array = C->node_note_array(); 333 if (_old_node_note_array != NULL) { 334 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*> 335 (C->comp_arena(), _old_node_note_array->length(), 336 0, NULL)); 337 } 338 339 // Pre-size the new_node table to avoid the need for range checks. 340 grow_new_node_array(C->unique()); 341 342 // Reset node counter so MachNodes start with _idx at 0 343 int nodes = C->unique(); // save value 344 C->set_unique(0); 345 346 // Recursively match trees from old space into new space. 347 // Correct leaves of new-space Nodes; they point to old-space. 348 _visited.Clear(); // Clear visit bits for xform call 349 C->set_cached_top_node(xform( C->top(), nodes )); 350 if (!C->failing()) { 351 Node* xroot = xform( C->root(), 1 ); 352 if (xroot == NULL) { 353 Matcher::soft_match_failure(); // recursive matching process failed 354 C->record_method_not_compilable("instruction match failed"); 355 } else { 356 // During matching shared constants were attached to C->root() 357 // because xroot wasn't available yet, so transfer the uses to 358 // the xroot. 359 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) { 360 Node* n = C->root()->fast_out(j); 361 if (C->node_arena()->contains(n)) { 362 assert(n->in(0) == C->root(), "should be control user"); 363 n->set_req(0, xroot); 364 --j; 365 --jmax; 366 } 367 } 368 369 // Generate new mach node for ConP #NULL 370 assert(new_ideal_null != NULL, "sanity"); 371 _mach_null = match_tree(new_ideal_null); 372 // Don't set control, it will confuse GCM since there are no uses. 373 // The control will be set when this node is used first time 374 // in find_base_for_derived(). 375 assert(_mach_null != NULL, ""); 376 377 C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL); 378 379#ifdef ASSERT 380 verify_new_nodes_only(xroot); 381#endif 382 } 383 } 384 if (C->top() == NULL || C->root() == NULL) { 385 C->record_method_not_compilable("graph lost"); // %%% cannot happen? 386 } 387 if (C->failing()) { 388 // delete old; 389 old->destruct_contents(); 390 return; 391 } 392 assert( C->top(), "" ); 393 assert( C->root(), "" ); 394 validate_null_checks(); 395 396 // Now smoke old-space 397 NOT_DEBUG( old->destruct_contents() ); 398 399 // ------------------------ 400 // Set up save-on-entry registers 401 Fixup_Save_On_Entry( ); 402} 403 404 405//------------------------------Fixup_Save_On_Entry---------------------------- 406// The stated purpose of this routine is to take care of save-on-entry 407// registers. However, the overall goal of the Match phase is to convert into 408// machine-specific instructions which have RegMasks to guide allocation. 409// So what this procedure really does is put a valid RegMask on each input 410// to the machine-specific variations of all Return, TailCall and Halt 411// instructions. It also adds edgs to define the save-on-entry values (and of 412// course gives them a mask). 413 414static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) { 415 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size ); 416 // Do all the pre-defined register masks 417 rms[TypeFunc::Control ] = RegMask::Empty; 418 rms[TypeFunc::I_O ] = RegMask::Empty; 419 rms[TypeFunc::Memory ] = RegMask::Empty; 420 rms[TypeFunc::ReturnAdr] = ret_adr; 421 rms[TypeFunc::FramePtr ] = fp; 422 return rms; 423} 424 425//---------------------------init_first_stack_mask----------------------------- 426// Create the initial stack mask used by values spilling to the stack. 427// Disallow any debug info in outgoing argument areas by setting the 428// initial mask accordingly. 429void Matcher::init_first_stack_mask() { 430 431 // Allocate storage for spill masks as masks for the appropriate load type. 432 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+4)); 433 434 idealreg2spillmask [Op_RegN] = &rms[0]; 435 idealreg2spillmask [Op_RegI] = &rms[1]; 436 idealreg2spillmask [Op_RegL] = &rms[2]; 437 idealreg2spillmask [Op_RegF] = &rms[3]; 438 idealreg2spillmask [Op_RegD] = &rms[4]; 439 idealreg2spillmask [Op_RegP] = &rms[5]; 440 441 idealreg2debugmask [Op_RegN] = &rms[6]; 442 idealreg2debugmask [Op_RegI] = &rms[7]; 443 idealreg2debugmask [Op_RegL] = &rms[8]; 444 idealreg2debugmask [Op_RegF] = &rms[9]; 445 idealreg2debugmask [Op_RegD] = &rms[10]; 446 idealreg2debugmask [Op_RegP] = &rms[11]; 447 448 idealreg2mhdebugmask[Op_RegN] = &rms[12]; 449 idealreg2mhdebugmask[Op_RegI] = &rms[13]; 450 idealreg2mhdebugmask[Op_RegL] = &rms[14]; 451 idealreg2mhdebugmask[Op_RegF] = &rms[15]; 452 idealreg2mhdebugmask[Op_RegD] = &rms[16]; 453 idealreg2mhdebugmask[Op_RegP] = &rms[17]; 454 455 idealreg2spillmask [Op_VecS] = &rms[18]; 456 idealreg2spillmask [Op_VecD] = &rms[19]; 457 idealreg2spillmask [Op_VecX] = &rms[20]; 458 idealreg2spillmask [Op_VecY] = &rms[21]; 459 460 OptoReg::Name i; 461 462 // At first, start with the empty mask 463 C->FIRST_STACK_mask().Clear(); 464 465 // Add in the incoming argument area 466 OptoReg::Name init = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 467 for (i = init; i < _in_arg_limit; i = OptoReg::add(i,1)) 468 C->FIRST_STACK_mask().Insert(i); 469 470 // Add in all bits past the outgoing argument area 471 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)), 472 "must be able to represent all call arguments in reg mask"); 473 init = _out_arg_limit; 474 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) 475 C->FIRST_STACK_mask().Insert(i); 476 477 // Finally, set the "infinite stack" bit. 478 C->FIRST_STACK_mask().set_AllStack(); 479 480 // Make spill masks. Registers for their class, plus FIRST_STACK_mask. 481 RegMask aligned_stack_mask = C->FIRST_STACK_mask(); 482 // Keep spill masks aligned. 483 aligned_stack_mask.clear_to_pairs(); 484 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 485 486 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP]; 487#ifdef _LP64 488 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN]; 489 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask()); 490 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask); 491#else 492 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask()); 493#endif 494 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI]; 495 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask()); 496 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL]; 497 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask); 498 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF]; 499 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask()); 500 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD]; 501 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask); 502 503 if (Matcher::vector_size_supported(T_BYTE,4)) { 504 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS]; 505 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask()); 506 } 507 if (Matcher::vector_size_supported(T_FLOAT,2)) { 508 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD]; 509 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask); 510 } 511 if (Matcher::vector_size_supported(T_FLOAT,4)) { 512 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX); 513 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 514 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX]; 515 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask); 516 } 517 if (Matcher::vector_size_supported(T_FLOAT,8)) { 518 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY); 519 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 520 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY]; 521 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask); 522 } 523 if (UseFPUForSpilling) { 524 // This mask logic assumes that the spill operations are 525 // symmetric and that the registers involved are the same size. 526 // On sparc for instance we may have to use 64 bit moves will 527 // kill 2 registers when used with F0-F31. 528 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]); 529 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]); 530#ifdef _LP64 531 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]); 532 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 533 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 534 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); 535#else 536 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); 537#ifdef ARM 538 // ARM has support for moving 64bit values between a pair of 539 // integer registers and a double register 540 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 541 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 542#endif 543#endif 544 } 545 546 // Make up debug masks. Any spill slot plus callee-save registers. 547 // Caller-save registers are assumed to be trashable by the various 548 // inline-cache fixup routines. 549 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN]; 550 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI]; 551 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL]; 552 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF]; 553 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD]; 554 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP]; 555 556 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN]; 557 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI]; 558 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL]; 559 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF]; 560 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD]; 561 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP]; 562 563 // Prevent stub compilations from attempting to reference 564 // callee-saved registers from debug info 565 bool exclude_soe = !Compile::current()->is_method_compilation(); 566 567 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { 568 // registers the caller has to save do not work 569 if( _register_save_policy[i] == 'C' || 570 _register_save_policy[i] == 'A' || 571 (_register_save_policy[i] == 'E' && exclude_soe) ) { 572 idealreg2debugmask [Op_RegN]->Remove(i); 573 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call 574 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug 575 idealreg2debugmask [Op_RegF]->Remove(i); // masks 576 idealreg2debugmask [Op_RegD]->Remove(i); 577 idealreg2debugmask [Op_RegP]->Remove(i); 578 579 idealreg2mhdebugmask[Op_RegN]->Remove(i); 580 idealreg2mhdebugmask[Op_RegI]->Remove(i); 581 idealreg2mhdebugmask[Op_RegL]->Remove(i); 582 idealreg2mhdebugmask[Op_RegF]->Remove(i); 583 idealreg2mhdebugmask[Op_RegD]->Remove(i); 584 idealreg2mhdebugmask[Op_RegP]->Remove(i); 585 } 586 } 587 588 // Subtract the register we use to save the SP for MethodHandle 589 // invokes to from the debug mask. 590 const RegMask save_mask = method_handle_invoke_SP_save_mask(); 591 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask); 592 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask); 593 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask); 594 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask); 595 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask); 596 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask); 597} 598 599//---------------------------is_save_on_entry---------------------------------- 600bool Matcher::is_save_on_entry( int reg ) { 601 return 602 _register_save_policy[reg] == 'E' || 603 _register_save_policy[reg] == 'A' || // Save-on-entry register? 604 // Also save argument registers in the trampolining stubs 605 (C->save_argument_registers() && is_spillable_arg(reg)); 606} 607 608//---------------------------Fixup_Save_On_Entry------------------------------- 609void Matcher::Fixup_Save_On_Entry( ) { 610 init_first_stack_mask(); 611 612 Node *root = C->root(); // Short name for root 613 // Count number of save-on-entry registers. 614 uint soe_cnt = number_of_saved_registers(); 615 uint i; 616 617 // Find the procedure Start Node 618 StartNode *start = C->start(); 619 assert( start, "Expect a start node" ); 620 621 // Save argument registers in the trampolining stubs 622 if( C->save_argument_registers() ) 623 for( i = 0; i < _last_Mach_Reg; i++ ) 624 if( is_spillable_arg(i) ) 625 soe_cnt++; 626 627 // Input RegMask array shared by all Returns. 628 // The type for doubles and longs has a count of 2, but 629 // there is only 1 returned value 630 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1); 631 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 632 // Returns have 0 or 1 returned values depending on call signature. 633 // Return register is specified by return_value in the AD file. 634 if (ret_edge_cnt > TypeFunc::Parms) 635 ret_rms[TypeFunc::Parms+0] = _return_value_mask; 636 637 // Input RegMask array shared by all Rethrows. 638 uint reth_edge_cnt = TypeFunc::Parms+1; 639 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 640 // Rethrow takes exception oop only, but in the argument 0 slot. 641 reth_rms[TypeFunc::Parms] = mreg2regmask[find_receiver(false)]; 642#ifdef _LP64 643 // Need two slots for ptrs in 64-bit land 644 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(find_receiver(false)),1)); 645#endif 646 647 // Input RegMask array shared by all TailCalls 648 uint tail_call_edge_cnt = TypeFunc::Parms+2; 649 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 650 651 // Input RegMask array shared by all TailJumps 652 uint tail_jump_edge_cnt = TypeFunc::Parms+2; 653 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 654 655 // TailCalls have 2 returned values (target & moop), whose masks come 656 // from the usual MachNode/MachOper mechanism. Find a sample 657 // TailCall to extract these masks and put the correct masks into 658 // the tail_call_rms array. 659 for( i=1; i < root->req(); i++ ) { 660 MachReturnNode *m = root->in(i)->as_MachReturn(); 661 if( m->ideal_Opcode() == Op_TailCall ) { 662 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 663 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 664 break; 665 } 666 } 667 668 // TailJumps have 2 returned values (target & ex_oop), whose masks come 669 // from the usual MachNode/MachOper mechanism. Find a sample 670 // TailJump to extract these masks and put the correct masks into 671 // the tail_jump_rms array. 672 for( i=1; i < root->req(); i++ ) { 673 MachReturnNode *m = root->in(i)->as_MachReturn(); 674 if( m->ideal_Opcode() == Op_TailJump ) { 675 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 676 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 677 break; 678 } 679 } 680 681 // Input RegMask array shared by all Halts 682 uint halt_edge_cnt = TypeFunc::Parms; 683 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 684 685 // Capture the return input masks into each exit flavor 686 for( i=1; i < root->req(); i++ ) { 687 MachReturnNode *exit = root->in(i)->as_MachReturn(); 688 switch( exit->ideal_Opcode() ) { 689 case Op_Return : exit->_in_rms = ret_rms; break; 690 case Op_Rethrow : exit->_in_rms = reth_rms; break; 691 case Op_TailCall : exit->_in_rms = tail_call_rms; break; 692 case Op_TailJump : exit->_in_rms = tail_jump_rms; break; 693 case Op_Halt : exit->_in_rms = halt_rms; break; 694 default : ShouldNotReachHere(); 695 } 696 } 697 698 // Next unused projection number from Start. 699 int proj_cnt = C->tf()->domain()->cnt(); 700 701 // Do all the save-on-entry registers. Make projections from Start for 702 // them, and give them a use at the exit points. To the allocator, they 703 // look like incoming register arguments. 704 for( i = 0; i < _last_Mach_Reg; i++ ) { 705 if( is_save_on_entry(i) ) { 706 707 // Add the save-on-entry to the mask array 708 ret_rms [ ret_edge_cnt] = mreg2regmask[i]; 709 reth_rms [ reth_edge_cnt] = mreg2regmask[i]; 710 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i]; 711 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i]; 712 // Halts need the SOE registers, but only in the stack as debug info. 713 // A just-prior uncommon-trap or deoptimization will use the SOE regs. 714 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]]; 715 716 Node *mproj; 717 718 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's 719 // into a single RegD. 720 if( (i&1) == 0 && 721 _register_save_type[i ] == Op_RegF && 722 _register_save_type[i+1] == Op_RegF && 723 is_save_on_entry(i+1) ) { 724 // Add other bit for double 725 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 726 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 727 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 728 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 729 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 730 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD ); 731 proj_cnt += 2; // Skip 2 for doubles 732 } 733 else if( (i&1) == 1 && // Else check for high half of double 734 _register_save_type[i-1] == Op_RegF && 735 _register_save_type[i ] == Op_RegF && 736 is_save_on_entry(i-1) ) { 737 ret_rms [ ret_edge_cnt] = RegMask::Empty; 738 reth_rms [ reth_edge_cnt] = RegMask::Empty; 739 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 740 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 741 halt_rms [ halt_edge_cnt] = RegMask::Empty; 742 mproj = C->top(); 743 } 744 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's 745 // into a single RegL. 746 else if( (i&1) == 0 && 747 _register_save_type[i ] == Op_RegI && 748 _register_save_type[i+1] == Op_RegI && 749 is_save_on_entry(i+1) ) { 750 // Add other bit for long 751 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 752 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 753 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 754 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 755 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 756 mproj = new (C, 1) MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL ); 757 proj_cnt += 2; // Skip 2 for longs 758 } 759 else if( (i&1) == 1 && // Else check for high half of long 760 _register_save_type[i-1] == Op_RegI && 761 _register_save_type[i ] == Op_RegI && 762 is_save_on_entry(i-1) ) { 763 ret_rms [ ret_edge_cnt] = RegMask::Empty; 764 reth_rms [ reth_edge_cnt] = RegMask::Empty; 765 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 766 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 767 halt_rms [ halt_edge_cnt] = RegMask::Empty; 768 mproj = C->top(); 769 } else { 770 // Make a projection for it off the Start 771 mproj = new (C, 1) MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] ); 772 } 773 774 ret_edge_cnt ++; 775 reth_edge_cnt ++; 776 tail_call_edge_cnt ++; 777 tail_jump_edge_cnt ++; 778 halt_edge_cnt ++; 779 780 // Add a use of the SOE register to all exit paths 781 for( uint j=1; j < root->req(); j++ ) 782 root->in(j)->add_req(mproj); 783 } // End of if a save-on-entry register 784 } // End of for all machine registers 785} 786 787//------------------------------init_spill_mask-------------------------------- 788void Matcher::init_spill_mask( Node *ret ) { 789 if( idealreg2regmask[Op_RegI] ) return; // One time only init 790 791 OptoReg::c_frame_pointer = c_frame_pointer(); 792 c_frame_ptr_mask = c_frame_pointer(); 793#ifdef _LP64 794 // pointers are twice as big 795 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1)); 796#endif 797 798 // Start at OptoReg::stack0() 799 STACK_ONLY_mask.Clear(); 800 OptoReg::Name init = OptoReg::stack2reg(0); 801 // STACK_ONLY_mask is all stack bits 802 OptoReg::Name i; 803 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) 804 STACK_ONLY_mask.Insert(i); 805 // Also set the "infinite stack" bit. 806 STACK_ONLY_mask.set_AllStack(); 807 808 // Copy the register names over into the shared world 809 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { 810 // SharedInfo::regName[i] = regName[i]; 811 // Handy RegMasks per machine register 812 mreg2regmask[i].Insert(i); 813 } 814 815 // Grab the Frame Pointer 816 Node *fp = ret->in(TypeFunc::FramePtr); 817 Node *mem = ret->in(TypeFunc::Memory); 818 const TypePtr* atp = TypePtr::BOTTOM; 819 // Share frame pointer while making spill ops 820 set_shared(fp); 821 822 // Compute generic short-offset Loads 823#ifdef _LP64 824 MachNode *spillCP = match_tree(new (C, 3) LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM)); 825#endif 826 MachNode *spillI = match_tree(new (C, 3) LoadINode(NULL,mem,fp,atp)); 827 MachNode *spillL = match_tree(new (C, 3) LoadLNode(NULL,mem,fp,atp)); 828 MachNode *spillF = match_tree(new (C, 3) LoadFNode(NULL,mem,fp,atp)); 829 MachNode *spillD = match_tree(new (C, 3) LoadDNode(NULL,mem,fp,atp)); 830 MachNode *spillP = match_tree(new (C, 3) LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM)); 831 assert(spillI != NULL && spillL != NULL && spillF != NULL && 832 spillD != NULL && spillP != NULL, ""); 833 834 // Get the ADLC notion of the right regmask, for each basic type. 835#ifdef _LP64 836 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask(); 837#endif 838 idealreg2regmask[Op_RegI] = &spillI->out_RegMask(); 839 idealreg2regmask[Op_RegL] = &spillL->out_RegMask(); 840 idealreg2regmask[Op_RegF] = &spillF->out_RegMask(); 841 idealreg2regmask[Op_RegD] = &spillD->out_RegMask(); 842 idealreg2regmask[Op_RegP] = &spillP->out_RegMask(); 843 844 // Vector regmasks. 845 if (Matcher::vector_size_supported(T_BYTE,4)) { 846 TypeVect::VECTS = TypeVect::make(T_BYTE, 4); 847 MachNode *spillVectS = match_tree(new (C, 3) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS)); 848 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask(); 849 } 850 if (Matcher::vector_size_supported(T_FLOAT,2)) { 851 MachNode *spillVectD = match_tree(new (C, 3) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD)); 852 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask(); 853 } 854 if (Matcher::vector_size_supported(T_FLOAT,4)) { 855 MachNode *spillVectX = match_tree(new (C, 3) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX)); 856 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask(); 857 } 858 if (Matcher::vector_size_supported(T_FLOAT,8)) { 859 MachNode *spillVectY = match_tree(new (C, 3) LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY)); 860 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask(); 861 } 862} 863 864#ifdef ASSERT 865static void match_alias_type(Compile* C, Node* n, Node* m) { 866 if (!VerifyAliases) return; // do not go looking for trouble by default 867 const TypePtr* nat = n->adr_type(); 868 const TypePtr* mat = m->adr_type(); 869 int nidx = C->get_alias_index(nat); 870 int midx = C->get_alias_index(mat); 871 // Detune the assert for cases like (AndI 0xFF (LoadB p)). 872 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) { 873 for (uint i = 1; i < n->req(); i++) { 874 Node* n1 = n->in(i); 875 const TypePtr* n1at = n1->adr_type(); 876 if (n1at != NULL) { 877 nat = n1at; 878 nidx = C->get_alias_index(n1at); 879 } 880 } 881 } 882 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases: 883 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) { 884 switch (n->Opcode()) { 885 case Op_PrefetchRead: 886 case Op_PrefetchWrite: 887 case Op_PrefetchAllocation: 888 nidx = Compile::AliasIdxRaw; 889 nat = TypeRawPtr::BOTTOM; 890 break; 891 } 892 } 893 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) { 894 switch (n->Opcode()) { 895 case Op_ClearArray: 896 midx = Compile::AliasIdxRaw; 897 mat = TypeRawPtr::BOTTOM; 898 break; 899 } 900 } 901 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) { 902 switch (n->Opcode()) { 903 case Op_Return: 904 case Op_Rethrow: 905 case Op_Halt: 906 case Op_TailCall: 907 case Op_TailJump: 908 nidx = Compile::AliasIdxBot; 909 nat = TypePtr::BOTTOM; 910 break; 911 } 912 } 913 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) { 914 switch (n->Opcode()) { 915 case Op_StrComp: 916 case Op_StrEquals: 917 case Op_StrIndexOf: 918 case Op_AryEq: 919 case Op_MemBarVolatile: 920 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type? 921 nidx = Compile::AliasIdxTop; 922 nat = NULL; 923 break; 924 } 925 } 926 if (nidx != midx) { 927 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) { 928 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx); 929 n->dump(); 930 m->dump(); 931 } 932 assert(C->subsume_loads() && C->must_alias(nat, midx), 933 "must not lose alias info when matching"); 934 } 935} 936#endif 937 938 939//------------------------------MStack----------------------------------------- 940// State and MStack class used in xform() and find_shared() iterative methods. 941enum Node_State { Pre_Visit, // node has to be pre-visited 942 Visit, // visit node 943 Post_Visit, // post-visit node 944 Alt_Post_Visit // alternative post-visit path 945 }; 946 947class MStack: public Node_Stack { 948 public: 949 MStack(int size) : Node_Stack(size) { } 950 951 void push(Node *n, Node_State ns) { 952 Node_Stack::push(n, (uint)ns); 953 } 954 void push(Node *n, Node_State ns, Node *parent, int indx) { 955 ++_inode_top; 956 if ((_inode_top + 1) >= _inode_max) grow(); 957 _inode_top->node = parent; 958 _inode_top->indx = (uint)indx; 959 ++_inode_top; 960 _inode_top->node = n; 961 _inode_top->indx = (uint)ns; 962 } 963 Node *parent() { 964 pop(); 965 return node(); 966 } 967 Node_State state() const { 968 return (Node_State)index(); 969 } 970 void set_state(Node_State ns) { 971 set_index((uint)ns); 972 } 973}; 974 975 976//------------------------------xform------------------------------------------ 977// Given a Node in old-space, Match him (Label/Reduce) to produce a machine 978// Node in new-space. Given a new-space Node, recursively walk his children. 979Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; } 980Node *Matcher::xform( Node *n, int max_stack ) { 981 // Use one stack to keep both: child's node/state and parent's node/index 982 MStack mstack(max_stack * 2 * 2); // C->unique() * 2 * 2 983 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root 984 985 while (mstack.is_nonempty()) { 986 n = mstack.node(); // Leave node on stack 987 Node_State nstate = mstack.state(); 988 if (nstate == Visit) { 989 mstack.set_state(Post_Visit); 990 Node *oldn = n; 991 // Old-space or new-space check 992 if (!C->node_arena()->contains(n)) { 993 // Old space! 994 Node* m; 995 if (has_new_node(n)) { // Not yet Label/Reduced 996 m = new_node(n); 997 } else { 998 if (!is_dontcare(n)) { // Matcher can match this guy 999 // Calls match special. They match alone with no children. 1000 // Their children, the incoming arguments, match normally. 1001 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n); 1002 if (C->failing()) return NULL; 1003 if (m == NULL) { Matcher::soft_match_failure(); return NULL; } 1004 } else { // Nothing the matcher cares about 1005 if( n->is_Proj() && n->in(0)->is_Multi()) { // Projections? 1006 // Convert to machine-dependent projection 1007 m = n->in(0)->as_Multi()->match( n->as_Proj(), this ); 1008#ifdef ASSERT 1009 _new2old_map.map(m->_idx, n); 1010#endif 1011 if (m->in(0) != NULL) // m might be top 1012 collect_null_checks(m, n); 1013 } else { // Else just a regular 'ol guy 1014 m = n->clone(); // So just clone into new-space 1015#ifdef ASSERT 1016 _new2old_map.map(m->_idx, n); 1017#endif 1018 // Def-Use edges will be added incrementally as Uses 1019 // of this node are matched. 1020 assert(m->outcnt() == 0, "no Uses of this clone yet"); 1021 } 1022 } 1023 1024 set_new_node(n, m); // Map old to new 1025 if (_old_node_note_array != NULL) { 1026 Node_Notes* nn = C->locate_node_notes(_old_node_note_array, 1027 n->_idx); 1028 C->set_node_notes_at(m->_idx, nn); 1029 } 1030 debug_only(match_alias_type(C, n, m)); 1031 } 1032 n = m; // n is now a new-space node 1033 mstack.set_node(n); 1034 } 1035 1036 // New space! 1037 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty()) 1038 1039 int i; 1040 // Put precedence edges on stack first (match them last). 1041 for (i = oldn->req(); (uint)i < oldn->len(); i++) { 1042 Node *m = oldn->in(i); 1043 if (m == NULL) break; 1044 // set -1 to call add_prec() instead of set_req() during Step1 1045 mstack.push(m, Visit, n, -1); 1046 } 1047 1048 // For constant debug info, I'd rather have unmatched constants. 1049 int cnt = n->req(); 1050 JVMState* jvms = n->jvms(); 1051 int debug_cnt = jvms ? jvms->debug_start() : cnt; 1052 1053 // Now do only debug info. Clone constants rather than matching. 1054 // Constants are represented directly in the debug info without 1055 // the need for executable machine instructions. 1056 // Monitor boxes are also represented directly. 1057 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do 1058 Node *m = n->in(i); // Get input 1059 int op = m->Opcode(); 1060 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites"); 1061 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || 1062 op == Op_ConF || op == Op_ConD || op == Op_ConL 1063 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp 1064 ) { 1065 m = m->clone(); 1066#ifdef ASSERT 1067 _new2old_map.map(m->_idx, n); 1068#endif 1069 mstack.push(m, Post_Visit, n, i); // Don't need to visit 1070 mstack.push(m->in(0), Visit, m, 0); 1071 } else { 1072 mstack.push(m, Visit, n, i); 1073 } 1074 } 1075 1076 // And now walk his children, and convert his inputs to new-space. 1077 for( ; i >= 0; --i ) { // For all normal inputs do 1078 Node *m = n->in(i); // Get input 1079 if(m != NULL) 1080 mstack.push(m, Visit, n, i); 1081 } 1082 1083 } 1084 else if (nstate == Post_Visit) { 1085 // Set xformed input 1086 Node *p = mstack.parent(); 1087 if (p != NULL) { // root doesn't have parent 1088 int i = (int)mstack.index(); 1089 if (i >= 0) 1090 p->set_req(i, n); // required input 1091 else if (i == -1) 1092 p->add_prec(n); // precedence input 1093 else 1094 ShouldNotReachHere(); 1095 } 1096 mstack.pop(); // remove processed node from stack 1097 } 1098 else { 1099 ShouldNotReachHere(); 1100 } 1101 } // while (mstack.is_nonempty()) 1102 return n; // Return new-space Node 1103} 1104 1105//------------------------------warp_outgoing_stk_arg------------------------ 1106OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) { 1107 // Convert outgoing argument location to a pre-biased stack offset 1108 if (reg->is_stack()) { 1109 OptoReg::Name warped = reg->reg2stack(); 1110 // Adjust the stack slot offset to be the register number used 1111 // by the allocator. 1112 warped = OptoReg::add(begin_out_arg_area, warped); 1113 // Keep track of the largest numbered stack slot used for an arg. 1114 // Largest used slot per call-site indicates the amount of stack 1115 // that is killed by the call. 1116 if( warped >= out_arg_limit_per_call ) 1117 out_arg_limit_per_call = OptoReg::add(warped,1); 1118 if (!RegMask::can_represent_arg(warped)) { 1119 C->record_method_not_compilable_all_tiers("unsupported calling sequence"); 1120 return OptoReg::Bad; 1121 } 1122 return warped; 1123 } 1124 return OptoReg::as_OptoReg(reg); 1125} 1126 1127 1128//------------------------------match_sfpt------------------------------------- 1129// Helper function to match call instructions. Calls match special. 1130// They match alone with no children. Their children, the incoming 1131// arguments, match normally. 1132MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) { 1133 MachSafePointNode *msfpt = NULL; 1134 MachCallNode *mcall = NULL; 1135 uint cnt; 1136 // Split out case for SafePoint vs Call 1137 CallNode *call; 1138 const TypeTuple *domain; 1139 ciMethod* method = NULL; 1140 bool is_method_handle_invoke = false; // for special kill effects 1141 if( sfpt->is_Call() ) { 1142 call = sfpt->as_Call(); 1143 domain = call->tf()->domain(); 1144 cnt = domain->cnt(); 1145 1146 // Match just the call, nothing else 1147 MachNode *m = match_tree(call); 1148 if (C->failing()) return NULL; 1149 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; } 1150 1151 // Copy data from the Ideal SafePoint to the machine version 1152 mcall = m->as_MachCall(); 1153 1154 mcall->set_tf( call->tf()); 1155 mcall->set_entry_point(call->entry_point()); 1156 mcall->set_cnt( call->cnt()); 1157 1158 if( mcall->is_MachCallJava() ) { 1159 MachCallJavaNode *mcall_java = mcall->as_MachCallJava(); 1160 const CallJavaNode *call_java = call->as_CallJava(); 1161 method = call_java->method(); 1162 mcall_java->_method = method; 1163 mcall_java->_bci = call_java->_bci; 1164 mcall_java->_optimized_virtual = call_java->is_optimized_virtual(); 1165 is_method_handle_invoke = call_java->is_method_handle_invoke(); 1166 mcall_java->_method_handle_invoke = is_method_handle_invoke; 1167 if (is_method_handle_invoke) { 1168 C->set_has_method_handle_invokes(true); 1169 } 1170 if( mcall_java->is_MachCallStaticJava() ) 1171 mcall_java->as_MachCallStaticJava()->_name = 1172 call_java->as_CallStaticJava()->_name; 1173 if( mcall_java->is_MachCallDynamicJava() ) 1174 mcall_java->as_MachCallDynamicJava()->_vtable_index = 1175 call_java->as_CallDynamicJava()->_vtable_index; 1176 } 1177 else if( mcall->is_MachCallRuntime() ) { 1178 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name; 1179 } 1180 msfpt = mcall; 1181 } 1182 // This is a non-call safepoint 1183 else { 1184 call = NULL; 1185 domain = NULL; 1186 MachNode *mn = match_tree(sfpt); 1187 if (C->failing()) return NULL; 1188 msfpt = mn->as_MachSafePoint(); 1189 cnt = TypeFunc::Parms; 1190 } 1191 1192 // Advertise the correct memory effects (for anti-dependence computation). 1193 msfpt->set_adr_type(sfpt->adr_type()); 1194 1195 // Allocate a private array of RegMasks. These RegMasks are not shared. 1196 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt ); 1197 // Empty them all. 1198 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt ); 1199 1200 // Do all the pre-defined non-Empty register masks 1201 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask; 1202 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask; 1203 1204 // Place first outgoing argument can possibly be put. 1205 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 1206 assert( is_even(begin_out_arg_area), "" ); 1207 // Compute max outgoing register number per call site. 1208 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area; 1209 // Calls to C may hammer extra stack slots above and beyond any arguments. 1210 // These are usually backing store for register arguments for varargs. 1211 if( call != NULL && call->is_CallRuntime() ) 1212 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed()); 1213 1214 1215 // Do the normal argument list (parameters) register masks 1216 int argcnt = cnt - TypeFunc::Parms; 1217 if( argcnt > 0 ) { // Skip it all if we have no args 1218 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 1219 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 1220 int i; 1221 for( i = 0; i < argcnt; i++ ) { 1222 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 1223 } 1224 // V-call to pick proper calling convention 1225 call->calling_convention( sig_bt, parm_regs, argcnt ); 1226 1227#ifdef ASSERT 1228 // Sanity check users' calling convention. Really handy during 1229 // the initial porting effort. Fairly expensive otherwise. 1230 { for (int i = 0; i<argcnt; i++) { 1231 if( !parm_regs[i].first()->is_valid() && 1232 !parm_regs[i].second()->is_valid() ) continue; 1233 VMReg reg1 = parm_regs[i].first(); 1234 VMReg reg2 = parm_regs[i].second(); 1235 for (int j = 0; j < i; j++) { 1236 if( !parm_regs[j].first()->is_valid() && 1237 !parm_regs[j].second()->is_valid() ) continue; 1238 VMReg reg3 = parm_regs[j].first(); 1239 VMReg reg4 = parm_regs[j].second(); 1240 if( !reg1->is_valid() ) { 1241 assert( !reg2->is_valid(), "valid halvsies" ); 1242 } else if( !reg3->is_valid() ) { 1243 assert( !reg4->is_valid(), "valid halvsies" ); 1244 } else { 1245 assert( reg1 != reg2, "calling conv. must produce distinct regs"); 1246 assert( reg1 != reg3, "calling conv. must produce distinct regs"); 1247 assert( reg1 != reg4, "calling conv. must produce distinct regs"); 1248 assert( reg2 != reg3, "calling conv. must produce distinct regs"); 1249 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs"); 1250 assert( reg3 != reg4, "calling conv. must produce distinct regs"); 1251 } 1252 } 1253 } 1254 } 1255#endif 1256 1257 // Visit each argument. Compute its outgoing register mask. 1258 // Return results now can have 2 bits returned. 1259 // Compute max over all outgoing arguments both per call-site 1260 // and over the entire method. 1261 for( i = 0; i < argcnt; i++ ) { 1262 // Address of incoming argument mask to fill in 1263 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms]; 1264 if( !parm_regs[i].first()->is_valid() && 1265 !parm_regs[i].second()->is_valid() ) { 1266 continue; // Avoid Halves 1267 } 1268 // Grab first register, adjust stack slots and insert in mask. 1269 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call ); 1270 if (OptoReg::is_valid(reg1)) 1271 rm->Insert( reg1 ); 1272 // Grab second register (if any), adjust stack slots and insert in mask. 1273 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call ); 1274 if (OptoReg::is_valid(reg2)) 1275 rm->Insert( reg2 ); 1276 } // End of for all arguments 1277 1278 // Compute number of stack slots needed to restore stack in case of 1279 // Pascal-style argument popping. 1280 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area; 1281 } 1282 1283 if (is_method_handle_invoke) { 1284 // Kill some extra stack space in case method handles want to do 1285 // a little in-place argument insertion. 1286 // FIXME: Is this still necessary? 1287 int regs_per_word = NOT_LP64(1) LP64_ONLY(2); // %%% make a global const! 1288 out_arg_limit_per_call += Method::extra_stack_entries() * regs_per_word; 1289 // Do not update mcall->_argsize because (a) the extra space is not 1290 // pushed as arguments and (b) _argsize is dead (not used anywhere). 1291 } 1292 1293 // Compute the max stack slot killed by any call. These will not be 1294 // available for debug info, and will be used to adjust FIRST_STACK_mask 1295 // after all call sites have been visited. 1296 if( _out_arg_limit < out_arg_limit_per_call) 1297 _out_arg_limit = out_arg_limit_per_call; 1298 1299 if (mcall) { 1300 // Kill the outgoing argument area, including any non-argument holes and 1301 // any legacy C-killed slots. Use Fat-Projections to do the killing. 1302 // Since the max-per-method covers the max-per-call-site and debug info 1303 // is excluded on the max-per-method basis, debug info cannot land in 1304 // this killed area. 1305 uint r_cnt = mcall->tf()->range()->cnt(); 1306 MachProjNode *proj = new (C, 1) MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj ); 1307 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) { 1308 C->record_method_not_compilable_all_tiers("unsupported outgoing calling sequence"); 1309 } else { 1310 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++) 1311 proj->_rout.Insert(OptoReg::Name(i)); 1312 } 1313 if( proj->_rout.is_NotEmpty() ) 1314 _proj_list.push(proj); 1315 } 1316 // Transfer the safepoint information from the call to the mcall 1317 // Move the JVMState list 1318 msfpt->set_jvms(sfpt->jvms()); 1319 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) { 1320 jvms->set_map(sfpt); 1321 } 1322 1323 // Debug inputs begin just after the last incoming parameter 1324 assert( (mcall == NULL) || (mcall->jvms() == NULL) || 1325 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "" ); 1326 1327 // Move the OopMap 1328 msfpt->_oop_map = sfpt->_oop_map; 1329 1330 // Registers killed by the call are set in the local scheduling pass 1331 // of Global Code Motion. 1332 return msfpt; 1333} 1334 1335//---------------------------match_tree---------------------------------------- 1336// Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part 1337// of the whole-sale conversion from Ideal to Mach Nodes. Also used for 1338// making GotoNodes while building the CFG and in init_spill_mask() to identify 1339// a Load's result RegMask for memoization in idealreg2regmask[] 1340MachNode *Matcher::match_tree( const Node *n ) { 1341 assert( n->Opcode() != Op_Phi, "cannot match" ); 1342 assert( !n->is_block_start(), "cannot match" ); 1343 // Set the mark for all locally allocated State objects. 1344 // When this call returns, the _states_arena arena will be reset 1345 // freeing all State objects. 1346 ResourceMark rm( &_states_arena ); 1347 1348 LabelRootDepth = 0; 1349 1350 // StoreNodes require their Memory input to match any LoadNodes 1351 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ; 1352#ifdef ASSERT 1353 Node* save_mem_node = _mem_node; 1354 _mem_node = n->is_Store() ? (Node*)n : NULL; 1355#endif 1356 // State object for root node of match tree 1357 // Allocate it on _states_arena - stack allocation can cause stack overflow. 1358 State *s = new (&_states_arena) State; 1359 s->_kids[0] = NULL; 1360 s->_kids[1] = NULL; 1361 s->_leaf = (Node*)n; 1362 // Label the input tree, allocating labels from top-level arena 1363 Label_Root( n, s, n->in(0), mem ); 1364 if (C->failing()) return NULL; 1365 1366 // The minimum cost match for the whole tree is found at the root State 1367 uint mincost = max_juint; 1368 uint cost = max_juint; 1369 uint i; 1370 for( i = 0; i < NUM_OPERANDS; i++ ) { 1371 if( s->valid(i) && // valid entry and 1372 s->_cost[i] < cost && // low cost and 1373 s->_rule[i] >= NUM_OPERANDS ) // not an operand 1374 cost = s->_cost[mincost=i]; 1375 } 1376 if (mincost == max_juint) { 1377#ifndef PRODUCT 1378 tty->print("No matching rule for:"); 1379 s->dump(); 1380#endif 1381 Matcher::soft_match_failure(); 1382 return NULL; 1383 } 1384 // Reduce input tree based upon the state labels to machine Nodes 1385 MachNode *m = ReduceInst( s, s->_rule[mincost], mem ); 1386#ifdef ASSERT 1387 _old2new_map.map(n->_idx, m); 1388 _new2old_map.map(m->_idx, (Node*)n); 1389#endif 1390 1391 // Add any Matcher-ignored edges 1392 uint cnt = n->req(); 1393 uint start = 1; 1394 if( mem != (Node*)1 ) start = MemNode::Memory+1; 1395 if( n->is_AddP() ) { 1396 assert( mem == (Node*)1, "" ); 1397 start = AddPNode::Base+1; 1398 } 1399 for( i = start; i < cnt; i++ ) { 1400 if( !n->match_edge(i) ) { 1401 if( i < m->req() ) 1402 m->ins_req( i, n->in(i) ); 1403 else 1404 m->add_req( n->in(i) ); 1405 } 1406 } 1407 1408 debug_only( _mem_node = save_mem_node; ) 1409 return m; 1410} 1411 1412 1413//------------------------------match_into_reg--------------------------------- 1414// Choose to either match this Node in a register or part of the current 1415// match tree. Return true for requiring a register and false for matching 1416// as part of the current match tree. 1417static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) { 1418 1419 const Type *t = m->bottom_type(); 1420 1421 if (t->singleton()) { 1422 // Never force constants into registers. Allow them to match as 1423 // constants or registers. Copies of the same value will share 1424 // the same register. See find_shared_node. 1425 return false; 1426 } else { // Not a constant 1427 // Stop recursion if they have different Controls. 1428 Node* m_control = m->in(0); 1429 // Control of load's memory can post-dominates load's control. 1430 // So use it since load can't float above its memory. 1431 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL; 1432 if (control && m_control && control != m_control && control != mem_control) { 1433 1434 // Actually, we can live with the most conservative control we 1435 // find, if it post-dominates the others. This allows us to 1436 // pick up load/op/store trees where the load can float a little 1437 // above the store. 1438 Node *x = control; 1439 const uint max_scan = 6; // Arbitrary scan cutoff 1440 uint j; 1441 for (j=0; j<max_scan; j++) { 1442 if (x->is_Region()) // Bail out at merge points 1443 return true; 1444 x = x->in(0); 1445 if (x == m_control) // Does 'control' post-dominate 1446 break; // m->in(0)? If so, we can use it 1447 if (x == mem_control) // Does 'control' post-dominate 1448 break; // mem_control? If so, we can use it 1449 } 1450 if (j == max_scan) // No post-domination before scan end? 1451 return true; // Then break the match tree up 1452 } 1453 if (m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) { 1454 // These are commonly used in address expressions and can 1455 // efficiently fold into them on X64 in some cases. 1456 return false; 1457 } 1458 } 1459 1460 // Not forceable cloning. If shared, put it into a register. 1461 return shared; 1462} 1463 1464 1465//------------------------------Instruction Selection-------------------------- 1466// Label method walks a "tree" of nodes, using the ADLC generated DFA to match 1467// ideal nodes to machine instructions. Trees are delimited by shared Nodes, 1468// things the Matcher does not match (e.g., Memory), and things with different 1469// Controls (hence forced into different blocks). We pass in the Control 1470// selected for this entire State tree. 1471 1472// The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the 1473// Store and the Load must have identical Memories (as well as identical 1474// pointers). Since the Matcher does not have anything for Memory (and 1475// does not handle DAGs), I have to match the Memory input myself. If the 1476// Tree root is a Store, I require all Loads to have the identical memory. 1477Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){ 1478 // Since Label_Root is a recursive function, its possible that we might run 1479 // out of stack space. See bugs 6272980 & 6227033 for more info. 1480 LabelRootDepth++; 1481 if (LabelRootDepth > MaxLabelRootDepth) { 1482 C->record_method_not_compilable_all_tiers("Out of stack space, increase MaxLabelRootDepth"); 1483 return NULL; 1484 } 1485 uint care = 0; // Edges matcher cares about 1486 uint cnt = n->req(); 1487 uint i = 0; 1488 1489 // Examine children for memory state 1490 // Can only subsume a child into your match-tree if that child's memory state 1491 // is not modified along the path to another input. 1492 // It is unsafe even if the other inputs are separate roots. 1493 Node *input_mem = NULL; 1494 for( i = 1; i < cnt; i++ ) { 1495 if( !n->match_edge(i) ) continue; 1496 Node *m = n->in(i); // Get ith input 1497 assert( m, "expect non-null children" ); 1498 if( m->is_Load() ) { 1499 if( input_mem == NULL ) { 1500 input_mem = m->in(MemNode::Memory); 1501 } else if( input_mem != m->in(MemNode::Memory) ) { 1502 input_mem = NodeSentinel; 1503 } 1504 } 1505 } 1506 1507 for( i = 1; i < cnt; i++ ){// For my children 1508 if( !n->match_edge(i) ) continue; 1509 Node *m = n->in(i); // Get ith input 1510 // Allocate states out of a private arena 1511 State *s = new (&_states_arena) State; 1512 svec->_kids[care++] = s; 1513 assert( care <= 2, "binary only for now" ); 1514 1515 // Recursively label the State tree. 1516 s->_kids[0] = NULL; 1517 s->_kids[1] = NULL; 1518 s->_leaf = m; 1519 1520 // Check for leaves of the State Tree; things that cannot be a part of 1521 // the current tree. If it finds any, that value is matched as a 1522 // register operand. If not, then the normal matching is used. 1523 if( match_into_reg(n, m, control, i, is_shared(m)) || 1524 // 1525 // Stop recursion if this is LoadNode and the root of this tree is a 1526 // StoreNode and the load & store have different memories. 1527 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) || 1528 // Can NOT include the match of a subtree when its memory state 1529 // is used by any of the other subtrees 1530 (input_mem == NodeSentinel) ) { 1531#ifndef PRODUCT 1532 // Print when we exclude matching due to different memory states at input-loads 1533 if( PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel) 1534 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ) { 1535 tty->print_cr("invalid input_mem"); 1536 } 1537#endif 1538 // Switch to a register-only opcode; this value must be in a register 1539 // and cannot be subsumed as part of a larger instruction. 1540 s->DFA( m->ideal_reg(), m ); 1541 1542 } else { 1543 // If match tree has no control and we do, adopt it for entire tree 1544 if( control == NULL && m->in(0) != NULL && m->req() > 1 ) 1545 control = m->in(0); // Pick up control 1546 // Else match as a normal part of the match tree. 1547 control = Label_Root(m,s,control,mem); 1548 if (C->failing()) return NULL; 1549 } 1550 } 1551 1552 1553 // Call DFA to match this node, and return 1554 svec->DFA( n->Opcode(), n ); 1555 1556#ifdef ASSERT 1557 uint x; 1558 for( x = 0; x < _LAST_MACH_OPER; x++ ) 1559 if( svec->valid(x) ) 1560 break; 1561 1562 if (x >= _LAST_MACH_OPER) { 1563 n->dump(); 1564 svec->dump(); 1565 assert( false, "bad AD file" ); 1566 } 1567#endif 1568 return control; 1569} 1570 1571 1572// Con nodes reduced using the same rule can share their MachNode 1573// which reduces the number of copies of a constant in the final 1574// program. The register allocator is free to split uses later to 1575// split live ranges. 1576MachNode* Matcher::find_shared_node(Node* leaf, uint rule) { 1577 if (!leaf->is_Con() && !leaf->is_DecodeN()) return NULL; 1578 1579 // See if this Con has already been reduced using this rule. 1580 if (_shared_nodes.Size() <= leaf->_idx) return NULL; 1581 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx); 1582 if (last != NULL && rule == last->rule()) { 1583 // Don't expect control change for DecodeN 1584 if (leaf->is_DecodeN()) 1585 return last; 1586 // Get the new space root. 1587 Node* xroot = new_node(C->root()); 1588 if (xroot == NULL) { 1589 // This shouldn't happen give the order of matching. 1590 return NULL; 1591 } 1592 1593 // Shared constants need to have their control be root so they 1594 // can be scheduled properly. 1595 Node* control = last->in(0); 1596 if (control != xroot) { 1597 if (control == NULL || control == C->root()) { 1598 last->set_req(0, xroot); 1599 } else { 1600 assert(false, "unexpected control"); 1601 return NULL; 1602 } 1603 } 1604 return last; 1605 } 1606 return NULL; 1607} 1608 1609 1610//------------------------------ReduceInst------------------------------------- 1611// Reduce a State tree (with given Control) into a tree of MachNodes. 1612// This routine (and it's cohort ReduceOper) convert Ideal Nodes into 1613// complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes. 1614// Each MachNode has a number of complicated MachOper operands; each 1615// MachOper also covers a further tree of Ideal Nodes. 1616 1617// The root of the Ideal match tree is always an instruction, so we enter 1618// the recursion here. After building the MachNode, we need to recurse 1619// the tree checking for these cases: 1620// (1) Child is an instruction - 1621// Build the instruction (recursively), add it as an edge. 1622// Build a simple operand (register) to hold the result of the instruction. 1623// (2) Child is an interior part of an instruction - 1624// Skip over it (do nothing) 1625// (3) Child is the start of a operand - 1626// Build the operand, place it inside the instruction 1627// Call ReduceOper. 1628MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) { 1629 assert( rule >= NUM_OPERANDS, "called with operand rule" ); 1630 1631 MachNode* shared_node = find_shared_node(s->_leaf, rule); 1632 if (shared_node != NULL) { 1633 return shared_node; 1634 } 1635 1636 // Build the object to represent this state & prepare for recursive calls 1637 MachNode *mach = s->MachNodeGenerator( rule, C ); 1638 mach->_opnds[0] = s->MachOperGenerator( _reduceOp[rule], C ); 1639 assert( mach->_opnds[0] != NULL, "Missing result operand" ); 1640 Node *leaf = s->_leaf; 1641 // Check for instruction or instruction chain rule 1642 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) { 1643 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf), 1644 "duplicating node that's already been matched"); 1645 // Instruction 1646 mach->add_req( leaf->in(0) ); // Set initial control 1647 // Reduce interior of complex instruction 1648 ReduceInst_Interior( s, rule, mem, mach, 1 ); 1649 } else { 1650 // Instruction chain rules are data-dependent on their inputs 1651 mach->add_req(0); // Set initial control to none 1652 ReduceInst_Chain_Rule( s, rule, mem, mach ); 1653 } 1654 1655 // If a Memory was used, insert a Memory edge 1656 if( mem != (Node*)1 ) { 1657 mach->ins_req(MemNode::Memory,mem); 1658#ifdef ASSERT 1659 // Verify adr type after matching memory operation 1660 const MachOper* oper = mach->memory_operand(); 1661 if (oper != NULL && oper != (MachOper*)-1) { 1662 // It has a unique memory operand. Find corresponding ideal mem node. 1663 Node* m = NULL; 1664 if (leaf->is_Mem()) { 1665 m = leaf; 1666 } else { 1667 m = _mem_node; 1668 assert(m != NULL && m->is_Mem(), "expecting memory node"); 1669 } 1670 const Type* mach_at = mach->adr_type(); 1671 // DecodeN node consumed by an address may have different type 1672 // then its input. Don't compare types for such case. 1673 if (m->adr_type() != mach_at && 1674 (m->in(MemNode::Address)->is_DecodeN() || 1675 m->in(MemNode::Address)->is_AddP() && 1676 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeN() || 1677 m->in(MemNode::Address)->is_AddP() && 1678 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() && 1679 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeN())) { 1680 mach_at = m->adr_type(); 1681 } 1682 if (m->adr_type() != mach_at) { 1683 m->dump(); 1684 tty->print_cr("mach:"); 1685 mach->dump(1); 1686 } 1687 assert(m->adr_type() == mach_at, "matcher should not change adr type"); 1688 } 1689#endif 1690 } 1691 1692 // If the _leaf is an AddP, insert the base edge 1693 if( leaf->is_AddP() ) 1694 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base)); 1695 1696 uint num_proj = _proj_list.size(); 1697 1698 // Perform any 1-to-many expansions required 1699 MachNode *ex = mach->Expand(s,_proj_list, mem); 1700 if( ex != mach ) { 1701 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match"); 1702 if( ex->in(1)->is_Con() ) 1703 ex->in(1)->set_req(0, C->root()); 1704 // Remove old node from the graph 1705 for( uint i=0; i<mach->req(); i++ ) { 1706 mach->set_req(i,NULL); 1707 } 1708#ifdef ASSERT 1709 _new2old_map.map(ex->_idx, s->_leaf); 1710#endif 1711 } 1712 1713 // PhaseChaitin::fixup_spills will sometimes generate spill code 1714 // via the matcher. By the time, nodes have been wired into the CFG, 1715 // and any further nodes generated by expand rules will be left hanging 1716 // in space, and will not get emitted as output code. Catch this. 1717 // Also, catch any new register allocation constraints ("projections") 1718 // generated belatedly during spill code generation. 1719 if (_allocation_started) { 1720 guarantee(ex == mach, "no expand rules during spill generation"); 1721 guarantee(_proj_list.size() == num_proj, "no allocation during spill generation"); 1722 } 1723 1724 if (leaf->is_Con() || leaf->is_DecodeN()) { 1725 // Record the con for sharing 1726 _shared_nodes.map(leaf->_idx, ex); 1727 } 1728 1729 return ex; 1730} 1731 1732void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) { 1733 // 'op' is what I am expecting to receive 1734 int op = _leftOp[rule]; 1735 // Operand type to catch childs result 1736 // This is what my child will give me. 1737 int opnd_class_instance = s->_rule[op]; 1738 // Choose between operand class or not. 1739 // This is what I will receive. 1740 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op; 1741 // New rule for child. Chase operand classes to get the actual rule. 1742 int newrule = s->_rule[catch_op]; 1743 1744 if( newrule < NUM_OPERANDS ) { 1745 // Chain from operand or operand class, may be output of shared node 1746 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS, 1747 "Bad AD file: Instruction chain rule must chain from operand"); 1748 // Insert operand into array of operands for this instruction 1749 mach->_opnds[1] = s->MachOperGenerator( opnd_class_instance, C ); 1750 1751 ReduceOper( s, newrule, mem, mach ); 1752 } else { 1753 // Chain from the result of an instruction 1754 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand"); 1755 mach->_opnds[1] = s->MachOperGenerator( _reduceOp[catch_op], C ); 1756 Node *mem1 = (Node*)1; 1757 debug_only(Node *save_mem_node = _mem_node;) 1758 mach->add_req( ReduceInst(s, newrule, mem1) ); 1759 debug_only(_mem_node = save_mem_node;) 1760 } 1761 return; 1762} 1763 1764 1765uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) { 1766 if( s->_leaf->is_Load() ) { 1767 Node *mem2 = s->_leaf->in(MemNode::Memory); 1768 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" ); 1769 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;) 1770 mem = mem2; 1771 } 1772 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) { 1773 if( mach->in(0) == NULL ) 1774 mach->set_req(0, s->_leaf->in(0)); 1775 } 1776 1777 // Now recursively walk the state tree & add operand list. 1778 for( uint i=0; i<2; i++ ) { // binary tree 1779 State *newstate = s->_kids[i]; 1780 if( newstate == NULL ) break; // Might only have 1 child 1781 // 'op' is what I am expecting to receive 1782 int op; 1783 if( i == 0 ) { 1784 op = _leftOp[rule]; 1785 } else { 1786 op = _rightOp[rule]; 1787 } 1788 // Operand type to catch childs result 1789 // This is what my child will give me. 1790 int opnd_class_instance = newstate->_rule[op]; 1791 // Choose between operand class or not. 1792 // This is what I will receive. 1793 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op; 1794 // New rule for child. Chase operand classes to get the actual rule. 1795 int newrule = newstate->_rule[catch_op]; 1796 1797 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction? 1798 // Operand/operandClass 1799 // Insert operand into array of operands for this instruction 1800 mach->_opnds[num_opnds++] = newstate->MachOperGenerator( opnd_class_instance, C ); 1801 ReduceOper( newstate, newrule, mem, mach ); 1802 1803 } else { // Child is internal operand or new instruction 1804 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction? 1805 // internal operand --> call ReduceInst_Interior 1806 // Interior of complex instruction. Do nothing but recurse. 1807 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds ); 1808 } else { 1809 // instruction --> call build operand( ) to catch result 1810 // --> ReduceInst( newrule ) 1811 mach->_opnds[num_opnds++] = s->MachOperGenerator( _reduceOp[catch_op], C ); 1812 Node *mem1 = (Node*)1; 1813 debug_only(Node *save_mem_node = _mem_node;) 1814 mach->add_req( ReduceInst( newstate, newrule, mem1 ) ); 1815 debug_only(_mem_node = save_mem_node;) 1816 } 1817 } 1818 assert( mach->_opnds[num_opnds-1], "" ); 1819 } 1820 return num_opnds; 1821} 1822 1823// This routine walks the interior of possible complex operands. 1824// At each point we check our children in the match tree: 1825// (1) No children - 1826// We are a leaf; add _leaf field as an input to the MachNode 1827// (2) Child is an internal operand - 1828// Skip over it ( do nothing ) 1829// (3) Child is an instruction - 1830// Call ReduceInst recursively and 1831// and instruction as an input to the MachNode 1832void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) { 1833 assert( rule < _LAST_MACH_OPER, "called with operand rule" ); 1834 State *kid = s->_kids[0]; 1835 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" ); 1836 1837 // Leaf? And not subsumed? 1838 if( kid == NULL && !_swallowed[rule] ) { 1839 mach->add_req( s->_leaf ); // Add leaf pointer 1840 return; // Bail out 1841 } 1842 1843 if( s->_leaf->is_Load() ) { 1844 assert( mem == (Node*)1, "multiple Memories being matched at once?" ); 1845 mem = s->_leaf->in(MemNode::Memory); 1846 debug_only(_mem_node = s->_leaf;) 1847 } 1848 if( s->_leaf->in(0) && s->_leaf->req() > 1) { 1849 if( !mach->in(0) ) 1850 mach->set_req(0,s->_leaf->in(0)); 1851 else { 1852 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" ); 1853 } 1854 } 1855 1856 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree 1857 int newrule; 1858 if( i == 0 ) 1859 newrule = kid->_rule[_leftOp[rule]]; 1860 else 1861 newrule = kid->_rule[_rightOp[rule]]; 1862 1863 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction? 1864 // Internal operand; recurse but do nothing else 1865 ReduceOper( kid, newrule, mem, mach ); 1866 1867 } else { // Child is a new instruction 1868 // Reduce the instruction, and add a direct pointer from this 1869 // machine instruction to the newly reduced one. 1870 Node *mem1 = (Node*)1; 1871 debug_only(Node *save_mem_node = _mem_node;) 1872 mach->add_req( ReduceInst( kid, newrule, mem1 ) ); 1873 debug_only(_mem_node = save_mem_node;) 1874 } 1875 } 1876} 1877 1878 1879// ------------------------------------------------------------------------- 1880// Java-Java calling convention 1881// (what you use when Java calls Java) 1882 1883//------------------------------find_receiver---------------------------------- 1884// For a given signature, return the OptoReg for parameter 0. 1885OptoReg::Name Matcher::find_receiver( bool is_outgoing ) { 1886 VMRegPair regs; 1887 BasicType sig_bt = T_OBJECT; 1888 calling_convention(&sig_bt, ®s, 1, is_outgoing); 1889 // Return argument 0 register. In the LP64 build pointers 1890 // take 2 registers, but the VM wants only the 'main' name. 1891 return OptoReg::as_OptoReg(regs.first()); 1892} 1893 1894// A method-klass-holder may be passed in the inline_cache_reg 1895// and then expanded into the inline_cache_reg and a method_oop register 1896// defined in ad_<arch>.cpp 1897 1898 1899//------------------------------find_shared------------------------------------ 1900// Set bits if Node is shared or otherwise a root 1901void Matcher::find_shared( Node *n ) { 1902 // Allocate stack of size C->unique() * 2 to avoid frequent realloc 1903 MStack mstack(C->unique() * 2); 1904 // Mark nodes as address_visited if they are inputs to an address expression 1905 VectorSet address_visited(Thread::current()->resource_area()); 1906 mstack.push(n, Visit); // Don't need to pre-visit root node 1907 while (mstack.is_nonempty()) { 1908 n = mstack.node(); // Leave node on stack 1909 Node_State nstate = mstack.state(); 1910 uint nop = n->Opcode(); 1911 if (nstate == Pre_Visit) { 1912 if (address_visited.test(n->_idx)) { // Visited in address already? 1913 // Flag as visited and shared now. 1914 set_visited(n); 1915 } 1916 if (is_visited(n)) { // Visited already? 1917 // Node is shared and has no reason to clone. Flag it as shared. 1918 // This causes it to match into a register for the sharing. 1919 set_shared(n); // Flag as shared and 1920 mstack.pop(); // remove node from stack 1921 continue; 1922 } 1923 nstate = Visit; // Not already visited; so visit now 1924 } 1925 if (nstate == Visit) { 1926 mstack.set_state(Post_Visit); 1927 set_visited(n); // Flag as visited now 1928 bool mem_op = false; 1929 1930 switch( nop ) { // Handle some opcodes special 1931 case Op_Phi: // Treat Phis as shared roots 1932 case Op_Parm: 1933 case Op_Proj: // All handled specially during matching 1934 case Op_SafePointScalarObject: 1935 set_shared(n); 1936 set_dontcare(n); 1937 break; 1938 case Op_If: 1939 case Op_CountedLoopEnd: 1940 mstack.set_state(Alt_Post_Visit); // Alternative way 1941 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps 1942 // with matching cmp/branch in 1 instruction. The Matcher needs the 1943 // Bool and CmpX side-by-side, because it can only get at constants 1944 // that are at the leaves of Match trees, and the Bool's condition acts 1945 // as a constant here. 1946 mstack.push(n->in(1), Visit); // Clone the Bool 1947 mstack.push(n->in(0), Pre_Visit); // Visit control input 1948 continue; // while (mstack.is_nonempty()) 1949 case Op_ConvI2D: // These forms efficiently match with a prior 1950 case Op_ConvI2F: // Load but not a following Store 1951 if( n->in(1)->is_Load() && // Prior load 1952 n->outcnt() == 1 && // Not already shared 1953 n->unique_out()->is_Store() ) // Following store 1954 set_shared(n); // Force it to be a root 1955 break; 1956 case Op_ReverseBytesI: 1957 case Op_ReverseBytesL: 1958 if( n->in(1)->is_Load() && // Prior load 1959 n->outcnt() == 1 ) // Not already shared 1960 set_shared(n); // Force it to be a root 1961 break; 1962 case Op_BoxLock: // Cant match until we get stack-regs in ADLC 1963 case Op_IfFalse: 1964 case Op_IfTrue: 1965 case Op_MachProj: 1966 case Op_MergeMem: 1967 case Op_Catch: 1968 case Op_CatchProj: 1969 case Op_CProj: 1970 case Op_JumpProj: 1971 case Op_JProj: 1972 case Op_NeverBranch: 1973 set_dontcare(n); 1974 break; 1975 case Op_Jump: 1976 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared) 1977 mstack.push(n->in(0), Pre_Visit); // Visit Control input 1978 continue; // while (mstack.is_nonempty()) 1979 case Op_StrComp: 1980 case Op_StrEquals: 1981 case Op_StrIndexOf: 1982 case Op_AryEq: 1983 set_shared(n); // Force result into register (it will be anyways) 1984 break; 1985 case Op_ConP: { // Convert pointers above the centerline to NUL 1986 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 1987 const TypePtr* tp = tn->type()->is_ptr(); 1988 if (tp->_ptr == TypePtr::AnyNull) { 1989 tn->set_type(TypePtr::NULL_PTR); 1990 } 1991 break; 1992 } 1993 case Op_ConN: { // Convert narrow pointers above the centerline to NUL 1994 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 1995 const TypePtr* tp = tn->type()->make_ptr(); 1996 if (tp && tp->_ptr == TypePtr::AnyNull) { 1997 tn->set_type(TypeNarrowOop::NULL_PTR); 1998 } 1999 break; 2000 } 2001 case Op_Binary: // These are introduced in the Post_Visit state. 2002 ShouldNotReachHere(); 2003 break; 2004 case Op_ClearArray: 2005 case Op_SafePoint: 2006 mem_op = true; 2007 break; 2008 default: 2009 if( n->is_Store() ) { 2010 // Do match stores, despite no ideal reg 2011 mem_op = true; 2012 break; 2013 } 2014 if( n->is_Mem() ) { // Loads and LoadStores 2015 mem_op = true; 2016 // Loads must be root of match tree due to prior load conflict 2017 if( C->subsume_loads() == false ) 2018 set_shared(n); 2019 } 2020 // Fall into default case 2021 if( !n->ideal_reg() ) 2022 set_dontcare(n); // Unmatchable Nodes 2023 } // end_switch 2024 2025 for(int i = n->req() - 1; i >= 0; --i) { // For my children 2026 Node *m = n->in(i); // Get ith input 2027 if (m == NULL) continue; // Ignore NULLs 2028 uint mop = m->Opcode(); 2029 2030 // Must clone all producers of flags, or we will not match correctly. 2031 // Suppose a compare setting int-flags is shared (e.g., a switch-tree) 2032 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags 2033 // are also there, so we may match a float-branch to int-flags and 2034 // expect the allocator to haul the flags from the int-side to the 2035 // fp-side. No can do. 2036 if( _must_clone[mop] ) { 2037 mstack.push(m, Visit); 2038 continue; // for(int i = ...) 2039 } 2040 2041 if( mop == Op_AddP && m->in(AddPNode::Base)->Opcode() == Op_DecodeN ) { 2042 // Bases used in addresses must be shared but since 2043 // they are shared through a DecodeN they may appear 2044 // to have a single use so force sharing here. 2045 set_shared(m->in(AddPNode::Base)->in(1)); 2046 } 2047 2048 // Clone addressing expressions as they are "free" in memory access instructions 2049 if( mem_op && i == MemNode::Address && mop == Op_AddP ) { 2050 // Some inputs for address expression are not put on stack 2051 // to avoid marking them as shared and forcing them into register 2052 // if they are used only in address expressions. 2053 // But they should be marked as shared if there are other uses 2054 // besides address expressions. 2055 2056 Node *off = m->in(AddPNode::Offset); 2057 if( off->is_Con() && 2058 // When there are other uses besides address expressions 2059 // put it on stack and mark as shared. 2060 !is_visited(m) ) { 2061 address_visited.test_set(m->_idx); // Flag as address_visited 2062 Node *adr = m->in(AddPNode::Address); 2063 2064 // Intel, ARM and friends can handle 2 adds in addressing mode 2065 if( clone_shift_expressions && adr->is_AddP() && 2066 // AtomicAdd is not an addressing expression. 2067 // Cheap to find it by looking for screwy base. 2068 !adr->in(AddPNode::Base)->is_top() && 2069 // Are there other uses besides address expressions? 2070 !is_visited(adr) ) { 2071 address_visited.set(adr->_idx); // Flag as address_visited 2072 Node *shift = adr->in(AddPNode::Offset); 2073 // Check for shift by small constant as well 2074 if( shift->Opcode() == Op_LShiftX && shift->in(2)->is_Con() && 2075 shift->in(2)->get_int() <= 3 && 2076 // Are there other uses besides address expressions? 2077 !is_visited(shift) ) { 2078 address_visited.set(shift->_idx); // Flag as address_visited 2079 mstack.push(shift->in(2), Visit); 2080 Node *conv = shift->in(1); 2081#ifdef _LP64 2082 // Allow Matcher to match the rule which bypass 2083 // ConvI2L operation for an array index on LP64 2084 // if the index value is positive. 2085 if( conv->Opcode() == Op_ConvI2L && 2086 conv->as_Type()->type()->is_long()->_lo >= 0 && 2087 // Are there other uses besides address expressions? 2088 !is_visited(conv) ) { 2089 address_visited.set(conv->_idx); // Flag as address_visited 2090 mstack.push(conv->in(1), Pre_Visit); 2091 } else 2092#endif 2093 mstack.push(conv, Pre_Visit); 2094 } else { 2095 mstack.push(shift, Pre_Visit); 2096 } 2097 mstack.push(adr->in(AddPNode::Address), Pre_Visit); 2098 mstack.push(adr->in(AddPNode::Base), Pre_Visit); 2099 } else { // Sparc, Alpha, PPC and friends 2100 mstack.push(adr, Pre_Visit); 2101 } 2102 2103 // Clone X+offset as it also folds into most addressing expressions 2104 mstack.push(off, Visit); 2105 mstack.push(m->in(AddPNode::Base), Pre_Visit); 2106 continue; // for(int i = ...) 2107 } // if( off->is_Con() ) 2108 } // if( mem_op && 2109 mstack.push(m, Pre_Visit); 2110 } // for(int i = ...) 2111 } 2112 else if (nstate == Alt_Post_Visit) { 2113 mstack.pop(); // Remove node from stack 2114 // We cannot remove the Cmp input from the Bool here, as the Bool may be 2115 // shared and all users of the Bool need to move the Cmp in parallel. 2116 // This leaves both the Bool and the If pointing at the Cmp. To 2117 // prevent the Matcher from trying to Match the Cmp along both paths 2118 // BoolNode::match_edge always returns a zero. 2119 2120 // We reorder the Op_If in a pre-order manner, so we can visit without 2121 // accidentally sharing the Cmp (the Bool and the If make 2 users). 2122 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool 2123 } 2124 else if (nstate == Post_Visit) { 2125 mstack.pop(); // Remove node from stack 2126 2127 // Now hack a few special opcodes 2128 switch( n->Opcode() ) { // Handle some opcodes special 2129 case Op_StorePConditional: 2130 case Op_StoreIConditional: 2131 case Op_StoreLConditional: 2132 case Op_CompareAndSwapI: 2133 case Op_CompareAndSwapL: 2134 case Op_CompareAndSwapP: 2135 case Op_CompareAndSwapN: { // Convert trinary to binary-tree 2136 Node *newval = n->in(MemNode::ValueIn ); 2137 Node *oldval = n->in(LoadStoreNode::ExpectedIn); 2138 Node *pair = new (C, 3) BinaryNode( oldval, newval ); 2139 n->set_req(MemNode::ValueIn,pair); 2140 n->del_req(LoadStoreNode::ExpectedIn); 2141 break; 2142 } 2143 case Op_CMoveD: // Convert trinary to binary-tree 2144 case Op_CMoveF: 2145 case Op_CMoveI: 2146 case Op_CMoveL: 2147 case Op_CMoveN: 2148 case Op_CMoveP: { 2149 // Restructure into a binary tree for Matching. It's possible that 2150 // we could move this code up next to the graph reshaping for IfNodes 2151 // or vice-versa, but I do not want to debug this for Ladybird. 2152 // 10/2/2000 CNC. 2153 Node *pair1 = new (C, 3) BinaryNode(n->in(1),n->in(1)->in(1)); 2154 n->set_req(1,pair1); 2155 Node *pair2 = new (C, 3) BinaryNode(n->in(2),n->in(3)); 2156 n->set_req(2,pair2); 2157 n->del_req(3); 2158 break; 2159 } 2160 case Op_LoopLimit: { 2161 Node *pair1 = new (C, 3) BinaryNode(n->in(1),n->in(2)); 2162 n->set_req(1,pair1); 2163 n->set_req(2,n->in(3)); 2164 n->del_req(3); 2165 break; 2166 } 2167 case Op_StrEquals: { 2168 Node *pair1 = new (C, 3) BinaryNode(n->in(2),n->in(3)); 2169 n->set_req(2,pair1); 2170 n->set_req(3,n->in(4)); 2171 n->del_req(4); 2172 break; 2173 } 2174 case Op_StrComp: 2175 case Op_StrIndexOf: { 2176 Node *pair1 = new (C, 3) BinaryNode(n->in(2),n->in(3)); 2177 n->set_req(2,pair1); 2178 Node *pair2 = new (C, 3) BinaryNode(n->in(4),n->in(5)); 2179 n->set_req(3,pair2); 2180 n->del_req(5); 2181 n->del_req(4); 2182 break; 2183 } 2184 default: 2185 break; 2186 } 2187 } 2188 else { 2189 ShouldNotReachHere(); 2190 } 2191 } // end of while (mstack.is_nonempty()) 2192} 2193 2194#ifdef ASSERT 2195// machine-independent root to machine-dependent root 2196void Matcher::dump_old2new_map() { 2197 _old2new_map.dump(); 2198} 2199#endif 2200 2201//---------------------------collect_null_checks------------------------------- 2202// Find null checks in the ideal graph; write a machine-specific node for 2203// it. Used by later implicit-null-check handling. Actually collects 2204// either an IfTrue or IfFalse for the common NOT-null path, AND the ideal 2205// value being tested. 2206void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) { 2207 Node *iff = proj->in(0); 2208 if( iff->Opcode() == Op_If ) { 2209 // During matching If's have Bool & Cmp side-by-side 2210 BoolNode *b = iff->in(1)->as_Bool(); 2211 Node *cmp = iff->in(2); 2212 int opc = cmp->Opcode(); 2213 if (opc != Op_CmpP && opc != Op_CmpN) return; 2214 2215 const Type* ct = cmp->in(2)->bottom_type(); 2216 if (ct == TypePtr::NULL_PTR || 2217 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) { 2218 2219 bool push_it = false; 2220 if( proj->Opcode() == Op_IfTrue ) { 2221 extern int all_null_checks_found; 2222 all_null_checks_found++; 2223 if( b->_test._test == BoolTest::ne ) { 2224 push_it = true; 2225 } 2226 } else { 2227 assert( proj->Opcode() == Op_IfFalse, "" ); 2228 if( b->_test._test == BoolTest::eq ) { 2229 push_it = true; 2230 } 2231 } 2232 if( push_it ) { 2233 _null_check_tests.push(proj); 2234 Node* val = cmp->in(1); 2235#ifdef _LP64 2236 if (val->bottom_type()->isa_narrowoop() && 2237 !Matcher::narrow_oop_use_complex_address()) { 2238 // 2239 // Look for DecodeN node which should be pinned to orig_proj. 2240 // On platforms (Sparc) which can not handle 2 adds 2241 // in addressing mode we have to keep a DecodeN node and 2242 // use it to do implicit NULL check in address. 2243 // 2244 // DecodeN node was pinned to non-null path (orig_proj) during 2245 // CastPP transformation in final_graph_reshaping_impl(). 2246 // 2247 uint cnt = orig_proj->outcnt(); 2248 for (uint i = 0; i < orig_proj->outcnt(); i++) { 2249 Node* d = orig_proj->raw_out(i); 2250 if (d->is_DecodeN() && d->in(1) == val) { 2251 val = d; 2252 val->set_req(0, NULL); // Unpin now. 2253 // Mark this as special case to distinguish from 2254 // a regular case: CmpP(DecodeN, NULL). 2255 val = (Node*)(((intptr_t)val) | 1); 2256 break; 2257 } 2258 } 2259 } 2260#endif 2261 _null_check_tests.push(val); 2262 } 2263 } 2264 } 2265} 2266 2267//---------------------------validate_null_checks------------------------------ 2268// Its possible that the value being NULL checked is not the root of a match 2269// tree. If so, I cannot use the value in an implicit null check. 2270void Matcher::validate_null_checks( ) { 2271 uint cnt = _null_check_tests.size(); 2272 for( uint i=0; i < cnt; i+=2 ) { 2273 Node *test = _null_check_tests[i]; 2274 Node *val = _null_check_tests[i+1]; 2275 bool is_decoden = ((intptr_t)val) & 1; 2276 val = (Node*)(((intptr_t)val) & ~1); 2277 if (has_new_node(val)) { 2278 Node* new_val = new_node(val); 2279 if (is_decoden) { 2280 assert(val->is_DecodeN() && val->in(0) == NULL, "sanity"); 2281 // Note: new_val may have a control edge if 2282 // the original ideal node DecodeN was matched before 2283 // it was unpinned in Matcher::collect_null_checks(). 2284 // Unpin the mach node and mark it. 2285 new_val->set_req(0, NULL); 2286 new_val = (Node*)(((intptr_t)new_val) | 1); 2287 } 2288 // Is a match-tree root, so replace with the matched value 2289 _null_check_tests.map(i+1, new_val); 2290 } else { 2291 // Yank from candidate list 2292 _null_check_tests.map(i+1,_null_check_tests[--cnt]); 2293 _null_check_tests.map(i,_null_check_tests[--cnt]); 2294 _null_check_tests.pop(); 2295 _null_check_tests.pop(); 2296 i-=2; 2297 } 2298 } 2299} 2300 2301// Used by the DFA in dfa_xxx.cpp. Check for a following barrier or 2302// atomic instruction acting as a store_load barrier without any 2303// intervening volatile load, and thus we don't need a barrier here. 2304// We retain the Node to act as a compiler ordering barrier. 2305bool Matcher::post_store_load_barrier(const Node *vmb) { 2306 Compile *C = Compile::current(); 2307 assert( vmb->is_MemBar(), "" ); 2308 assert( vmb->Opcode() != Op_MemBarAcquire, "" ); 2309 const MemBarNode *mem = (const MemBarNode*)vmb; 2310 2311 // Get the Proj node, ctrl, that can be used to iterate forward 2312 Node *ctrl = NULL; 2313 DUIterator_Fast imax, i = mem->fast_outs(imax); 2314 while( true ) { 2315 ctrl = mem->fast_out(i); // Throw out-of-bounds if proj not found 2316 assert( ctrl->is_Proj(), "only projections here" ); 2317 ProjNode *proj = (ProjNode*)ctrl; 2318 if( proj->_con == TypeFunc::Control && 2319 !C->node_arena()->contains(ctrl) ) // Unmatched old-space only 2320 break; 2321 i++; 2322 } 2323 2324 for( DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++ ) { 2325 Node *x = ctrl->fast_out(j); 2326 int xop = x->Opcode(); 2327 2328 // We don't need current barrier if we see another or a lock 2329 // before seeing volatile load. 2330 // 2331 // Op_Fastunlock previously appeared in the Op_* list below. 2332 // With the advent of 1-0 lock operations we're no longer guaranteed 2333 // that a monitor exit operation contains a serializing instruction. 2334 2335 if (xop == Op_MemBarVolatile || 2336 xop == Op_FastLock || 2337 xop == Op_CompareAndSwapL || 2338 xop == Op_CompareAndSwapP || 2339 xop == Op_CompareAndSwapN || 2340 xop == Op_CompareAndSwapI) 2341 return true; 2342 2343 if (x->is_MemBar()) { 2344 // We must retain this membar if there is an upcoming volatile 2345 // load, which will be preceded by acquire membar. 2346 if (xop == Op_MemBarAcquire) 2347 return false; 2348 // For other kinds of barriers, check by pretending we 2349 // are them, and seeing if we can be removed. 2350 else 2351 return post_store_load_barrier((const MemBarNode*)x); 2352 } 2353 2354 // Delicate code to detect case of an upcoming fastlock block 2355 if( x->is_If() && x->req() > 1 && 2356 !C->node_arena()->contains(x) ) { // Unmatched old-space only 2357 Node *iff = x; 2358 Node *bol = iff->in(1); 2359 // The iff might be some random subclass of If or bol might be Con-Top 2360 if (!bol->is_Bool()) return false; 2361 assert( bol->req() > 1, "" ); 2362 return (bol->in(1)->Opcode() == Op_FastUnlock); 2363 } 2364 // probably not necessary to check for these 2365 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) 2366 return false; 2367 } 2368 return false; 2369} 2370 2371//============================================================================= 2372//---------------------------State--------------------------------------------- 2373State::State(void) { 2374#ifdef ASSERT 2375 _id = 0; 2376 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 2377 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 2378 //memset(_cost, -1, sizeof(_cost)); 2379 //memset(_rule, -1, sizeof(_rule)); 2380#endif 2381 memset(_valid, 0, sizeof(_valid)); 2382} 2383 2384#ifdef ASSERT 2385State::~State() { 2386 _id = 99; 2387 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 2388 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 2389 memset(_cost, -3, sizeof(_cost)); 2390 memset(_rule, -3, sizeof(_rule)); 2391} 2392#endif 2393 2394#ifndef PRODUCT 2395//---------------------------dump---------------------------------------------- 2396void State::dump() { 2397 tty->print("\n"); 2398 dump(0); 2399} 2400 2401void State::dump(int depth) { 2402 for( int j = 0; j < depth; j++ ) 2403 tty->print(" "); 2404 tty->print("--N: "); 2405 _leaf->dump(); 2406 uint i; 2407 for( i = 0; i < _LAST_MACH_OPER; i++ ) 2408 // Check for valid entry 2409 if( valid(i) ) { 2410 for( int j = 0; j < depth; j++ ) 2411 tty->print(" "); 2412 assert(_cost[i] != max_juint, "cost must be a valid value"); 2413 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule"); 2414 tty->print_cr("%s %d %s", 2415 ruleName[i], _cost[i], ruleName[_rule[i]] ); 2416 } 2417 tty->print_cr(""); 2418 2419 for( i=0; i<2; i++ ) 2420 if( _kids[i] ) 2421 _kids[i]->dump(depth+1); 2422} 2423#endif 2424