matcher.cpp revision 13244:ebbb31f0437e
10SN/A/* 21169Sjoehw * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 30SN/A * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 40SN/A * 5798Sjoehw * This code is free software; you can redistribute it and/or modify it 6798Sjoehw * under the terms of the GNU General Public License version 2 only, as 7798Sjoehw * published by the Free Software Foundation. 8798Sjoehw * 9798Sjoehw * This code is distributed in the hope that it will be useful, but WITHOUT 10798Sjoehw * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 110SN/A * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 120SN/A * version 2 for more details (a copy is included in the LICENSE file that 130SN/A * accompanied this code). 140SN/A * 150SN/A * You should have received a copy of the GNU General Public License version 160SN/A * 2 along with this work; if not, write to the Free Software Foundation, 170SN/A * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 180SN/A * 190SN/A * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 200SN/A * or visit www.oracle.com if you need additional information or have any 210SN/A * questions. 220SN/A * 230SN/A */ 240SN/A 250SN/A#include "precompiled.hpp" 260SN/A#include "memory/allocation.inline.hpp" 270SN/A#include "memory/resourceArea.hpp" 280SN/A#include "opto/ad.hpp" 290SN/A#include "opto/addnode.hpp" 300SN/A#include "opto/callnode.hpp" 310SN/A#include "opto/idealGraphPrinter.hpp" 320SN/A#include "opto/matcher.hpp" 330SN/A#include "opto/memnode.hpp" 340SN/A#include "opto/movenode.hpp" 350SN/A#include "opto/opcodes.hpp" 360SN/A#include "opto/regmask.hpp" 370SN/A#include "opto/rootnode.hpp" 380SN/A#include "opto/runtime.hpp" 390SN/A#include "opto/type.hpp" 400SN/A#include "opto/vectornode.hpp" 410SN/A#include "runtime/os.hpp" 420SN/A#include "runtime/sharedRuntime.hpp" 430SN/A 440SN/AOptoReg::Name OptoReg::c_frame_pointer; 45798Sjoehw 460SN/Aconst RegMask *Matcher::idealreg2regmask[_last_machine_leaf]; 470SN/ARegMask Matcher::mreg2regmask[_last_Mach_Reg]; 480SN/ARegMask Matcher::STACK_ONLY_mask; 490SN/ARegMask Matcher::c_frame_ptr_mask; 500SN/Aconst uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE; 510SN/Aconst uint Matcher::_end_rematerialize = _END_REMATERIALIZE; 520SN/A 530SN/A//---------------------------Matcher------------------------------------------- 540SN/AMatcher::Matcher() 550SN/A: PhaseTransform( Phase::Ins_Select ), 560SN/A#ifdef ASSERT 570SN/A _old2new_map(C->comp_arena()), 580SN/A _new2old_map(C->comp_arena()), 590SN/A#endif 600SN/A _shared_nodes(C->comp_arena()), 610SN/A _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp), 620SN/A _swallowed(swallowed), 630SN/A _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE), 640SN/A _end_inst_chain_rule(_END_INST_CHAIN_RULE), 650SN/A _must_clone(must_clone), 660SN/A _register_save_policy(register_save_policy), 670SN/A _c_reg_save_policy(c_reg_save_policy), 680SN/A _register_save_type(register_save_type), 690SN/A _ruleName(ruleName), 700SN/A _allocation_started(false), 710SN/A _states_arena(Chunk::medium_size), 720SN/A _visited(&_states_arena), 730SN/A _shared(&_states_arena), 740SN/A _dontcare(&_states_arena) { 750SN/A C->set_matcher(this); 760SN/A 770SN/A idealreg2spillmask [Op_RegI] = NULL; 780SN/A idealreg2spillmask [Op_RegN] = NULL; 790SN/A idealreg2spillmask [Op_RegL] = NULL; 800SN/A idealreg2spillmask [Op_RegF] = NULL; 810SN/A idealreg2spillmask [Op_RegD] = NULL; 820SN/A idealreg2spillmask [Op_RegP] = NULL; 830SN/A idealreg2spillmask [Op_VecS] = NULL; 840SN/A idealreg2spillmask [Op_VecD] = NULL; 850SN/A idealreg2spillmask [Op_VecX] = NULL; 860SN/A idealreg2spillmask [Op_VecY] = NULL; 870SN/A idealreg2spillmask [Op_VecZ] = NULL; 880SN/A idealreg2spillmask [Op_RegFlags] = NULL; 890SN/A 900SN/A idealreg2debugmask [Op_RegI] = NULL; 910SN/A idealreg2debugmask [Op_RegN] = NULL; 920SN/A idealreg2debugmask [Op_RegL] = NULL; 930SN/A idealreg2debugmask [Op_RegF] = NULL; 940SN/A idealreg2debugmask [Op_RegD] = NULL; 951169Sjoehw idealreg2debugmask [Op_RegP] = NULL; 960SN/A idealreg2debugmask [Op_VecS] = NULL; 970SN/A idealreg2debugmask [Op_VecD] = NULL; 980SN/A idealreg2debugmask [Op_VecX] = NULL; 990SN/A idealreg2debugmask [Op_VecY] = NULL; 1000SN/A idealreg2debugmask [Op_VecZ] = NULL; 1010SN/A idealreg2debugmask [Op_RegFlags] = NULL; 1020SN/A 1030SN/A idealreg2mhdebugmask[Op_RegI] = NULL; 1040SN/A idealreg2mhdebugmask[Op_RegN] = NULL; 1050SN/A idealreg2mhdebugmask[Op_RegL] = NULL; 1060SN/A idealreg2mhdebugmask[Op_RegF] = NULL; 1070SN/A idealreg2mhdebugmask[Op_RegD] = NULL; 1080SN/A idealreg2mhdebugmask[Op_RegP] = NULL; 1090SN/A idealreg2mhdebugmask[Op_VecS] = NULL; 1100SN/A idealreg2mhdebugmask[Op_VecD] = NULL; 1110SN/A idealreg2mhdebugmask[Op_VecX] = NULL; 1120SN/A idealreg2mhdebugmask[Op_VecY] = NULL; 1130SN/A idealreg2mhdebugmask[Op_VecZ] = NULL; 1140SN/A idealreg2mhdebugmask[Op_RegFlags] = NULL; 1150SN/A 1160SN/A debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node 1170SN/A} 1180SN/A 1190SN/A//------------------------------warp_incoming_stk_arg------------------------ 1200SN/A// This warps a VMReg into an OptoReg::Name 1210SN/AOptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) { 1220SN/A OptoReg::Name warped; 1230SN/A if( reg->is_stack() ) { // Stack slot argument? 1240SN/A warped = OptoReg::add(_old_SP, reg->reg2stack() ); 1250SN/A warped = OptoReg::add(warped, C->out_preserve_stack_slots()); 1260SN/A if( warped >= _in_arg_limit ) 1270SN/A _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen 1280SN/A if (!RegMask::can_represent_arg(warped)) { 1290SN/A // the compiler cannot represent this method's calling sequence 1300SN/A C->record_method_not_compilable("unsupported incoming calling sequence"); 1310SN/A return OptoReg::Bad; 1320SN/A } 1330SN/A return warped; 1340SN/A } 1350SN/A return OptoReg::as_OptoReg(reg); 1360SN/A} 1370SN/A 1380SN/A//---------------------------compute_old_SP------------------------------------ 1390SN/AOptoReg::Name Compile::compute_old_SP() { 1400SN/A int fixed = fixed_slots(); 1410SN/A int preserve = in_preserve_stack_slots(); 1420SN/A return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots())); 1430SN/A} 1440SN/A 1450SN/A 1460SN/A 1470SN/A#ifdef ASSERT 1480SN/Avoid Matcher::verify_new_nodes_only(Node* xroot) { 1490SN/A // Make sure that the new graph only references new nodes 1500SN/A ResourceMark rm; 1510SN/A Unique_Node_List worklist; 1520SN/A VectorSet visited(Thread::current()->resource_area()); 1530SN/A worklist.push(xroot); 1540SN/A while (worklist.size() > 0) { 1550SN/A Node* n = worklist.pop(); 1560SN/A visited <<= n->_idx; 1570SN/A assert(C->node_arena()->contains(n), "dead node"); 1580SN/A for (uint j = 0; j < n->req(); j++) { 1590SN/A Node* in = n->in(j); 1600SN/A if (in != NULL) { 1610SN/A assert(C->node_arena()->contains(in), "dead node"); 1620SN/A if (!visited.test(in->_idx)) { 1630SN/A worklist.push(in); 1640SN/A } 1650SN/A } 1660SN/A } 1670SN/A } 1680SN/A} 1690SN/A#endif 1700SN/A 1710SN/A 1720SN/A//---------------------------match--------------------------------------------- 1730SN/Avoid Matcher::match( ) { 1740SN/A if( MaxLabelRootDepth < 100 ) { // Too small? 1750SN/A assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum"); 1760SN/A MaxLabelRootDepth = 100; 1770SN/A } 1780SN/A // One-time initialization of some register masks. 1790SN/A init_spill_mask( C->root()->in(1) ); 1800SN/A _return_addr_mask = return_addr(); 1810SN/A#ifdef _LP64 1820SN/A // Pointers take 2 slots in 64-bit land 1830SN/A _return_addr_mask.Insert(OptoReg::add(return_addr(),1)); 1840SN/A#endif 1850SN/A 1860SN/A // Map a Java-signature return type into return register-value 1870SN/A // machine registers for 0, 1 and 2 returned values. 1880SN/A const TypeTuple *range = C->tf()->range(); 1890SN/A if( range->cnt() > TypeFunc::Parms ) { // If not a void function 1900SN/A // Get ideal-register return type 1910SN/A uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg(); 1920SN/A // Get machine return register 1930SN/A uint sop = C->start()->Opcode(); 1940SN/A OptoRegPair regs = return_value(ireg, false); 1950SN/A 1960SN/A // And mask for same 1970SN/A _return_value_mask = RegMask(regs.first()); 1980SN/A if( OptoReg::is_valid(regs.second()) ) 1990SN/A _return_value_mask.Insert(regs.second()); 2000SN/A } 2010SN/A 2020SN/A // --------------- 2030SN/A // Frame Layout 2040SN/A 2050SN/A // Need the method signature to determine the incoming argument types, 2060SN/A // because the types determine which registers the incoming arguments are 2070SN/A // in, and this affects the matched code. 2080SN/A const TypeTuple *domain = C->tf()->domain(); 2090SN/A uint argcnt = domain->cnt() - TypeFunc::Parms; 2100SN/A BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 2110SN/A VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 2120SN/A _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt ); 2130SN/A _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt ); 2140SN/A uint i; 2150SN/A for( i = 0; i<argcnt; i++ ) { 2160SN/A sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 2170SN/A } 2180SN/A 2190SN/A // Pass array of ideal registers and length to USER code (from the AD file) 2200SN/A // that will convert this to an array of register numbers. 2210SN/A const StartNode *start = C->start(); 2220SN/A start->calling_convention( sig_bt, vm_parm_regs, argcnt ); 2230SN/A#ifdef ASSERT 2240SN/A // Sanity check users' calling convention. Real handy while trying to 2250SN/A // get the initial port correct. 2260SN/A { for (uint i = 0; i<argcnt; i++) { 2270SN/A if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 2280SN/A assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" ); 2290SN/A _parm_regs[i].set_bad(); 2300SN/A continue; 2310SN/A } 2320SN/A VMReg parm_reg = vm_parm_regs[i].first(); 2330SN/A assert(parm_reg->is_valid(), "invalid arg?"); 2340SN/A if (parm_reg->is_reg()) { 2350SN/A OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg); 2360SN/A assert(can_be_java_arg(opto_parm_reg) || 2370SN/A C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) || 2380SN/A opto_parm_reg == inline_cache_reg(), 2390SN/A "parameters in register must be preserved by runtime stubs"); 2400SN/A } 2410SN/A for (uint j = 0; j < i; j++) { 2420SN/A assert(parm_reg != vm_parm_regs[j].first(), 2430SN/A "calling conv. must produce distinct regs"); 2440SN/A } 2450SN/A } 2460SN/A } 2470SN/A#endif 2480SN/A 2490SN/A // Do some initial frame layout. 2500SN/A 2510SN/A // Compute the old incoming SP (may be called FP) as 2520SN/A // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2. 2530SN/A _old_SP = C->compute_old_SP(); 2540SN/A assert( is_even(_old_SP), "must be even" ); 2550SN/A 2560SN/A // Compute highest incoming stack argument as 2570SN/A // _old_SP + out_preserve_stack_slots + incoming argument size. 2580SN/A _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 2590SN/A assert( is_even(_in_arg_limit), "out_preserve must be even" ); 2600SN/A for( i = 0; i < argcnt; i++ ) { 2610SN/A // Permit args to have no register 2620SN/A _calling_convention_mask[i].Clear(); 2630SN/A if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 2640SN/A continue; 2650SN/A } 2660SN/A // calling_convention returns stack arguments as a count of 2670SN/A // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to 2680SN/A // the allocators point of view, taking into account all the 2690SN/A // preserve area, locks & pad2. 2700SN/A 2710SN/A OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first()); 2720SN/A if( OptoReg::is_valid(reg1)) 2730SN/A _calling_convention_mask[i].Insert(reg1); 2740SN/A 2750SN/A OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second()); 2760SN/A if( OptoReg::is_valid(reg2)) 2770SN/A _calling_convention_mask[i].Insert(reg2); 2780SN/A 2790SN/A // Saved biased stack-slot register number 2800SN/A _parm_regs[i].set_pair(reg2, reg1); 2810SN/A } 2820SN/A 2830SN/A // Finally, make sure the incoming arguments take up an even number of 2840SN/A // words, in case the arguments or locals need to contain doubleword stack 2850SN/A // slots. The rest of the system assumes that stack slot pairs (in 2860SN/A // particular, in the spill area) which look aligned will in fact be 2870SN/A // aligned relative to the stack pointer in the target machine. Double 2880SN/A // stack slots will always be allocated aligned. 2890SN/A _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong)); 2900SN/A 2910SN/A // Compute highest outgoing stack argument as 2920SN/A // _new_SP + out_preserve_stack_slots + max(outgoing argument size). 2930SN/A _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 2940SN/A assert( is_even(_out_arg_limit), "out_preserve must be even" ); 2950SN/A 2960SN/A if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) { 2970SN/A // the compiler cannot represent this method's calling sequence 2980SN/A C->record_method_not_compilable("must be able to represent all call arguments in reg mask"); 2990SN/A } 3000SN/A 3010SN/A if (C->failing()) return; // bailed out on incoming arg failure 3020SN/A 3030SN/A // --------------- 3040SN/A // Collect roots of matcher trees. Every node for which 3050SN/A // _shared[_idx] is cleared is guaranteed to not be shared, and thus 3060SN/A // can be a valid interior of some tree. 3070SN/A find_shared( C->root() ); 3080SN/A find_shared( C->top() ); 3090SN/A 3100SN/A C->print_method(PHASE_BEFORE_MATCHING); 3110SN/A 3120SN/A // Create new ideal node ConP #NULL even if it does exist in old space 3130SN/A // to avoid false sharing if the corresponding mach node is not used. 3140SN/A // The corresponding mach node is only used in rare cases for derived 3150SN/A // pointers. 3160SN/A Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR); 3170SN/A 3180SN/A // Swap out to old-space; emptying new-space 3190SN/A Arena *old = C->node_arena()->move_contents(C->old_arena()); 3200SN/A 3210SN/A // Save debug and profile information for nodes in old space: 3220SN/A _old_node_note_array = C->node_note_array(); 323798Sjoehw if (_old_node_note_array != NULL) { 3240SN/A C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*> 325798Sjoehw (C->comp_arena(), _old_node_note_array->length(), 326798Sjoehw 0, NULL)); 3270SN/A } 3280SN/A 3290SN/A // Pre-size the new_node table to avoid the need for range checks. 3300SN/A grow_new_node_array(C->unique()); 3310SN/A 3320SN/A // Reset node counter so MachNodes start with _idx at 0 3330SN/A int live_nodes = C->live_nodes(); 3340SN/A C->set_unique(0); 3350SN/A C->reset_dead_node_list(); 3360SN/A 3370SN/A // Recursively match trees from old space into new space. 3380SN/A // Correct leaves of new-space Nodes; they point to old-space. 3390SN/A _visited.Clear(); // Clear visit bits for xform call 3400SN/A C->set_cached_top_node(xform( C->top(), live_nodes )); 3410SN/A if (!C->failing()) { 3420SN/A Node* xroot = xform( C->root(), 1 ); 3430SN/A if (xroot == NULL) { 3440SN/A Matcher::soft_match_failure(); // recursive matching process failed 3450SN/A C->record_method_not_compilable("instruction match failed"); 3460SN/A } else { 3470SN/A // During matching shared constants were attached to C->root() 3480SN/A // because xroot wasn't available yet, so transfer the uses to 3490SN/A // the xroot. 3500SN/A for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) { 3510SN/A Node* n = C->root()->fast_out(j); 3520SN/A if (C->node_arena()->contains(n)) { 3530SN/A assert(n->in(0) == C->root(), "should be control user"); 3540SN/A n->set_req(0, xroot); 3550SN/A --j; 3560SN/A --jmax; 3570SN/A } 3580SN/A } 3590SN/A 3600SN/A // Generate new mach node for ConP #NULL 3610SN/A assert(new_ideal_null != NULL, "sanity"); 3620SN/A _mach_null = match_tree(new_ideal_null); 3630SN/A // Don't set control, it will confuse GCM since there are no uses. 3640SN/A // The control will be set when this node is used first time 3650SN/A // in find_base_for_derived(). 3660SN/A assert(_mach_null != NULL, ""); 3670SN/A 3680SN/A C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL); 3690SN/A 3700SN/A#ifdef ASSERT 3710SN/A verify_new_nodes_only(xroot); 3720SN/A#endif 3730SN/A } 3740SN/A } 3750SN/A if (C->top() == NULL || C->root() == NULL) { 3760SN/A C->record_method_not_compilable("graph lost"); // %%% cannot happen? 3770SN/A } 3780SN/A if (C->failing()) { 3790SN/A // delete old; 3800SN/A old->destruct_contents(); 3810SN/A return; 3820SN/A } 3830SN/A assert( C->top(), "" ); 3840SN/A assert( C->root(), "" ); 3850SN/A validate_null_checks(); 3860SN/A 3870SN/A // Now smoke old-space 3880SN/A NOT_DEBUG( old->destruct_contents() ); 3890SN/A 3900SN/A // ------------------------ 3910SN/A // Set up save-on-entry registers 3920SN/A Fixup_Save_On_Entry( ); 3930SN/A} 3940SN/A 3950SN/A 3960SN/A//------------------------------Fixup_Save_On_Entry---------------------------- 3970SN/A// The stated purpose of this routine is to take care of save-on-entry 3980SN/A// registers. However, the overall goal of the Match phase is to convert into 3990SN/A// machine-specific instructions which have RegMasks to guide allocation. 4000SN/A// So what this procedure really does is put a valid RegMask on each input 4010SN/A// to the machine-specific variations of all Return, TailCall and Halt 4020SN/A// instructions. It also adds edgs to define the save-on-entry values (and of 4030SN/A// course gives them a mask). 4040SN/A 4050SN/Astatic RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) { 4060SN/A RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size ); 4070SN/A // Do all the pre-defined register masks 4080SN/A rms[TypeFunc::Control ] = RegMask::Empty; 4090SN/A rms[TypeFunc::I_O ] = RegMask::Empty; 4100SN/A rms[TypeFunc::Memory ] = RegMask::Empty; 4110SN/A rms[TypeFunc::ReturnAdr] = ret_adr; 4120SN/A rms[TypeFunc::FramePtr ] = fp; 4130SN/A return rms; 4140SN/A} 4150SN/A 4160SN/A//---------------------------init_first_stack_mask----------------------------- 4170SN/A// Create the initial stack mask used by values spilling to the stack. 4180SN/A// Disallow any debug info in outgoing argument areas by setting the 4190SN/A// initial mask accordingly. 4200SN/Avoid Matcher::init_first_stack_mask() { 4210SN/A 4220SN/A // Allocate storage for spill masks as masks for the appropriate load type. 4230SN/A RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5)); 4240SN/A 4250SN/A idealreg2spillmask [Op_RegN] = &rms[0]; 4260SN/A idealreg2spillmask [Op_RegI] = &rms[1]; 4270SN/A idealreg2spillmask [Op_RegL] = &rms[2]; 4280SN/A idealreg2spillmask [Op_RegF] = &rms[3]; 4290SN/A idealreg2spillmask [Op_RegD] = &rms[4]; 4300SN/A idealreg2spillmask [Op_RegP] = &rms[5]; 4310SN/A 4320SN/A idealreg2debugmask [Op_RegN] = &rms[6]; 4330SN/A idealreg2debugmask [Op_RegI] = &rms[7]; 4340SN/A idealreg2debugmask [Op_RegL] = &rms[8]; 4350SN/A idealreg2debugmask [Op_RegF] = &rms[9]; 4360SN/A idealreg2debugmask [Op_RegD] = &rms[10]; 4370SN/A idealreg2debugmask [Op_RegP] = &rms[11]; 4380SN/A 4390SN/A idealreg2mhdebugmask[Op_RegN] = &rms[12]; 4400SN/A idealreg2mhdebugmask[Op_RegI] = &rms[13]; 4410SN/A idealreg2mhdebugmask[Op_RegL] = &rms[14]; 4420SN/A idealreg2mhdebugmask[Op_RegF] = &rms[15]; 4430SN/A idealreg2mhdebugmask[Op_RegD] = &rms[16]; 4440SN/A idealreg2mhdebugmask[Op_RegP] = &rms[17]; 4450SN/A 4460SN/A idealreg2spillmask [Op_VecS] = &rms[18]; 4470SN/A idealreg2spillmask [Op_VecD] = &rms[19]; 4480SN/A idealreg2spillmask [Op_VecX] = &rms[20]; 4490SN/A idealreg2spillmask [Op_VecY] = &rms[21]; 4500SN/A idealreg2spillmask [Op_VecZ] = &rms[22]; 4510SN/A 4520SN/A OptoReg::Name i; 4530SN/A 4540SN/A // At first, start with the empty mask 4550SN/A C->FIRST_STACK_mask().Clear(); 4560SN/A 4570SN/A // Add in the incoming argument area 4580SN/A OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 4590SN/A for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) { 4600SN/A C->FIRST_STACK_mask().Insert(i); 4610SN/A } 4620SN/A // Add in all bits past the outgoing argument area 4630SN/A guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)), 4640SN/A "must be able to represent all call arguments in reg mask"); 4650SN/A OptoReg::Name init = _out_arg_limit; 4660SN/A for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) { 4670SN/A C->FIRST_STACK_mask().Insert(i); 4680SN/A } 4690SN/A // Finally, set the "infinite stack" bit. 4700SN/A C->FIRST_STACK_mask().set_AllStack(); 4710SN/A 4720SN/A // Make spill masks. Registers for their class, plus FIRST_STACK_mask. 4730SN/A RegMask aligned_stack_mask = C->FIRST_STACK_mask(); 4740SN/A // Keep spill masks aligned. 4750SN/A aligned_stack_mask.clear_to_pairs(); 4760SN/A assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 4770SN/A 4780SN/A *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP]; 4790SN/A#ifdef _LP64 4800SN/A *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN]; 4810SN/A idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask()); 4820SN/A idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask); 4830SN/A#else 4840SN/A idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask()); 4850SN/A#endif 4860SN/A *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI]; 4870SN/A idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask()); 4880SN/A *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL]; 4890SN/A idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask); 4900SN/A *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF]; 4910SN/A idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask()); 4920SN/A *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD]; 4930SN/A idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask); 4940SN/A 4950SN/A if (Matcher::vector_size_supported(T_BYTE,4)) { 4960SN/A *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS]; 4970SN/A idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask()); 4980SN/A } 4990SN/A if (Matcher::vector_size_supported(T_FLOAT,2)) { 5000SN/A // For VecD we need dual alignment and 8 bytes (2 slots) for spills. 5010SN/A // RA guarantees such alignment since it is needed for Double and Long values. 5020SN/A *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD]; 5030SN/A idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask); 5040SN/A } 5050SN/A if (Matcher::vector_size_supported(T_FLOAT,4)) { 5060SN/A // For VecX we need quadro alignment and 16 bytes (4 slots) for spills. 5070SN/A // 5080SN/A // RA can use input arguments stack slots for spills but until RA 5090SN/A // we don't know frame size and offset of input arg stack slots. 5100SN/A // 5110SN/A // Exclude last input arg stack slots to avoid spilling vectors there 5120SN/A // otherwise vector spills could stomp over stack slots in caller frame. 5130SN/A OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 5140SN/A for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) { 5150SN/A aligned_stack_mask.Remove(in); 5160SN/A in = OptoReg::add(in, -1); 5170SN/A } 5180SN/A aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX); 5190SN/A assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 5200SN/A *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX]; 5210SN/A idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask); 5220SN/A } 5230SN/A if (Matcher::vector_size_supported(T_FLOAT,8)) { 5240SN/A // For VecY we need octo alignment and 32 bytes (8 slots) for spills. 5250SN/A OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 5260SN/A for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) { 5270SN/A aligned_stack_mask.Remove(in); 5280SN/A in = OptoReg::add(in, -1); 5290SN/A } 5300SN/A aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY); 5310SN/A assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 5320SN/A *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY]; 5330SN/A idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask); 5340SN/A } 5350SN/A if (Matcher::vector_size_supported(T_FLOAT,16)) { 5360SN/A // For VecZ we need enough alignment and 64 bytes (16 slots) for spills. 5370SN/A OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 5380SN/A for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) { 5390SN/A aligned_stack_mask.Remove(in); 5400SN/A in = OptoReg::add(in, -1); 5410SN/A } 5420SN/A aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ); 5430SN/A assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 5440SN/A *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ]; 5450SN/A idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask); 5460SN/A } 5470SN/A if (UseFPUForSpilling) { 5480SN/A // This mask logic assumes that the spill operations are 5490SN/A // symmetric and that the registers involved are the same size. 5500SN/A // On sparc for instance we may have to use 64 bit moves will 5510SN/A // kill 2 registers when used with F0-F31. 5520SN/A idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]); 5530SN/A idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]); 5540SN/A#ifdef _LP64 5550SN/A idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]); 5560SN/A idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 5570SN/A idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 5580SN/A idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); 5590SN/A#else 5600SN/A idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); 5610SN/A#ifdef ARM 5620SN/A // ARM has support for moving 64bit values between a pair of 5630SN/A // integer registers and a double register 5640SN/A idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 5650SN/A idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 5660SN/A#endif 5670SN/A#endif 5680SN/A } 5690SN/A 5700SN/A // Make up debug masks. Any spill slot plus callee-save registers. 5710SN/A // Caller-save registers are assumed to be trashable by the various 5720SN/A // inline-cache fixup routines. 5730SN/A *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN]; 5740SN/A *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI]; 5750SN/A *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL]; 5760SN/A *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF]; 5770SN/A *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD]; 5780SN/A *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP]; 5790SN/A 5800SN/A *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN]; 5810SN/A *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI]; 5820SN/A *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL]; 5830SN/A *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF]; 5840SN/A *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD]; 5850SN/A *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP]; 5860SN/A 5870SN/A // Prevent stub compilations from attempting to reference 5880SN/A // callee-saved registers from debug info 5890SN/A bool exclude_soe = !Compile::current()->is_method_compilation(); 5900SN/A 5910SN/A for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { 5920SN/A // registers the caller has to save do not work 5930SN/A if( _register_save_policy[i] == 'C' || 5940SN/A _register_save_policy[i] == 'A' || 5950SN/A (_register_save_policy[i] == 'E' && exclude_soe) ) { 5960SN/A idealreg2debugmask [Op_RegN]->Remove(i); 5970SN/A idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call 5980SN/A idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug 5990SN/A idealreg2debugmask [Op_RegF]->Remove(i); // masks 6000SN/A idealreg2debugmask [Op_RegD]->Remove(i); 6010SN/A idealreg2debugmask [Op_RegP]->Remove(i); 6020SN/A 6030SN/A idealreg2mhdebugmask[Op_RegN]->Remove(i); 6040SN/A idealreg2mhdebugmask[Op_RegI]->Remove(i); 6050SN/A idealreg2mhdebugmask[Op_RegL]->Remove(i); 6060SN/A idealreg2mhdebugmask[Op_RegF]->Remove(i); 6070SN/A idealreg2mhdebugmask[Op_RegD]->Remove(i); 6080SN/A idealreg2mhdebugmask[Op_RegP]->Remove(i); 6090SN/A } 6100SN/A } 6110SN/A 6120SN/A // Subtract the register we use to save the SP for MethodHandle 6130SN/A // invokes to from the debug mask. 6140SN/A const RegMask save_mask = method_handle_invoke_SP_save_mask(); 6150SN/A idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask); 6160SN/A idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask); 6170SN/A idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask); 6180SN/A idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask); 6190SN/A idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask); 6200SN/A idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask); 6210SN/A} 6220SN/A 6230SN/A//---------------------------is_save_on_entry---------------------------------- 6240SN/Abool Matcher::is_save_on_entry( int reg ) { 6250SN/A return 6260SN/A _register_save_policy[reg] == 'E' || 6270SN/A _register_save_policy[reg] == 'A' || // Save-on-entry register? 6280SN/A // Also save argument registers in the trampolining stubs 6290SN/A (C->save_argument_registers() && is_spillable_arg(reg)); 6300SN/A} 6310SN/A 6320SN/A//---------------------------Fixup_Save_On_Entry------------------------------- 6330SN/Avoid Matcher::Fixup_Save_On_Entry( ) { 6340SN/A init_first_stack_mask(); 6350SN/A 6360SN/A Node *root = C->root(); // Short name for root 6370SN/A // Count number of save-on-entry registers. 6380SN/A uint soe_cnt = number_of_saved_registers(); 6390SN/A uint i; 6400SN/A 6410SN/A // Find the procedure Start Node 6420SN/A StartNode *start = C->start(); 6430SN/A assert( start, "Expect a start node" ); 6440SN/A 6450SN/A // Save argument registers in the trampolining stubs 6460SN/A if( C->save_argument_registers() ) 6470SN/A for( i = 0; i < _last_Mach_Reg; i++ ) 6480SN/A if( is_spillable_arg(i) ) 6490SN/A soe_cnt++; 6500SN/A 6510SN/A // Input RegMask array shared by all Returns. 6520SN/A // The type for doubles and longs has a count of 2, but 6530SN/A // there is only 1 returned value 6540SN/A uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1); 6550SN/A RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 6560SN/A // Returns have 0 or 1 returned values depending on call signature. 6570SN/A // Return register is specified by return_value in the AD file. 6580SN/A if (ret_edge_cnt > TypeFunc::Parms) 6590SN/A ret_rms[TypeFunc::Parms+0] = _return_value_mask; 6600SN/A 6610SN/A // Input RegMask array shared by all Rethrows. 6620SN/A uint reth_edge_cnt = TypeFunc::Parms+1; 6630SN/A RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 6640SN/A // Rethrow takes exception oop only, but in the argument 0 slot. 6650SN/A OptoReg::Name reg = find_receiver(false); 6660SN/A if (reg >= 0) { 6670SN/A reth_rms[TypeFunc::Parms] = mreg2regmask[reg]; 6680SN/A#ifdef _LP64 6690SN/A // Need two slots for ptrs in 64-bit land 6700SN/A reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1)); 6710SN/A#endif 6720SN/A } 6730SN/A 6740SN/A // Input RegMask array shared by all TailCalls 6750SN/A uint tail_call_edge_cnt = TypeFunc::Parms+2; 6760SN/A RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 6770SN/A 6780SN/A // Input RegMask array shared by all TailJumps 6790SN/A uint tail_jump_edge_cnt = TypeFunc::Parms+2; 6800SN/A RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 6810SN/A 6820SN/A // TailCalls have 2 returned values (target & moop), whose masks come 6830SN/A // from the usual MachNode/MachOper mechanism. Find a sample 6840SN/A // TailCall to extract these masks and put the correct masks into 6850SN/A // the tail_call_rms array. 6860SN/A for( i=1; i < root->req(); i++ ) { 6870SN/A MachReturnNode *m = root->in(i)->as_MachReturn(); 6880SN/A if( m->ideal_Opcode() == Op_TailCall ) { 6890SN/A tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 6900SN/A tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 6910SN/A break; 6920SN/A } 6930SN/A } 6940SN/A 6950SN/A // TailJumps have 2 returned values (target & ex_oop), whose masks come 6960SN/A // from the usual MachNode/MachOper mechanism. Find a sample 6970SN/A // TailJump to extract these masks and put the correct masks into 6980SN/A // the tail_jump_rms array. 6990SN/A for( i=1; i < root->req(); i++ ) { 7000SN/A MachReturnNode *m = root->in(i)->as_MachReturn(); 7010SN/A if( m->ideal_Opcode() == Op_TailJump ) { 7020SN/A tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 7030SN/A tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 7040SN/A break; 7050SN/A } 7060SN/A } 7070SN/A 7080SN/A // Input RegMask array shared by all Halts 7090SN/A uint halt_edge_cnt = TypeFunc::Parms; 7100SN/A RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 7110SN/A 7120SN/A // Capture the return input masks into each exit flavor 7130SN/A for( i=1; i < root->req(); i++ ) { 7140SN/A MachReturnNode *exit = root->in(i)->as_MachReturn(); 7150SN/A switch( exit->ideal_Opcode() ) { 7160SN/A case Op_Return : exit->_in_rms = ret_rms; break; 7170SN/A case Op_Rethrow : exit->_in_rms = reth_rms; break; 7180SN/A case Op_TailCall : exit->_in_rms = tail_call_rms; break; 7190SN/A case Op_TailJump : exit->_in_rms = tail_jump_rms; break; 7200SN/A case Op_Halt : exit->_in_rms = halt_rms; break; 7210SN/A default : ShouldNotReachHere(); 7220SN/A } 7230SN/A } 7240SN/A 7250SN/A // Next unused projection number from Start. 7260SN/A int proj_cnt = C->tf()->domain()->cnt(); 7270SN/A 7280SN/A // Do all the save-on-entry registers. Make projections from Start for 7290SN/A // them, and give them a use at the exit points. To the allocator, they 7300SN/A // look like incoming register arguments. 7310SN/A for( i = 0; i < _last_Mach_Reg; i++ ) { 7320SN/A if( is_save_on_entry(i) ) { 7330SN/A 7340SN/A // Add the save-on-entry to the mask array 7350SN/A ret_rms [ ret_edge_cnt] = mreg2regmask[i]; 7360SN/A reth_rms [ reth_edge_cnt] = mreg2regmask[i]; 7370SN/A tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i]; 7380SN/A tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i]; 7390SN/A // Halts need the SOE registers, but only in the stack as debug info. 7400SN/A // A just-prior uncommon-trap or deoptimization will use the SOE regs. 7410SN/A halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]]; 7420SN/A 7430SN/A Node *mproj; 7440SN/A 7450SN/A // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's 7460SN/A // into a single RegD. 7470SN/A if( (i&1) == 0 && 7480SN/A _register_save_type[i ] == Op_RegF && 7490SN/A _register_save_type[i+1] == Op_RegF && 7500SN/A is_save_on_entry(i+1) ) { 7510SN/A // Add other bit for double 7520SN/A ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 7530SN/A reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 7540SN/A tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 7550SN/A tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 7560SN/A halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 7570SN/A mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD ); 7580SN/A proj_cnt += 2; // Skip 2 for doubles 7590SN/A } 7600SN/A else if( (i&1) == 1 && // Else check for high half of double 7610SN/A _register_save_type[i-1] == Op_RegF && 7620SN/A _register_save_type[i ] == Op_RegF && 7630SN/A is_save_on_entry(i-1) ) { 7640SN/A ret_rms [ ret_edge_cnt] = RegMask::Empty; 7650SN/A reth_rms [ reth_edge_cnt] = RegMask::Empty; 7660SN/A tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 7670SN/A tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 7680SN/A halt_rms [ halt_edge_cnt] = RegMask::Empty; 7690SN/A mproj = C->top(); 7700SN/A } 7710SN/A // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's 7720SN/A // into a single RegL. 7730SN/A else if( (i&1) == 0 && 7740SN/A _register_save_type[i ] == Op_RegI && 7750SN/A _register_save_type[i+1] == Op_RegI && 7760SN/A is_save_on_entry(i+1) ) { 7770SN/A // Add other bit for long 7780SN/A ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 7790SN/A reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 7800SN/A tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 7810SN/A tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 7820SN/A halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 7830SN/A mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL ); 7840SN/A proj_cnt += 2; // Skip 2 for longs 7850SN/A } 7860SN/A else if( (i&1) == 1 && // Else check for high half of long 7870SN/A _register_save_type[i-1] == Op_RegI && 7880SN/A _register_save_type[i ] == Op_RegI && 7890SN/A is_save_on_entry(i-1) ) { 7900SN/A ret_rms [ ret_edge_cnt] = RegMask::Empty; 7910SN/A reth_rms [ reth_edge_cnt] = RegMask::Empty; 7920SN/A tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 7930SN/A tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 7940SN/A halt_rms [ halt_edge_cnt] = RegMask::Empty; 7950SN/A mproj = C->top(); 7960SN/A } else { 7970SN/A // Make a projection for it off the Start 7980SN/A mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] ); 7990SN/A } 8000SN/A 8010SN/A ret_edge_cnt ++; 8020SN/A reth_edge_cnt ++; 8030SN/A tail_call_edge_cnt ++; 8040SN/A tail_jump_edge_cnt ++; 8050SN/A halt_edge_cnt ++; 8060SN/A 8070SN/A // Add a use of the SOE register to all exit paths 8080SN/A for( uint j=1; j < root->req(); j++ ) 8090SN/A root->in(j)->add_req(mproj); 8100SN/A } // End of if a save-on-entry register 8110SN/A } // End of for all machine registers 8120SN/A} 8130SN/A 8140SN/A//------------------------------init_spill_mask-------------------------------- 8150SN/Avoid Matcher::init_spill_mask( Node *ret ) { 8160SN/A if( idealreg2regmask[Op_RegI] ) return; // One time only init 8170SN/A 8180SN/A OptoReg::c_frame_pointer = c_frame_pointer(); 8190SN/A c_frame_ptr_mask = c_frame_pointer(); 8200SN/A#ifdef _LP64 8210SN/A // pointers are twice as big 8220SN/A c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1)); 8230SN/A#endif 8240SN/A 8250SN/A // Start at OptoReg::stack0() 8260SN/A STACK_ONLY_mask.Clear(); 8270SN/A OptoReg::Name init = OptoReg::stack2reg(0); 8280SN/A // STACK_ONLY_mask is all stack bits 8290SN/A OptoReg::Name i; 8300SN/A for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) 8310SN/A STACK_ONLY_mask.Insert(i); 8320SN/A // Also set the "infinite stack" bit. 8330SN/A STACK_ONLY_mask.set_AllStack(); 8340SN/A 8350SN/A // Copy the register names over into the shared world 8360SN/A for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) { 8370SN/A // SharedInfo::regName[i] = regName[i]; 8380SN/A // Handy RegMasks per machine register 8390SN/A mreg2regmask[i].Insert(i); 8400SN/A } 8410SN/A 8420SN/A // Grab the Frame Pointer 8430SN/A Node *fp = ret->in(TypeFunc::FramePtr); 8440SN/A Node *mem = ret->in(TypeFunc::Memory); 8450SN/A const TypePtr* atp = TypePtr::BOTTOM; 8460SN/A // Share frame pointer while making spill ops 8470SN/A set_shared(fp); 8480SN/A 8490SN/A // Compute generic short-offset Loads 8500SN/A#ifdef _LP64 8510SN/A MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered)); 8520SN/A#endif 8530SN/A MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered)); 8540SN/A MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false)); 8550SN/A MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered)); 8560SN/A MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered)); 8570SN/A MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered)); 8580SN/A assert(spillI != NULL && spillL != NULL && spillF != NULL && 8590SN/A spillD != NULL && spillP != NULL, ""); 8600SN/A // Get the ADLC notion of the right regmask, for each basic type. 8610SN/A#ifdef _LP64 8620SN/A idealreg2regmask[Op_RegN] = &spillCP->out_RegMask(); 8630SN/A#endif 8640SN/A idealreg2regmask[Op_RegI] = &spillI->out_RegMask(); 8650SN/A idealreg2regmask[Op_RegL] = &spillL->out_RegMask(); 8660SN/A idealreg2regmask[Op_RegF] = &spillF->out_RegMask(); 8670SN/A idealreg2regmask[Op_RegD] = &spillD->out_RegMask(); 8680SN/A idealreg2regmask[Op_RegP] = &spillP->out_RegMask(); 8690SN/A 8700SN/A // Vector regmasks. 8710SN/A if (Matcher::vector_size_supported(T_BYTE,4)) { 8720SN/A TypeVect::VECTS = TypeVect::make(T_BYTE, 4); 8730SN/A MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS)); 8740SN/A idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask(); 8750SN/A } 8760SN/A if (Matcher::vector_size_supported(T_FLOAT,2)) { 8770SN/A MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD)); 8780SN/A idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask(); 879 } 880 if (Matcher::vector_size_supported(T_FLOAT,4)) { 881 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX)); 882 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask(); 883 } 884 if (Matcher::vector_size_supported(T_FLOAT,8)) { 885 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY)); 886 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask(); 887 } 888 if (Matcher::vector_size_supported(T_FLOAT,16)) { 889 MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ)); 890 idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask(); 891 } 892} 893 894#ifdef ASSERT 895static void match_alias_type(Compile* C, Node* n, Node* m) { 896 if (!VerifyAliases) return; // do not go looking for trouble by default 897 const TypePtr* nat = n->adr_type(); 898 const TypePtr* mat = m->adr_type(); 899 int nidx = C->get_alias_index(nat); 900 int midx = C->get_alias_index(mat); 901 // Detune the assert for cases like (AndI 0xFF (LoadB p)). 902 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) { 903 for (uint i = 1; i < n->req(); i++) { 904 Node* n1 = n->in(i); 905 const TypePtr* n1at = n1->adr_type(); 906 if (n1at != NULL) { 907 nat = n1at; 908 nidx = C->get_alias_index(n1at); 909 } 910 } 911 } 912 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases: 913 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) { 914 switch (n->Opcode()) { 915 case Op_PrefetchAllocation: 916 nidx = Compile::AliasIdxRaw; 917 nat = TypeRawPtr::BOTTOM; 918 break; 919 } 920 } 921 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) { 922 switch (n->Opcode()) { 923 case Op_ClearArray: 924 midx = Compile::AliasIdxRaw; 925 mat = TypeRawPtr::BOTTOM; 926 break; 927 } 928 } 929 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) { 930 switch (n->Opcode()) { 931 case Op_Return: 932 case Op_Rethrow: 933 case Op_Halt: 934 case Op_TailCall: 935 case Op_TailJump: 936 nidx = Compile::AliasIdxBot; 937 nat = TypePtr::BOTTOM; 938 break; 939 } 940 } 941 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) { 942 switch (n->Opcode()) { 943 case Op_StrComp: 944 case Op_StrEquals: 945 case Op_StrIndexOf: 946 case Op_StrIndexOfChar: 947 case Op_AryEq: 948 case Op_HasNegatives: 949 case Op_MemBarVolatile: 950 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type? 951 case Op_StrInflatedCopy: 952 case Op_StrCompressedCopy: 953 case Op_OnSpinWait: 954 case Op_EncodeISOArray: 955 nidx = Compile::AliasIdxTop; 956 nat = NULL; 957 break; 958 } 959 } 960 if (nidx != midx) { 961 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) { 962 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx); 963 n->dump(); 964 m->dump(); 965 } 966 assert(C->subsume_loads() && C->must_alias(nat, midx), 967 "must not lose alias info when matching"); 968 } 969} 970#endif 971 972//------------------------------xform------------------------------------------ 973// Given a Node in old-space, Match him (Label/Reduce) to produce a machine 974// Node in new-space. Given a new-space Node, recursively walk his children. 975Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; } 976Node *Matcher::xform( Node *n, int max_stack ) { 977 // Use one stack to keep both: child's node/state and parent's node/index 978 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2 979 mstack.push(n, Visit, NULL, -1); // set NULL as parent to indicate root 980 while (mstack.is_nonempty()) { 981 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions"); 982 if (C->failing()) return NULL; 983 n = mstack.node(); // Leave node on stack 984 Node_State nstate = mstack.state(); 985 if (nstate == Visit) { 986 mstack.set_state(Post_Visit); 987 Node *oldn = n; 988 // Old-space or new-space check 989 if (!C->node_arena()->contains(n)) { 990 // Old space! 991 Node* m; 992 if (has_new_node(n)) { // Not yet Label/Reduced 993 m = new_node(n); 994 } else { 995 if (!is_dontcare(n)) { // Matcher can match this guy 996 // Calls match special. They match alone with no children. 997 // Their children, the incoming arguments, match normally. 998 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n); 999 if (C->failing()) return NULL; 1000 if (m == NULL) { Matcher::soft_match_failure(); return NULL; } 1001 } else { // Nothing the matcher cares about 1002 if (n->is_Proj() && n->in(0) != NULL && n->in(0)->is_Multi()) { // Projections? 1003 // Convert to machine-dependent projection 1004 m = n->in(0)->as_Multi()->match( n->as_Proj(), this ); 1005#ifdef ASSERT 1006 _new2old_map.map(m->_idx, n); 1007#endif 1008 if (m->in(0) != NULL) // m might be top 1009 collect_null_checks(m, n); 1010 } else { // Else just a regular 'ol guy 1011 m = n->clone(); // So just clone into new-space 1012#ifdef ASSERT 1013 _new2old_map.map(m->_idx, n); 1014#endif 1015 // Def-Use edges will be added incrementally as Uses 1016 // of this node are matched. 1017 assert(m->outcnt() == 0, "no Uses of this clone yet"); 1018 } 1019 } 1020 1021 set_new_node(n, m); // Map old to new 1022 if (_old_node_note_array != NULL) { 1023 Node_Notes* nn = C->locate_node_notes(_old_node_note_array, 1024 n->_idx); 1025 C->set_node_notes_at(m->_idx, nn); 1026 } 1027 debug_only(match_alias_type(C, n, m)); 1028 } 1029 n = m; // n is now a new-space node 1030 mstack.set_node(n); 1031 } 1032 1033 // New space! 1034 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty()) 1035 1036 int i; 1037 // Put precedence edges on stack first (match them last). 1038 for (i = oldn->req(); (uint)i < oldn->len(); i++) { 1039 Node *m = oldn->in(i); 1040 if (m == NULL) break; 1041 // set -1 to call add_prec() instead of set_req() during Step1 1042 mstack.push(m, Visit, n, -1); 1043 } 1044 1045 // Handle precedence edges for interior nodes 1046 for (i = n->len()-1; (uint)i >= n->req(); i--) { 1047 Node *m = n->in(i); 1048 if (m == NULL || C->node_arena()->contains(m)) continue; 1049 n->rm_prec(i); 1050 // set -1 to call add_prec() instead of set_req() during Step1 1051 mstack.push(m, Visit, n, -1); 1052 } 1053 1054 // For constant debug info, I'd rather have unmatched constants. 1055 int cnt = n->req(); 1056 JVMState* jvms = n->jvms(); 1057 int debug_cnt = jvms ? jvms->debug_start() : cnt; 1058 1059 // Now do only debug info. Clone constants rather than matching. 1060 // Constants are represented directly in the debug info without 1061 // the need for executable machine instructions. 1062 // Monitor boxes are also represented directly. 1063 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do 1064 Node *m = n->in(i); // Get input 1065 int op = m->Opcode(); 1066 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites"); 1067 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass || 1068 op == Op_ConF || op == Op_ConD || op == Op_ConL 1069 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp 1070 ) { 1071 m = m->clone(); 1072#ifdef ASSERT 1073 _new2old_map.map(m->_idx, n); 1074#endif 1075 mstack.push(m, Post_Visit, n, i); // Don't need to visit 1076 mstack.push(m->in(0), Visit, m, 0); 1077 } else { 1078 mstack.push(m, Visit, n, i); 1079 } 1080 } 1081 1082 // And now walk his children, and convert his inputs to new-space. 1083 for( ; i >= 0; --i ) { // For all normal inputs do 1084 Node *m = n->in(i); // Get input 1085 if(m != NULL) 1086 mstack.push(m, Visit, n, i); 1087 } 1088 1089 } 1090 else if (nstate == Post_Visit) { 1091 // Set xformed input 1092 Node *p = mstack.parent(); 1093 if (p != NULL) { // root doesn't have parent 1094 int i = (int)mstack.index(); 1095 if (i >= 0) 1096 p->set_req(i, n); // required input 1097 else if (i == -1) 1098 p->add_prec(n); // precedence input 1099 else 1100 ShouldNotReachHere(); 1101 } 1102 mstack.pop(); // remove processed node from stack 1103 } 1104 else { 1105 ShouldNotReachHere(); 1106 } 1107 } // while (mstack.is_nonempty()) 1108 return n; // Return new-space Node 1109} 1110 1111//------------------------------warp_outgoing_stk_arg------------------------ 1112OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) { 1113 // Convert outgoing argument location to a pre-biased stack offset 1114 if (reg->is_stack()) { 1115 OptoReg::Name warped = reg->reg2stack(); 1116 // Adjust the stack slot offset to be the register number used 1117 // by the allocator. 1118 warped = OptoReg::add(begin_out_arg_area, warped); 1119 // Keep track of the largest numbered stack slot used for an arg. 1120 // Largest used slot per call-site indicates the amount of stack 1121 // that is killed by the call. 1122 if( warped >= out_arg_limit_per_call ) 1123 out_arg_limit_per_call = OptoReg::add(warped,1); 1124 if (!RegMask::can_represent_arg(warped)) { 1125 C->record_method_not_compilable("unsupported calling sequence"); 1126 return OptoReg::Bad; 1127 } 1128 return warped; 1129 } 1130 return OptoReg::as_OptoReg(reg); 1131} 1132 1133 1134//------------------------------match_sfpt------------------------------------- 1135// Helper function to match call instructions. Calls match special. 1136// They match alone with no children. Their children, the incoming 1137// arguments, match normally. 1138MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) { 1139 MachSafePointNode *msfpt = NULL; 1140 MachCallNode *mcall = NULL; 1141 uint cnt; 1142 // Split out case for SafePoint vs Call 1143 CallNode *call; 1144 const TypeTuple *domain; 1145 ciMethod* method = NULL; 1146 bool is_method_handle_invoke = false; // for special kill effects 1147 if( sfpt->is_Call() ) { 1148 call = sfpt->as_Call(); 1149 domain = call->tf()->domain(); 1150 cnt = domain->cnt(); 1151 1152 // Match just the call, nothing else 1153 MachNode *m = match_tree(call); 1154 if (C->failing()) return NULL; 1155 if( m == NULL ) { Matcher::soft_match_failure(); return NULL; } 1156 1157 // Copy data from the Ideal SafePoint to the machine version 1158 mcall = m->as_MachCall(); 1159 1160 mcall->set_tf( call->tf()); 1161 mcall->set_entry_point(call->entry_point()); 1162 mcall->set_cnt( call->cnt()); 1163 1164 if( mcall->is_MachCallJava() ) { 1165 MachCallJavaNode *mcall_java = mcall->as_MachCallJava(); 1166 const CallJavaNode *call_java = call->as_CallJava(); 1167 method = call_java->method(); 1168 mcall_java->_method = method; 1169 mcall_java->_bci = call_java->_bci; 1170 mcall_java->_optimized_virtual = call_java->is_optimized_virtual(); 1171 is_method_handle_invoke = call_java->is_method_handle_invoke(); 1172 mcall_java->_method_handle_invoke = is_method_handle_invoke; 1173 mcall_java->_override_symbolic_info = call_java->override_symbolic_info(); 1174 if (is_method_handle_invoke) { 1175 C->set_has_method_handle_invokes(true); 1176 } 1177 if( mcall_java->is_MachCallStaticJava() ) 1178 mcall_java->as_MachCallStaticJava()->_name = 1179 call_java->as_CallStaticJava()->_name; 1180 if( mcall_java->is_MachCallDynamicJava() ) 1181 mcall_java->as_MachCallDynamicJava()->_vtable_index = 1182 call_java->as_CallDynamicJava()->_vtable_index; 1183 } 1184 else if( mcall->is_MachCallRuntime() ) { 1185 mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name; 1186 } 1187 msfpt = mcall; 1188 } 1189 // This is a non-call safepoint 1190 else { 1191 call = NULL; 1192 domain = NULL; 1193 MachNode *mn = match_tree(sfpt); 1194 if (C->failing()) return NULL; 1195 msfpt = mn->as_MachSafePoint(); 1196 cnt = TypeFunc::Parms; 1197 } 1198 1199 // Advertise the correct memory effects (for anti-dependence computation). 1200 msfpt->set_adr_type(sfpt->adr_type()); 1201 1202 // Allocate a private array of RegMasks. These RegMasks are not shared. 1203 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt ); 1204 // Empty them all. 1205 memset( msfpt->_in_rms, 0, sizeof(RegMask)*cnt ); 1206 1207 // Do all the pre-defined non-Empty register masks 1208 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask; 1209 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask; 1210 1211 // Place first outgoing argument can possibly be put. 1212 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 1213 assert( is_even(begin_out_arg_area), "" ); 1214 // Compute max outgoing register number per call site. 1215 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area; 1216 // Calls to C may hammer extra stack slots above and beyond any arguments. 1217 // These are usually backing store for register arguments for varargs. 1218 if( call != NULL && call->is_CallRuntime() ) 1219 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed()); 1220 1221 1222 // Do the normal argument list (parameters) register masks 1223 int argcnt = cnt - TypeFunc::Parms; 1224 if( argcnt > 0 ) { // Skip it all if we have no args 1225 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 1226 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 1227 int i; 1228 for( i = 0; i < argcnt; i++ ) { 1229 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 1230 } 1231 // V-call to pick proper calling convention 1232 call->calling_convention( sig_bt, parm_regs, argcnt ); 1233 1234#ifdef ASSERT 1235 // Sanity check users' calling convention. Really handy during 1236 // the initial porting effort. Fairly expensive otherwise. 1237 { for (int i = 0; i<argcnt; i++) { 1238 if( !parm_regs[i].first()->is_valid() && 1239 !parm_regs[i].second()->is_valid() ) continue; 1240 VMReg reg1 = parm_regs[i].first(); 1241 VMReg reg2 = parm_regs[i].second(); 1242 for (int j = 0; j < i; j++) { 1243 if( !parm_regs[j].first()->is_valid() && 1244 !parm_regs[j].second()->is_valid() ) continue; 1245 VMReg reg3 = parm_regs[j].first(); 1246 VMReg reg4 = parm_regs[j].second(); 1247 if( !reg1->is_valid() ) { 1248 assert( !reg2->is_valid(), "valid halvsies" ); 1249 } else if( !reg3->is_valid() ) { 1250 assert( !reg4->is_valid(), "valid halvsies" ); 1251 } else { 1252 assert( reg1 != reg2, "calling conv. must produce distinct regs"); 1253 assert( reg1 != reg3, "calling conv. must produce distinct regs"); 1254 assert( reg1 != reg4, "calling conv. must produce distinct regs"); 1255 assert( reg2 != reg3, "calling conv. must produce distinct regs"); 1256 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs"); 1257 assert( reg3 != reg4, "calling conv. must produce distinct regs"); 1258 } 1259 } 1260 } 1261 } 1262#endif 1263 1264 // Visit each argument. Compute its outgoing register mask. 1265 // Return results now can have 2 bits returned. 1266 // Compute max over all outgoing arguments both per call-site 1267 // and over the entire method. 1268 for( i = 0; i < argcnt; i++ ) { 1269 // Address of incoming argument mask to fill in 1270 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms]; 1271 if( !parm_regs[i].first()->is_valid() && 1272 !parm_regs[i].second()->is_valid() ) { 1273 continue; // Avoid Halves 1274 } 1275 // Grab first register, adjust stack slots and insert in mask. 1276 OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call ); 1277 if (OptoReg::is_valid(reg1)) 1278 rm->Insert( reg1 ); 1279 // Grab second register (if any), adjust stack slots and insert in mask. 1280 OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call ); 1281 if (OptoReg::is_valid(reg2)) 1282 rm->Insert( reg2 ); 1283 } // End of for all arguments 1284 1285 // Compute number of stack slots needed to restore stack in case of 1286 // Pascal-style argument popping. 1287 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area; 1288 } 1289 1290 // Compute the max stack slot killed by any call. These will not be 1291 // available for debug info, and will be used to adjust FIRST_STACK_mask 1292 // after all call sites have been visited. 1293 if( _out_arg_limit < out_arg_limit_per_call) 1294 _out_arg_limit = out_arg_limit_per_call; 1295 1296 if (mcall) { 1297 // Kill the outgoing argument area, including any non-argument holes and 1298 // any legacy C-killed slots. Use Fat-Projections to do the killing. 1299 // Since the max-per-method covers the max-per-call-site and debug info 1300 // is excluded on the max-per-method basis, debug info cannot land in 1301 // this killed area. 1302 uint r_cnt = mcall->tf()->range()->cnt(); 1303 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj ); 1304 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) { 1305 C->record_method_not_compilable("unsupported outgoing calling sequence"); 1306 } else { 1307 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++) 1308 proj->_rout.Insert(OptoReg::Name(i)); 1309 } 1310 if (proj->_rout.is_NotEmpty()) { 1311 push_projection(proj); 1312 } 1313 } 1314 // Transfer the safepoint information from the call to the mcall 1315 // Move the JVMState list 1316 msfpt->set_jvms(sfpt->jvms()); 1317 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) { 1318 jvms->set_map(sfpt); 1319 } 1320 1321 // Debug inputs begin just after the last incoming parameter 1322 assert((mcall == NULL) || (mcall->jvms() == NULL) || 1323 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), ""); 1324 1325 // Move the OopMap 1326 msfpt->_oop_map = sfpt->_oop_map; 1327 1328 // Add additional edges. 1329 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) { 1330 // For these calls we can not add MachConstantBase in expand(), as the 1331 // ins are not complete then. 1332 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node()); 1333 if (msfpt->jvms() && 1334 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) { 1335 // We added an edge before jvms, so we must adapt the position of the ins. 1336 msfpt->jvms()->adapt_position(+1); 1337 } 1338 } 1339 1340 // Registers killed by the call are set in the local scheduling pass 1341 // of Global Code Motion. 1342 return msfpt; 1343} 1344 1345//---------------------------match_tree---------------------------------------- 1346// Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part 1347// of the whole-sale conversion from Ideal to Mach Nodes. Also used for 1348// making GotoNodes while building the CFG and in init_spill_mask() to identify 1349// a Load's result RegMask for memoization in idealreg2regmask[] 1350MachNode *Matcher::match_tree( const Node *n ) { 1351 assert( n->Opcode() != Op_Phi, "cannot match" ); 1352 assert( !n->is_block_start(), "cannot match" ); 1353 // Set the mark for all locally allocated State objects. 1354 // When this call returns, the _states_arena arena will be reset 1355 // freeing all State objects. 1356 ResourceMark rm( &_states_arena ); 1357 1358 LabelRootDepth = 0; 1359 1360 // StoreNodes require their Memory input to match any LoadNodes 1361 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ; 1362#ifdef ASSERT 1363 Node* save_mem_node = _mem_node; 1364 _mem_node = n->is_Store() ? (Node*)n : NULL; 1365#endif 1366 // State object for root node of match tree 1367 // Allocate it on _states_arena - stack allocation can cause stack overflow. 1368 State *s = new (&_states_arena) State; 1369 s->_kids[0] = NULL; 1370 s->_kids[1] = NULL; 1371 s->_leaf = (Node*)n; 1372 // Label the input tree, allocating labels from top-level arena 1373 Label_Root( n, s, n->in(0), mem ); 1374 if (C->failing()) return NULL; 1375 1376 // The minimum cost match for the whole tree is found at the root State 1377 uint mincost = max_juint; 1378 uint cost = max_juint; 1379 uint i; 1380 for( i = 0; i < NUM_OPERANDS; i++ ) { 1381 if( s->valid(i) && // valid entry and 1382 s->_cost[i] < cost && // low cost and 1383 s->_rule[i] >= NUM_OPERANDS ) // not an operand 1384 cost = s->_cost[mincost=i]; 1385 } 1386 if (mincost == max_juint) { 1387#ifndef PRODUCT 1388 tty->print("No matching rule for:"); 1389 s->dump(); 1390#endif 1391 Matcher::soft_match_failure(); 1392 return NULL; 1393 } 1394 // Reduce input tree based upon the state labels to machine Nodes 1395 MachNode *m = ReduceInst( s, s->_rule[mincost], mem ); 1396#ifdef ASSERT 1397 _old2new_map.map(n->_idx, m); 1398 _new2old_map.map(m->_idx, (Node*)n); 1399#endif 1400 1401 // Add any Matcher-ignored edges 1402 uint cnt = n->req(); 1403 uint start = 1; 1404 if( mem != (Node*)1 ) start = MemNode::Memory+1; 1405 if( n->is_AddP() ) { 1406 assert( mem == (Node*)1, "" ); 1407 start = AddPNode::Base+1; 1408 } 1409 for( i = start; i < cnt; i++ ) { 1410 if( !n->match_edge(i) ) { 1411 if( i < m->req() ) 1412 m->ins_req( i, n->in(i) ); 1413 else 1414 m->add_req( n->in(i) ); 1415 } 1416 } 1417 1418 debug_only( _mem_node = save_mem_node; ) 1419 return m; 1420} 1421 1422 1423//------------------------------match_into_reg--------------------------------- 1424// Choose to either match this Node in a register or part of the current 1425// match tree. Return true for requiring a register and false for matching 1426// as part of the current match tree. 1427static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) { 1428 1429 const Type *t = m->bottom_type(); 1430 1431 if (t->singleton()) { 1432 // Never force constants into registers. Allow them to match as 1433 // constants or registers. Copies of the same value will share 1434 // the same register. See find_shared_node. 1435 return false; 1436 } else { // Not a constant 1437 // Stop recursion if they have different Controls. 1438 Node* m_control = m->in(0); 1439 // Control of load's memory can post-dominates load's control. 1440 // So use it since load can't float above its memory. 1441 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL; 1442 if (control && m_control && control != m_control && control != mem_control) { 1443 1444 // Actually, we can live with the most conservative control we 1445 // find, if it post-dominates the others. This allows us to 1446 // pick up load/op/store trees where the load can float a little 1447 // above the store. 1448 Node *x = control; 1449 const uint max_scan = 6; // Arbitrary scan cutoff 1450 uint j; 1451 for (j=0; j<max_scan; j++) { 1452 if (x->is_Region()) // Bail out at merge points 1453 return true; 1454 x = x->in(0); 1455 if (x == m_control) // Does 'control' post-dominate 1456 break; // m->in(0)? If so, we can use it 1457 if (x == mem_control) // Does 'control' post-dominate 1458 break; // mem_control? If so, we can use it 1459 } 1460 if (j == max_scan) // No post-domination before scan end? 1461 return true; // Then break the match tree up 1462 } 1463 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) || 1464 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) { 1465 // These are commonly used in address expressions and can 1466 // efficiently fold into them on X64 in some cases. 1467 return false; 1468 } 1469 } 1470 1471 // Not forceable cloning. If shared, put it into a register. 1472 return shared; 1473} 1474 1475 1476//------------------------------Instruction Selection-------------------------- 1477// Label method walks a "tree" of nodes, using the ADLC generated DFA to match 1478// ideal nodes to machine instructions. Trees are delimited by shared Nodes, 1479// things the Matcher does not match (e.g., Memory), and things with different 1480// Controls (hence forced into different blocks). We pass in the Control 1481// selected for this entire State tree. 1482 1483// The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the 1484// Store and the Load must have identical Memories (as well as identical 1485// pointers). Since the Matcher does not have anything for Memory (and 1486// does not handle DAGs), I have to match the Memory input myself. If the 1487// Tree root is a Store, I require all Loads to have the identical memory. 1488Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){ 1489 // Since Label_Root is a recursive function, its possible that we might run 1490 // out of stack space. See bugs 6272980 & 6227033 for more info. 1491 LabelRootDepth++; 1492 if (LabelRootDepth > MaxLabelRootDepth) { 1493 C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth"); 1494 return NULL; 1495 } 1496 uint care = 0; // Edges matcher cares about 1497 uint cnt = n->req(); 1498 uint i = 0; 1499 1500 // Examine children for memory state 1501 // Can only subsume a child into your match-tree if that child's memory state 1502 // is not modified along the path to another input. 1503 // It is unsafe even if the other inputs are separate roots. 1504 Node *input_mem = NULL; 1505 for( i = 1; i < cnt; i++ ) { 1506 if( !n->match_edge(i) ) continue; 1507 Node *m = n->in(i); // Get ith input 1508 assert( m, "expect non-null children" ); 1509 if( m->is_Load() ) { 1510 if( input_mem == NULL ) { 1511 input_mem = m->in(MemNode::Memory); 1512 } else if( input_mem != m->in(MemNode::Memory) ) { 1513 input_mem = NodeSentinel; 1514 } 1515 } 1516 } 1517 1518 for( i = 1; i < cnt; i++ ){// For my children 1519 if( !n->match_edge(i) ) continue; 1520 Node *m = n->in(i); // Get ith input 1521 // Allocate states out of a private arena 1522 State *s = new (&_states_arena) State; 1523 svec->_kids[care++] = s; 1524 assert( care <= 2, "binary only for now" ); 1525 1526 // Recursively label the State tree. 1527 s->_kids[0] = NULL; 1528 s->_kids[1] = NULL; 1529 s->_leaf = m; 1530 1531 // Check for leaves of the State Tree; things that cannot be a part of 1532 // the current tree. If it finds any, that value is matched as a 1533 // register operand. If not, then the normal matching is used. 1534 if( match_into_reg(n, m, control, i, is_shared(m)) || 1535 // 1536 // Stop recursion if this is LoadNode and the root of this tree is a 1537 // StoreNode and the load & store have different memories. 1538 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) || 1539 // Can NOT include the match of a subtree when its memory state 1540 // is used by any of the other subtrees 1541 (input_mem == NodeSentinel) ) { 1542 // Print when we exclude matching due to different memory states at input-loads 1543 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel) 1544 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) { 1545 tty->print_cr("invalid input_mem"); 1546 } 1547 // Switch to a register-only opcode; this value must be in a register 1548 // and cannot be subsumed as part of a larger instruction. 1549 s->DFA( m->ideal_reg(), m ); 1550 1551 } else { 1552 // If match tree has no control and we do, adopt it for entire tree 1553 if( control == NULL && m->in(0) != NULL && m->req() > 1 ) 1554 control = m->in(0); // Pick up control 1555 // Else match as a normal part of the match tree. 1556 control = Label_Root(m,s,control,mem); 1557 if (C->failing()) return NULL; 1558 } 1559 } 1560 1561 1562 // Call DFA to match this node, and return 1563 svec->DFA( n->Opcode(), n ); 1564 1565#ifdef ASSERT 1566 uint x; 1567 for( x = 0; x < _LAST_MACH_OPER; x++ ) 1568 if( svec->valid(x) ) 1569 break; 1570 1571 if (x >= _LAST_MACH_OPER) { 1572 n->dump(); 1573 svec->dump(); 1574 assert( false, "bad AD file" ); 1575 } 1576#endif 1577 return control; 1578} 1579 1580 1581// Con nodes reduced using the same rule can share their MachNode 1582// which reduces the number of copies of a constant in the final 1583// program. The register allocator is free to split uses later to 1584// split live ranges. 1585MachNode* Matcher::find_shared_node(Node* leaf, uint rule) { 1586 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL; 1587 1588 // See if this Con has already been reduced using this rule. 1589 if (_shared_nodes.Size() <= leaf->_idx) return NULL; 1590 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx); 1591 if (last != NULL && rule == last->rule()) { 1592 // Don't expect control change for DecodeN 1593 if (leaf->is_DecodeNarrowPtr()) 1594 return last; 1595 // Get the new space root. 1596 Node* xroot = new_node(C->root()); 1597 if (xroot == NULL) { 1598 // This shouldn't happen give the order of matching. 1599 return NULL; 1600 } 1601 1602 // Shared constants need to have their control be root so they 1603 // can be scheduled properly. 1604 Node* control = last->in(0); 1605 if (control != xroot) { 1606 if (control == NULL || control == C->root()) { 1607 last->set_req(0, xroot); 1608 } else { 1609 assert(false, "unexpected control"); 1610 return NULL; 1611 } 1612 } 1613 return last; 1614 } 1615 return NULL; 1616} 1617 1618 1619//------------------------------ReduceInst------------------------------------- 1620// Reduce a State tree (with given Control) into a tree of MachNodes. 1621// This routine (and it's cohort ReduceOper) convert Ideal Nodes into 1622// complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes. 1623// Each MachNode has a number of complicated MachOper operands; each 1624// MachOper also covers a further tree of Ideal Nodes. 1625 1626// The root of the Ideal match tree is always an instruction, so we enter 1627// the recursion here. After building the MachNode, we need to recurse 1628// the tree checking for these cases: 1629// (1) Child is an instruction - 1630// Build the instruction (recursively), add it as an edge. 1631// Build a simple operand (register) to hold the result of the instruction. 1632// (2) Child is an interior part of an instruction - 1633// Skip over it (do nothing) 1634// (3) Child is the start of a operand - 1635// Build the operand, place it inside the instruction 1636// Call ReduceOper. 1637MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) { 1638 assert( rule >= NUM_OPERANDS, "called with operand rule" ); 1639 1640 MachNode* shared_node = find_shared_node(s->_leaf, rule); 1641 if (shared_node != NULL) { 1642 return shared_node; 1643 } 1644 1645 // Build the object to represent this state & prepare for recursive calls 1646 MachNode *mach = s->MachNodeGenerator(rule); 1647 guarantee(mach != NULL, "Missing MachNode"); 1648 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]); 1649 assert( mach->_opnds[0] != NULL, "Missing result operand" ); 1650 Node *leaf = s->_leaf; 1651 // Check for instruction or instruction chain rule 1652 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) { 1653 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf), 1654 "duplicating node that's already been matched"); 1655 // Instruction 1656 mach->add_req( leaf->in(0) ); // Set initial control 1657 // Reduce interior of complex instruction 1658 ReduceInst_Interior( s, rule, mem, mach, 1 ); 1659 } else { 1660 // Instruction chain rules are data-dependent on their inputs 1661 mach->add_req(0); // Set initial control to none 1662 ReduceInst_Chain_Rule( s, rule, mem, mach ); 1663 } 1664 1665 // If a Memory was used, insert a Memory edge 1666 if( mem != (Node*)1 ) { 1667 mach->ins_req(MemNode::Memory,mem); 1668#ifdef ASSERT 1669 // Verify adr type after matching memory operation 1670 const MachOper* oper = mach->memory_operand(); 1671 if (oper != NULL && oper != (MachOper*)-1) { 1672 // It has a unique memory operand. Find corresponding ideal mem node. 1673 Node* m = NULL; 1674 if (leaf->is_Mem()) { 1675 m = leaf; 1676 } else { 1677 m = _mem_node; 1678 assert(m != NULL && m->is_Mem(), "expecting memory node"); 1679 } 1680 const Type* mach_at = mach->adr_type(); 1681 // DecodeN node consumed by an address may have different type 1682 // then its input. Don't compare types for such case. 1683 if (m->adr_type() != mach_at && 1684 (m->in(MemNode::Address)->is_DecodeNarrowPtr() || 1685 m->in(MemNode::Address)->is_AddP() && 1686 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr() || 1687 m->in(MemNode::Address)->is_AddP() && 1688 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() && 1689 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr())) { 1690 mach_at = m->adr_type(); 1691 } 1692 if (m->adr_type() != mach_at) { 1693 m->dump(); 1694 tty->print_cr("mach:"); 1695 mach->dump(1); 1696 } 1697 assert(m->adr_type() == mach_at, "matcher should not change adr type"); 1698 } 1699#endif 1700 } 1701 1702 // If the _leaf is an AddP, insert the base edge 1703 if (leaf->is_AddP()) { 1704 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base)); 1705 } 1706 1707 uint number_of_projections_prior = number_of_projections(); 1708 1709 // Perform any 1-to-many expansions required 1710 MachNode *ex = mach->Expand(s, _projection_list, mem); 1711 if (ex != mach) { 1712 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match"); 1713 if( ex->in(1)->is_Con() ) 1714 ex->in(1)->set_req(0, C->root()); 1715 // Remove old node from the graph 1716 for( uint i=0; i<mach->req(); i++ ) { 1717 mach->set_req(i,NULL); 1718 } 1719#ifdef ASSERT 1720 _new2old_map.map(ex->_idx, s->_leaf); 1721#endif 1722 } 1723 1724 // PhaseChaitin::fixup_spills will sometimes generate spill code 1725 // via the matcher. By the time, nodes have been wired into the CFG, 1726 // and any further nodes generated by expand rules will be left hanging 1727 // in space, and will not get emitted as output code. Catch this. 1728 // Also, catch any new register allocation constraints ("projections") 1729 // generated belatedly during spill code generation. 1730 if (_allocation_started) { 1731 guarantee(ex == mach, "no expand rules during spill generation"); 1732 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation"); 1733 } 1734 1735 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) { 1736 // Record the con for sharing 1737 _shared_nodes.map(leaf->_idx, ex); 1738 } 1739 1740 return ex; 1741} 1742 1743void Matcher::handle_precedence_edges(Node* n, MachNode *mach) { 1744 for (uint i = n->req(); i < n->len(); i++) { 1745 if (n->in(i) != NULL) { 1746 mach->add_prec(n->in(i)); 1747 } 1748 } 1749} 1750 1751void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) { 1752 // 'op' is what I am expecting to receive 1753 int op = _leftOp[rule]; 1754 // Operand type to catch childs result 1755 // This is what my child will give me. 1756 int opnd_class_instance = s->_rule[op]; 1757 // Choose between operand class or not. 1758 // This is what I will receive. 1759 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op; 1760 // New rule for child. Chase operand classes to get the actual rule. 1761 int newrule = s->_rule[catch_op]; 1762 1763 if( newrule < NUM_OPERANDS ) { 1764 // Chain from operand or operand class, may be output of shared node 1765 assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS, 1766 "Bad AD file: Instruction chain rule must chain from operand"); 1767 // Insert operand into array of operands for this instruction 1768 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance); 1769 1770 ReduceOper( s, newrule, mem, mach ); 1771 } else { 1772 // Chain from the result of an instruction 1773 assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand"); 1774 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]); 1775 Node *mem1 = (Node*)1; 1776 debug_only(Node *save_mem_node = _mem_node;) 1777 mach->add_req( ReduceInst(s, newrule, mem1) ); 1778 debug_only(_mem_node = save_mem_node;) 1779 } 1780 return; 1781} 1782 1783 1784uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) { 1785 handle_precedence_edges(s->_leaf, mach); 1786 1787 if( s->_leaf->is_Load() ) { 1788 Node *mem2 = s->_leaf->in(MemNode::Memory); 1789 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" ); 1790 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;) 1791 mem = mem2; 1792 } 1793 if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) { 1794 if( mach->in(0) == NULL ) 1795 mach->set_req(0, s->_leaf->in(0)); 1796 } 1797 1798 // Now recursively walk the state tree & add operand list. 1799 for( uint i=0; i<2; i++ ) { // binary tree 1800 State *newstate = s->_kids[i]; 1801 if( newstate == NULL ) break; // Might only have 1 child 1802 // 'op' is what I am expecting to receive 1803 int op; 1804 if( i == 0 ) { 1805 op = _leftOp[rule]; 1806 } else { 1807 op = _rightOp[rule]; 1808 } 1809 // Operand type to catch childs result 1810 // This is what my child will give me. 1811 int opnd_class_instance = newstate->_rule[op]; 1812 // Choose between operand class or not. 1813 // This is what I will receive. 1814 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op; 1815 // New rule for child. Chase operand classes to get the actual rule. 1816 int newrule = newstate->_rule[catch_op]; 1817 1818 if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction? 1819 // Operand/operandClass 1820 // Insert operand into array of operands for this instruction 1821 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance); 1822 ReduceOper( newstate, newrule, mem, mach ); 1823 1824 } else { // Child is internal operand or new instruction 1825 if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction? 1826 // internal operand --> call ReduceInst_Interior 1827 // Interior of complex instruction. Do nothing but recurse. 1828 num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds ); 1829 } else { 1830 // instruction --> call build operand( ) to catch result 1831 // --> ReduceInst( newrule ) 1832 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]); 1833 Node *mem1 = (Node*)1; 1834 debug_only(Node *save_mem_node = _mem_node;) 1835 mach->add_req( ReduceInst( newstate, newrule, mem1 ) ); 1836 debug_only(_mem_node = save_mem_node;) 1837 } 1838 } 1839 assert( mach->_opnds[num_opnds-1], "" ); 1840 } 1841 return num_opnds; 1842} 1843 1844// This routine walks the interior of possible complex operands. 1845// At each point we check our children in the match tree: 1846// (1) No children - 1847// We are a leaf; add _leaf field as an input to the MachNode 1848// (2) Child is an internal operand - 1849// Skip over it ( do nothing ) 1850// (3) Child is an instruction - 1851// Call ReduceInst recursively and 1852// and instruction as an input to the MachNode 1853void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) { 1854 assert( rule < _LAST_MACH_OPER, "called with operand rule" ); 1855 State *kid = s->_kids[0]; 1856 assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" ); 1857 1858 // Leaf? And not subsumed? 1859 if( kid == NULL && !_swallowed[rule] ) { 1860 mach->add_req( s->_leaf ); // Add leaf pointer 1861 return; // Bail out 1862 } 1863 1864 if( s->_leaf->is_Load() ) { 1865 assert( mem == (Node*)1, "multiple Memories being matched at once?" ); 1866 mem = s->_leaf->in(MemNode::Memory); 1867 debug_only(_mem_node = s->_leaf;) 1868 } 1869 1870 handle_precedence_edges(s->_leaf, mach); 1871 1872 if( s->_leaf->in(0) && s->_leaf->req() > 1) { 1873 if( !mach->in(0) ) 1874 mach->set_req(0,s->_leaf->in(0)); 1875 else { 1876 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" ); 1877 } 1878 } 1879 1880 for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) { // binary tree 1881 int newrule; 1882 if( i == 0) 1883 newrule = kid->_rule[_leftOp[rule]]; 1884 else 1885 newrule = kid->_rule[_rightOp[rule]]; 1886 1887 if( newrule < _LAST_MACH_OPER ) { // Operand or instruction? 1888 // Internal operand; recurse but do nothing else 1889 ReduceOper( kid, newrule, mem, mach ); 1890 1891 } else { // Child is a new instruction 1892 // Reduce the instruction, and add a direct pointer from this 1893 // machine instruction to the newly reduced one. 1894 Node *mem1 = (Node*)1; 1895 debug_only(Node *save_mem_node = _mem_node;) 1896 mach->add_req( ReduceInst( kid, newrule, mem1 ) ); 1897 debug_only(_mem_node = save_mem_node;) 1898 } 1899 } 1900} 1901 1902 1903// ------------------------------------------------------------------------- 1904// Java-Java calling convention 1905// (what you use when Java calls Java) 1906 1907//------------------------------find_receiver---------------------------------- 1908// For a given signature, return the OptoReg for parameter 0. 1909OptoReg::Name Matcher::find_receiver( bool is_outgoing ) { 1910 VMRegPair regs; 1911 BasicType sig_bt = T_OBJECT; 1912 calling_convention(&sig_bt, ®s, 1, is_outgoing); 1913 // Return argument 0 register. In the LP64 build pointers 1914 // take 2 registers, but the VM wants only the 'main' name. 1915 return OptoReg::as_OptoReg(regs.first()); 1916} 1917 1918// This function identifies sub-graphs in which a 'load' node is 1919// input to two different nodes, and such that it can be matched 1920// with BMI instructions like blsi, blsr, etc. 1921// Example : for b = -a[i] & a[i] can be matched to blsi r32, m32. 1922// The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL* 1923// refers to the same node. 1924#ifdef X86 1925// Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop) 1926// This is a temporary solution until we make DAGs expressible in ADL. 1927template<typename ConType> 1928class FusedPatternMatcher { 1929 Node* _op1_node; 1930 Node* _mop_node; 1931 int _con_op; 1932 1933 static int match_next(Node* n, int next_op, int next_op_idx) { 1934 if (n->in(1) == NULL || n->in(2) == NULL) { 1935 return -1; 1936 } 1937 1938 if (next_op_idx == -1) { // n is commutative, try rotations 1939 if (n->in(1)->Opcode() == next_op) { 1940 return 1; 1941 } else if (n->in(2)->Opcode() == next_op) { 1942 return 2; 1943 } 1944 } else { 1945 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index"); 1946 if (n->in(next_op_idx)->Opcode() == next_op) { 1947 return next_op_idx; 1948 } 1949 } 1950 return -1; 1951 } 1952public: 1953 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) : 1954 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { } 1955 1956 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative 1957 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative 1958 typename ConType::NativeType con_value) { 1959 if (_op1_node->Opcode() != op1) { 1960 return false; 1961 } 1962 if (_mop_node->outcnt() > 2) { 1963 return false; 1964 } 1965 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx); 1966 if (op1_op2_idx == -1) { 1967 return false; 1968 } 1969 // Memory operation must be the other edge 1970 int op1_mop_idx = (op1_op2_idx & 1) + 1; 1971 1972 // Check that the mop node is really what we want 1973 if (_op1_node->in(op1_mop_idx) == _mop_node) { 1974 Node *op2_node = _op1_node->in(op1_op2_idx); 1975 if (op2_node->outcnt() > 1) { 1976 return false; 1977 } 1978 assert(op2_node->Opcode() == op2, "Should be"); 1979 op2_con_idx = match_next(op2_node, _con_op, op2_con_idx); 1980 if (op2_con_idx == -1) { 1981 return false; 1982 } 1983 // Memory operation must be the other edge 1984 int op2_mop_idx = (op2_con_idx & 1) + 1; 1985 // Check that the memory operation is the same node 1986 if (op2_node->in(op2_mop_idx) == _mop_node) { 1987 // Now check the constant 1988 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type(); 1989 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) { 1990 return true; 1991 } 1992 } 1993 } 1994 return false; 1995 } 1996}; 1997 1998 1999bool Matcher::is_bmi_pattern(Node *n, Node *m) { 2000 if (n != NULL && m != NULL) { 2001 if (m->Opcode() == Op_LoadI) { 2002 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI); 2003 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) || 2004 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) || 2005 bmii.match(Op_XorI, -1, Op_AddI, -1, -1); 2006 } else if (m->Opcode() == Op_LoadL) { 2007 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL); 2008 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) || 2009 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) || 2010 bmil.match(Op_XorL, -1, Op_AddL, -1, -1); 2011 } 2012 } 2013 return false; 2014} 2015#endif // X86 2016 2017bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 2018 Node *off = m->in(AddPNode::Offset); 2019 if (off->is_Con()) { 2020 address_visited.test_set(m->_idx); // Flag as address_visited 2021 mstack.push(m->in(AddPNode::Address), Pre_Visit); 2022 // Clone X+offset as it also folds into most addressing expressions 2023 mstack.push(off, Visit); 2024 mstack.push(m->in(AddPNode::Base), Pre_Visit); 2025 return true; 2026 } 2027 return false; 2028} 2029 2030// A method-klass-holder may be passed in the inline_cache_reg 2031// and then expanded into the inline_cache_reg and a method_oop register 2032// defined in ad_<arch>.cpp 2033 2034//------------------------------find_shared------------------------------------ 2035// Set bits if Node is shared or otherwise a root 2036void Matcher::find_shared( Node *n ) { 2037 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc 2038 MStack mstack(C->live_nodes() * 2); 2039 // Mark nodes as address_visited if they are inputs to an address expression 2040 VectorSet address_visited(Thread::current()->resource_area()); 2041 mstack.push(n, Visit); // Don't need to pre-visit root node 2042 while (mstack.is_nonempty()) { 2043 n = mstack.node(); // Leave node on stack 2044 Node_State nstate = mstack.state(); 2045 uint nop = n->Opcode(); 2046 if (nstate == Pre_Visit) { 2047 if (address_visited.test(n->_idx)) { // Visited in address already? 2048 // Flag as visited and shared now. 2049 set_visited(n); 2050 } 2051 if (is_visited(n)) { // Visited already? 2052 // Node is shared and has no reason to clone. Flag it as shared. 2053 // This causes it to match into a register for the sharing. 2054 set_shared(n); // Flag as shared and 2055 mstack.pop(); // remove node from stack 2056 continue; 2057 } 2058 nstate = Visit; // Not already visited; so visit now 2059 } 2060 if (nstate == Visit) { 2061 mstack.set_state(Post_Visit); 2062 set_visited(n); // Flag as visited now 2063 bool mem_op = false; 2064 2065 switch( nop ) { // Handle some opcodes special 2066 case Op_Phi: // Treat Phis as shared roots 2067 case Op_Parm: 2068 case Op_Proj: // All handled specially during matching 2069 case Op_SafePointScalarObject: 2070 set_shared(n); 2071 set_dontcare(n); 2072 break; 2073 case Op_If: 2074 case Op_CountedLoopEnd: 2075 mstack.set_state(Alt_Post_Visit); // Alternative way 2076 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps 2077 // with matching cmp/branch in 1 instruction. The Matcher needs the 2078 // Bool and CmpX side-by-side, because it can only get at constants 2079 // that are at the leaves of Match trees, and the Bool's condition acts 2080 // as a constant here. 2081 mstack.push(n->in(1), Visit); // Clone the Bool 2082 mstack.push(n->in(0), Pre_Visit); // Visit control input 2083 continue; // while (mstack.is_nonempty()) 2084 case Op_ConvI2D: // These forms efficiently match with a prior 2085 case Op_ConvI2F: // Load but not a following Store 2086 if( n->in(1)->is_Load() && // Prior load 2087 n->outcnt() == 1 && // Not already shared 2088 n->unique_out()->is_Store() ) // Following store 2089 set_shared(n); // Force it to be a root 2090 break; 2091 case Op_ReverseBytesI: 2092 case Op_ReverseBytesL: 2093 if( n->in(1)->is_Load() && // Prior load 2094 n->outcnt() == 1 ) // Not already shared 2095 set_shared(n); // Force it to be a root 2096 break; 2097 case Op_BoxLock: // Cant match until we get stack-regs in ADLC 2098 case Op_IfFalse: 2099 case Op_IfTrue: 2100 case Op_MachProj: 2101 case Op_MergeMem: 2102 case Op_Catch: 2103 case Op_CatchProj: 2104 case Op_CProj: 2105 case Op_JumpProj: 2106 case Op_JProj: 2107 case Op_NeverBranch: 2108 set_dontcare(n); 2109 break; 2110 case Op_Jump: 2111 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared) 2112 mstack.push(n->in(0), Pre_Visit); // Visit Control input 2113 continue; // while (mstack.is_nonempty()) 2114 case Op_StrComp: 2115 case Op_StrEquals: 2116 case Op_StrIndexOf: 2117 case Op_StrIndexOfChar: 2118 case Op_AryEq: 2119 case Op_HasNegatives: 2120 case Op_StrInflatedCopy: 2121 case Op_StrCompressedCopy: 2122 case Op_EncodeISOArray: 2123 case Op_FmaD: 2124 case Op_FmaF: 2125 case Op_FmaVD: 2126 case Op_FmaVF: 2127 set_shared(n); // Force result into register (it will be anyways) 2128 break; 2129 case Op_ConP: { // Convert pointers above the centerline to NUL 2130 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 2131 const TypePtr* tp = tn->type()->is_ptr(); 2132 if (tp->_ptr == TypePtr::AnyNull) { 2133 tn->set_type(TypePtr::NULL_PTR); 2134 } 2135 break; 2136 } 2137 case Op_ConN: { // Convert narrow pointers above the centerline to NUL 2138 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 2139 const TypePtr* tp = tn->type()->make_ptr(); 2140 if (tp && tp->_ptr == TypePtr::AnyNull) { 2141 tn->set_type(TypeNarrowOop::NULL_PTR); 2142 } 2143 break; 2144 } 2145 case Op_Binary: // These are introduced in the Post_Visit state. 2146 ShouldNotReachHere(); 2147 break; 2148 case Op_ClearArray: 2149 case Op_SafePoint: 2150 mem_op = true; 2151 break; 2152 default: 2153 if( n->is_Store() ) { 2154 // Do match stores, despite no ideal reg 2155 mem_op = true; 2156 break; 2157 } 2158 if( n->is_Mem() ) { // Loads and LoadStores 2159 mem_op = true; 2160 // Loads must be root of match tree due to prior load conflict 2161 if( C->subsume_loads() == false ) 2162 set_shared(n); 2163 } 2164 // Fall into default case 2165 if( !n->ideal_reg() ) 2166 set_dontcare(n); // Unmatchable Nodes 2167 } // end_switch 2168 2169 for(int i = n->req() - 1; i >= 0; --i) { // For my children 2170 Node *m = n->in(i); // Get ith input 2171 if (m == NULL) continue; // Ignore NULLs 2172 uint mop = m->Opcode(); 2173 2174 // Must clone all producers of flags, or we will not match correctly. 2175 // Suppose a compare setting int-flags is shared (e.g., a switch-tree) 2176 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags 2177 // are also there, so we may match a float-branch to int-flags and 2178 // expect the allocator to haul the flags from the int-side to the 2179 // fp-side. No can do. 2180 if( _must_clone[mop] ) { 2181 mstack.push(m, Visit); 2182 continue; // for(int i = ...) 2183 } 2184 2185 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) { 2186 // Bases used in addresses must be shared but since 2187 // they are shared through a DecodeN they may appear 2188 // to have a single use so force sharing here. 2189 set_shared(m->in(AddPNode::Base)->in(1)); 2190 } 2191 2192 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node. 2193#ifdef X86 2194 if (UseBMI1Instructions && is_bmi_pattern(n, m)) { 2195 mstack.push(m, Visit); 2196 continue; 2197 } 2198#endif 2199 2200 // Clone addressing expressions as they are "free" in memory access instructions 2201 if (mem_op && i == MemNode::Address && mop == Op_AddP && 2202 // When there are other uses besides address expressions 2203 // put it on stack and mark as shared. 2204 !is_visited(m)) { 2205 // Some inputs for address expression are not put on stack 2206 // to avoid marking them as shared and forcing them into register 2207 // if they are used only in address expressions. 2208 // But they should be marked as shared if there are other uses 2209 // besides address expressions. 2210 2211 if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) { 2212 continue; 2213 } 2214 } // if( mem_op && 2215 mstack.push(m, Pre_Visit); 2216 } // for(int i = ...) 2217 } 2218 else if (nstate == Alt_Post_Visit) { 2219 mstack.pop(); // Remove node from stack 2220 // We cannot remove the Cmp input from the Bool here, as the Bool may be 2221 // shared and all users of the Bool need to move the Cmp in parallel. 2222 // This leaves both the Bool and the If pointing at the Cmp. To 2223 // prevent the Matcher from trying to Match the Cmp along both paths 2224 // BoolNode::match_edge always returns a zero. 2225 2226 // We reorder the Op_If in a pre-order manner, so we can visit without 2227 // accidentally sharing the Cmp (the Bool and the If make 2 users). 2228 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool 2229 } 2230 else if (nstate == Post_Visit) { 2231 mstack.pop(); // Remove node from stack 2232 2233 // Now hack a few special opcodes 2234 switch( n->Opcode() ) { // Handle some opcodes special 2235 case Op_StorePConditional: 2236 case Op_StoreIConditional: 2237 case Op_StoreLConditional: 2238 case Op_CompareAndExchangeB: 2239 case Op_CompareAndExchangeS: 2240 case Op_CompareAndExchangeI: 2241 case Op_CompareAndExchangeL: 2242 case Op_CompareAndExchangeP: 2243 case Op_CompareAndExchangeN: 2244 case Op_WeakCompareAndSwapB: 2245 case Op_WeakCompareAndSwapS: 2246 case Op_WeakCompareAndSwapI: 2247 case Op_WeakCompareAndSwapL: 2248 case Op_WeakCompareAndSwapP: 2249 case Op_WeakCompareAndSwapN: 2250 case Op_CompareAndSwapB: 2251 case Op_CompareAndSwapS: 2252 case Op_CompareAndSwapI: 2253 case Op_CompareAndSwapL: 2254 case Op_CompareAndSwapP: 2255 case Op_CompareAndSwapN: { // Convert trinary to binary-tree 2256 Node *newval = n->in(MemNode::ValueIn ); 2257 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn); 2258 Node *pair = new BinaryNode( oldval, newval ); 2259 n->set_req(MemNode::ValueIn,pair); 2260 n->del_req(LoadStoreConditionalNode::ExpectedIn); 2261 break; 2262 } 2263 case Op_CMoveD: // Convert trinary to binary-tree 2264 case Op_CMoveF: 2265 case Op_CMoveI: 2266 case Op_CMoveL: 2267 case Op_CMoveN: 2268 case Op_CMoveP: 2269 case Op_CMoveVD: { 2270 // Restructure into a binary tree for Matching. It's possible that 2271 // we could move this code up next to the graph reshaping for IfNodes 2272 // or vice-versa, but I do not want to debug this for Ladybird. 2273 // 10/2/2000 CNC. 2274 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1)); 2275 n->set_req(1,pair1); 2276 Node *pair2 = new BinaryNode(n->in(2),n->in(3)); 2277 n->set_req(2,pair2); 2278 n->del_req(3); 2279 break; 2280 } 2281 case Op_LoopLimit: { 2282 Node *pair1 = new BinaryNode(n->in(1),n->in(2)); 2283 n->set_req(1,pair1); 2284 n->set_req(2,n->in(3)); 2285 n->del_req(3); 2286 break; 2287 } 2288 case Op_StrEquals: 2289 case Op_StrIndexOfChar: { 2290 Node *pair1 = new BinaryNode(n->in(2),n->in(3)); 2291 n->set_req(2,pair1); 2292 n->set_req(3,n->in(4)); 2293 n->del_req(4); 2294 break; 2295 } 2296 case Op_StrComp: 2297 case Op_StrIndexOf: { 2298 Node *pair1 = new BinaryNode(n->in(2),n->in(3)); 2299 n->set_req(2,pair1); 2300 Node *pair2 = new BinaryNode(n->in(4),n->in(5)); 2301 n->set_req(3,pair2); 2302 n->del_req(5); 2303 n->del_req(4); 2304 break; 2305 } 2306 case Op_StrCompressedCopy: 2307 case Op_StrInflatedCopy: 2308 case Op_EncodeISOArray: { 2309 // Restructure into a binary tree for Matching. 2310 Node* pair = new BinaryNode(n->in(3), n->in(4)); 2311 n->set_req(3, pair); 2312 n->del_req(4); 2313 break; 2314 } 2315 case Op_FmaD: 2316 case Op_FmaF: 2317 case Op_FmaVD: 2318 case Op_FmaVF: { 2319 // Restructure into a binary tree for Matching. 2320 Node* pair = new BinaryNode(n->in(1), n->in(2)); 2321 n->set_req(2, pair); 2322 n->set_req(1, n->in(3)); 2323 n->del_req(3); 2324 break; 2325 } 2326 default: 2327 break; 2328 } 2329 } 2330 else { 2331 ShouldNotReachHere(); 2332 } 2333 } // end of while (mstack.is_nonempty()) 2334} 2335 2336#ifdef ASSERT 2337// machine-independent root to machine-dependent root 2338void Matcher::dump_old2new_map() { 2339 _old2new_map.dump(); 2340} 2341#endif 2342 2343//---------------------------collect_null_checks------------------------------- 2344// Find null checks in the ideal graph; write a machine-specific node for 2345// it. Used by later implicit-null-check handling. Actually collects 2346// either an IfTrue or IfFalse for the common NOT-null path, AND the ideal 2347// value being tested. 2348void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) { 2349 Node *iff = proj->in(0); 2350 if( iff->Opcode() == Op_If ) { 2351 // During matching If's have Bool & Cmp side-by-side 2352 BoolNode *b = iff->in(1)->as_Bool(); 2353 Node *cmp = iff->in(2); 2354 int opc = cmp->Opcode(); 2355 if (opc != Op_CmpP && opc != Op_CmpN) return; 2356 2357 const Type* ct = cmp->in(2)->bottom_type(); 2358 if (ct == TypePtr::NULL_PTR || 2359 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) { 2360 2361 bool push_it = false; 2362 if( proj->Opcode() == Op_IfTrue ) { 2363#ifndef PRODUCT 2364 extern int all_null_checks_found; 2365 all_null_checks_found++; 2366#endif 2367 if( b->_test._test == BoolTest::ne ) { 2368 push_it = true; 2369 } 2370 } else { 2371 assert( proj->Opcode() == Op_IfFalse, "" ); 2372 if( b->_test._test == BoolTest::eq ) { 2373 push_it = true; 2374 } 2375 } 2376 if( push_it ) { 2377 _null_check_tests.push(proj); 2378 Node* val = cmp->in(1); 2379#ifdef _LP64 2380 if (val->bottom_type()->isa_narrowoop() && 2381 !Matcher::narrow_oop_use_complex_address()) { 2382 // 2383 // Look for DecodeN node which should be pinned to orig_proj. 2384 // On platforms (Sparc) which can not handle 2 adds 2385 // in addressing mode we have to keep a DecodeN node and 2386 // use it to do implicit NULL check in address. 2387 // 2388 // DecodeN node was pinned to non-null path (orig_proj) during 2389 // CastPP transformation in final_graph_reshaping_impl(). 2390 // 2391 uint cnt = orig_proj->outcnt(); 2392 for (uint i = 0; i < orig_proj->outcnt(); i++) { 2393 Node* d = orig_proj->raw_out(i); 2394 if (d->is_DecodeN() && d->in(1) == val) { 2395 val = d; 2396 val->set_req(0, NULL); // Unpin now. 2397 // Mark this as special case to distinguish from 2398 // a regular case: CmpP(DecodeN, NULL). 2399 val = (Node*)(((intptr_t)val) | 1); 2400 break; 2401 } 2402 } 2403 } 2404#endif 2405 _null_check_tests.push(val); 2406 } 2407 } 2408 } 2409} 2410 2411//---------------------------validate_null_checks------------------------------ 2412// Its possible that the value being NULL checked is not the root of a match 2413// tree. If so, I cannot use the value in an implicit null check. 2414void Matcher::validate_null_checks( ) { 2415 uint cnt = _null_check_tests.size(); 2416 for( uint i=0; i < cnt; i+=2 ) { 2417 Node *test = _null_check_tests[i]; 2418 Node *val = _null_check_tests[i+1]; 2419 bool is_decoden = ((intptr_t)val) & 1; 2420 val = (Node*)(((intptr_t)val) & ~1); 2421 if (has_new_node(val)) { 2422 Node* new_val = new_node(val); 2423 if (is_decoden) { 2424 assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity"); 2425 // Note: new_val may have a control edge if 2426 // the original ideal node DecodeN was matched before 2427 // it was unpinned in Matcher::collect_null_checks(). 2428 // Unpin the mach node and mark it. 2429 new_val->set_req(0, NULL); 2430 new_val = (Node*)(((intptr_t)new_val) | 1); 2431 } 2432 // Is a match-tree root, so replace with the matched value 2433 _null_check_tests.map(i+1, new_val); 2434 } else { 2435 // Yank from candidate list 2436 _null_check_tests.map(i+1,_null_check_tests[--cnt]); 2437 _null_check_tests.map(i,_null_check_tests[--cnt]); 2438 _null_check_tests.pop(); 2439 _null_check_tests.pop(); 2440 i-=2; 2441 } 2442 } 2443} 2444 2445// Used by the DFA in dfa_xxx.cpp. Check for a following barrier or 2446// atomic instruction acting as a store_load barrier without any 2447// intervening volatile load, and thus we don't need a barrier here. 2448// We retain the Node to act as a compiler ordering barrier. 2449bool Matcher::post_store_load_barrier(const Node* vmb) { 2450 Compile* C = Compile::current(); 2451 assert(vmb->is_MemBar(), ""); 2452 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, ""); 2453 const MemBarNode* membar = vmb->as_MemBar(); 2454 2455 // Get the Ideal Proj node, ctrl, that can be used to iterate forward 2456 Node* ctrl = NULL; 2457 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) { 2458 Node* p = membar->fast_out(i); 2459 assert(p->is_Proj(), "only projections here"); 2460 if ((p->as_Proj()->_con == TypeFunc::Control) && 2461 !C->node_arena()->contains(p)) { // Unmatched old-space only 2462 ctrl = p; 2463 break; 2464 } 2465 } 2466 assert((ctrl != NULL), "missing control projection"); 2467 2468 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) { 2469 Node *x = ctrl->fast_out(j); 2470 int xop = x->Opcode(); 2471 2472 // We don't need current barrier if we see another or a lock 2473 // before seeing volatile load. 2474 // 2475 // Op_Fastunlock previously appeared in the Op_* list below. 2476 // With the advent of 1-0 lock operations we're no longer guaranteed 2477 // that a monitor exit operation contains a serializing instruction. 2478 2479 if (xop == Op_MemBarVolatile || 2480 xop == Op_CompareAndExchangeB || 2481 xop == Op_CompareAndExchangeS || 2482 xop == Op_CompareAndExchangeI || 2483 xop == Op_CompareAndExchangeL || 2484 xop == Op_CompareAndExchangeP || 2485 xop == Op_CompareAndExchangeN || 2486 xop == Op_WeakCompareAndSwapB || 2487 xop == Op_WeakCompareAndSwapS || 2488 xop == Op_WeakCompareAndSwapL || 2489 xop == Op_WeakCompareAndSwapP || 2490 xop == Op_WeakCompareAndSwapN || 2491 xop == Op_WeakCompareAndSwapI || 2492 xop == Op_CompareAndSwapB || 2493 xop == Op_CompareAndSwapS || 2494 xop == Op_CompareAndSwapL || 2495 xop == Op_CompareAndSwapP || 2496 xop == Op_CompareAndSwapN || 2497 xop == Op_CompareAndSwapI) { 2498 return true; 2499 } 2500 2501 // Op_FastLock previously appeared in the Op_* list above. 2502 // With biased locking we're no longer guaranteed that a monitor 2503 // enter operation contains a serializing instruction. 2504 if ((xop == Op_FastLock) && !UseBiasedLocking) { 2505 return true; 2506 } 2507 2508 if (x->is_MemBar()) { 2509 // We must retain this membar if there is an upcoming volatile 2510 // load, which will be followed by acquire membar. 2511 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) { 2512 return false; 2513 } else { 2514 // For other kinds of barriers, check by pretending we 2515 // are them, and seeing if we can be removed. 2516 return post_store_load_barrier(x->as_MemBar()); 2517 } 2518 } 2519 2520 // probably not necessary to check for these 2521 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) { 2522 return false; 2523 } 2524 } 2525 return false; 2526} 2527 2528// Check whether node n is a branch to an uncommon trap that we could 2529// optimize as test with very high branch costs in case of going to 2530// the uncommon trap. The code must be able to be recompiled to use 2531// a cheaper test. 2532bool Matcher::branches_to_uncommon_trap(const Node *n) { 2533 // Don't do it for natives, adapters, or runtime stubs 2534 Compile *C = Compile::current(); 2535 if (!C->is_method_compilation()) return false; 2536 2537 assert(n->is_If(), "You should only call this on if nodes."); 2538 IfNode *ifn = n->as_If(); 2539 2540 Node *ifFalse = NULL; 2541 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) { 2542 if (ifn->fast_out(i)->is_IfFalse()) { 2543 ifFalse = ifn->fast_out(i); 2544 break; 2545 } 2546 } 2547 assert(ifFalse, "An If should have an ifFalse. Graph is broken."); 2548 2549 Node *reg = ifFalse; 2550 int cnt = 4; // We must protect against cycles. Limit to 4 iterations. 2551 // Alternatively use visited set? Seems too expensive. 2552 while (reg != NULL && cnt > 0) { 2553 CallNode *call = NULL; 2554 RegionNode *nxt_reg = NULL; 2555 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) { 2556 Node *o = reg->fast_out(i); 2557 if (o->is_Call()) { 2558 call = o->as_Call(); 2559 } 2560 if (o->is_Region()) { 2561 nxt_reg = o->as_Region(); 2562 } 2563 } 2564 2565 if (call && 2566 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) { 2567 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type(); 2568 if (trtype->isa_int() && trtype->is_int()->is_con()) { 2569 jint tr_con = trtype->is_int()->get_con(); 2570 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con); 2571 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con); 2572 assert((int)reason < (int)BitsPerInt, "recode bit map"); 2573 2574 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason) 2575 && action != Deoptimization::Action_none) { 2576 // This uncommon trap is sure to recompile, eventually. 2577 // When that happens, C->too_many_traps will prevent 2578 // this transformation from happening again. 2579 return true; 2580 } 2581 } 2582 } 2583 2584 reg = nxt_reg; 2585 cnt--; 2586 } 2587 2588 return false; 2589} 2590 2591//============================================================================= 2592//---------------------------State--------------------------------------------- 2593State::State(void) { 2594#ifdef ASSERT 2595 _id = 0; 2596 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 2597 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 2598 //memset(_cost, -1, sizeof(_cost)); 2599 //memset(_rule, -1, sizeof(_rule)); 2600#endif 2601 memset(_valid, 0, sizeof(_valid)); 2602} 2603 2604#ifdef ASSERT 2605State::~State() { 2606 _id = 99; 2607 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 2608 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 2609 memset(_cost, -3, sizeof(_cost)); 2610 memset(_rule, -3, sizeof(_rule)); 2611} 2612#endif 2613 2614#ifndef PRODUCT 2615//---------------------------dump---------------------------------------------- 2616void State::dump() { 2617 tty->print("\n"); 2618 dump(0); 2619} 2620 2621void State::dump(int depth) { 2622 for( int j = 0; j < depth; j++ ) 2623 tty->print(" "); 2624 tty->print("--N: "); 2625 _leaf->dump(); 2626 uint i; 2627 for( i = 0; i < _LAST_MACH_OPER; i++ ) 2628 // Check for valid entry 2629 if( valid(i) ) { 2630 for( int j = 0; j < depth; j++ ) 2631 tty->print(" "); 2632 assert(_cost[i] != max_juint, "cost must be a valid value"); 2633 assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule"); 2634 tty->print_cr("%s %d %s", 2635 ruleName[i], _cost[i], ruleName[_rule[i]] ); 2636 } 2637 tty->cr(); 2638 2639 for( i=0; i<2; i++ ) 2640 if( _kids[i] ) 2641 _kids[i]->dump(depth+1); 2642} 2643#endif 2644