machnode.cpp revision 1472:c18cbe5936b8
1193323Sed/* 2193323Sed * Copyright (c) 1997, 2009, Oracle and/or its affiliates. All rights reserved. 3193323Sed * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4193323Sed * 5193323Sed * This code is free software; you can redistribute it and/or modify it 6193323Sed * under the terms of the GNU General Public License version 2 only, as 7193323Sed * published by the Free Software Foundation. 8193323Sed * 9193323Sed * This code is distributed in the hope that it will be useful, but WITHOUT 10193323Sed * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11193323Sed * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12193323Sed * version 2 for more details (a copy is included in the LICENSE file that 13193323Sed * accompanied this code). 14193323Sed * 15249423Sdim * You should have received a copy of the GNU General Public License version 16234353Sdim * 2 along with this work; if not, write to the Free Software Foundation, 17234353Sdim * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18249423Sdim * 19249423Sdim * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20249423Sdim * or visit www.oracle.com if you need additional information or have any 21249423Sdim * questions. 22234353Sdim * 23198090Srdivacky */ 24226633Sdim 25193323Sed#include "incls/_precompiled.incl" 26193323Sed#include "incls/_machnode.cpp.incl" 27224145Sdim 28224145Sdim//============================================================================= 29224145Sdim// Return the value requested 30193323Sed// result register lookup, corresponding to int_format 31193323Sedint MachOper::reg(PhaseRegAlloc *ra_, const Node *node) const { 32251662Sdim return (int)ra_->get_encode(node); 33251662Sdim} 34224145Sdim// input register lookup, corresponding to ext_format 35224145Sdimint MachOper::reg(PhaseRegAlloc *ra_, const Node *node, int idx) const { 36224145Sdim return (int)(ra_->get_encode(node->in(idx))); 37224145Sdim} 38193323Sedintptr_t MachOper::constant() const { return 0x00; } 39224145Sdimbool MachOper::constant_is_oop() const { return false; } 40224145Sdimjdouble MachOper::constantD() const { ShouldNotReachHere(); return 0.0; } 41224145Sdimjfloat MachOper::constantF() const { ShouldNotReachHere(); return 0.0; } 42224145Sdimjlong MachOper::constantL() const { ShouldNotReachHere(); return CONST64(0) ; } 43224145SdimTypeOopPtr *MachOper::oop() const { return NULL; } 44234353Sdimint MachOper::ccode() const { return 0x00; } 45234353Sdim// A zero, default, indicates this value is not needed. 46234353Sdim// May need to lookup the base register, as done in int_ and ext_format 47234353Sdimint MachOper::base (PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; } 48234353Sdimint MachOper::index(PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; } 49234353Sdimint MachOper::scale() const { return 0x00; } 50234353Sdimint MachOper::disp (PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; } 51234353Sdimint MachOper::constant_disp() const { return 0; } 52234353Sdimint MachOper::base_position() const { return -1; } // no base input 53193323Sedint MachOper::index_position() const { return -1; } // no index input 54251662Sdim// Check for PC-Relative displacement 55251662Sdimbool MachOper::disp_is_oop() const { return false; } 56251662Sdim// Return the label 57224145SdimLabel* MachOper::label() const { ShouldNotReachHere(); return 0; } 58224145Sdimintptr_t MachOper::method() const { ShouldNotReachHere(); return 0; } 59224145Sdim 60224145Sdim 61193323Sed//------------------------------negate----------------------------------------- 62224145Sdim// Negate conditional branches. Error for non-branch operands 63224145Sdimvoid MachOper::negate() { 64224145Sdim ShouldNotCallThis(); 65224145Sdim} 66224145Sdim 67224145Sdim//-----------------------------type-------------------------------------------- 68224145Sdimconst Type *MachOper::type() const { 69193323Sed return Type::BOTTOM; 70224145Sdim} 71193323Sed 72234353Sdim//------------------------------in_RegMask------------------------------------- 73234353Sdimconst RegMask *MachOper::in_RegMask(int index) const { 74234353Sdim ShouldNotReachHere(); 75234353Sdim return NULL; 76234353Sdim} 77234353Sdim 78234353Sdim//------------------------------dump_spec-------------------------------------- 79234353Sdim// Print any per-operand special info 80234353Sdim#ifndef PRODUCT 81234353Sdimvoid MachOper::dump_spec(outputStream *st) const { } 82234353Sdim#endif 83234353Sdim 84224145Sdim//------------------------------hash------------------------------------------- 85224145Sdim// Print any per-operand special info 86224145Sdimuint MachOper::hash() const { 87224145Sdim ShouldNotCallThis(); 88224145Sdim return 5; 89193323Sed} 90224145Sdim 91224145Sdim//------------------------------cmp-------------------------------------------- 92224145Sdim// Print any per-operand special info 93224145Sdimuint MachOper::cmp( const MachOper &oper ) const { 94193323Sed ShouldNotCallThis(); 95224145Sdim return opcode() == oper.opcode(); 96224145Sdim} 97224145Sdim 98224145Sdim//------------------------------hash------------------------------------------- 99224145Sdim// Print any per-operand special info 100224145Sdimuint labelOper::hash() const { 101224145Sdim return _block_num; 102193323Sed} 103224145Sdim 104224145Sdim//------------------------------cmp-------------------------------------------- 105224145Sdim// Print any per-operand special info 106224145Sdimuint labelOper::cmp( const MachOper &oper ) const { 107224145Sdim return (opcode() == oper.opcode()) && (_label == oper.label()); 108224145Sdim} 109224145Sdim 110224145Sdim//------------------------------hash------------------------------------------- 111193323Sed// Print any per-operand special info 112224145Sdimuint methodOper::hash() const { 113193323Sed return (uint)_method; 114193323Sed} 115224145Sdim 116224145Sdim//------------------------------cmp-------------------------------------------- 117224145Sdim// Print any per-operand special info 118224145Sdimuint methodOper::cmp( const MachOper &oper ) const { 119224145Sdim return (opcode() == oper.opcode()) && (_method == oper.method()); 120193323Sed} 121224145Sdim 122224145Sdim 123224145Sdim//============================================================================= 124224145Sdim//------------------------------MachNode--------------------------------------- 125193323Sed 126224145Sdim//------------------------------emit------------------------------------------- 127224145Sdimvoid MachNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 128224145Sdim #ifdef ASSERT 129224145Sdim tty->print("missing MachNode emit function: "); 130193323Sed dump(); 131224145Sdim #endif 132224145Sdim ShouldNotCallThis(); 133224145Sdim} 134193323Sed 135224145Sdim//------------------------------size------------------------------------------- 136224145Sdim// Size of instruction in bytes 137224145Sdimuint MachNode::size(PhaseRegAlloc *ra_) const { 138224145Sdim // If a virtual was not defined for this specific instruction, 139224145Sdim // Call the helper which finds the size by emitting the bits. 140224145Sdim return MachNode::emit_size(ra_); 141193323Sed} 142224145Sdim 143193323Sed//------------------------------size------------------------------------------- 144234353Sdim// Helper function that computes size by emitting code 145234353Sdimuint MachNode::emit_size(PhaseRegAlloc *ra_) const { 146234353Sdim // Emit into a trash buffer and count bytes emitted. 147234353Sdim assert(ra_ == ra_->C->regalloc(), "sanity"); 148234353Sdim return ra_->C->scratch_emit_size(this); 149224145Sdim} 150234353Sdim 151234353Sdim 152234353Sdim 153234353Sdim//------------------------------hash------------------------------------------- 154224145Sdimuint MachNode::hash() const { 155224145Sdim uint no = num_opnds(); 156193323Sed uint sum = rule(); 157193323Sed for( uint i=0; i<no; i++ ) 158224145Sdim sum += _opnds[i]->hash(); 159224145Sdim return sum+Node::hash(); 160224145Sdim} 161193323Sed 162224145Sdim//-----------------------------cmp--------------------------------------------- 163224145Sdimuint MachNode::cmp( const Node &node ) const { 164224145Sdim MachNode& n = *((Node&)node).as_Mach(); 165224145Sdim uint no = num_opnds(); 166224145Sdim if( no != n.num_opnds() ) return 0; 167224145Sdim if( rule() != n.rule() ) return 0; 168224145Sdim for( uint i=0; i<no; i++ ) // All operands must match 169234353Sdim if( !_opnds[i]->cmp( *n._opnds[i] ) ) 170224145Sdim return 0; // mis-matched operands 171224145Sdim return 1; // match 172224145Sdim} 173224145Sdim 174224145Sdim// Return an equivalent instruction using memory for cisc_operand position 175226633SdimMachNode *MachNode::cisc_version(int offset, Compile* C) { 176224145Sdim ShouldNotCallThis(); 177224145Sdim return NULL; 178224145Sdim} 179224145Sdim 180224145Sdimvoid MachNode::use_cisc_RegMask() { 181224145Sdim ShouldNotReachHere(); 182249423Sdim} 183224145Sdim 184193323Sed 185193323Sed//-----------------------------in_RegMask-------------------------------------- 186224145Sdimconst RegMask &MachNode::in_RegMask( uint idx ) const { 187224145Sdim uint numopnds = num_opnds(); // Virtual call for number of operands 188224145Sdim uint skipped = oper_input_base(); // Sum of leaves skipped so far 189224145Sdim if( idx < skipped ) { 190193323Sed assert( ideal_Opcode() == Op_AddP, "expected base ptr here" ); 191224145Sdim assert( idx == 1, "expected base ptr here" ); 192224145Sdim // debug info can be anywhere 193224145Sdim return *Compile::current()->matcher()->idealreg2spillmask[Op_RegP]; 194224145Sdim } 195224145Sdim uint opcnt = 1; // First operand 196224145Sdim uint num_edges = _opnds[1]->num_edges(); // leaves for first operand 197224145Sdim while( idx >= skipped+num_edges ) { 198224145Sdim skipped += num_edges; 199193323Sed opcnt++; // Bump operand count 200224145Sdim assert( opcnt < numopnds, "Accessing non-existent operand" ); 201224145Sdim num_edges = _opnds[opcnt]->num_edges(); // leaves for next operand 202224145Sdim } 203224145Sdim 204224145Sdim const RegMask *rm = cisc_RegMask(); 205224145Sdim if( rm == NULL || (int)opcnt != cisc_operand() ) { 206224145Sdim rm = _opnds[opcnt]->in_RegMask(idx-skipped); 207234353Sdim } 208234353Sdim return *rm; 209234353Sdim} 210224145Sdim 211224145Sdim//-----------------------------memory_inputs-------------------------------- 212224145Sdimconst MachOper* MachNode::memory_inputs(Node* &base, Node* &index) const { 213224145Sdim const MachOper* oper = memory_operand(); 214224145Sdim 215224145Sdim if (oper == (MachOper*)-1) { 216224145Sdim base = NodeSentinel; 217224145Sdim index = NodeSentinel; 218224145Sdim } else { 219224145Sdim base = NULL; 220224145Sdim index = NULL; 221224145Sdim if (oper != NULL) { 222224145Sdim // It has a unique memory operand. Find its index. 223224145Sdim int oper_idx = num_opnds(); 224224145Sdim while (--oper_idx >= 0) { 225224145Sdim if (_opnds[oper_idx] == oper) break; 226224145Sdim } 227224145Sdim int oper_pos = operand_index(oper_idx); 228224145Sdim int base_pos = oper->base_position(); 229224145Sdim if (base_pos >= 0) { 230224145Sdim base = _in[oper_pos+base_pos]; 231224145Sdim } 232224145Sdim int index_pos = oper->index_position(); 233224145Sdim if (index_pos >= 0) { 234224145Sdim index = _in[oper_pos+index_pos]; 235224145Sdim } 236193323Sed } 237234353Sdim } 238234353Sdim 239193323Sed return oper; 240193323Sed} 241224145Sdim 242224145Sdim//-----------------------------get_base_and_disp---------------------------- 243224145Sdimconst Node* MachNode::get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const { 244224145Sdim 245224145Sdim // Find the memory inputs using our helper function 246224145Sdim Node* base; 247234353Sdim Node* index; 248224145Sdim const MachOper* oper = memory_inputs(base, index); 249224145Sdim 250193323Sed if (oper == NULL) { 251193323Sed // Base has been set to NULL 252224145Sdim offset = 0; 253224145Sdim } else if (oper == (MachOper*)-1) { 254224145Sdim // Base has been set to NodeSentinel 255224145Sdim // There is not a unique memory use here. We will fall to AliasIdxBot. 256224145Sdim offset = Type::OffsetBot; 257224145Sdim } else { 258224145Sdim // Base may be NULL, even if offset turns out to be != 0 259224145Sdim 260226633Sdim intptr_t disp = oper->constant_disp(); 261224145Sdim int scale = oper->scale(); 262224145Sdim // Now we have collected every part of the ADLC MEMORY_INTER. 263224145Sdim // See if it adds up to a base + offset. 264224145Sdim if (index != NULL) { 265224145Sdim const Type* t_index = index->bottom_type(); 266224145Sdim if (t_index->isa_narrowoop()) { // EncodeN, LoadN, LoadConN, LoadNKlass. 267224145Sdim // Memory references through narrow oops have a 268224145Sdim // funny base so grab the type from the index: 269224145Sdim // [R12 + narrow_oop_reg<<3 + offset] 270224145Sdim assert(base == NULL, "Memory references through narrow oops have no base"); 271224145Sdim offset = disp; 272224145Sdim adr_type = t_index->make_ptr()->add_offset(offset); 273224145Sdim return NULL; 274224145Sdim } else if (!index->is_Con()) { 275224145Sdim disp = Type::OffsetBot; 276224145Sdim } else if (disp != Type::OffsetBot) { 277224145Sdim const TypeX* ti = t_index->isa_intptr_t(); 278224145Sdim if (ti == NULL) { 279224145Sdim disp = Type::OffsetBot; // a random constant?? 280224145Sdim } else { 281224145Sdim disp += ti->get_con() << scale; 282224145Sdim } 283224145Sdim } 284224145Sdim } 285224145Sdim offset = disp; 286234353Sdim 287224145Sdim // In i486.ad, indOffset32X uses base==RegI and disp==RegP, 288224145Sdim // this will prevent alias analysis without the following support: 289224145Sdim // Lookup the TypePtr used by indOffset32X, a compile-time constant oop, 290224145Sdim // Add the offset determined by the "base", or use Type::OffsetBot. 291224145Sdim if( adr_type == TYPE_PTR_SENTINAL ) { 292224145Sdim const TypePtr *t_disp = oper->disp_as_type(); // only !NULL for indOffset32X 293224145Sdim if (t_disp != NULL) { 294224145Sdim offset = Type::OffsetBot; 295224145Sdim const Type* t_base = base->bottom_type(); 296224145Sdim if (t_base->isa_intptr_t()) { 297224145Sdim const TypeX *t_offset = t_base->is_intptr_t(); 298226633Sdim if( t_offset->is_con() ) { 299224145Sdim offset = t_offset->get_con(); 300224145Sdim } 301224145Sdim } 302224145Sdim adr_type = t_disp->add_offset(offset); 303224145Sdim } else if( base == NULL && offset != 0 && offset != Type::OffsetBot ) { 304224145Sdim // Use ideal type if it is oop ptr. 305224145Sdim const TypePtr *tp = oper->type()->isa_ptr(); 306193323Sed if( tp != NULL) { 307224145Sdim adr_type = tp; 308224145Sdim } 309224145Sdim } 310224145Sdim } 311224145Sdim 312224145Sdim } 313224145Sdim return base; 314224145Sdim} 315224145Sdim 316224145Sdim 317224145Sdim//---------------------------------adr_type--------------------------------- 318224145Sdimconst class TypePtr *MachNode::adr_type() const { 319224145Sdim intptr_t offset = 0; 320224145Sdim const TypePtr *adr_type = TYPE_PTR_SENTINAL; // attempt computing adr_type 321224145Sdim const Node *base = get_base_and_disp(offset, adr_type); 322224145Sdim if( adr_type != TYPE_PTR_SENTINAL ) { 323224145Sdim return adr_type; // get_base_and_disp has the answer 324224145Sdim } 325224145Sdim 326224145Sdim // Direct addressing modes have no base node, simply an indirect 327224145Sdim // offset, which is always to raw memory. 328224145Sdim // %%%%% Someday we'd like to allow constant oop offsets which 329224145Sdim // would let Intel load from static globals in 1 instruction. 330224145Sdim // Currently Intel requires 2 instructions and a register temp. 331224145Sdim if (base == NULL) { 332224145Sdim // NULL base, zero offset means no memory at all (a null pointer!) 333251662Sdim if (offset == 0) { 334251662Sdim return NULL; 335251662Sdim } 336251662Sdim // NULL base, any offset means any pointer whatever 337224145Sdim if (offset == Type::OffsetBot) { 338251662Sdim return TypePtr::BOTTOM; 339224145Sdim } 340224145Sdim // %%% make offset be intptr_t 341224145Sdim assert(!Universe::heap()->is_in_reserved((oop)offset), "must be a raw ptr"); 342234353Sdim return TypeRawPtr::BOTTOM; 343234353Sdim } 344251662Sdim 345251662Sdim // base of -1 with no particular offset means all of memory 346251662Sdim if (base == NodeSentinel) return TypePtr::BOTTOM; 347234353Sdim 348234353Sdim const Type* t = base->bottom_type(); 349224145Sdim if (UseCompressedOops && Universe::narrow_oop_shift() == 0) { 350193323Sed // 32-bit unscaled narrow oop can be the base of any address expression 351224145Sdim t = t->make_ptr(); 352224145Sdim } 353224145Sdim if (t->isa_intptr_t() && offset != 0 && offset != Type::OffsetBot) { 354193323Sed // We cannot assert that the offset does not look oop-ish here. 355224145Sdim // Depending on the heap layout the cardmark base could land 356224145Sdim // inside some oopish region. It definitely does for Win2K. 357224145Sdim // The sum of cardmark-base plus shift-by-9-oop lands outside 358224145Sdim // the oop-ish area but we can't assert for that statically. 359224145Sdim return TypeRawPtr::BOTTOM; 360224145Sdim } 361224145Sdim 362193323Sed const TypePtr *tp = t->isa_ptr(); 363224145Sdim 364224145Sdim // be conservative if we do not recognize the type 365224145Sdim if (tp == NULL) { 366224145Sdim assert(false, "this path may produce not optimal code"); 367224145Sdim return TypePtr::BOTTOM; 368224145Sdim } 369224145Sdim assert(tp->base() != Type::AnyPtr, "not a bare pointer"); 370224145Sdim 371224145Sdim return tp->add_offset(offset); 372224145Sdim} 373224145Sdim 374224145Sdim 375224145Sdim//-----------------------------operand_index--------------------------------- 376224145Sdimint MachNode::operand_index( uint operand ) const { 377226633Sdim if( operand < 1 ) return -1; 378226633Sdim assert(operand < num_opnds(), "oob"); 379226633Sdim if( _opnds[operand]->num_edges() == 0 ) return -1; 380226633Sdim 381226633Sdim uint skipped = oper_input_base(); // Sum of leaves skipped so far 382234353Sdim for (uint opcnt = 1; opcnt < operand; opcnt++) { 383234353Sdim uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand 384234353Sdim skipped += num_edges; 385224145Sdim } 386224145Sdim return skipped; 387224145Sdim} 388251662Sdim 389251662Sdim 390224145Sdim//------------------------------negate----------------------------------------- 391224145Sdim// Negate conditional branches. Error for non-branch Nodes 392224145Sdimvoid MachNode::negate() { 393224145Sdim ShouldNotCallThis(); 394224145Sdim} 395224145Sdim 396224145Sdim//------------------------------peephole--------------------------------------- 397224145Sdim// Apply peephole rule(s) to this instruction 398224145SdimMachNode *MachNode::peephole( Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted, Compile* C ) { 399193323Sed return NULL; 400224145Sdim} 401224145Sdim 402224145Sdim//------------------------------add_case_label--------------------------------- 403224145Sdim// Adds the label for the case 404234353Sdimvoid MachNode::add_case_label( int index_num, Label* blockLabel) { 405234353Sdim ShouldNotCallThis(); 406234353Sdim} 407193323Sed 408224145Sdim//------------------------------label_set-------------------------------------- 409224145Sdim// Set the Label for a LabelOper, if an operand for this instruction 410224145Sdimvoid MachNode::label_set( Label& label, uint block_num ) { 411224145Sdim ShouldNotCallThis(); 412224145Sdim} 413224145Sdim 414224145Sdim//------------------------------method_set------------------------------------- 415224145Sdim// Set the absolute address of a method 416224145Sdimvoid MachNode::method_set( intptr_t addr ) { 417224145Sdim ShouldNotCallThis(); 418224145Sdim} 419224145Sdim 420224145Sdim//------------------------------rematerialize---------------------------------- 421224145Sdimbool MachNode::rematerialize() const { 422224145Sdim // Temps are always rematerializable 423224145Sdim if (is_MachTemp()) return true; 424193323Sed 425224145Sdim uint r = rule(); // Match rule 426224145Sdim if( r < Matcher::_begin_rematerialize || 427193323Sed r >= Matcher::_end_rematerialize ) 428224145Sdim return false; 429224145Sdim 430224145Sdim // For 2-address instructions, the input live range is also the output 431224145Sdim // live range. Remateralizing does not make progress on the that live range. 432224145Sdim if( two_adr() ) return false; 433224145Sdim 434224145Sdim // Check for rematerializing float constants, or not 435234353Sdim if( !Matcher::rematerialize_float_constants ) { 436224145Sdim int op = ideal_Opcode(); 437224145Sdim if( op == Op_ConF || op == Op_ConD ) 438224145Sdim return false; 439224145Sdim } 440224145Sdim 441224145Sdim // Defining flags - can't spill these! Must remateralize. 442224145Sdim if( ideal_reg() == Op_RegFlags ) 443224145Sdim return true; 444193323Sed 445224145Sdim // Stretching lots of inputs - don't do it. 446193323Sed if( req() > 2 ) 447193323Sed return false; 448224145Sdim 449224145Sdim // Don't remateralize somebody with bound inputs - it stretches a 450224145Sdim // fixed register lifetime. 451224145Sdim uint idx = oper_input_base(); 452224145Sdim if( req() > idx ) { 453193323Sed const RegMask &rm = in_RegMask(idx); 454224145Sdim if( rm.is_bound1() || rm.is_bound2() ) 455224145Sdim return false; 456193323Sed } 457224145Sdim 458193323Sed return true; 459193323Sed} 460224145Sdim 461193323Sed#ifndef PRODUCT 462193323Sed//------------------------------dump_spec-------------------------------------- 463193323Sed// Print any per-operand special info 464193323Sedvoid MachNode::dump_spec(outputStream *st) const { 465193323Sed uint cnt = num_opnds(); 466234353Sdim for( uint i=0; i<cnt; i++ ) 467193323Sed _opnds[i]->dump_spec(st); 468234353Sdim const TypePtr *t = adr_type(); 469193323Sed if( t ) { 470193323Sed Compile* C = Compile::current(); 471193323Sed if( C->alias_type(t)->is_volatile() ) 472193323Sed st->print(" Volatile!"); 473224145Sdim } 474224145Sdim} 475193323Sed 476193323Sed//------------------------------dump_format------------------------------------ 477234353Sdim// access to virtual 478234353Sdimvoid MachNode::dump_format(PhaseRegAlloc *ra, outputStream *st) const { 479234353Sdim format(ra, st); // access to virtual 480234353Sdim} 481234353Sdim#endif 482234353Sdim 483234353Sdim//============================================================================= 484234353Sdim#ifndef PRODUCT 485234353Sdimvoid MachTypeNode::dump_spec(outputStream *st) const { 486234353Sdim _bottom_type->dump_on(st); 487234353Sdim} 488234353Sdim#endif 489234353Sdim 490224145Sdim//============================================================================= 491193323Sed#ifndef PRODUCT 492234353Sdimvoid MachNullCheckNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 493234353Sdim int reg = ra_->get_reg_first(in(1)->in(_vidx)); 494234353Sdim tty->print("%s %s", Name(), Matcher::regName[reg]); 495224145Sdim} 496234353Sdim#endif 497234353Sdim 498224145Sdimvoid MachNullCheckNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 499224145Sdim // only emits entries in the null-pointer exception handler table 500224145Sdim} 501193323Sed 502224145Sdimconst RegMask &MachNullCheckNode::in_RegMask( uint idx ) const { 503234353Sdim if( idx == 0 ) return RegMask::Empty; 504224145Sdim else return in(1)->as_Mach()->out_RegMask(); 505224145Sdim} 506224145Sdim 507193323Sed//============================================================================= 508193323Sedconst Type *MachProjNode::bottom_type() const { 509193323Sed if( _ideal_reg == fat_proj ) return Type::BOTTOM; 510193323Sed // Try the normal mechanism first 511224145Sdim const Type *t = in(0)->bottom_type(); 512193323Sed if( t->base() == Type::Tuple ) { 513193323Sed const TypeTuple *tt = t->is_tuple(); 514193323Sed if (_con < tt->cnt()) 515193323Sed return tt->field_at(_con); 516193323Sed } 517193323Sed // Else use generic type from ideal register set 518193323Sed assert((uint)_ideal_reg < (uint)_last_machine_leaf && Type::mreg2type[_ideal_reg], "in bounds"); 519193323Sed return Type::mreg2type[_ideal_reg]; 520193323Sed} 521193323Sed 522193323Sedconst TypePtr *MachProjNode::adr_type() const { 523224145Sdim if (bottom_type() == Type::MEMORY) { 524193323Sed // in(0) might be a narrow MemBar; otherwise we will report TypePtr::BOTTOM 525193323Sed const TypePtr* adr_type = in(0)->adr_type(); 526193323Sed #ifdef ASSERT 527193323Sed if (!is_error_reported() && !Node::in_dump()) 528193323Sed assert(adr_type != NULL, "source must have adr_type"); 529193323Sed #endif 530193323Sed return adr_type; 531193323Sed } 532193323Sed assert(bottom_type()->base() != Type::Memory, "no other memories?"); 533193323Sed return NULL; 534193323Sed} 535193323Sed 536193323Sed#ifndef PRODUCT 537193323Sedvoid MachProjNode::dump_spec(outputStream *st) const { 538193323Sed ProjNode::dump_spec(st); 539193323Sed switch (_ideal_reg) { 540193323Sed case unmatched_proj: st->print("/unmatched"); break; 541193323Sed case fat_proj: st->print("/fat"); if (WizardMode) _rout.dump(); break; 542193323Sed } 543193323Sed} 544193323Sed#endif 545193323Sed 546193323Sed//============================================================================= 547193323Sed#ifndef PRODUCT 548193323Sedvoid MachIfNode::dump_spec(outputStream *st) const { 549193323Sed st->print("P=%f, C=%f",_prob, _fcnt); 550224145Sdim} 551224145Sdim#endif 552224145Sdim 553224145Sdim//============================================================================= 554193323Seduint MachReturnNode::size_of() const { return sizeof(*this); } 555224145Sdim 556193323Sed//------------------------------Registers-------------------------------------- 557193323Sedconst RegMask &MachReturnNode::in_RegMask( uint idx ) const { 558193323Sed return _in_rms[idx]; 559234353Sdim} 560234353Sdim 561234353Sdimconst TypePtr *MachReturnNode::adr_type() const { 562234353Sdim // most returns and calls are assumed to consume & modify all of memory 563193323Sed // the matcher will copy non-wide adr_types from ideal originals 564193323Sed return _adr_type; 565193323Sed} 566224145Sdim 567224145Sdim//============================================================================= 568224145Sdimconst Type *MachSafePointNode::bottom_type() const { return TypeTuple::MEMBAR; } 569224145Sdim 570224145Sdim//------------------------------Registers-------------------------------------- 571224145Sdimconst RegMask &MachSafePointNode::in_RegMask( uint idx ) const { 572224145Sdim // Values in the domain use the users calling convention, embodied in the 573224145Sdim // _in_rms array of RegMasks. 574224145Sdim if( idx < TypeFunc::Parms ) return _in_rms[idx]; 575224145Sdim 576224145Sdim if (SafePointNode::needs_polling_address_input() && 577224145Sdim idx == TypeFunc::Parms && 578224145Sdim ideal_Opcode() == Op_SafePoint) { 579224145Sdim return MachNode::in_RegMask(idx); 580224145Sdim } 581224145Sdim 582224145Sdim // Values outside the domain represent debug info 583224145Sdim return *Compile::current()->matcher()->idealreg2spillmask[in(idx)->ideal_reg()]; 584224145Sdim} 585224145Sdim 586198090Srdivacky 587224145Sdim//============================================================================= 588224145Sdim 589224145Sdimuint MachCallNode::cmp( const Node &n ) const 590224145Sdim{ return _tf == ((MachCallNode&)n)._tf; } 591224145Sdimconst Type *MachCallNode::bottom_type() const { return tf()->range(); } 592224145Sdimconst Type *MachCallNode::Value(PhaseTransform *phase) const { return tf()->range(); } 593234353Sdim 594234353Sdim#ifndef PRODUCT 595234353Sdimvoid MachCallNode::dump_spec(outputStream *st) const { 596234353Sdim st->print("# "); 597234353Sdim tf()->dump_on(st); 598239462Sdim if (_cnt != COUNT_UNKNOWN) st->print(" C=%f",_cnt); 599239462Sdim if (jvms() != NULL) jvms()->dump_spec(st); 600234353Sdim} 601234353Sdim#endif 602234353Sdim 603234353Sdim 604234353Sdimbool MachCallNode::return_value_is_used() const { 605234353Sdim if (tf()->range()->cnt() == TypeFunc::Parms) { 606234353Sdim // void return 607234353Sdim return false; 608234353Sdim } 609234353Sdim 610249423Sdim // find the projection corresponding to the return value 611249423Sdim for (DUIterator_Fast imax, i = fast_outs(imax); i < imax; i++) { 612234353Sdim Node *use = fast_out(i); 613234353Sdim if (!use->is_Proj()) continue; 614234353Sdim if (use->as_Proj()->_con == TypeFunc::Parms) { 615234353Sdim return true; 616234353Sdim } 617234353Sdim } 618234353Sdim return false; 619234353Sdim} 620234353Sdim 621234353Sdim 622234353Sdim//------------------------------Registers-------------------------------------- 623234353Sdimconst RegMask &MachCallNode::in_RegMask( uint idx ) const { 624234353Sdim // Values in the domain use the users calling convention, embodied in the 625234353Sdim // _in_rms array of RegMasks. 626234353Sdim if (idx < tf()->domain()->cnt()) return _in_rms[idx]; 627234353Sdim // Values outside the domain represent debug info 628234353Sdim return *Compile::current()->matcher()->idealreg2debugmask[in(idx)->ideal_reg()]; 629234353Sdim} 630234353Sdim 631234353Sdim//============================================================================= 632234353Sdimuint MachCallJavaNode::size_of() const { return sizeof(*this); } 633251662Sdimuint MachCallJavaNode::cmp( const Node &n ) const { 634234353Sdim MachCallJavaNode &call = (MachCallJavaNode&)n; 635234353Sdim return MachCallNode::cmp(call) && _method->equals(call._method); 636234353Sdim} 637224145Sdim#ifndef PRODUCT 638224145Sdimvoid MachCallJavaNode::dump_spec(outputStream *st) const { 639224145Sdim if (_method_handle_invoke) 640224145Sdim st->print("MethodHandle "); 641224145Sdim if (_method) { 642198090Srdivacky _method->print_short_name(st); 643198090Srdivacky st->print(" "); 644224145Sdim } 645224145Sdim MachCallNode::dump_spec(st); 646224145Sdim} 647224145Sdim#endif 648224145Sdim 649224145Sdim//------------------------------Registers-------------------------------------- 650224145Sdimconst RegMask &MachCallJavaNode::in_RegMask(uint idx) const { 651224145Sdim // Values in the domain use the users calling convention, embodied in the 652224145Sdim // _in_rms array of RegMasks. 653224145Sdim if (idx < tf()->domain()->cnt()) return _in_rms[idx]; 654224145Sdim // Values outside the domain represent debug info 655224145Sdim Matcher* m = Compile::current()->matcher(); 656224145Sdim // If this call is a MethodHandle invoke we have to use a different 657224145Sdim // debugmask which does not include the register we use to save the 658224145Sdim // SP over MH invokes. 659224145Sdim RegMask** debugmask = _method_handle_invoke ? m->idealreg2mhdebugmask : m->idealreg2debugmask; 660224145Sdim return *debugmask[in(idx)->ideal_reg()]; 661224145Sdim} 662224145Sdim 663224145Sdim//============================================================================= 664224145Sdimuint MachCallStaticJavaNode::size_of() const { return sizeof(*this); } 665224145Sdimuint MachCallStaticJavaNode::cmp( const Node &n ) const { 666224145Sdim MachCallStaticJavaNode &call = (MachCallStaticJavaNode&)n; 667224145Sdim return MachCallJavaNode::cmp(call) && _name == call._name; 668224145Sdim} 669224145Sdim 670224145Sdim//----------------------------uncommon_trap_request---------------------------- 671224145Sdim// If this is an uncommon trap, return the request code, else zero. 672224145Sdimint MachCallStaticJavaNode::uncommon_trap_request() const { 673224145Sdim if (_name != NULL && !strcmp(_name, "uncommon_trap")) { 674224145Sdim return CallStaticJavaNode::extract_uncommon_trap_request(this); 675224145Sdim } 676224145Sdim return 0; 677224145Sdim} 678224145Sdim 679224145Sdim#ifndef PRODUCT 680224145Sdim// Helper for summarizing uncommon_trap arguments. 681224145Sdimvoid MachCallStaticJavaNode::dump_trap_args(outputStream *st) const { 682224145Sdim int trap_req = uncommon_trap_request(); 683239462Sdim if (trap_req != 0) { 684224145Sdim char buf[100]; 685224145Sdim st->print("(%s)", 686224145Sdim Deoptimization::format_trap_request(buf, sizeof(buf), 687234353Sdim trap_req)); 688224145Sdim } 689224145Sdim} 690224145Sdim 691224145Sdimvoid MachCallStaticJavaNode::dump_spec(outputStream *st) const { 692224145Sdim st->print("Static "); 693224145Sdim if (_name != NULL) { 694193323Sed st->print("wrapper for: %s", _name ); 695224145Sdim dump_trap_args(st); 696224145Sdim st->print(" "); 697224145Sdim } 698193323Sed MachCallJavaNode::dump_spec(st); 699224145Sdim} 700224145Sdim#endif 701224145Sdim 702226633Sdim//============================================================================= 703226633Sdim#ifndef PRODUCT 704226633Sdimvoid MachCallDynamicJavaNode::dump_spec(outputStream *st) const { 705224145Sdim st->print("Dynamic "); 706224145Sdim MachCallJavaNode::dump_spec(st); 707193323Sed} 708224145Sdim#endif 709224145Sdim//============================================================================= 710224145Sdimuint MachCallRuntimeNode::size_of() const { return sizeof(*this); } 711224145Sdimuint MachCallRuntimeNode::cmp( const Node &n ) const { 712234353Sdim MachCallRuntimeNode &call = (MachCallRuntimeNode&)n; 713193323Sed return MachCallNode::cmp(call) && !strcmp(_name,call._name); 714224145Sdim} 715224145Sdim#ifndef PRODUCT 716224145Sdimvoid MachCallRuntimeNode::dump_spec(outputStream *st) const { 717224145Sdim st->print("%s ",_name); 718224145Sdim MachCallNode::dump_spec(st); 719224145Sdim} 720224145Sdim#endif 721193323Sed//============================================================================= 722234353Sdim// A shared JVMState for all HaltNodes. Indicates the start of debug info 723193323Sed// is at TypeFunc::Parms. Only required for SOE register spill handling - 724234353Sdim// to indicate where the stack-slot-only debug info inputs begin. 725193323Sed// There is no other JVM state needed here. 726234353SdimJVMState jvms_for_throw(0); 727193323SedJVMState *MachHaltNode::jvms() const { 728224145Sdim return &jvms_for_throw; 729224145Sdim} 730224145Sdim 731224145Sdim//============================================================================= 732224145Sdim#ifndef PRODUCT 733224145Sdimvoid labelOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { 734224145Sdim st->print("B%d", _block_num); 735224145Sdim} 736234353Sdim#endif // PRODUCT 737224145Sdim 738234353Sdim//============================================================================= 739234353Sdim#ifndef PRODUCT 740193323Sedvoid methodOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const { 741224145Sdim st->print(INTPTR_FORMAT, _method); 742224145Sdim} 743226633Sdim#endif // PRODUCT 744226633Sdim