chaitin.cpp revision 579:0fbdb4381b99
1/* 2 * Copyright 2000-2009 Sun Microsystems, Inc. All Rights Reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 * CA 95054 USA or visit www.sun.com if you need additional information or 21 * have any questions. 22 * 23 */ 24 25#include "incls/_precompiled.incl" 26#include "incls/_chaitin.cpp.incl" 27 28//============================================================================= 29 30#ifndef PRODUCT 31void LRG::dump( ) const { 32 ttyLocker ttyl; 33 tty->print("%d ",num_regs()); 34 _mask.dump(); 35 if( _msize_valid ) { 36 if( mask_size() == compute_mask_size() ) tty->print(", #%d ",_mask_size); 37 else tty->print(", #!!!_%d_vs_%d ",_mask_size,_mask.Size()); 38 } else { 39 tty->print(", #?(%d) ",_mask.Size()); 40 } 41 42 tty->print("EffDeg: "); 43 if( _degree_valid ) tty->print( "%d ", _eff_degree ); 44 else tty->print("? "); 45 46 if( is_multidef() ) { 47 tty->print("MultiDef "); 48 if (_defs != NULL) { 49 tty->print("("); 50 for (int i = 0; i < _defs->length(); i++) { 51 tty->print("N%d ", _defs->at(i)->_idx); 52 } 53 tty->print(") "); 54 } 55 } 56 else if( _def == 0 ) tty->print("Dead "); 57 else tty->print("Def: N%d ",_def->_idx); 58 59 tty->print("Cost:%4.2g Area:%4.2g Score:%4.2g ",_cost,_area, score()); 60 // Flags 61 if( _is_oop ) tty->print("Oop "); 62 if( _is_float ) tty->print("Float "); 63 if( _was_spilled1 ) tty->print("Spilled "); 64 if( _was_spilled2 ) tty->print("Spilled2 "); 65 if( _direct_conflict ) tty->print("Direct_conflict "); 66 if( _fat_proj ) tty->print("Fat "); 67 if( _was_lo ) tty->print("Lo "); 68 if( _has_copy ) tty->print("Copy "); 69 if( _at_risk ) tty->print("Risk "); 70 71 if( _must_spill ) tty->print("Must_spill "); 72 if( _is_bound ) tty->print("Bound "); 73 if( _msize_valid ) { 74 if( _degree_valid && lo_degree() ) tty->print("Trivial "); 75 } 76 77 tty->cr(); 78} 79#endif 80 81//------------------------------score------------------------------------------ 82// Compute score from cost and area. Low score is best to spill. 83static double raw_score( double cost, double area ) { 84 return cost - (area*RegisterCostAreaRatio) * 1.52588e-5; 85} 86 87double LRG::score() const { 88 // Scale _area by RegisterCostAreaRatio/64K then subtract from cost. 89 // Bigger area lowers score, encourages spilling this live range. 90 // Bigger cost raise score, prevents spilling this live range. 91 // (Note: 1/65536 is the magic constant below; I dont trust the C optimizer 92 // to turn a divide by a constant into a multiply by the reciprical). 93 double score = raw_score( _cost, _area); 94 95 // Account for area. Basically, LRGs covering large areas are better 96 // to spill because more other LRGs get freed up. 97 if( _area == 0.0 ) // No area? Then no progress to spill 98 return 1e35; 99 100 if( _was_spilled2 ) // If spilled once before, we are unlikely 101 return score + 1e30; // to make progress again. 102 103 if( _cost >= _area*3.0 ) // Tiny area relative to cost 104 return score + 1e17; // Probably no progress to spill 105 106 if( (_cost+_cost) >= _area*3.0 ) // Small area relative to cost 107 return score + 1e10; // Likely no progress to spill 108 109 return score; 110} 111 112//------------------------------LRG_List--------------------------------------- 113LRG_List::LRG_List( uint max ) : _cnt(max), _max(max), _lidxs(NEW_RESOURCE_ARRAY(uint,max)) { 114 memset( _lidxs, 0, sizeof(uint)*max ); 115} 116 117void LRG_List::extend( uint nidx, uint lidx ) { 118 _nesting.check(); 119 if( nidx >= _max ) { 120 uint size = 16; 121 while( size <= nidx ) size <<=1; 122 _lidxs = REALLOC_RESOURCE_ARRAY( uint, _lidxs, _max, size ); 123 _max = size; 124 } 125 while( _cnt <= nidx ) 126 _lidxs[_cnt++] = 0; 127 _lidxs[nidx] = lidx; 128} 129 130#define NUMBUCKS 3 131 132//------------------------------Chaitin---------------------------------------- 133PhaseChaitin::PhaseChaitin(uint unique, PhaseCFG &cfg, Matcher &matcher) 134 : PhaseRegAlloc(unique, cfg, matcher, 135#ifndef PRODUCT 136 print_chaitin_statistics 137#else 138 NULL 139#endif 140 ), 141 _names(unique), _uf_map(unique), 142 _maxlrg(0), _live(0), 143 _spilled_once(Thread::current()->resource_area()), 144 _spilled_twice(Thread::current()->resource_area()), 145 _lo_degree(0), _lo_stk_degree(0), _hi_degree(0), _simplified(0), 146 _oldphi(unique) 147#ifndef PRODUCT 148 , _trace_spilling(TraceSpilling || C->method_has_option("TraceSpilling")) 149#endif 150{ 151 NOT_PRODUCT( Compile::TracePhase t3("ctorChaitin", &_t_ctorChaitin, TimeCompiler); ) 152 uint i,j; 153 // Build a list of basic blocks, sorted by frequency 154 _blks = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks ); 155 // Experiment with sorting strategies to speed compilation 156 double cutoff = BLOCK_FREQUENCY(1.0); // Cutoff for high frequency bucket 157 Block **buckets[NUMBUCKS]; // Array of buckets 158 uint buckcnt[NUMBUCKS]; // Array of bucket counters 159 double buckval[NUMBUCKS]; // Array of bucket value cutoffs 160 for( i = 0; i < NUMBUCKS; i++ ) { 161 buckets[i] = NEW_RESOURCE_ARRAY( Block *, _cfg._num_blocks ); 162 buckcnt[i] = 0; 163 // Bump by three orders of magnitude each time 164 cutoff *= 0.001; 165 buckval[i] = cutoff; 166 for( j = 0; j < _cfg._num_blocks; j++ ) { 167 buckets[i][j] = NULL; 168 } 169 } 170 // Sort blocks into buckets 171 for( i = 0; i < _cfg._num_blocks; i++ ) { 172 for( j = 0; j < NUMBUCKS; j++ ) { 173 if( (j == NUMBUCKS-1) || (_cfg._blocks[i]->_freq > buckval[j]) ) { 174 // Assign block to end of list for appropriate bucket 175 buckets[j][buckcnt[j]++] = _cfg._blocks[i]; 176 break; // kick out of inner loop 177 } 178 } 179 } 180 // Dump buckets into final block array 181 uint blkcnt = 0; 182 for( i = 0; i < NUMBUCKS; i++ ) { 183 for( j = 0; j < buckcnt[i]; j++ ) { 184 _blks[blkcnt++] = buckets[i][j]; 185 } 186 } 187 188 assert(blkcnt == _cfg._num_blocks, "Block array not totally filled"); 189} 190 191void PhaseChaitin::Register_Allocate() { 192 193 // Above the OLD FP (and in registers) are the incoming arguments. Stack 194 // slots in this area are called "arg_slots". Above the NEW FP (and in 195 // registers) is the outgoing argument area; above that is the spill/temp 196 // area. These are all "frame_slots". Arg_slots start at the zero 197 // stack_slots and count up to the known arg_size. Frame_slots start at 198 // the stack_slot #arg_size and go up. After allocation I map stack 199 // slots to actual offsets. Stack-slots in the arg_slot area are biased 200 // by the frame_size; stack-slots in the frame_slot area are biased by 0. 201 202 _trip_cnt = 0; 203 _alternate = 0; 204 _matcher._allocation_started = true; 205 206 ResourceArea live_arena; // Arena for liveness & IFG info 207 ResourceMark rm(&live_arena); 208 209 // Need live-ness for the IFG; need the IFG for coalescing. If the 210 // liveness is JUST for coalescing, then I can get some mileage by renaming 211 // all copy-related live ranges low and then using the max copy-related 212 // live range as a cut-off for LIVE and the IFG. In other words, I can 213 // build a subset of LIVE and IFG just for copies. 214 PhaseLive live(_cfg,_names,&live_arena); 215 216 // Need IFG for coalescing and coloring 217 PhaseIFG ifg( &live_arena ); 218 _ifg = &ifg; 219 220 if (C->unique() > _names.Size()) _names.extend(C->unique()-1, 0); 221 222 // Come out of SSA world to the Named world. Assign (virtual) registers to 223 // Nodes. Use the same register for all inputs and the output of PhiNodes 224 // - effectively ending SSA form. This requires either coalescing live 225 // ranges or inserting copies. For the moment, we insert "virtual copies" 226 // - we pretend there is a copy prior to each Phi in predecessor blocks. 227 // We will attempt to coalesce such "virtual copies" before we manifest 228 // them for real. 229 de_ssa(); 230 231#ifdef ASSERT 232 // Veify the graph before RA. 233 verify(&live_arena); 234#endif 235 236 { 237 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) 238 _live = NULL; // Mark live as being not available 239 rm.reset_to_mark(); // Reclaim working storage 240 IndexSet::reset_memory(C, &live_arena); 241 ifg.init(_maxlrg); // Empty IFG 242 gather_lrg_masks( false ); // Collect LRG masks 243 live.compute( _maxlrg ); // Compute liveness 244 _live = &live; // Mark LIVE as being available 245 } 246 247 // Base pointers are currently "used" by instructions which define new 248 // derived pointers. This makes base pointers live up to the where the 249 // derived pointer is made, but not beyond. Really, they need to be live 250 // across any GC point where the derived value is live. So this code looks 251 // at all the GC points, and "stretches" the live range of any base pointer 252 // to the GC point. 253 if( stretch_base_pointer_live_ranges(&live_arena) ) { 254 NOT_PRODUCT( Compile::TracePhase t3("computeLive (sbplr)", &_t_computeLive, TimeCompiler); ) 255 // Since some live range stretched, I need to recompute live 256 _live = NULL; 257 rm.reset_to_mark(); // Reclaim working storage 258 IndexSet::reset_memory(C, &live_arena); 259 ifg.init(_maxlrg); 260 gather_lrg_masks( false ); 261 live.compute( _maxlrg ); 262 _live = &live; 263 } 264 // Create the interference graph using virtual copies 265 build_ifg_virtual( ); // Include stack slots this time 266 267 // Aggressive (but pessimistic) copy coalescing. 268 // This pass works on virtual copies. Any virtual copies which are not 269 // coalesced get manifested as actual copies 270 { 271 // The IFG is/was triangular. I am 'squaring it up' so Union can run 272 // faster. Union requires a 'for all' operation which is slow on the 273 // triangular adjacency matrix (quick reminder: the IFG is 'sparse' - 274 // meaning I can visit all the Nodes neighbors less than a Node in time 275 // O(# of neighbors), but I have to visit all the Nodes greater than a 276 // given Node and search them for an instance, i.e., time O(#MaxLRG)). 277 _ifg->SquareUp(); 278 279 PhaseAggressiveCoalesce coalesce( *this ); 280 coalesce.coalesce_driver( ); 281 // Insert un-coalesced copies. Visit all Phis. Where inputs to a Phi do 282 // not match the Phi itself, insert a copy. 283 coalesce.insert_copies(_matcher); 284 } 285 286 // After aggressive coalesce, attempt a first cut at coloring. 287 // To color, we need the IFG and for that we need LIVE. 288 { 289 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) 290 _live = NULL; 291 rm.reset_to_mark(); // Reclaim working storage 292 IndexSet::reset_memory(C, &live_arena); 293 ifg.init(_maxlrg); 294 gather_lrg_masks( true ); 295 live.compute( _maxlrg ); 296 _live = &live; 297 } 298 299 // Build physical interference graph 300 uint must_spill = 0; 301 must_spill = build_ifg_physical( &live_arena ); 302 // If we have a guaranteed spill, might as well spill now 303 if( must_spill ) { 304 if( !_maxlrg ) return; 305 // Bail out if unique gets too large (ie - unique > MaxNodeLimit) 306 C->check_node_count(10*must_spill, "out of nodes before split"); 307 if (C->failing()) return; 308 _maxlrg = Split( _maxlrg ); // Split spilling LRG everywhere 309 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor) 310 // or we failed to split 311 C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after physical split"); 312 if (C->failing()) return; 313 314 NOT_PRODUCT( C->verify_graph_edges(); ) 315 316 compact(); // Compact LRGs; return new lower max lrg 317 318 { 319 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) 320 _live = NULL; 321 rm.reset_to_mark(); // Reclaim working storage 322 IndexSet::reset_memory(C, &live_arena); 323 ifg.init(_maxlrg); // Build a new interference graph 324 gather_lrg_masks( true ); // Collect intersect mask 325 live.compute( _maxlrg ); // Compute LIVE 326 _live = &live; 327 } 328 build_ifg_physical( &live_arena ); 329 _ifg->SquareUp(); 330 _ifg->Compute_Effective_Degree(); 331 // Only do conservative coalescing if requested 332 if( OptoCoalesce ) { 333 // Conservative (and pessimistic) copy coalescing of those spills 334 PhaseConservativeCoalesce coalesce( *this ); 335 // If max live ranges greater than cutoff, don't color the stack. 336 // This cutoff can be larger than below since it is only done once. 337 coalesce.coalesce_driver( ); 338 } 339 compress_uf_map_for_nodes(); 340 341#ifdef ASSERT 342 verify(&live_arena, true); 343#endif 344 } else { 345 ifg.SquareUp(); 346 ifg.Compute_Effective_Degree(); 347#ifdef ASSERT 348 set_was_low(); 349#endif 350 } 351 352 // Prepare for Simplify & Select 353 cache_lrg_info(); // Count degree of LRGs 354 355 // Simplify the InterFerence Graph by removing LRGs of low degree. 356 // LRGs of low degree are trivially colorable. 357 Simplify(); 358 359 // Select colors by re-inserting LRGs back into the IFG in reverse order. 360 // Return whether or not something spills. 361 uint spills = Select( ); 362 363 // If we spill, split and recycle the entire thing 364 while( spills ) { 365 if( _trip_cnt++ > 24 ) { 366 DEBUG_ONLY( dump_for_spill_split_recycle(); ) 367 if( _trip_cnt > 27 ) { 368 C->record_method_not_compilable("failed spill-split-recycle sanity check"); 369 return; 370 } 371 } 372 373 if( !_maxlrg ) return; 374 _maxlrg = Split( _maxlrg ); // Split spilling LRG everywhere 375 // Bail out if unique gets too large (ie - unique > MaxNodeLimit - 2*NodeLimitFudgeFactor) 376 C->check_node_count(2*NodeLimitFudgeFactor, "out of nodes after split"); 377 if (C->failing()) return; 378 379 compact(); // Compact LRGs; return new lower max lrg 380 381 // Nuke the live-ness and interference graph and LiveRanGe info 382 { 383 NOT_PRODUCT( Compile::TracePhase t3("computeLive", &_t_computeLive, TimeCompiler); ) 384 _live = NULL; 385 rm.reset_to_mark(); // Reclaim working storage 386 IndexSet::reset_memory(C, &live_arena); 387 ifg.init(_maxlrg); 388 389 // Create LiveRanGe array. 390 // Intersect register masks for all USEs and DEFs 391 gather_lrg_masks( true ); 392 live.compute( _maxlrg ); 393 _live = &live; 394 } 395 must_spill = build_ifg_physical( &live_arena ); 396 _ifg->SquareUp(); 397 _ifg->Compute_Effective_Degree(); 398 399 // Only do conservative coalescing if requested 400 if( OptoCoalesce ) { 401 // Conservative (and pessimistic) copy coalescing 402 PhaseConservativeCoalesce coalesce( *this ); 403 // Check for few live ranges determines how aggressive coalesce is. 404 coalesce.coalesce_driver( ); 405 } 406 compress_uf_map_for_nodes(); 407#ifdef ASSERT 408 verify(&live_arena, true); 409#endif 410 cache_lrg_info(); // Count degree of LRGs 411 412 // Simplify the InterFerence Graph by removing LRGs of low degree. 413 // LRGs of low degree are trivially colorable. 414 Simplify(); 415 416 // Select colors by re-inserting LRGs back into the IFG in reverse order. 417 // Return whether or not something spills. 418 spills = Select( ); 419 } 420 421 // Count number of Simplify-Select trips per coloring success. 422 _allocator_attempts += _trip_cnt + 1; 423 _allocator_successes += 1; 424 425 // Peephole remove copies 426 post_allocate_copy_removal(); 427 428#ifdef ASSERT 429 // Veify the graph after RA. 430 verify(&live_arena); 431#endif 432 433 // max_reg is past the largest *register* used. 434 // Convert that to a frame_slot number. 435 if( _max_reg <= _matcher._new_SP ) 436 _framesize = C->out_preserve_stack_slots(); 437 else _framesize = _max_reg -_matcher._new_SP; 438 assert((int)(_matcher._new_SP+_framesize) >= (int)_matcher._out_arg_limit, "framesize must be large enough"); 439 440 // This frame must preserve the required fp alignment 441 _framesize = round_to(_framesize, Matcher::stack_alignment_in_slots()); 442 assert( _framesize >= 0 && _framesize <= 1000000, "sanity check" ); 443#ifndef PRODUCT 444 _total_framesize += _framesize; 445 if( (int)_framesize > _max_framesize ) 446 _max_framesize = _framesize; 447#endif 448 449 // Convert CISC spills 450 fixup_spills(); 451 452 // Log regalloc results 453 CompileLog* log = Compile::current()->log(); 454 if (log != NULL) { 455 log->elem("regalloc attempts='%d' success='%d'", _trip_cnt, !C->failing()); 456 } 457 458 if (C->failing()) return; 459 460 NOT_PRODUCT( C->verify_graph_edges(); ) 461 462 // Move important info out of the live_arena to longer lasting storage. 463 alloc_node_regs(_names.Size()); 464 for( uint i=0; i < _names.Size(); i++ ) { 465 if( _names[i] ) { // Live range associated with Node? 466 LRG &lrg = lrgs( _names[i] ); 467 if( lrg.num_regs() == 1 ) { 468 _node_regs[i].set1( lrg.reg() ); 469 } else { // Must be a register-pair 470 if( !lrg._fat_proj ) { // Must be aligned adjacent register pair 471 // Live ranges record the highest register in their mask. 472 // We want the low register for the AD file writer's convenience. 473 _node_regs[i].set2( OptoReg::add(lrg.reg(),-1) ); 474 } else { // Misaligned; extract 2 bits 475 OptoReg::Name hi = lrg.reg(); // Get hi register 476 lrg.Remove(hi); // Yank from mask 477 int lo = lrg.mask().find_first_elem(); // Find lo 478 _node_regs[i].set_pair( hi, lo ); 479 } 480 } 481 if( lrg._is_oop ) _node_oops.set(i); 482 } else { 483 _node_regs[i].set_bad(); 484 } 485 } 486 487 // Done! 488 _live = NULL; 489 _ifg = NULL; 490 C->set_indexSet_arena(NULL); // ResourceArea is at end of scope 491} 492 493//------------------------------de_ssa----------------------------------------- 494void PhaseChaitin::de_ssa() { 495 // Set initial Names for all Nodes. Most Nodes get the virtual register 496 // number. A few get the ZERO live range number. These do not 497 // get allocated, but instead rely on correct scheduling to ensure that 498 // only one instance is simultaneously live at a time. 499 uint lr_counter = 1; 500 for( uint i = 0; i < _cfg._num_blocks; i++ ) { 501 Block *b = _cfg._blocks[i]; 502 uint cnt = b->_nodes.size(); 503 504 // Handle all the normal Nodes in the block 505 for( uint j = 0; j < cnt; j++ ) { 506 Node *n = b->_nodes[j]; 507 // Pre-color to the zero live range, or pick virtual register 508 const RegMask &rm = n->out_RegMask(); 509 _names.map( n->_idx, rm.is_NotEmpty() ? lr_counter++ : 0 ); 510 } 511 } 512 // Reset the Union-Find mapping to be identity 513 reset_uf_map(lr_counter); 514} 515 516 517//------------------------------gather_lrg_masks------------------------------- 518// Gather LiveRanGe information, including register masks. Modification of 519// cisc spillable in_RegMasks should not be done before AggressiveCoalesce. 520void PhaseChaitin::gather_lrg_masks( bool after_aggressive ) { 521 522 // Nail down the frame pointer live range 523 uint fp_lrg = n2lidx(_cfg._root->in(1)->in(TypeFunc::FramePtr)); 524 lrgs(fp_lrg)._cost += 1e12; // Cost is infinite 525 526 // For all blocks 527 for( uint i = 0; i < _cfg._num_blocks; i++ ) { 528 Block *b = _cfg._blocks[i]; 529 530 // For all instructions 531 for( uint j = 1; j < b->_nodes.size(); j++ ) { 532 Node *n = b->_nodes[j]; 533 uint input_edge_start =1; // Skip control most nodes 534 if( n->is_Mach() ) input_edge_start = n->as_Mach()->oper_input_base(); 535 uint idx = n->is_Copy(); 536 537 // Get virtual register number, same as LiveRanGe index 538 uint vreg = n2lidx(n); 539 LRG &lrg = lrgs(vreg); 540 if( vreg ) { // No vreg means un-allocable (e.g. memory) 541 542 // Collect has-copy bit 543 if( idx ) { 544 lrg._has_copy = 1; 545 uint clidx = n2lidx(n->in(idx)); 546 LRG ©_src = lrgs(clidx); 547 copy_src._has_copy = 1; 548 } 549 550 // Check for float-vs-int live range (used in register-pressure 551 // calculations) 552 const Type *n_type = n->bottom_type(); 553 if( n_type->is_floatingpoint() ) 554 lrg._is_float = 1; 555 556 // Check for twice prior spilling. Once prior spilling might have 557 // spilled 'soft', 2nd prior spill should have spilled 'hard' and 558 // further spilling is unlikely to make progress. 559 if( _spilled_once.test(n->_idx) ) { 560 lrg._was_spilled1 = 1; 561 if( _spilled_twice.test(n->_idx) ) 562 lrg._was_spilled2 = 1; 563 } 564 565#ifndef PRODUCT 566 if (trace_spilling() && lrg._def != NULL) { 567 // collect defs for MultiDef printing 568 if (lrg._defs == NULL) { 569 lrg._defs = new (_ifg->_arena) GrowableArray<Node*>(); 570 lrg._defs->append(lrg._def); 571 } 572 lrg._defs->append(n); 573 } 574#endif 575 576 // Check for a single def LRG; these can spill nicely 577 // via rematerialization. Flag as NULL for no def found 578 // yet, or 'n' for single def or -1 for many defs. 579 lrg._def = lrg._def ? NodeSentinel : n; 580 581 // Limit result register mask to acceptable registers 582 const RegMask &rm = n->out_RegMask(); 583 lrg.AND( rm ); 584 // Check for bound register masks 585 const RegMask &lrgmask = lrg.mask(); 586 if( lrgmask.is_bound1() || lrgmask.is_bound2() ) 587 lrg._is_bound = 1; 588 589 // Check for maximum frequency value 590 if( lrg._maxfreq < b->_freq ) 591 lrg._maxfreq = b->_freq; 592 593 int ireg = n->ideal_reg(); 594 assert( !n->bottom_type()->isa_oop_ptr() || ireg == Op_RegP, 595 "oops must be in Op_RegP's" ); 596 // Check for oop-iness, or long/double 597 // Check for multi-kill projection 598 switch( ireg ) { 599 case MachProjNode::fat_proj: 600 // Fat projections have size equal to number of registers killed 601 lrg.set_num_regs(rm.Size()); 602 lrg.set_reg_pressure(lrg.num_regs()); 603 lrg._fat_proj = 1; 604 lrg._is_bound = 1; 605 break; 606 case Op_RegP: 607#ifdef _LP64 608 lrg.set_num_regs(2); // Size is 2 stack words 609#else 610 lrg.set_num_regs(1); // Size is 1 stack word 611#endif 612 // Register pressure is tracked relative to the maximum values 613 // suggested for that platform, INTPRESSURE and FLOATPRESSURE, 614 // and relative to other types which compete for the same regs. 615 // 616 // The following table contains suggested values based on the 617 // architectures as defined in each .ad file. 618 // INTPRESSURE and FLOATPRESSURE may be tuned differently for 619 // compile-speed or performance. 620 // Note1: 621 // SPARC and SPARCV9 reg_pressures are at 2 instead of 1 622 // since .ad registers are defined as high and low halves. 623 // These reg_pressure values remain compatible with the code 624 // in is_high_pressure() which relates get_invalid_mask_size(), 625 // Block::_reg_pressure and INTPRESSURE, FLOATPRESSURE. 626 // Note2: 627 // SPARC -d32 has 24 registers available for integral values, 628 // but only 10 of these are safe for 64-bit longs. 629 // Using set_reg_pressure(2) for both int and long means 630 // the allocator will believe it can fit 26 longs into 631 // registers. Using 2 for longs and 1 for ints means the 632 // allocator will attempt to put 52 integers into registers. 633 // The settings below limit this problem to methods with 634 // many long values which are being run on 32-bit SPARC. 635 // 636 // ------------------- reg_pressure -------------------- 637 // Each entry is reg_pressure_per_value,number_of_regs 638 // RegL RegI RegFlags RegF RegD INTPRESSURE FLOATPRESSURE 639 // IA32 2 1 1 1 1 6 6 640 // IA64 1 1 1 1 1 50 41 641 // SPARC 2 2 2 2 2 48 (24) 52 (26) 642 // SPARCV9 2 2 2 2 2 48 (24) 52 (26) 643 // AMD64 1 1 1 1 1 14 15 644 // ----------------------------------------------------- 645#if defined(SPARC) 646 lrg.set_reg_pressure(2); // use for v9 as well 647#else 648 lrg.set_reg_pressure(1); // normally one value per register 649#endif 650 if( n_type->isa_oop_ptr() ) { 651 lrg._is_oop = 1; 652 } 653 break; 654 case Op_RegL: // Check for long or double 655 case Op_RegD: 656 lrg.set_num_regs(2); 657 // Define platform specific register pressure 658#ifdef SPARC 659 lrg.set_reg_pressure(2); 660#elif defined(IA32) 661 if( ireg == Op_RegL ) { 662 lrg.set_reg_pressure(2); 663 } else { 664 lrg.set_reg_pressure(1); 665 } 666#else 667 lrg.set_reg_pressure(1); // normally one value per register 668#endif 669 // If this def of a double forces a mis-aligned double, 670 // flag as '_fat_proj' - really flag as allowing misalignment 671 // AND changes how we count interferences. A mis-aligned 672 // double can interfere with TWO aligned pairs, or effectively 673 // FOUR registers! 674 if( rm.is_misaligned_Pair() ) { 675 lrg._fat_proj = 1; 676 lrg._is_bound = 1; 677 } 678 break; 679 case Op_RegF: 680 case Op_RegI: 681 case Op_RegN: 682 case Op_RegFlags: 683 case 0: // not an ideal register 684 lrg.set_num_regs(1); 685#ifdef SPARC 686 lrg.set_reg_pressure(2); 687#else 688 lrg.set_reg_pressure(1); 689#endif 690 break; 691 default: 692 ShouldNotReachHere(); 693 } 694 } 695 696 // Now do the same for inputs 697 uint cnt = n->req(); 698 // Setup for CISC SPILLING 699 uint inp = (uint)AdlcVMDeps::Not_cisc_spillable; 700 if( UseCISCSpill && after_aggressive ) { 701 inp = n->cisc_operand(); 702 if( inp != (uint)AdlcVMDeps::Not_cisc_spillable ) 703 // Convert operand number to edge index number 704 inp = n->as_Mach()->operand_index(inp); 705 } 706 // Prepare register mask for each input 707 for( uint k = input_edge_start; k < cnt; k++ ) { 708 uint vreg = n2lidx(n->in(k)); 709 if( !vreg ) continue; 710 711 // If this instruction is CISC Spillable, add the flags 712 // bit to its appropriate input 713 if( UseCISCSpill && after_aggressive && inp == k ) { 714#ifndef PRODUCT 715 if( TraceCISCSpill ) { 716 tty->print(" use_cisc_RegMask: "); 717 n->dump(); 718 } 719#endif 720 n->as_Mach()->use_cisc_RegMask(); 721 } 722 723 LRG &lrg = lrgs(vreg); 724 // // Testing for floating point code shape 725 // Node *test = n->in(k); 726 // if( test->is_Mach() ) { 727 // MachNode *m = test->as_Mach(); 728 // int op = m->ideal_Opcode(); 729 // if (n->is_Call() && (op == Op_AddF || op == Op_MulF) ) { 730 // int zzz = 1; 731 // } 732 // } 733 734 // Limit result register mask to acceptable registers. 735 // Do not limit registers from uncommon uses before 736 // AggressiveCoalesce. This effectively pre-virtual-splits 737 // around uncommon uses of common defs. 738 const RegMask &rm = n->in_RegMask(k); 739 if( !after_aggressive && 740 _cfg._bbs[n->in(k)->_idx]->_freq > 1000*b->_freq ) { 741 // Since we are BEFORE aggressive coalesce, leave the register 742 // mask untrimmed by the call. This encourages more coalescing. 743 // Later, AFTER aggressive, this live range will have to spill 744 // but the spiller handles slow-path calls very nicely. 745 } else { 746 lrg.AND( rm ); 747 } 748 // Check for bound register masks 749 const RegMask &lrgmask = lrg.mask(); 750 if( lrgmask.is_bound1() || lrgmask.is_bound2() ) 751 lrg._is_bound = 1; 752 // If this use of a double forces a mis-aligned double, 753 // flag as '_fat_proj' - really flag as allowing misalignment 754 // AND changes how we count interferences. A mis-aligned 755 // double can interfere with TWO aligned pairs, or effectively 756 // FOUR registers! 757 if( lrg.num_regs() == 2 && !lrg._fat_proj && rm.is_misaligned_Pair() ) { 758 lrg._fat_proj = 1; 759 lrg._is_bound = 1; 760 } 761 // if the LRG is an unaligned pair, we will have to spill 762 // so clear the LRG's register mask if it is not already spilled 763 if ( !n->is_SpillCopy() && 764 (lrg._def == NULL || lrg.is_multidef() || !lrg._def->is_SpillCopy()) && 765 lrgmask.is_misaligned_Pair()) { 766 lrg.Clear(); 767 } 768 769 // Check for maximum frequency value 770 if( lrg._maxfreq < b->_freq ) 771 lrg._maxfreq = b->_freq; 772 773 } // End for all allocated inputs 774 } // end for all instructions 775 } // end for all blocks 776 777 // Final per-liverange setup 778 for( uint i2=0; i2<_maxlrg; i2++ ) { 779 LRG &lrg = lrgs(i2); 780 if( lrg.num_regs() == 2 && !lrg._fat_proj ) 781 lrg.ClearToPairs(); 782 lrg.compute_set_mask_size(); 783 if( lrg.not_free() ) { // Handle case where we lose from the start 784 lrg.set_reg(OptoReg::Name(LRG::SPILL_REG)); 785 lrg._direct_conflict = 1; 786 } 787 lrg.set_degree(0); // no neighbors in IFG yet 788 } 789} 790 791//------------------------------set_was_low------------------------------------ 792// Set the was-lo-degree bit. Conservative coalescing should not change the 793// colorability of the graph. If any live range was of low-degree before 794// coalescing, it should Simplify. This call sets the was-lo-degree bit. 795// The bit is checked in Simplify. 796void PhaseChaitin::set_was_low() { 797#ifdef ASSERT 798 for( uint i = 1; i < _maxlrg; i++ ) { 799 int size = lrgs(i).num_regs(); 800 uint old_was_lo = lrgs(i)._was_lo; 801 lrgs(i)._was_lo = 0; 802 if( lrgs(i).lo_degree() ) { 803 lrgs(i)._was_lo = 1; // Trivially of low degree 804 } else { // Else check the Brigg's assertion 805 // Brigg's observation is that the lo-degree neighbors of a 806 // hi-degree live range will not interfere with the color choices 807 // of said hi-degree live range. The Simplify reverse-stack-coloring 808 // order takes care of the details. Hence you do not have to count 809 // low-degree neighbors when determining if this guy colors. 810 int briggs_degree = 0; 811 IndexSet *s = _ifg->neighbors(i); 812 IndexSetIterator elements(s); 813 uint lidx; 814 while((lidx = elements.next()) != 0) { 815 if( !lrgs(lidx).lo_degree() ) 816 briggs_degree += MAX2(size,lrgs(lidx).num_regs()); 817 } 818 if( briggs_degree < lrgs(i).degrees_of_freedom() ) 819 lrgs(i)._was_lo = 1; // Low degree via the briggs assertion 820 } 821 assert(old_was_lo <= lrgs(i)._was_lo, "_was_lo may not decrease"); 822 } 823#endif 824} 825 826#define REGISTER_CONSTRAINED 16 827 828//------------------------------cache_lrg_info--------------------------------- 829// Compute cost/area ratio, in case we spill. Build the lo-degree list. 830void PhaseChaitin::cache_lrg_info( ) { 831 832 for( uint i = 1; i < _maxlrg; i++ ) { 833 LRG &lrg = lrgs(i); 834 835 // Check for being of low degree: means we can be trivially colored. 836 // Low degree, dead or must-spill guys just get to simplify right away 837 if( lrg.lo_degree() || 838 !lrg.alive() || 839 lrg._must_spill ) { 840 // Split low degree list into those guys that must get a 841 // register and those that can go to register or stack. 842 // The idea is LRGs that can go register or stack color first when 843 // they have a good chance of getting a register. The register-only 844 // lo-degree live ranges always get a register. 845 OptoReg::Name hi_reg = lrg.mask().find_last_elem(); 846 if( OptoReg::is_stack(hi_reg)) { // Can go to stack? 847 lrg._next = _lo_stk_degree; 848 _lo_stk_degree = i; 849 } else { 850 lrg._next = _lo_degree; 851 _lo_degree = i; 852 } 853 } else { // Else high degree 854 lrgs(_hi_degree)._prev = i; 855 lrg._next = _hi_degree; 856 lrg._prev = 0; 857 _hi_degree = i; 858 } 859 } 860} 861 862//------------------------------Pre-Simplify----------------------------------- 863// Simplify the IFG by removing LRGs of low degree that have NO copies 864void PhaseChaitin::Pre_Simplify( ) { 865 866 // Warm up the lo-degree no-copy list 867 int lo_no_copy = 0; 868 for( uint i = 1; i < _maxlrg; i++ ) { 869 if( (lrgs(i).lo_degree() && !lrgs(i)._has_copy) || 870 !lrgs(i).alive() || 871 lrgs(i)._must_spill ) { 872 lrgs(i)._next = lo_no_copy; 873 lo_no_copy = i; 874 } 875 } 876 877 while( lo_no_copy ) { 878 uint lo = lo_no_copy; 879 lo_no_copy = lrgs(lo)._next; 880 int size = lrgs(lo).num_regs(); 881 882 // Put the simplified guy on the simplified list. 883 lrgs(lo)._next = _simplified; 884 _simplified = lo; 885 886 // Yank this guy from the IFG. 887 IndexSet *adj = _ifg->remove_node( lo ); 888 889 // If any neighbors' degrees fall below their number of 890 // allowed registers, then put that neighbor on the low degree 891 // list. Note that 'degree' can only fall and 'numregs' is 892 // unchanged by this action. Thus the two are equal at most once, 893 // so LRGs hit the lo-degree worklists at most once. 894 IndexSetIterator elements(adj); 895 uint neighbor; 896 while ((neighbor = elements.next()) != 0) { 897 LRG *n = &lrgs(neighbor); 898 assert( _ifg->effective_degree(neighbor) == n->degree(), "" ); 899 900 // Check for just becoming of-low-degree 901 if( n->just_lo_degree() && !n->_has_copy ) { 902 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice"); 903 // Put on lo-degree list 904 n->_next = lo_no_copy; 905 lo_no_copy = neighbor; 906 } 907 } 908 } // End of while lo-degree no_copy worklist not empty 909 910 // No more lo-degree no-copy live ranges to simplify 911} 912 913//------------------------------Simplify--------------------------------------- 914// Simplify the IFG by removing LRGs of low degree. 915void PhaseChaitin::Simplify( ) { 916 917 while( 1 ) { // Repeat till simplified it all 918 // May want to explore simplifying lo_degree before _lo_stk_degree. 919 // This might result in more spills coloring into registers during 920 // Select(). 921 while( _lo_degree || _lo_stk_degree ) { 922 // If possible, pull from lo_stk first 923 uint lo; 924 if( _lo_degree ) { 925 lo = _lo_degree; 926 _lo_degree = lrgs(lo)._next; 927 } else { 928 lo = _lo_stk_degree; 929 _lo_stk_degree = lrgs(lo)._next; 930 } 931 932 // Put the simplified guy on the simplified list. 933 lrgs(lo)._next = _simplified; 934 _simplified = lo; 935 // If this guy is "at risk" then mark his current neighbors 936 if( lrgs(lo)._at_risk ) { 937 IndexSetIterator elements(_ifg->neighbors(lo)); 938 uint datum; 939 while ((datum = elements.next()) != 0) { 940 lrgs(datum)._risk_bias = lo; 941 } 942 } 943 944 // Yank this guy from the IFG. 945 IndexSet *adj = _ifg->remove_node( lo ); 946 947 // If any neighbors' degrees fall below their number of 948 // allowed registers, then put that neighbor on the low degree 949 // list. Note that 'degree' can only fall and 'numregs' is 950 // unchanged by this action. Thus the two are equal at most once, 951 // so LRGs hit the lo-degree worklist at most once. 952 IndexSetIterator elements(adj); 953 uint neighbor; 954 while ((neighbor = elements.next()) != 0) { 955 LRG *n = &lrgs(neighbor); 956#ifdef ASSERT 957 if( VerifyOpto || VerifyRegisterAllocator ) { 958 assert( _ifg->effective_degree(neighbor) == n->degree(), "" ); 959 } 960#endif 961 962 // Check for just becoming of-low-degree just counting registers. 963 // _must_spill live ranges are already on the low degree list. 964 if( n->just_lo_degree() && !n->_must_spill ) { 965 assert(!(*_ifg->_yanked)[neighbor],"Cannot move to lo degree twice"); 966 // Pull from hi-degree list 967 uint prev = n->_prev; 968 uint next = n->_next; 969 if( prev ) lrgs(prev)._next = next; 970 else _hi_degree = next; 971 lrgs(next)._prev = prev; 972 n->_next = _lo_degree; 973 _lo_degree = neighbor; 974 } 975 } 976 } // End of while lo-degree/lo_stk_degree worklist not empty 977 978 // Check for got everything: is hi-degree list empty? 979 if( !_hi_degree ) break; 980 981 // Time to pick a potential spill guy 982 uint lo_score = _hi_degree; 983 double score = lrgs(lo_score).score(); 984 double area = lrgs(lo_score)._area; 985 986 // Find cheapest guy 987 debug_only( int lo_no_simplify=0; ); 988 for( uint i = _hi_degree; i; i = lrgs(i)._next ) { 989 assert( !(*_ifg->_yanked)[i], "" ); 990 // It's just vaguely possible to move hi-degree to lo-degree without 991 // going through a just-lo-degree stage: If you remove a double from 992 // a float live range it's degree will drop by 2 and you can skip the 993 // just-lo-degree stage. It's very rare (shows up after 5000+ methods 994 // in -Xcomp of Java2Demo). So just choose this guy to simplify next. 995 if( lrgs(i).lo_degree() ) { 996 lo_score = i; 997 break; 998 } 999 debug_only( if( lrgs(i)._was_lo ) lo_no_simplify=i; ); 1000 double iscore = lrgs(i).score(); 1001 double iarea = lrgs(i)._area; 1002 1003 // Compare cost/area of i vs cost/area of lo_score. Smaller cost/area 1004 // wins. Ties happen because all live ranges in question have spilled 1005 // a few times before and the spill-score adds a huge number which 1006 // washes out the low order bits. We are choosing the lesser of 2 1007 // evils; in this case pick largest area to spill. 1008 if( iscore < score || 1009 (iscore == score && iarea > area && lrgs(lo_score)._was_spilled2) ) { 1010 lo_score = i; 1011 score = iscore; 1012 area = iarea; 1013 } 1014 } 1015 LRG *lo_lrg = &lrgs(lo_score); 1016 // The live range we choose for spilling is either hi-degree, or very 1017 // rarely it can be low-degree. If we choose a hi-degree live range 1018 // there better not be any lo-degree choices. 1019 assert( lo_lrg->lo_degree() || !lo_no_simplify, "Live range was lo-degree before coalesce; should simplify" ); 1020 1021 // Pull from hi-degree list 1022 uint prev = lo_lrg->_prev; 1023 uint next = lo_lrg->_next; 1024 if( prev ) lrgs(prev)._next = next; 1025 else _hi_degree = next; 1026 lrgs(next)._prev = prev; 1027 // Jam him on the lo-degree list, despite his high degree. 1028 // Maybe he'll get a color, and maybe he'll spill. 1029 // Only Select() will know. 1030 lrgs(lo_score)._at_risk = true; 1031 _lo_degree = lo_score; 1032 lo_lrg->_next = 0; 1033 1034 } // End of while not simplified everything 1035 1036} 1037 1038//------------------------------bias_color------------------------------------- 1039// Choose a color using the biasing heuristic 1040OptoReg::Name PhaseChaitin::bias_color( LRG &lrg, int chunk ) { 1041 1042 // Check for "at_risk" LRG's 1043 uint risk_lrg = Find(lrg._risk_bias); 1044 if( risk_lrg != 0 ) { 1045 // Walk the colored neighbors of the "at_risk" candidate 1046 // Choose a color which is both legal and already taken by a neighbor 1047 // of the "at_risk" candidate in order to improve the chances of the 1048 // "at_risk" candidate of coloring 1049 IndexSetIterator elements(_ifg->neighbors(risk_lrg)); 1050 uint datum; 1051 while ((datum = elements.next()) != 0) { 1052 OptoReg::Name reg = lrgs(datum).reg(); 1053 // If this LRG's register is legal for us, choose it 1054 if( reg >= chunk && reg < chunk + RegMask::CHUNK_SIZE && 1055 lrg.mask().Member(OptoReg::add(reg,-chunk)) && 1056 (lrg.num_regs()==1 || // either size 1 1057 (reg&1) == 1) ) // or aligned (adjacent reg is available since we already cleared-to-pairs) 1058 return reg; 1059 } 1060 } 1061 1062 uint copy_lrg = Find(lrg._copy_bias); 1063 if( copy_lrg != 0 ) { 1064 // If he has a color, 1065 if( !(*(_ifg->_yanked))[copy_lrg] ) { 1066 OptoReg::Name reg = lrgs(copy_lrg).reg(); 1067 // And it is legal for you, 1068 if( reg >= chunk && reg < chunk + RegMask::CHUNK_SIZE && 1069 lrg.mask().Member(OptoReg::add(reg,-chunk)) && 1070 (lrg.num_regs()==1 || // either size 1 1071 (reg&1) == 1) ) // or aligned (adjacent reg is available since we already cleared-to-pairs) 1072 return reg; 1073 } else if( chunk == 0 ) { 1074 // Choose a color which is legal for him 1075 RegMask tempmask = lrg.mask(); 1076 tempmask.AND(lrgs(copy_lrg).mask()); 1077 OptoReg::Name reg; 1078 if( lrg.num_regs() == 1 ) { 1079 reg = tempmask.find_first_elem(); 1080 } else { 1081 tempmask.ClearToPairs(); 1082 reg = tempmask.find_first_pair(); 1083 } 1084 if( OptoReg::is_valid(reg) ) 1085 return reg; 1086 } 1087 } 1088 1089 // If no bias info exists, just go with the register selection ordering 1090 if( lrg.num_regs() == 2 ) { 1091 // Find an aligned pair 1092 return OptoReg::add(lrg.mask().find_first_pair(),chunk); 1093 } 1094 1095 // CNC - Fun hack. Alternate 1st and 2nd selection. Enables post-allocate 1096 // copy removal to remove many more copies, by preventing a just-assigned 1097 // register from being repeatedly assigned. 1098 OptoReg::Name reg = lrg.mask().find_first_elem(); 1099 if( (++_alternate & 1) && OptoReg::is_valid(reg) ) { 1100 // This 'Remove; find; Insert' idiom is an expensive way to find the 1101 // SECOND element in the mask. 1102 lrg.Remove(reg); 1103 OptoReg::Name reg2 = lrg.mask().find_first_elem(); 1104 lrg.Insert(reg); 1105 if( OptoReg::is_reg(reg2)) 1106 reg = reg2; 1107 } 1108 return OptoReg::add( reg, chunk ); 1109} 1110 1111//------------------------------choose_color----------------------------------- 1112// Choose a color in the current chunk 1113OptoReg::Name PhaseChaitin::choose_color( LRG &lrg, int chunk ) { 1114 assert( C->in_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP-1)), "must not allocate stack0 (inside preserve area)"); 1115 assert(C->out_preserve_stack_slots() == 0 || chunk != 0 || lrg._is_bound || lrg.mask().is_bound1() || !lrg.mask().Member(OptoReg::Name(_matcher._old_SP+0)), "must not allocate stack0 (inside preserve area)"); 1116 1117 if( lrg.num_regs() == 1 || // Common Case 1118 !lrg._fat_proj ) // Aligned+adjacent pairs ok 1119 // Use a heuristic to "bias" the color choice 1120 return bias_color(lrg, chunk); 1121 1122 assert( lrg.num_regs() >= 2, "dead live ranges do not color" ); 1123 1124 // Fat-proj case or misaligned double argument. 1125 assert(lrg.compute_mask_size() == lrg.num_regs() || 1126 lrg.num_regs() == 2,"fat projs exactly color" ); 1127 assert( !chunk, "always color in 1st chunk" ); 1128 // Return the highest element in the set. 1129 return lrg.mask().find_last_elem(); 1130} 1131 1132//------------------------------Select----------------------------------------- 1133// Select colors by re-inserting LRGs back into the IFG. LRGs are re-inserted 1134// in reverse order of removal. As long as nothing of hi-degree was yanked, 1135// everything going back is guaranteed a color. Select that color. If some 1136// hi-degree LRG cannot get a color then we record that we must spill. 1137uint PhaseChaitin::Select( ) { 1138 uint spill_reg = LRG::SPILL_REG; 1139 _max_reg = OptoReg::Name(0); // Past max register used 1140 while( _simplified ) { 1141 // Pull next LRG from the simplified list - in reverse order of removal 1142 uint lidx = _simplified; 1143 LRG *lrg = &lrgs(lidx); 1144 _simplified = lrg->_next; 1145 1146 1147#ifndef PRODUCT 1148 if (trace_spilling()) { 1149 ttyLocker ttyl; 1150 tty->print_cr("L%d selecting degree %d degrees_of_freedom %d", lidx, lrg->degree(), 1151 lrg->degrees_of_freedom()); 1152 lrg->dump(); 1153 } 1154#endif 1155 1156 // Re-insert into the IFG 1157 _ifg->re_insert(lidx); 1158 if( !lrg->alive() ) continue; 1159 // capture allstackedness flag before mask is hacked 1160 const int is_allstack = lrg->mask().is_AllStack(); 1161 1162 // Yeah, yeah, yeah, I know, I know. I can refactor this 1163 // to avoid the GOTO, although the refactored code will not 1164 // be much clearer. We arrive here IFF we have a stack-based 1165 // live range that cannot color in the current chunk, and it 1166 // has to move into the next free stack chunk. 1167 int chunk = 0; // Current chunk is first chunk 1168 retry_next_chunk: 1169 1170 // Remove neighbor colors 1171 IndexSet *s = _ifg->neighbors(lidx); 1172 1173 debug_only(RegMask orig_mask = lrg->mask();) 1174 IndexSetIterator elements(s); 1175 uint neighbor; 1176 while ((neighbor = elements.next()) != 0) { 1177 // Note that neighbor might be a spill_reg. In this case, exclusion 1178 // of its color will be a no-op, since the spill_reg chunk is in outer 1179 // space. Also, if neighbor is in a different chunk, this exclusion 1180 // will be a no-op. (Later on, if lrg runs out of possible colors in 1181 // its chunk, a new chunk of color may be tried, in which case 1182 // examination of neighbors is started again, at retry_next_chunk.) 1183 LRG &nlrg = lrgs(neighbor); 1184 OptoReg::Name nreg = nlrg.reg(); 1185 // Only subtract masks in the same chunk 1186 if( nreg >= chunk && nreg < chunk + RegMask::CHUNK_SIZE ) { 1187#ifndef PRODUCT 1188 uint size = lrg->mask().Size(); 1189 RegMask rm = lrg->mask(); 1190#endif 1191 lrg->SUBTRACT(nlrg.mask()); 1192#ifndef PRODUCT 1193 if (trace_spilling() && lrg->mask().Size() != size) { 1194 ttyLocker ttyl; 1195 tty->print("L%d ", lidx); 1196 rm.dump(); 1197 tty->print(" intersected L%d ", neighbor); 1198 nlrg.mask().dump(); 1199 tty->print(" removed "); 1200 rm.SUBTRACT(lrg->mask()); 1201 rm.dump(); 1202 tty->print(" leaving "); 1203 lrg->mask().dump(); 1204 tty->cr(); 1205 } 1206#endif 1207 } 1208 } 1209 //assert(is_allstack == lrg->mask().is_AllStack(), "nbrs must not change AllStackedness"); 1210 // Aligned pairs need aligned masks 1211 if( lrg->num_regs() == 2 && !lrg->_fat_proj ) 1212 lrg->ClearToPairs(); 1213 1214 // Check if a color is available and if so pick the color 1215 OptoReg::Name reg = choose_color( *lrg, chunk ); 1216#ifdef SPARC 1217 debug_only(lrg->compute_set_mask_size()); 1218 assert(lrg->num_regs() != 2 || lrg->is_bound() || is_even(reg-1), "allocate all doubles aligned"); 1219#endif 1220 1221 //--------------- 1222 // If we fail to color and the AllStack flag is set, trigger 1223 // a chunk-rollover event 1224 if(!OptoReg::is_valid(OptoReg::add(reg,-chunk)) && is_allstack) { 1225 // Bump register mask up to next stack chunk 1226 chunk += RegMask::CHUNK_SIZE; 1227 lrg->Set_All(); 1228 1229 goto retry_next_chunk; 1230 } 1231 1232 //--------------- 1233 // Did we get a color? 1234 else if( OptoReg::is_valid(reg)) { 1235#ifndef PRODUCT 1236 RegMask avail_rm = lrg->mask(); 1237#endif 1238 1239 // Record selected register 1240 lrg->set_reg(reg); 1241 1242 if( reg >= _max_reg ) // Compute max register limit 1243 _max_reg = OptoReg::add(reg,1); 1244 // Fold reg back into normal space 1245 reg = OptoReg::add(reg,-chunk); 1246 1247 // If the live range is not bound, then we actually had some choices 1248 // to make. In this case, the mask has more bits in it than the colors 1249 // choosen. Restrict the mask to just what was picked. 1250 if( lrg->num_regs() == 1 ) { // Size 1 live range 1251 lrg->Clear(); // Clear the mask 1252 lrg->Insert(reg); // Set regmask to match selected reg 1253 lrg->set_mask_size(1); 1254 } else if( !lrg->_fat_proj ) { 1255 // For pairs, also insert the low bit of the pair 1256 assert( lrg->num_regs() == 2, "unbound fatproj???" ); 1257 lrg->Clear(); // Clear the mask 1258 lrg->Insert(reg); // Set regmask to match selected reg 1259 lrg->Insert(OptoReg::add(reg,-1)); 1260 lrg->set_mask_size(2); 1261 } else { // Else fatproj 1262 // mask must be equal to fatproj bits, by definition 1263 } 1264#ifndef PRODUCT 1265 if (trace_spilling()) { 1266 ttyLocker ttyl; 1267 tty->print("L%d selected ", lidx); 1268 lrg->mask().dump(); 1269 tty->print(" from "); 1270 avail_rm.dump(); 1271 tty->cr(); 1272 } 1273#endif 1274 // Note that reg is the highest-numbered register in the newly-bound mask. 1275 } // end color available case 1276 1277 //--------------- 1278 // Live range is live and no colors available 1279 else { 1280 assert( lrg->alive(), "" ); 1281 assert( !lrg->_fat_proj || lrg->is_multidef() || 1282 lrg->_def->outcnt() > 0, "fat_proj cannot spill"); 1283 assert( !orig_mask.is_AllStack(), "All Stack does not spill" ); 1284 1285 // Assign the special spillreg register 1286 lrg->set_reg(OptoReg::Name(spill_reg++)); 1287 // Do not empty the regmask; leave mask_size lying around 1288 // for use during Spilling 1289#ifndef PRODUCT 1290 if( trace_spilling() ) { 1291 ttyLocker ttyl; 1292 tty->print("L%d spilling with neighbors: ", lidx); 1293 s->dump(); 1294 debug_only(tty->print(" original mask: ")); 1295 debug_only(orig_mask.dump()); 1296 dump_lrg(lidx); 1297 } 1298#endif 1299 } // end spill case 1300 1301 } 1302 1303 return spill_reg-LRG::SPILL_REG; // Return number of spills 1304} 1305 1306 1307//------------------------------copy_was_spilled------------------------------- 1308// Copy 'was_spilled'-edness from the source Node to the dst Node. 1309void PhaseChaitin::copy_was_spilled( Node *src, Node *dst ) { 1310 if( _spilled_once.test(src->_idx) ) { 1311 _spilled_once.set(dst->_idx); 1312 lrgs(Find(dst))._was_spilled1 = 1; 1313 if( _spilled_twice.test(src->_idx) ) { 1314 _spilled_twice.set(dst->_idx); 1315 lrgs(Find(dst))._was_spilled2 = 1; 1316 } 1317 } 1318} 1319 1320//------------------------------set_was_spilled-------------------------------- 1321// Set the 'spilled_once' or 'spilled_twice' flag on a node. 1322void PhaseChaitin::set_was_spilled( Node *n ) { 1323 if( _spilled_once.test_set(n->_idx) ) 1324 _spilled_twice.set(n->_idx); 1325} 1326 1327//------------------------------fixup_spills----------------------------------- 1328// Convert Ideal spill instructions into proper FramePtr + offset Loads and 1329// Stores. Use-def chains are NOT preserved, but Node->LRG->reg maps are. 1330void PhaseChaitin::fixup_spills() { 1331 // This function does only cisc spill work. 1332 if( !UseCISCSpill ) return; 1333 1334 NOT_PRODUCT( Compile::TracePhase t3("fixupSpills", &_t_fixupSpills, TimeCompiler); ) 1335 1336 // Grab the Frame Pointer 1337 Node *fp = _cfg._broot->head()->in(1)->in(TypeFunc::FramePtr); 1338 1339 // For all blocks 1340 for( uint i = 0; i < _cfg._num_blocks; i++ ) { 1341 Block *b = _cfg._blocks[i]; 1342 1343 // For all instructions in block 1344 uint last_inst = b->end_idx(); 1345 for( uint j = 1; j <= last_inst; j++ ) { 1346 Node *n = b->_nodes[j]; 1347 1348 // Dead instruction??? 1349 assert( n->outcnt() != 0 ||// Nothing dead after post alloc 1350 C->top() == n || // Or the random TOP node 1351 n->is_Proj(), // Or a fat-proj kill node 1352 "No dead instructions after post-alloc" ); 1353 1354 int inp = n->cisc_operand(); 1355 if( inp != AdlcVMDeps::Not_cisc_spillable ) { 1356 // Convert operand number to edge index number 1357 MachNode *mach = n->as_Mach(); 1358 inp = mach->operand_index(inp); 1359 Node *src = n->in(inp); // Value to load or store 1360 LRG &lrg_cisc = lrgs( Find_const(src) ); 1361 OptoReg::Name src_reg = lrg_cisc.reg(); 1362 // Doubles record the HIGH register of an adjacent pair. 1363 src_reg = OptoReg::add(src_reg,1-lrg_cisc.num_regs()); 1364 if( OptoReg::is_stack(src_reg) ) { // If input is on stack 1365 // This is a CISC Spill, get stack offset and construct new node 1366#ifndef PRODUCT 1367 if( TraceCISCSpill ) { 1368 tty->print(" reg-instr: "); 1369 n->dump(); 1370 } 1371#endif 1372 int stk_offset = reg2offset(src_reg); 1373 // Bailout if we might exceed node limit when spilling this instruction 1374 C->check_node_count(0, "out of nodes fixing spills"); 1375 if (C->failing()) return; 1376 // Transform node 1377 MachNode *cisc = mach->cisc_version(stk_offset, C)->as_Mach(); 1378 cisc->set_req(inp,fp); // Base register is frame pointer 1379 if( cisc->oper_input_base() > 1 && mach->oper_input_base() <= 1 ) { 1380 assert( cisc->oper_input_base() == 2, "Only adding one edge"); 1381 cisc->ins_req(1,src); // Requires a memory edge 1382 } 1383 b->_nodes.map(j,cisc); // Insert into basic block 1384 n->subsume_by(cisc); // Correct graph 1385 // 1386 ++_used_cisc_instructions; 1387#ifndef PRODUCT 1388 if( TraceCISCSpill ) { 1389 tty->print(" cisc-instr: "); 1390 cisc->dump(); 1391 } 1392#endif 1393 } else { 1394#ifndef PRODUCT 1395 if( TraceCISCSpill ) { 1396 tty->print(" using reg-instr: "); 1397 n->dump(); 1398 } 1399#endif 1400 ++_unused_cisc_instructions; // input can be on stack 1401 } 1402 } 1403 1404 } // End of for all instructions 1405 1406 } // End of for all blocks 1407} 1408 1409//------------------------------find_base_for_derived-------------------------- 1410// Helper to stretch above; recursively discover the base Node for a 1411// given derived Node. Easy for AddP-related machine nodes, but needs 1412// to be recursive for derived Phis. 1413Node *PhaseChaitin::find_base_for_derived( Node **derived_base_map, Node *derived, uint &maxlrg ) { 1414 // See if already computed; if so return it 1415 if( derived_base_map[derived->_idx] ) 1416 return derived_base_map[derived->_idx]; 1417 1418 // See if this happens to be a base. 1419 // NOTE: we use TypePtr instead of TypeOopPtr because we can have 1420 // pointers derived from NULL! These are always along paths that 1421 // can't happen at run-time but the optimizer cannot deduce it so 1422 // we have to handle it gracefully. 1423 const TypePtr *tj = derived->bottom_type()->isa_ptr(); 1424 // If its an OOP with a non-zero offset, then it is derived. 1425 if( tj->_offset == 0 ) { 1426 derived_base_map[derived->_idx] = derived; 1427 return derived; 1428 } 1429 // Derived is NULL+offset? Base is NULL! 1430 if( derived->is_Con() ) { 1431 Node *base = new (C, 1) ConPNode( TypePtr::NULL_PTR ); 1432 uint no_lidx = 0; // an unmatched constant in debug info has no LRG 1433 _names.extend(base->_idx, no_lidx); 1434 derived_base_map[derived->_idx] = base; 1435 return base; 1436 } 1437 1438 // Check for AddP-related opcodes 1439 if( !derived->is_Phi() ) { 1440 assert( derived->as_Mach()->ideal_Opcode() == Op_AddP, "" ); 1441 Node *base = derived->in(AddPNode::Base); 1442 derived_base_map[derived->_idx] = base; 1443 return base; 1444 } 1445 1446 // Recursively find bases for Phis. 1447 // First check to see if we can avoid a base Phi here. 1448 Node *base = find_base_for_derived( derived_base_map, derived->in(1),maxlrg); 1449 uint i; 1450 for( i = 2; i < derived->req(); i++ ) 1451 if( base != find_base_for_derived( derived_base_map,derived->in(i),maxlrg)) 1452 break; 1453 // Went to the end without finding any different bases? 1454 if( i == derived->req() ) { // No need for a base Phi here 1455 derived_base_map[derived->_idx] = base; 1456 return base; 1457 } 1458 1459 // Now we see we need a base-Phi here to merge the bases 1460 base = new (C, derived->req()) PhiNode( derived->in(0), base->bottom_type() ); 1461 for( i = 1; i < derived->req(); i++ ) 1462 base->init_req(i, find_base_for_derived(derived_base_map, derived->in(i), maxlrg)); 1463 1464 // Search the current block for an existing base-Phi 1465 Block *b = _cfg._bbs[derived->_idx]; 1466 for( i = 1; i <= b->end_idx(); i++ ) {// Search for matching Phi 1467 Node *phi = b->_nodes[i]; 1468 if( !phi->is_Phi() ) { // Found end of Phis with no match? 1469 b->_nodes.insert( i, base ); // Must insert created Phi here as base 1470 _cfg._bbs.map( base->_idx, b ); 1471 new_lrg(base,maxlrg++); 1472 break; 1473 } 1474 // See if Phi matches. 1475 uint j; 1476 for( j = 1; j < base->req(); j++ ) 1477 if( phi->in(j) != base->in(j) && 1478 !(phi->in(j)->is_Con() && base->in(j)->is_Con()) ) // allow different NULLs 1479 break; 1480 if( j == base->req() ) { // All inputs match? 1481 base = phi; // Then use existing 'phi' and drop 'base' 1482 break; 1483 } 1484 } 1485 1486 1487 // Cache info for later passes 1488 derived_base_map[derived->_idx] = base; 1489 return base; 1490} 1491 1492 1493//------------------------------stretch_base_pointer_live_ranges--------------- 1494// At each Safepoint, insert extra debug edges for each pair of derived value/ 1495// base pointer that is live across the Safepoint for oopmap building. The 1496// edge pairs get added in after sfpt->jvmtail()->oopoff(), but are in the 1497// required edge set. 1498bool PhaseChaitin::stretch_base_pointer_live_ranges( ResourceArea *a ) { 1499 int must_recompute_live = false; 1500 uint maxlrg = _maxlrg; 1501 Node **derived_base_map = (Node**)a->Amalloc(sizeof(Node*)*C->unique()); 1502 memset( derived_base_map, 0, sizeof(Node*)*C->unique() ); 1503 1504 // For all blocks in RPO do... 1505 for( uint i=0; i<_cfg._num_blocks; i++ ) { 1506 Block *b = _cfg._blocks[i]; 1507 // Note use of deep-copy constructor. I cannot hammer the original 1508 // liveout bits, because they are needed by the following coalesce pass. 1509 IndexSet liveout(_live->live(b)); 1510 1511 for( uint j = b->end_idx() + 1; j > 1; j-- ) { 1512 Node *n = b->_nodes[j-1]; 1513 1514 // Pre-split compares of loop-phis. Loop-phis form a cycle we would 1515 // like to see in the same register. Compare uses the loop-phi and so 1516 // extends its live range BUT cannot be part of the cycle. If this 1517 // extended live range overlaps with the update of the loop-phi value 1518 // we need both alive at the same time -- which requires at least 1 1519 // copy. But because Intel has only 2-address registers we end up with 1520 // at least 2 copies, one before the loop-phi update instruction and 1521 // one after. Instead we split the input to the compare just after the 1522 // phi. 1523 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_CmpI ) { 1524 Node *phi = n->in(1); 1525 if( phi->is_Phi() && phi->as_Phi()->region()->is_Loop() ) { 1526 Block *phi_block = _cfg._bbs[phi->_idx]; 1527 if( _cfg._bbs[phi_block->pred(2)->_idx] == b ) { 1528 const RegMask *mask = C->matcher()->idealreg2spillmask[Op_RegI]; 1529 Node *spill = new (C) MachSpillCopyNode( phi, *mask, *mask ); 1530 insert_proj( phi_block, 1, spill, maxlrg++ ); 1531 n->set_req(1,spill); 1532 must_recompute_live = true; 1533 } 1534 } 1535 } 1536 1537 // Get value being defined 1538 uint lidx = n2lidx(n); 1539 if( lidx && lidx < _maxlrg /* Ignore the occasional brand-new live range */) { 1540 // Remove from live-out set 1541 liveout.remove(lidx); 1542 1543 // Copies do not define a new value and so do not interfere. 1544 // Remove the copies source from the liveout set before interfering. 1545 uint idx = n->is_Copy(); 1546 if( idx ) liveout.remove( n2lidx(n->in(idx)) ); 1547 } 1548 1549 // Found a safepoint? 1550 JVMState *jvms = n->jvms(); 1551 if( jvms ) { 1552 // Now scan for a live derived pointer 1553 IndexSetIterator elements(&liveout); 1554 uint neighbor; 1555 while ((neighbor = elements.next()) != 0) { 1556 // Find reaching DEF for base and derived values 1557 // This works because we are still in SSA during this call. 1558 Node *derived = lrgs(neighbor)._def; 1559 const TypePtr *tj = derived->bottom_type()->isa_ptr(); 1560 // If its an OOP with a non-zero offset, then it is derived. 1561 if( tj && tj->_offset != 0 && tj->isa_oop_ptr() ) { 1562 Node *base = find_base_for_derived( derived_base_map, derived, maxlrg ); 1563 assert( base->_idx < _names.Size(), "" ); 1564 // Add reaching DEFs of derived pointer and base pointer as a 1565 // pair of inputs 1566 n->add_req( derived ); 1567 n->add_req( base ); 1568 1569 // See if the base pointer is already live to this point. 1570 // Since I'm working on the SSA form, live-ness amounts to 1571 // reaching def's. So if I find the base's live range then 1572 // I know the base's def reaches here. 1573 if( (n2lidx(base) >= _maxlrg ||// (Brand new base (hence not live) or 1574 !liveout.member( n2lidx(base) ) ) && // not live) AND 1575 (n2lidx(base) > 0) && // not a constant 1576 _cfg._bbs[base->_idx] != b ) { // base not def'd in blk) 1577 // Base pointer is not currently live. Since I stretched 1578 // the base pointer to here and it crosses basic-block 1579 // boundaries, the global live info is now incorrect. 1580 // Recompute live. 1581 must_recompute_live = true; 1582 } // End of if base pointer is not live to debug info 1583 } 1584 } // End of scan all live data for derived ptrs crossing GC point 1585 } // End of if found a GC point 1586 1587 // Make all inputs live 1588 if( !n->is_Phi() ) { // Phi function uses come from prior block 1589 for( uint k = 1; k < n->req(); k++ ) { 1590 uint lidx = n2lidx(n->in(k)); 1591 if( lidx < _maxlrg ) 1592 liveout.insert( lidx ); 1593 } 1594 } 1595 1596 } // End of forall instructions in block 1597 liveout.clear(); // Free the memory used by liveout. 1598 1599 } // End of forall blocks 1600 _maxlrg = maxlrg; 1601 1602 // If I created a new live range I need to recompute live 1603 if( maxlrg != _ifg->_maxlrg ) 1604 must_recompute_live = true; 1605 1606 return must_recompute_live != 0; 1607} 1608 1609 1610//------------------------------add_reference---------------------------------- 1611// Extend the node to LRG mapping 1612void PhaseChaitin::add_reference( const Node *node, const Node *old_node ) { 1613 _names.extend( node->_idx, n2lidx(old_node) ); 1614} 1615 1616//------------------------------dump------------------------------------------- 1617#ifndef PRODUCT 1618void PhaseChaitin::dump( const Node *n ) const { 1619 uint r = (n->_idx < _names.Size() ) ? Find_const(n) : 0; 1620 tty->print("L%d",r); 1621 if( r && n->Opcode() != Op_Phi ) { 1622 if( _node_regs ) { // Got a post-allocation copy of allocation? 1623 tty->print("["); 1624 OptoReg::Name second = get_reg_second(n); 1625 if( OptoReg::is_valid(second) ) { 1626 if( OptoReg::is_reg(second) ) 1627 tty->print("%s:",Matcher::regName[second]); 1628 else 1629 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(second)); 1630 } 1631 OptoReg::Name first = get_reg_first(n); 1632 if( OptoReg::is_reg(first) ) 1633 tty->print("%s]",Matcher::regName[first]); 1634 else 1635 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), reg2offset_unchecked(first)); 1636 } else 1637 n->out_RegMask().dump(); 1638 } 1639 tty->print("/N%d\t",n->_idx); 1640 tty->print("%s === ", n->Name()); 1641 uint k; 1642 for( k = 0; k < n->req(); k++) { 1643 Node *m = n->in(k); 1644 if( !m ) tty->print("_ "); 1645 else { 1646 uint r = (m->_idx < _names.Size() ) ? Find_const(m) : 0; 1647 tty->print("L%d",r); 1648 // Data MultiNode's can have projections with no real registers. 1649 // Don't die while dumping them. 1650 int op = n->Opcode(); 1651 if( r && op != Op_Phi && op != Op_Proj && op != Op_SCMemProj) { 1652 if( _node_regs ) { 1653 tty->print("["); 1654 OptoReg::Name second = get_reg_second(n->in(k)); 1655 if( OptoReg::is_valid(second) ) { 1656 if( OptoReg::is_reg(second) ) 1657 tty->print("%s:",Matcher::regName[second]); 1658 else 1659 tty->print("%s+%d:",OptoReg::regname(OptoReg::c_frame_pointer), 1660 reg2offset_unchecked(second)); 1661 } 1662 OptoReg::Name first = get_reg_first(n->in(k)); 1663 if( OptoReg::is_reg(first) ) 1664 tty->print("%s]",Matcher::regName[first]); 1665 else 1666 tty->print("%s+%d]",OptoReg::regname(OptoReg::c_frame_pointer), 1667 reg2offset_unchecked(first)); 1668 } else 1669 n->in_RegMask(k).dump(); 1670 } 1671 tty->print("/N%d ",m->_idx); 1672 } 1673 } 1674 if( k < n->len() && n->in(k) ) tty->print("| "); 1675 for( ; k < n->len(); k++ ) { 1676 Node *m = n->in(k); 1677 if( !m ) break; 1678 uint r = (m->_idx < _names.Size() ) ? Find_const(m) : 0; 1679 tty->print("L%d",r); 1680 tty->print("/N%d ",m->_idx); 1681 } 1682 if( n->is_Mach() ) n->as_Mach()->dump_spec(tty); 1683 else n->dump_spec(tty); 1684 if( _spilled_once.test(n->_idx ) ) { 1685 tty->print(" Spill_1"); 1686 if( _spilled_twice.test(n->_idx ) ) 1687 tty->print(" Spill_2"); 1688 } 1689 tty->print("\n"); 1690} 1691 1692void PhaseChaitin::dump( const Block * b ) const { 1693 b->dump_head( &_cfg._bbs ); 1694 1695 // For all instructions 1696 for( uint j = 0; j < b->_nodes.size(); j++ ) 1697 dump(b->_nodes[j]); 1698 // Print live-out info at end of block 1699 if( _live ) { 1700 tty->print("Liveout: "); 1701 IndexSet *live = _live->live(b); 1702 IndexSetIterator elements(live); 1703 tty->print("{"); 1704 uint i; 1705 while ((i = elements.next()) != 0) { 1706 tty->print("L%d ", Find_const(i)); 1707 } 1708 tty->print_cr("}"); 1709 } 1710 tty->print("\n"); 1711} 1712 1713void PhaseChaitin::dump() const { 1714 tty->print( "--- Chaitin -- argsize: %d framesize: %d ---\n", 1715 _matcher._new_SP, _framesize ); 1716 1717 // For all blocks 1718 for( uint i = 0; i < _cfg._num_blocks; i++ ) 1719 dump(_cfg._blocks[i]); 1720 // End of per-block dump 1721 tty->print("\n"); 1722 1723 if (!_ifg) { 1724 tty->print("(No IFG.)\n"); 1725 return; 1726 } 1727 1728 // Dump LRG array 1729 tty->print("--- Live RanGe Array ---\n"); 1730 for(uint i2 = 1; i2 < _maxlrg; i2++ ) { 1731 tty->print("L%d: ",i2); 1732 if( i2 < _ifg->_maxlrg ) lrgs(i2).dump( ); 1733 else tty->print("new LRG"); 1734 } 1735 tty->print_cr(""); 1736 1737 // Dump lo-degree list 1738 tty->print("Lo degree: "); 1739 for(uint i3 = _lo_degree; i3; i3 = lrgs(i3)._next ) 1740 tty->print("L%d ",i3); 1741 tty->print_cr(""); 1742 1743 // Dump lo-stk-degree list 1744 tty->print("Lo stk degree: "); 1745 for(uint i4 = _lo_stk_degree; i4; i4 = lrgs(i4)._next ) 1746 tty->print("L%d ",i4); 1747 tty->print_cr(""); 1748 1749 // Dump lo-degree list 1750 tty->print("Hi degree: "); 1751 for(uint i5 = _hi_degree; i5; i5 = lrgs(i5)._next ) 1752 tty->print("L%d ",i5); 1753 tty->print_cr(""); 1754} 1755 1756//------------------------------dump_degree_lists------------------------------ 1757void PhaseChaitin::dump_degree_lists() const { 1758 // Dump lo-degree list 1759 tty->print("Lo degree: "); 1760 for( uint i = _lo_degree; i; i = lrgs(i)._next ) 1761 tty->print("L%d ",i); 1762 tty->print_cr(""); 1763 1764 // Dump lo-stk-degree list 1765 tty->print("Lo stk degree: "); 1766 for(uint i2 = _lo_stk_degree; i2; i2 = lrgs(i2)._next ) 1767 tty->print("L%d ",i2); 1768 tty->print_cr(""); 1769 1770 // Dump lo-degree list 1771 tty->print("Hi degree: "); 1772 for(uint i3 = _hi_degree; i3; i3 = lrgs(i3)._next ) 1773 tty->print("L%d ",i3); 1774 tty->print_cr(""); 1775} 1776 1777//------------------------------dump_simplified-------------------------------- 1778void PhaseChaitin::dump_simplified() const { 1779 tty->print("Simplified: "); 1780 for( uint i = _simplified; i; i = lrgs(i)._next ) 1781 tty->print("L%d ",i); 1782 tty->print_cr(""); 1783} 1784 1785static char *print_reg( OptoReg::Name reg, const PhaseChaitin *pc, char *buf ) { 1786 if ((int)reg < 0) 1787 sprintf(buf, "<OptoReg::%d>", (int)reg); 1788 else if (OptoReg::is_reg(reg)) 1789 strcpy(buf, Matcher::regName[reg]); 1790 else 1791 sprintf(buf,"%s + #%d",OptoReg::regname(OptoReg::c_frame_pointer), 1792 pc->reg2offset(reg)); 1793 return buf+strlen(buf); 1794} 1795 1796//------------------------------dump_register---------------------------------- 1797// Dump a register name into a buffer. Be intelligent if we get called 1798// before allocation is complete. 1799char *PhaseChaitin::dump_register( const Node *n, char *buf ) const { 1800 if( !this ) { // Not got anything? 1801 sprintf(buf,"N%d",n->_idx); // Then use Node index 1802 } else if( _node_regs ) { 1803 // Post allocation, use direct mappings, no LRG info available 1804 print_reg( get_reg_first(n), this, buf ); 1805 } else { 1806 uint lidx = Find_const(n); // Grab LRG number 1807 if( !_ifg ) { 1808 sprintf(buf,"L%d",lidx); // No register binding yet 1809 } else if( !lidx ) { // Special, not allocated value 1810 strcpy(buf,"Special"); 1811 } else if( (lrgs(lidx).num_regs() == 1) 1812 ? !lrgs(lidx).mask().is_bound1() 1813 : !lrgs(lidx).mask().is_bound2() ) { 1814 sprintf(buf,"L%d",lidx); // No register binding yet 1815 } else { // Hah! We have a bound machine register 1816 print_reg( lrgs(lidx).reg(), this, buf ); 1817 } 1818 } 1819 return buf+strlen(buf); 1820} 1821 1822//----------------------dump_for_spill_split_recycle-------------------------- 1823void PhaseChaitin::dump_for_spill_split_recycle() const { 1824 if( WizardMode && (PrintCompilation || PrintOpto) ) { 1825 // Display which live ranges need to be split and the allocator's state 1826 tty->print_cr("Graph-Coloring Iteration %d will split the following live ranges", _trip_cnt); 1827 for( uint bidx = 1; bidx < _maxlrg; bidx++ ) { 1828 if( lrgs(bidx).alive() && lrgs(bidx).reg() >= LRG::SPILL_REG ) { 1829 tty->print("L%d: ", bidx); 1830 lrgs(bidx).dump(); 1831 } 1832 } 1833 tty->cr(); 1834 dump(); 1835 } 1836} 1837 1838//------------------------------dump_frame------------------------------------ 1839void PhaseChaitin::dump_frame() const { 1840 const char *fp = OptoReg::regname(OptoReg::c_frame_pointer); 1841 const TypeTuple *domain = C->tf()->domain(); 1842 const int argcnt = domain->cnt() - TypeFunc::Parms; 1843 1844 // Incoming arguments in registers dump 1845 for( int k = 0; k < argcnt; k++ ) { 1846 OptoReg::Name parmreg = _matcher._parm_regs[k].first(); 1847 if( OptoReg::is_reg(parmreg)) { 1848 const char *reg_name = OptoReg::regname(parmreg); 1849 tty->print("#r%3.3d %s", parmreg, reg_name); 1850 parmreg = _matcher._parm_regs[k].second(); 1851 if( OptoReg::is_reg(parmreg)) { 1852 tty->print(":%s", OptoReg::regname(parmreg)); 1853 } 1854 tty->print(" : parm %d: ", k); 1855 domain->field_at(k + TypeFunc::Parms)->dump(); 1856 tty->print_cr(""); 1857 } 1858 } 1859 1860 // Check for un-owned padding above incoming args 1861 OptoReg::Name reg = _matcher._new_SP; 1862 if( reg > _matcher._in_arg_limit ) { 1863 reg = OptoReg::add(reg, -1); 1864 tty->print_cr("#r%3.3d %s+%2d: pad0, owned by CALLER", reg, fp, reg2offset_unchecked(reg)); 1865 } 1866 1867 // Incoming argument area dump 1868 OptoReg::Name begin_in_arg = OptoReg::add(_matcher._old_SP,C->out_preserve_stack_slots()); 1869 while( reg > begin_in_arg ) { 1870 reg = OptoReg::add(reg, -1); 1871 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg)); 1872 int j; 1873 for( j = 0; j < argcnt; j++) { 1874 if( _matcher._parm_regs[j].first() == reg || 1875 _matcher._parm_regs[j].second() == reg ) { 1876 tty->print("parm %d: ",j); 1877 domain->field_at(j + TypeFunc::Parms)->dump(); 1878 tty->print_cr(""); 1879 break; 1880 } 1881 } 1882 if( j >= argcnt ) 1883 tty->print_cr("HOLE, owned by SELF"); 1884 } 1885 1886 // Old outgoing preserve area 1887 while( reg > _matcher._old_SP ) { 1888 reg = OptoReg::add(reg, -1); 1889 tty->print_cr("#r%3.3d %s+%2d: old out preserve",reg,fp,reg2offset_unchecked(reg)); 1890 } 1891 1892 // Old SP 1893 tty->print_cr("# -- Old %s -- Framesize: %d --",fp, 1894 reg2offset_unchecked(OptoReg::add(_matcher._old_SP,-1)) - reg2offset_unchecked(_matcher._new_SP)+jintSize); 1895 1896 // Preserve area dump 1897 reg = OptoReg::add(reg, -1); 1898 while( OptoReg::is_stack(reg)) { 1899 tty->print("#r%3.3d %s+%2d: ",reg,fp,reg2offset_unchecked(reg)); 1900 if( _matcher.return_addr() == reg ) 1901 tty->print_cr("return address"); 1902 else if( _matcher.return_addr() == OptoReg::add(reg,1) && 1903 VerifyStackAtCalls ) 1904 tty->print_cr("0xBADB100D +VerifyStackAtCalls"); 1905 else if ((int)OptoReg::reg2stack(reg) < C->fixed_slots()) 1906 tty->print_cr("Fixed slot %d", OptoReg::reg2stack(reg)); 1907 else 1908 tty->print_cr("pad2, in_preserve"); 1909 reg = OptoReg::add(reg, -1); 1910 } 1911 1912 // Spill area dump 1913 reg = OptoReg::add(_matcher._new_SP, _framesize ); 1914 while( reg > _matcher._out_arg_limit ) { 1915 reg = OptoReg::add(reg, -1); 1916 tty->print_cr("#r%3.3d %s+%2d: spill",reg,fp,reg2offset_unchecked(reg)); 1917 } 1918 1919 // Outgoing argument area dump 1920 while( reg > OptoReg::add(_matcher._new_SP, C->out_preserve_stack_slots()) ) { 1921 reg = OptoReg::add(reg, -1); 1922 tty->print_cr("#r%3.3d %s+%2d: outgoing argument",reg,fp,reg2offset_unchecked(reg)); 1923 } 1924 1925 // Outgoing new preserve area 1926 while( reg > _matcher._new_SP ) { 1927 reg = OptoReg::add(reg, -1); 1928 tty->print_cr("#r%3.3d %s+%2d: new out preserve",reg,fp,reg2offset_unchecked(reg)); 1929 } 1930 tty->print_cr("#"); 1931} 1932 1933//------------------------------dump_bb---------------------------------------- 1934void PhaseChaitin::dump_bb( uint pre_order ) const { 1935 tty->print_cr("---dump of B%d---",pre_order); 1936 for( uint i = 0; i < _cfg._num_blocks; i++ ) { 1937 Block *b = _cfg._blocks[i]; 1938 if( b->_pre_order == pre_order ) 1939 dump(b); 1940 } 1941} 1942 1943//------------------------------dump_lrg--------------------------------------- 1944void PhaseChaitin::dump_lrg( uint lidx ) const { 1945 tty->print_cr("---dump of L%d---",lidx); 1946 1947 if( _ifg ) { 1948 if( lidx >= _maxlrg ) { 1949 tty->print("Attempt to print live range index beyond max live range.\n"); 1950 return; 1951 } 1952 tty->print("L%d: ",lidx); 1953 lrgs(lidx).dump( ); 1954 } 1955 if( _ifg ) { tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx)); 1956 _ifg->neighbors(lidx)->dump(); 1957 tty->cr(); 1958 } 1959 // For all blocks 1960 for( uint i = 0; i < _cfg._num_blocks; i++ ) { 1961 Block *b = _cfg._blocks[i]; 1962 int dump_once = 0; 1963 1964 // For all instructions 1965 for( uint j = 0; j < b->_nodes.size(); j++ ) { 1966 Node *n = b->_nodes[j]; 1967 if( Find_const(n) == lidx ) { 1968 if( !dump_once++ ) { 1969 tty->cr(); 1970 b->dump_head( &_cfg._bbs ); 1971 } 1972 dump(n); 1973 continue; 1974 } 1975 uint cnt = n->req(); 1976 for( uint k = 1; k < cnt; k++ ) { 1977 Node *m = n->in(k); 1978 if (!m) continue; // be robust in the dumper 1979 if( Find_const(m) == lidx ) { 1980 if( !dump_once++ ) { 1981 tty->cr(); 1982 b->dump_head( &_cfg._bbs ); 1983 } 1984 dump(n); 1985 } 1986 } 1987 } 1988 } // End of per-block dump 1989 tty->cr(); 1990} 1991#endif // not PRODUCT 1992 1993//------------------------------print_chaitin_statistics------------------------------- 1994int PhaseChaitin::_final_loads = 0; 1995int PhaseChaitin::_final_stores = 0; 1996int PhaseChaitin::_final_memoves= 0; 1997int PhaseChaitin::_final_copies = 0; 1998double PhaseChaitin::_final_load_cost = 0; 1999double PhaseChaitin::_final_store_cost = 0; 2000double PhaseChaitin::_final_memove_cost= 0; 2001double PhaseChaitin::_final_copy_cost = 0; 2002int PhaseChaitin::_conserv_coalesce = 0; 2003int PhaseChaitin::_conserv_coalesce_pair = 0; 2004int PhaseChaitin::_conserv_coalesce_trie = 0; 2005int PhaseChaitin::_conserv_coalesce_quad = 0; 2006int PhaseChaitin::_post_alloc = 0; 2007int PhaseChaitin::_lost_opp_pp_coalesce = 0; 2008int PhaseChaitin::_lost_opp_cflow_coalesce = 0; 2009int PhaseChaitin::_used_cisc_instructions = 0; 2010int PhaseChaitin::_unused_cisc_instructions = 0; 2011int PhaseChaitin::_allocator_attempts = 0; 2012int PhaseChaitin::_allocator_successes = 0; 2013 2014#ifndef PRODUCT 2015uint PhaseChaitin::_high_pressure = 0; 2016uint PhaseChaitin::_low_pressure = 0; 2017 2018void PhaseChaitin::print_chaitin_statistics() { 2019 tty->print_cr("Inserted %d spill loads, %d spill stores, %d mem-mem moves and %d copies.", _final_loads, _final_stores, _final_memoves, _final_copies); 2020 tty->print_cr("Total load cost= %6.0f, store cost = %6.0f, mem-mem cost = %5.2f, copy cost = %5.0f.", _final_load_cost, _final_store_cost, _final_memove_cost, _final_copy_cost); 2021 tty->print_cr("Adjusted spill cost = %7.0f.", 2022 _final_load_cost*4.0 + _final_store_cost * 2.0 + 2023 _final_copy_cost*1.0 + _final_memove_cost*12.0); 2024 tty->print("Conservatively coalesced %d copies, %d pairs", 2025 _conserv_coalesce, _conserv_coalesce_pair); 2026 if( _conserv_coalesce_trie || _conserv_coalesce_quad ) 2027 tty->print(", %d tries, %d quads", _conserv_coalesce_trie, _conserv_coalesce_quad); 2028 tty->print_cr(", %d post alloc.", _post_alloc); 2029 if( _lost_opp_pp_coalesce || _lost_opp_cflow_coalesce ) 2030 tty->print_cr("Lost coalesce opportunity, %d private-private, and %d cflow interfered.", 2031 _lost_opp_pp_coalesce, _lost_opp_cflow_coalesce ); 2032 if( _used_cisc_instructions || _unused_cisc_instructions ) 2033 tty->print_cr("Used cisc instruction %d, remained in register %d", 2034 _used_cisc_instructions, _unused_cisc_instructions); 2035 if( _allocator_successes != 0 ) 2036 tty->print_cr("Average allocation trips %f", (float)_allocator_attempts/(float)_allocator_successes); 2037 tty->print_cr("High Pressure Blocks = %d, Low Pressure Blocks = %d", _high_pressure, _low_pressure); 2038} 2039#endif // not PRODUCT 2040