c1_LIR.cpp revision 7877:cc8363b030d5
1/* 2 * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25#include "precompiled.hpp" 26#include "c1/c1_InstructionPrinter.hpp" 27#include "c1/c1_LIR.hpp" 28#include "c1/c1_LIRAssembler.hpp" 29#include "c1/c1_ValueStack.hpp" 30#include "ci/ciInstance.hpp" 31#include "runtime/sharedRuntime.hpp" 32 33Register LIR_OprDesc::as_register() const { 34 return FrameMap::cpu_rnr2reg(cpu_regnr()); 35} 36 37Register LIR_OprDesc::as_register_lo() const { 38 return FrameMap::cpu_rnr2reg(cpu_regnrLo()); 39} 40 41Register LIR_OprDesc::as_register_hi() const { 42 return FrameMap::cpu_rnr2reg(cpu_regnrHi()); 43} 44 45#if defined(X86) 46 47XMMRegister LIR_OprDesc::as_xmm_float_reg() const { 48 return FrameMap::nr2xmmreg(xmm_regnr()); 49} 50 51XMMRegister LIR_OprDesc::as_xmm_double_reg() const { 52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation"); 53 return FrameMap::nr2xmmreg(xmm_regnrLo()); 54} 55 56#endif // X86 57 58#if defined(SPARC) || defined(PPC) 59 60FloatRegister LIR_OprDesc::as_float_reg() const { 61 return FrameMap::nr2floatreg(fpu_regnr()); 62} 63 64FloatRegister LIR_OprDesc::as_double_reg() const { 65 return FrameMap::nr2floatreg(fpu_regnrHi()); 66} 67 68#endif 69 70#if defined(ARM) || defined (AARCH64) 71 72FloatRegister LIR_OprDesc::as_float_reg() const { 73 return as_FloatRegister(fpu_regnr()); 74} 75 76FloatRegister LIR_OprDesc::as_double_reg() const { 77 return as_FloatRegister(fpu_regnrLo()); 78} 79 80#endif 81 82 83LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal(); 84 85LIR_Opr LIR_OprFact::value_type(ValueType* type) { 86 ValueTag tag = type->tag(); 87 switch (tag) { 88 case metaDataTag : { 89 ClassConstant* c = type->as_ClassConstant(); 90 if (c != NULL && !c->value()->is_loaded()) { 91 return LIR_OprFact::metadataConst(NULL); 92 } else if (c != NULL) { 93 return LIR_OprFact::metadataConst(c->value()->constant_encoding()); 94 } else { 95 MethodConstant* m = type->as_MethodConstant(); 96 assert (m != NULL, "not a class or a method?"); 97 return LIR_OprFact::metadataConst(m->value()->constant_encoding()); 98 } 99 } 100 case objectTag : { 101 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding()); 102 } 103 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value()); 104 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value()); 105 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value()); 106 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value()); 107 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value()); 108 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); 109 } 110} 111 112 113LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) { 114 switch (type->tag()) { 115 case objectTag: return LIR_OprFact::oopConst(NULL); 116 case addressTag:return LIR_OprFact::addressConst(0); 117 case intTag: return LIR_OprFact::intConst(0); 118 case floatTag: return LIR_OprFact::floatConst(0.0); 119 case longTag: return LIR_OprFact::longConst(0); 120 case doubleTag: return LIR_OprFact::doubleConst(0.0); 121 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1); 122 } 123 return illegalOpr; 124} 125 126 127 128//--------------------------------------------------- 129 130 131LIR_Address::Scale LIR_Address::scale(BasicType type) { 132 int elem_size = type2aelembytes(type); 133 switch (elem_size) { 134 case 1: return LIR_Address::times_1; 135 case 2: return LIR_Address::times_2; 136 case 4: return LIR_Address::times_4; 137 case 8: return LIR_Address::times_8; 138 } 139 ShouldNotReachHere(); 140 return LIR_Address::times_1; 141} 142 143 144#ifndef PRODUCT 145void LIR_Address::verify() const { 146#if defined(SPARC) || defined(PPC) 147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used"); 148 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 149#endif 150#ifdef ARM 151 assert(disp() == 0 || index()->is_illegal(), "can't have both"); 152 // Note: offsets higher than 4096 must not be rejected here. They can 153 // be handled by the back-end or will be rejected if not. 154#endif 155#ifdef _LP64 156 assert(base()->is_cpu_register(), "wrong base operand"); 157#ifndef AARCH64 158 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand"); 159#else 160 assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand"); 161#endif 162 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA, 163 "wrong type for addresses"); 164#else 165 assert(base()->is_single_cpu(), "wrong base operand"); 166 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand"); 167 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA, 168 "wrong type for addresses"); 169#endif 170} 171#endif 172 173 174//--------------------------------------------------- 175 176char LIR_OprDesc::type_char(BasicType t) { 177 switch (t) { 178 case T_ARRAY: 179 t = T_OBJECT; 180 case T_BOOLEAN: 181 case T_CHAR: 182 case T_FLOAT: 183 case T_DOUBLE: 184 case T_BYTE: 185 case T_SHORT: 186 case T_INT: 187 case T_LONG: 188 case T_OBJECT: 189 case T_ADDRESS: 190 case T_VOID: 191 return ::type2char(t); 192 case T_METADATA: 193 return 'M'; 194 case T_ILLEGAL: 195 return '?'; 196 197 default: 198 ShouldNotReachHere(); 199 return '?'; 200 } 201} 202 203#ifndef PRODUCT 204void LIR_OprDesc::validate_type() const { 205 206#ifdef ASSERT 207 if (!is_pointer() && !is_illegal()) { 208 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160 209 switch (as_BasicType(type_field())) { 210 case T_LONG: 211 assert((kindfield == cpu_register || kindfield == stack_value) && 212 size_field() == double_size, "must match"); 213 break; 214 case T_FLOAT: 215 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) 216 assert((kindfield == fpu_register || kindfield == stack_value 217 ARM_ONLY(|| kindfield == cpu_register) 218 PPC_ONLY(|| kindfield == cpu_register) ) && 219 size_field() == single_size, "must match"); 220 break; 221 case T_DOUBLE: 222 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI) 223 assert((kindfield == fpu_register || kindfield == stack_value 224 ARM_ONLY(|| kindfield == cpu_register) 225 PPC_ONLY(|| kindfield == cpu_register) ) && 226 size_field() == double_size, "must match"); 227 break; 228 case T_BOOLEAN: 229 case T_CHAR: 230 case T_BYTE: 231 case T_SHORT: 232 case T_INT: 233 case T_ADDRESS: 234 case T_OBJECT: 235 case T_METADATA: 236 case T_ARRAY: 237 assert((kindfield == cpu_register || kindfield == stack_value) && 238 size_field() == single_size, "must match"); 239 break; 240 241 case T_ILLEGAL: 242 // XXX TKR also means unknown right now 243 // assert(is_illegal(), "must match"); 244 break; 245 246 default: 247 ShouldNotReachHere(); 248 } 249 } 250#endif 251 252} 253#endif // PRODUCT 254 255 256bool LIR_OprDesc::is_oop() const { 257 if (is_pointer()) { 258 return pointer()->is_oop_pointer(); 259 } else { 260 OprType t= type_field(); 261 assert(t != unknown_type, "not set"); 262 return t == object_type; 263 } 264} 265 266 267 268void LIR_Op2::verify() const { 269#ifdef ASSERT 270 switch (code()) { 271 case lir_cmove: 272 case lir_xchg: 273 break; 274 275 default: 276 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(), 277 "can't produce oops from arith"); 278 } 279 280 if (TwoOperandLIRForm) { 281 switch (code()) { 282 case lir_add: 283 case lir_sub: 284 case lir_mul: 285 case lir_mul_strictfp: 286 case lir_div: 287 case lir_div_strictfp: 288 case lir_rem: 289 case lir_logic_and: 290 case lir_logic_or: 291 case lir_logic_xor: 292 case lir_shl: 293 case lir_shr: 294 assert(in_opr1() == result_opr(), "opr1 and result must match"); 295 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); 296 break; 297 298 // special handling for lir_ushr because of write barriers 299 case lir_ushr: 300 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant"); 301 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid"); 302 break; 303 304 } 305 } 306#endif 307} 308 309 310LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block) 311 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 312 , _cond(cond) 313 , _type(type) 314 , _label(block->label()) 315 , _block(block) 316 , _ublock(NULL) 317 , _stub(NULL) { 318} 319 320LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) : 321 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 322 , _cond(cond) 323 , _type(type) 324 , _label(stub->entry()) 325 , _block(NULL) 326 , _ublock(NULL) 327 , _stub(stub) { 328} 329 330LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock) 331 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL) 332 , _cond(cond) 333 , _type(type) 334 , _label(block->label()) 335 , _block(block) 336 , _ublock(ublock) 337 , _stub(NULL) 338{ 339} 340 341void LIR_OpBranch::change_block(BlockBegin* b) { 342 assert(_block != NULL, "must have old block"); 343 assert(_block->label() == label(), "must be equal"); 344 345 _block = b; 346 _label = b->label(); 347} 348 349void LIR_OpBranch::change_ublock(BlockBegin* b) { 350 assert(_ublock != NULL, "must have old block"); 351 _ublock = b; 352} 353 354void LIR_OpBranch::negate_cond() { 355 switch (_cond) { 356 case lir_cond_equal: _cond = lir_cond_notEqual; break; 357 case lir_cond_notEqual: _cond = lir_cond_equal; break; 358 case lir_cond_less: _cond = lir_cond_greaterEqual; break; 359 case lir_cond_lessEqual: _cond = lir_cond_greater; break; 360 case lir_cond_greaterEqual: _cond = lir_cond_less; break; 361 case lir_cond_greater: _cond = lir_cond_lessEqual; break; 362 default: ShouldNotReachHere(); 363 } 364} 365 366 367LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass, 368 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, 369 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, 370 CodeStub* stub) 371 372 : LIR_Op(code, result, NULL) 373 , _object(object) 374 , _array(LIR_OprFact::illegalOpr) 375 , _klass(klass) 376 , _tmp1(tmp1) 377 , _tmp2(tmp2) 378 , _tmp3(tmp3) 379 , _fast_check(fast_check) 380 , _stub(stub) 381 , _info_for_patch(info_for_patch) 382 , _info_for_exception(info_for_exception) 383 , _profiled_method(NULL) 384 , _profiled_bci(-1) 385 , _should_profile(false) 386{ 387 if (code == lir_checkcast) { 388 assert(info_for_exception != NULL, "checkcast throws exceptions"); 389 } else if (code == lir_instanceof) { 390 assert(info_for_exception == NULL, "instanceof throws no exceptions"); 391 } else { 392 ShouldNotReachHere(); 393 } 394} 395 396 397 398LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception) 399 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL) 400 , _object(object) 401 , _array(array) 402 , _klass(NULL) 403 , _tmp1(tmp1) 404 , _tmp2(tmp2) 405 , _tmp3(tmp3) 406 , _fast_check(false) 407 , _stub(NULL) 408 , _info_for_patch(NULL) 409 , _info_for_exception(info_for_exception) 410 , _profiled_method(NULL) 411 , _profiled_bci(-1) 412 , _should_profile(false) 413{ 414 if (code == lir_store_check) { 415 _stub = new ArrayStoreExceptionStub(object, info_for_exception); 416 assert(info_for_exception != NULL, "store_check throws exceptions"); 417 } else { 418 ShouldNotReachHere(); 419 } 420} 421 422 423LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length, 424 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info) 425 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info) 426 , _tmp(tmp) 427 , _src(src) 428 , _src_pos(src_pos) 429 , _dst(dst) 430 , _dst_pos(dst_pos) 431 , _flags(flags) 432 , _expected_type(expected_type) 433 , _length(length) { 434 _stub = new ArrayCopyStub(this); 435} 436 437LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res) 438 : LIR_Op(lir_updatecrc32, res, NULL) 439 , _crc(crc) 440 , _val(val) { 441} 442 443//-------------------verify-------------------------- 444 445void LIR_Op1::verify() const { 446 switch(code()) { 447 case lir_move: 448 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be"); 449 break; 450 case lir_null_check: 451 assert(in_opr()->is_register(), "must be"); 452 break; 453 case lir_return: 454 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be"); 455 break; 456 } 457} 458 459void LIR_OpRTCall::verify() const { 460 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function"); 461} 462 463//-------------------visits-------------------------- 464 465// complete rework of LIR instruction visitor. 466// The virtual calls for each instruction type is replaced by a big 467// switch that adds the operands for each instruction 468 469void LIR_OpVisitState::visit(LIR_Op* op) { 470 // copy information from the LIR_Op 471 reset(); 472 set_op(op); 473 474 switch (op->code()) { 475 476// LIR_Op0 477 case lir_word_align: // result and info always invalid 478 case lir_backwardbranch_target: // result and info always invalid 479 case lir_build_frame: // result and info always invalid 480 case lir_fpop_raw: // result and info always invalid 481 case lir_24bit_FPU: // result and info always invalid 482 case lir_reset_FPU: // result and info always invalid 483 case lir_breakpoint: // result and info always invalid 484 case lir_membar: // result and info always invalid 485 case lir_membar_acquire: // result and info always invalid 486 case lir_membar_release: // result and info always invalid 487 case lir_membar_loadload: // result and info always invalid 488 case lir_membar_storestore: // result and info always invalid 489 case lir_membar_loadstore: // result and info always invalid 490 case lir_membar_storeload: // result and info always invalid 491 { 492 assert(op->as_Op0() != NULL, "must be"); 493 assert(op->_info == NULL, "info not used by this instruction"); 494 assert(op->_result->is_illegal(), "not used"); 495 break; 496 } 497 498 case lir_nop: // may have info, result always invalid 499 case lir_std_entry: // may have result, info always invalid 500 case lir_osr_entry: // may have result, info always invalid 501 case lir_get_thread: // may have result, info always invalid 502 { 503 assert(op->as_Op0() != NULL, "must be"); 504 if (op->_info != NULL) do_info(op->_info); 505 if (op->_result->is_valid()) do_output(op->_result); 506 break; 507 } 508 509 510// LIR_OpLabel 511 case lir_label: // result and info always invalid 512 { 513 assert(op->as_OpLabel() != NULL, "must be"); 514 assert(op->_info == NULL, "info not used by this instruction"); 515 assert(op->_result->is_illegal(), "not used"); 516 break; 517 } 518 519 520// LIR_Op1 521 case lir_fxch: // input always valid, result and info always invalid 522 case lir_fld: // input always valid, result and info always invalid 523 case lir_ffree: // input always valid, result and info always invalid 524 case lir_push: // input always valid, result and info always invalid 525 case lir_pop: // input always valid, result and info always invalid 526 case lir_return: // input always valid, result and info always invalid 527 case lir_leal: // input and result always valid, info always invalid 528 case lir_neg: // input and result always valid, info always invalid 529 case lir_monaddr: // input and result always valid, info always invalid 530 case lir_null_check: // input and info always valid, result always invalid 531 case lir_move: // input and result always valid, may have info 532 case lir_pack64: // input and result always valid 533 case lir_unpack64: // input and result always valid 534 case lir_prefetchr: // input always valid, result and info always invalid 535 case lir_prefetchw: // input always valid, result and info always invalid 536 { 537 assert(op->as_Op1() != NULL, "must be"); 538 LIR_Op1* op1 = (LIR_Op1*)op; 539 540 if (op1->_info) do_info(op1->_info); 541 if (op1->_opr->is_valid()) do_input(op1->_opr); 542 if (op1->_result->is_valid()) do_output(op1->_result); 543 544 break; 545 } 546 547 case lir_safepoint: 548 { 549 assert(op->as_Op1() != NULL, "must be"); 550 LIR_Op1* op1 = (LIR_Op1*)op; 551 552 assert(op1->_info != NULL, ""); do_info(op1->_info); 553 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register 554 assert(op1->_result->is_illegal(), "safepoint does not produce value"); 555 556 break; 557 } 558 559// LIR_OpConvert; 560 case lir_convert: // input and result always valid, info always invalid 561 { 562 assert(op->as_OpConvert() != NULL, "must be"); 563 LIR_OpConvert* opConvert = (LIR_OpConvert*)op; 564 565 assert(opConvert->_info == NULL, "must be"); 566 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr); 567 if (opConvert->_result->is_valid()) do_output(opConvert->_result); 568#ifdef PPC 569 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1); 570 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2); 571#endif 572 do_stub(opConvert->_stub); 573 574 break; 575 } 576 577// LIR_OpBranch; 578 case lir_branch: // may have info, input and result register always invalid 579 case lir_cond_float_branch: // may have info, input and result register always invalid 580 { 581 assert(op->as_OpBranch() != NULL, "must be"); 582 LIR_OpBranch* opBranch = (LIR_OpBranch*)op; 583 584 if (opBranch->_info != NULL) do_info(opBranch->_info); 585 assert(opBranch->_result->is_illegal(), "not used"); 586 if (opBranch->_stub != NULL) opBranch->stub()->visit(this); 587 588 break; 589 } 590 591 592// LIR_OpAllocObj 593 case lir_alloc_object: 594 { 595 assert(op->as_OpAllocObj() != NULL, "must be"); 596 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op; 597 598 if (opAllocObj->_info) do_info(opAllocObj->_info); 599 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr); 600 do_temp(opAllocObj->_opr); 601 } 602 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1); 603 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2); 604 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3); 605 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4); 606 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result); 607 do_stub(opAllocObj->_stub); 608 break; 609 } 610 611 612// LIR_OpRoundFP; 613 case lir_roundfp: { 614 assert(op->as_OpRoundFP() != NULL, "must be"); 615 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op; 616 617 assert(op->_info == NULL, "info not used by this instruction"); 618 assert(opRoundFP->_tmp->is_illegal(), "not used"); 619 do_input(opRoundFP->_opr); 620 do_output(opRoundFP->_result); 621 622 break; 623 } 624 625 626// LIR_Op2 627 case lir_cmp: 628 case lir_cmp_l2i: 629 case lir_ucmp_fd2i: 630 case lir_cmp_fd2i: 631 case lir_add: 632 case lir_sub: 633 case lir_mul: 634 case lir_div: 635 case lir_rem: 636 case lir_sqrt: 637 case lir_abs: 638 case lir_logic_and: 639 case lir_logic_or: 640 case lir_logic_xor: 641 case lir_shl: 642 case lir_shr: 643 case lir_ushr: 644 case lir_xadd: 645 case lir_xchg: 646 case lir_assert: 647 { 648 assert(op->as_Op2() != NULL, "must be"); 649 LIR_Op2* op2 = (LIR_Op2*)op; 650 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 651 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 652 653 if (op2->_info) do_info(op2->_info); 654 if (op2->_opr1->is_valid()) do_input(op2->_opr1); 655 if (op2->_opr2->is_valid()) do_input(op2->_opr2); 656 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); 657 if (op2->_result->is_valid()) do_output(op2->_result); 658 if (op->code() == lir_xchg || op->code() == lir_xadd) { 659 // on ARM and PPC, return value is loaded first so could 660 // destroy inputs. On other platforms that implement those 661 // (x86, sparc), the extra constrainsts are harmless. 662 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); 663 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); 664 } 665 666 break; 667 } 668 669 // special handling for cmove: right input operand must not be equal 670 // to the result operand, otherwise the backend fails 671 case lir_cmove: 672 { 673 assert(op->as_Op2() != NULL, "must be"); 674 LIR_Op2* op2 = (LIR_Op2*)op; 675 676 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() && 677 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 678 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used"); 679 680 do_input(op2->_opr1); 681 do_input(op2->_opr2); 682 do_temp(op2->_opr2); 683 do_output(op2->_result); 684 685 break; 686 } 687 688 // vspecial handling for strict operations: register input operands 689 // as temp to guarantee that they do not overlap with other 690 // registers 691 case lir_mul_strictfp: 692 case lir_div_strictfp: 693 { 694 assert(op->as_Op2() != NULL, "must be"); 695 LIR_Op2* op2 = (LIR_Op2*)op; 696 697 assert(op2->_info == NULL, "not used"); 698 assert(op2->_opr1->is_valid(), "used"); 699 assert(op2->_opr2->is_valid(), "used"); 700 assert(op2->_result->is_valid(), "used"); 701 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 702 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 703 704 do_input(op2->_opr1); do_temp(op2->_opr1); 705 do_input(op2->_opr2); do_temp(op2->_opr2); 706 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); 707 do_output(op2->_result); 708 709 break; 710 } 711 712 case lir_throw: { 713 assert(op->as_Op2() != NULL, "must be"); 714 LIR_Op2* op2 = (LIR_Op2*)op; 715 716 if (op2->_info) do_info(op2->_info); 717 if (op2->_opr1->is_valid()) do_temp(op2->_opr1); 718 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter 719 assert(op2->_result->is_illegal(), "no result"); 720 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() && 721 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used"); 722 723 break; 724 } 725 726 case lir_unwind: { 727 assert(op->as_Op1() != NULL, "must be"); 728 LIR_Op1* op1 = (LIR_Op1*)op; 729 730 assert(op1->_info == NULL, "no info"); 731 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr); 732 assert(op1->_result->is_illegal(), "no result"); 733 734 break; 735 } 736 737 738 case lir_tan: 739 case lir_sin: 740 case lir_cos: 741 case lir_log: 742 case lir_log10: 743 case lir_exp: { 744 assert(op->as_Op2() != NULL, "must be"); 745 LIR_Op2* op2 = (LIR_Op2*)op; 746 747 // On x86 tan/sin/cos need two temporary fpu stack slots and 748 // log/log10 need one so handle opr2 and tmp as temp inputs. 749 // Register input operand as temp to guarantee that it doesn't 750 // overlap with the input. 751 assert(op2->_info == NULL, "not used"); 752 assert(op2->_tmp5->is_illegal(), "not used"); 753 assert(op2->_tmp2->is_valid() == (op->code() == lir_exp), "not used"); 754 assert(op2->_tmp3->is_valid() == (op->code() == lir_exp), "not used"); 755 assert(op2->_tmp4->is_valid() == (op->code() == lir_exp), "not used"); 756 assert(op2->_opr1->is_valid(), "used"); 757 do_input(op2->_opr1); do_temp(op2->_opr1); 758 759 if (op2->_opr2->is_valid()) do_temp(op2->_opr2); 760 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1); 761 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2); 762 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3); 763 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4); 764 if (op2->_result->is_valid()) do_output(op2->_result); 765 766 break; 767 } 768 769 case lir_pow: { 770 assert(op->as_Op2() != NULL, "must be"); 771 LIR_Op2* op2 = (LIR_Op2*)op; 772 773 // On x86 pow needs two temporary fpu stack slots: tmp1 and 774 // tmp2. Register input operands as temps to guarantee that it 775 // doesn't overlap with the temporary slots. 776 assert(op2->_info == NULL, "not used"); 777 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used"); 778 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid() 779 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used"); 780 assert(op2->_result->is_valid(), "used"); 781 782 do_input(op2->_opr1); do_temp(op2->_opr1); 783 do_input(op2->_opr2); do_temp(op2->_opr2); 784 do_temp(op2->_tmp1); 785 do_temp(op2->_tmp2); 786 do_temp(op2->_tmp3); 787 do_temp(op2->_tmp4); 788 do_temp(op2->_tmp5); 789 do_output(op2->_result); 790 791 break; 792 } 793 794// LIR_Op3 795 case lir_idiv: 796 case lir_irem: { 797 assert(op->as_Op3() != NULL, "must be"); 798 LIR_Op3* op3= (LIR_Op3*)op; 799 800 if (op3->_info) do_info(op3->_info); 801 if (op3->_opr1->is_valid()) do_input(op3->_opr1); 802 803 // second operand is input and temp, so ensure that second operand 804 // and third operand get not the same register 805 if (op3->_opr2->is_valid()) do_input(op3->_opr2); 806 if (op3->_opr2->is_valid()) do_temp(op3->_opr2); 807 if (op3->_opr3->is_valid()) do_temp(op3->_opr3); 808 809 if (op3->_result->is_valid()) do_output(op3->_result); 810 811 break; 812 } 813 814 815// LIR_OpJavaCall 816 case lir_static_call: 817 case lir_optvirtual_call: 818 case lir_icvirtual_call: 819 case lir_virtual_call: 820 case lir_dynamic_call: { 821 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall(); 822 assert(opJavaCall != NULL, "must be"); 823 824 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver); 825 826 // only visit register parameters 827 int n = opJavaCall->_arguments->length(); 828 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) { 829 if (!opJavaCall->_arguments->at(i)->is_pointer()) { 830 do_input(*opJavaCall->_arguments->adr_at(i)); 831 } 832 } 833 834 if (opJavaCall->_info) do_info(opJavaCall->_info); 835 if (opJavaCall->is_method_handle_invoke()) { 836 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr(); 837 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr); 838 } 839 do_call(); 840 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result); 841 842 break; 843 } 844 845 846// LIR_OpRTCall 847 case lir_rtcall: { 848 assert(op->as_OpRTCall() != NULL, "must be"); 849 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op; 850 851 // only visit register parameters 852 int n = opRTCall->_arguments->length(); 853 for (int i = 0; i < n; i++) { 854 if (!opRTCall->_arguments->at(i)->is_pointer()) { 855 do_input(*opRTCall->_arguments->adr_at(i)); 856 } 857 } 858 if (opRTCall->_info) do_info(opRTCall->_info); 859 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp); 860 do_call(); 861 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result); 862 863 break; 864 } 865 866 867// LIR_OpArrayCopy 868 case lir_arraycopy: { 869 assert(op->as_OpArrayCopy() != NULL, "must be"); 870 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op; 871 872 assert(opArrayCopy->_result->is_illegal(), "unused"); 873 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src); 874 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos); 875 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst); 876 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos); 877 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length); 878 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp); 879 if (opArrayCopy->_info) do_info(opArrayCopy->_info); 880 881 // the implementation of arraycopy always has a call into the runtime 882 do_call(); 883 884 break; 885 } 886 887 888// LIR_OpUpdateCRC32 889 case lir_updatecrc32: { 890 assert(op->as_OpUpdateCRC32() != NULL, "must be"); 891 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op; 892 893 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc); 894 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val); 895 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result); 896 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32"); 897 898 break; 899 } 900 901 902// LIR_OpLock 903 case lir_lock: 904 case lir_unlock: { 905 assert(op->as_OpLock() != NULL, "must be"); 906 LIR_OpLock* opLock = (LIR_OpLock*)op; 907 908 if (opLock->_info) do_info(opLock->_info); 909 910 // TODO: check if these operands really have to be temp 911 // (or if input is sufficient). This may have influence on the oop map! 912 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock); 913 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr); 914 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj); 915 916 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch); 917 assert(opLock->_result->is_illegal(), "unused"); 918 919 do_stub(opLock->_stub); 920 921 break; 922 } 923 924 925// LIR_OpDelay 926 case lir_delay_slot: { 927 assert(op->as_OpDelay() != NULL, "must be"); 928 LIR_OpDelay* opDelay = (LIR_OpDelay*)op; 929 930 visit(opDelay->delay_op()); 931 break; 932 } 933 934// LIR_OpTypeCheck 935 case lir_instanceof: 936 case lir_checkcast: 937 case lir_store_check: { 938 assert(op->as_OpTypeCheck() != NULL, "must be"); 939 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op; 940 941 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception); 942 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch); 943 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object); 944 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) { 945 do_temp(opTypeCheck->_object); 946 } 947 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array); 948 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1); 949 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2); 950 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3); 951 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result); 952 do_stub(opTypeCheck->_stub); 953 break; 954 } 955 956// LIR_OpCompareAndSwap 957 case lir_cas_long: 958 case lir_cas_obj: 959 case lir_cas_int: { 960 assert(op->as_OpCompareAndSwap() != NULL, "must be"); 961 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op; 962 963 assert(opCompareAndSwap->_addr->is_valid(), "used"); 964 assert(opCompareAndSwap->_cmp_value->is_valid(), "used"); 965 assert(opCompareAndSwap->_new_value->is_valid(), "used"); 966 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info); 967 do_input(opCompareAndSwap->_addr); 968 do_temp(opCompareAndSwap->_addr); 969 do_input(opCompareAndSwap->_cmp_value); 970 do_temp(opCompareAndSwap->_cmp_value); 971 do_input(opCompareAndSwap->_new_value); 972 do_temp(opCompareAndSwap->_new_value); 973 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1); 974 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2); 975 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result); 976 977 break; 978 } 979 980 981// LIR_OpAllocArray; 982 case lir_alloc_array: { 983 assert(op->as_OpAllocArray() != NULL, "must be"); 984 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op; 985 986 if (opAllocArray->_info) do_info(opAllocArray->_info); 987 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass); 988 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len); 989 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1); 990 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2); 991 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3); 992 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4); 993 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result); 994 do_stub(opAllocArray->_stub); 995 break; 996 } 997 998// LIR_OpProfileCall: 999 case lir_profile_call: { 1000 assert(op->as_OpProfileCall() != NULL, "must be"); 1001 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op; 1002 1003 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv); 1004 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo); 1005 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1); 1006 break; 1007 } 1008 1009// LIR_OpProfileType: 1010 case lir_profile_type: { 1011 assert(op->as_OpProfileType() != NULL, "must be"); 1012 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op; 1013 1014 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp); 1015 do_input(opProfileType->_obj); 1016 do_temp(opProfileType->_tmp); 1017 break; 1018 } 1019 default: 1020 ShouldNotReachHere(); 1021 } 1022} 1023 1024 1025void LIR_OpVisitState::do_stub(CodeStub* stub) { 1026 if (stub != NULL) { 1027 stub->visit(this); 1028 } 1029} 1030 1031XHandlers* LIR_OpVisitState::all_xhandler() { 1032 XHandlers* result = NULL; 1033 1034 int i; 1035 for (i = 0; i < info_count(); i++) { 1036 if (info_at(i)->exception_handlers() != NULL) { 1037 result = info_at(i)->exception_handlers(); 1038 break; 1039 } 1040 } 1041 1042#ifdef ASSERT 1043 for (i = 0; i < info_count(); i++) { 1044 assert(info_at(i)->exception_handlers() == NULL || 1045 info_at(i)->exception_handlers() == result, 1046 "only one xhandler list allowed per LIR-operation"); 1047 } 1048#endif 1049 1050 if (result != NULL) { 1051 return result; 1052 } else { 1053 return new XHandlers(); 1054 } 1055 1056 return result; 1057} 1058 1059 1060#ifdef ASSERT 1061bool LIR_OpVisitState::no_operands(LIR_Op* op) { 1062 visit(op); 1063 1064 return opr_count(inputMode) == 0 && 1065 opr_count(outputMode) == 0 && 1066 opr_count(tempMode) == 0 && 1067 info_count() == 0 && 1068 !has_call() && 1069 !has_slow_case(); 1070} 1071#endif 1072 1073//--------------------------------------------------- 1074 1075 1076void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) { 1077 masm->emit_call(this); 1078} 1079 1080void LIR_OpRTCall::emit_code(LIR_Assembler* masm) { 1081 masm->emit_rtcall(this); 1082} 1083 1084void LIR_OpLabel::emit_code(LIR_Assembler* masm) { 1085 masm->emit_opLabel(this); 1086} 1087 1088void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) { 1089 masm->emit_arraycopy(this); 1090 masm->append_code_stub(stub()); 1091} 1092 1093void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) { 1094 masm->emit_updatecrc32(this); 1095} 1096 1097void LIR_Op0::emit_code(LIR_Assembler* masm) { 1098 masm->emit_op0(this); 1099} 1100 1101void LIR_Op1::emit_code(LIR_Assembler* masm) { 1102 masm->emit_op1(this); 1103} 1104 1105void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) { 1106 masm->emit_alloc_obj(this); 1107 masm->append_code_stub(stub()); 1108} 1109 1110void LIR_OpBranch::emit_code(LIR_Assembler* masm) { 1111 masm->emit_opBranch(this); 1112 if (stub()) { 1113 masm->append_code_stub(stub()); 1114 } 1115} 1116 1117void LIR_OpConvert::emit_code(LIR_Assembler* masm) { 1118 masm->emit_opConvert(this); 1119 if (stub() != NULL) { 1120 masm->append_code_stub(stub()); 1121 } 1122} 1123 1124void LIR_Op2::emit_code(LIR_Assembler* masm) { 1125 masm->emit_op2(this); 1126} 1127 1128void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) { 1129 masm->emit_alloc_array(this); 1130 masm->append_code_stub(stub()); 1131} 1132 1133void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) { 1134 masm->emit_opTypeCheck(this); 1135 if (stub()) { 1136 masm->append_code_stub(stub()); 1137 } 1138} 1139 1140void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) { 1141 masm->emit_compare_and_swap(this); 1142} 1143 1144void LIR_Op3::emit_code(LIR_Assembler* masm) { 1145 masm->emit_op3(this); 1146} 1147 1148void LIR_OpLock::emit_code(LIR_Assembler* masm) { 1149 masm->emit_lock(this); 1150 if (stub()) { 1151 masm->append_code_stub(stub()); 1152 } 1153} 1154 1155#ifdef ASSERT 1156void LIR_OpAssert::emit_code(LIR_Assembler* masm) { 1157 masm->emit_assert(this); 1158} 1159#endif 1160 1161void LIR_OpDelay::emit_code(LIR_Assembler* masm) { 1162 masm->emit_delay(this); 1163} 1164 1165void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) { 1166 masm->emit_profile_call(this); 1167} 1168 1169void LIR_OpProfileType::emit_code(LIR_Assembler* masm) { 1170 masm->emit_profile_type(this); 1171} 1172 1173// LIR_List 1174LIR_List::LIR_List(Compilation* compilation, BlockBegin* block) 1175 : _operations(8) 1176 , _compilation(compilation) 1177#ifndef PRODUCT 1178 , _block(block) 1179#endif 1180#ifdef ASSERT 1181 , _file(NULL) 1182 , _line(0) 1183#endif 1184{ } 1185 1186 1187#ifdef ASSERT 1188void LIR_List::set_file_and_line(const char * file, int line) { 1189 const char * f = strrchr(file, '/'); 1190 if (f == NULL) f = strrchr(file, '\\'); 1191 if (f == NULL) { 1192 f = file; 1193 } else { 1194 f++; 1195 } 1196 _file = f; 1197 _line = line; 1198} 1199#endif 1200 1201 1202void LIR_List::append(LIR_InsertionBuffer* buffer) { 1203 assert(this == buffer->lir_list(), "wrong lir list"); 1204 const int n = _operations.length(); 1205 1206 if (buffer->number_of_ops() > 0) { 1207 // increase size of instructions list 1208 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL); 1209 // insert ops from buffer into instructions list 1210 int op_index = buffer->number_of_ops() - 1; 1211 int ip_index = buffer->number_of_insertion_points() - 1; 1212 int from_index = n - 1; 1213 int to_index = _operations.length() - 1; 1214 for (; ip_index >= 0; ip_index --) { 1215 int index = buffer->index_at(ip_index); 1216 // make room after insertion point 1217 while (index < from_index) { 1218 _operations.at_put(to_index --, _operations.at(from_index --)); 1219 } 1220 // insert ops from buffer 1221 for (int i = buffer->count_at(ip_index); i > 0; i --) { 1222 _operations.at_put(to_index --, buffer->op_at(op_index --)); 1223 } 1224 } 1225 } 1226 1227 buffer->finish(); 1228} 1229 1230 1231void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) { 1232 assert(reg->type() == T_OBJECT, "bad reg"); 1233 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info)); 1234} 1235 1236void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) { 1237 assert(reg->type() == T_METADATA, "bad reg"); 1238 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info)); 1239} 1240 1241void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1242 append(new LIR_Op1( 1243 lir_move, 1244 LIR_OprFact::address(addr), 1245 src, 1246 addr->type(), 1247 patch_code, 1248 info)); 1249} 1250 1251 1252void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1253 append(new LIR_Op1( 1254 lir_move, 1255 LIR_OprFact::address(address), 1256 dst, 1257 address->type(), 1258 patch_code, 1259 info, lir_move_volatile)); 1260} 1261 1262void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1263 append(new LIR_Op1( 1264 lir_move, 1265 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1266 dst, 1267 type, 1268 patch_code, 1269 info, lir_move_volatile)); 1270} 1271 1272 1273void LIR_List::prefetch(LIR_Address* addr, bool is_store) { 1274 append(new LIR_Op1( 1275 is_store ? lir_prefetchw : lir_prefetchr, 1276 LIR_OprFact::address(addr))); 1277} 1278 1279 1280void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1281 append(new LIR_Op1( 1282 lir_move, 1283 LIR_OprFact::intConst(v), 1284 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), 1285 type, 1286 patch_code, 1287 info)); 1288} 1289 1290 1291void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1292 append(new LIR_Op1( 1293 lir_move, 1294 LIR_OprFact::oopConst(o), 1295 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)), 1296 type, 1297 patch_code, 1298 info)); 1299} 1300 1301 1302void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1303 append(new LIR_Op1( 1304 lir_move, 1305 src, 1306 LIR_OprFact::address(addr), 1307 addr->type(), 1308 patch_code, 1309 info)); 1310} 1311 1312 1313void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1314 append(new LIR_Op1( 1315 lir_move, 1316 src, 1317 LIR_OprFact::address(addr), 1318 addr->type(), 1319 patch_code, 1320 info, 1321 lir_move_volatile)); 1322} 1323 1324void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) { 1325 append(new LIR_Op1( 1326 lir_move, 1327 src, 1328 LIR_OprFact::address(new LIR_Address(base, offset, type)), 1329 type, 1330 patch_code, 1331 info, lir_move_volatile)); 1332} 1333 1334 1335void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1336 append(new LIR_Op3( 1337 lir_idiv, 1338 left, 1339 right, 1340 tmp, 1341 res, 1342 info)); 1343} 1344 1345 1346void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1347 append(new LIR_Op3( 1348 lir_idiv, 1349 left, 1350 LIR_OprFact::intConst(right), 1351 tmp, 1352 res, 1353 info)); 1354} 1355 1356 1357void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1358 append(new LIR_Op3( 1359 lir_irem, 1360 left, 1361 right, 1362 tmp, 1363 res, 1364 info)); 1365} 1366 1367 1368void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) { 1369 append(new LIR_Op3( 1370 lir_irem, 1371 left, 1372 LIR_OprFact::intConst(right), 1373 tmp, 1374 res, 1375 info)); 1376} 1377 1378 1379void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) { 1380 append(new LIR_Op2( 1381 lir_cmp, 1382 condition, 1383 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)), 1384 LIR_OprFact::intConst(c), 1385 info)); 1386} 1387 1388 1389void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) { 1390 append(new LIR_Op2( 1391 lir_cmp, 1392 condition, 1393 reg, 1394 LIR_OprFact::address(addr), 1395 info)); 1396} 1397 1398void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4, 1399 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) { 1400 append(new LIR_OpAllocObj( 1401 klass, 1402 dst, 1403 t1, 1404 t2, 1405 t3, 1406 t4, 1407 header_size, 1408 object_size, 1409 init_check, 1410 stub)); 1411} 1412 1413void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) { 1414 append(new LIR_OpAllocArray( 1415 klass, 1416 len, 1417 dst, 1418 t1, 1419 t2, 1420 t3, 1421 t4, 1422 type, 1423 stub)); 1424} 1425 1426void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1427 append(new LIR_Op2( 1428 lir_shl, 1429 value, 1430 count, 1431 dst, 1432 tmp)); 1433} 1434 1435void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1436 append(new LIR_Op2( 1437 lir_shr, 1438 value, 1439 count, 1440 dst, 1441 tmp)); 1442} 1443 1444 1445void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) { 1446 append(new LIR_Op2( 1447 lir_ushr, 1448 value, 1449 count, 1450 dst, 1451 tmp)); 1452} 1453 1454void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) { 1455 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i, 1456 left, 1457 right, 1458 dst)); 1459} 1460 1461void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) { 1462 append(new LIR_OpLock( 1463 lir_lock, 1464 hdr, 1465 obj, 1466 lock, 1467 scratch, 1468 stub, 1469 info)); 1470} 1471 1472void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) { 1473 append(new LIR_OpLock( 1474 lir_unlock, 1475 hdr, 1476 obj, 1477 lock, 1478 scratch, 1479 stub, 1480 NULL)); 1481} 1482 1483 1484void check_LIR() { 1485 // cannot do the proper checking as PRODUCT and other modes return different results 1486 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table"); 1487} 1488 1489 1490 1491void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass, 1492 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, 1493 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub, 1494 ciMethod* profiled_method, int profiled_bci) { 1495 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass, 1496 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub); 1497 if (profiled_method != NULL) { 1498 c->set_profiled_method(profiled_method); 1499 c->set_profiled_bci(profiled_bci); 1500 c->set_should_profile(true); 1501 } 1502 append(c); 1503} 1504 1505void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) { 1506 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL); 1507 if (profiled_method != NULL) { 1508 c->set_profiled_method(profiled_method); 1509 c->set_profiled_bci(profiled_bci); 1510 c->set_should_profile(true); 1511 } 1512 append(c); 1513} 1514 1515 1516void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, 1517 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) { 1518 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception); 1519 if (profiled_method != NULL) { 1520 c->set_profiled_method(profiled_method); 1521 c->set_profiled_bci(profiled_bci); 1522 c->set_should_profile(true); 1523 } 1524 append(c); 1525} 1526 1527 1528void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1529 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1530 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result)); 1531} 1532 1533void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1534 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1535 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result)); 1536} 1537 1538void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value, 1539 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) { 1540 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result)); 1541} 1542 1543 1544#ifdef PRODUCT 1545 1546void print_LIR(BlockList* blocks) { 1547} 1548 1549#else 1550// LIR_OprDesc 1551void LIR_OprDesc::print() const { 1552 print(tty); 1553} 1554 1555void LIR_OprDesc::print(outputStream* out) const { 1556 if (is_illegal()) { 1557 return; 1558 } 1559 1560 out->print("["); 1561 if (is_pointer()) { 1562 pointer()->print_value_on(out); 1563 } else if (is_single_stack()) { 1564 out->print("stack:%d", single_stack_ix()); 1565 } else if (is_double_stack()) { 1566 out->print("dbl_stack:%d",double_stack_ix()); 1567 } else if (is_virtual()) { 1568 out->print("R%d", vreg_number()); 1569 } else if (is_single_cpu()) { 1570 out->print("%s", as_register()->name()); 1571 } else if (is_double_cpu()) { 1572 out->print("%s", as_register_hi()->name()); 1573 out->print("%s", as_register_lo()->name()); 1574#if defined(X86) 1575 } else if (is_single_xmm()) { 1576 out->print("%s", as_xmm_float_reg()->name()); 1577 } else if (is_double_xmm()) { 1578 out->print("%s", as_xmm_double_reg()->name()); 1579 } else if (is_single_fpu()) { 1580 out->print("fpu%d", fpu_regnr()); 1581 } else if (is_double_fpu()) { 1582 out->print("fpu%d", fpu_regnrLo()); 1583#elif defined(AARCH64) 1584 } else if (is_single_fpu()) { 1585 out->print("fpu%d", fpu_regnr()); 1586 } else if (is_double_fpu()) { 1587 out->print("fpu%d", fpu_regnrLo()); 1588#elif defined(ARM) 1589 } else if (is_single_fpu()) { 1590 out->print("s%d", fpu_regnr()); 1591 } else if (is_double_fpu()) { 1592 out->print("d%d", fpu_regnrLo() >> 1); 1593#else 1594 } else if (is_single_fpu()) { 1595 out->print("%s", as_float_reg()->name()); 1596 } else if (is_double_fpu()) { 1597 out->print("%s", as_double_reg()->name()); 1598#endif 1599 1600 } else if (is_illegal()) { 1601 out->print("-"); 1602 } else { 1603 out->print("Unknown Operand"); 1604 } 1605 if (!is_illegal()) { 1606 out->print("|%c", type_char()); 1607 } 1608 if (is_register() && is_last_use()) { 1609 out->print("(last_use)"); 1610 } 1611 out->print("]"); 1612} 1613 1614 1615// LIR_Address 1616void LIR_Const::print_value_on(outputStream* out) const { 1617 switch (type()) { 1618 case T_ADDRESS:out->print("address:%d",as_jint()); break; 1619 case T_INT: out->print("int:%d", as_jint()); break; 1620 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break; 1621 case T_FLOAT: out->print("flt:%f", as_jfloat()); break; 1622 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break; 1623 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break; 1624 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break; 1625 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break; 1626 } 1627} 1628 1629// LIR_Address 1630void LIR_Address::print_value_on(outputStream* out) const { 1631 out->print("Base:"); _base->print(out); 1632 if (!_index->is_illegal()) { 1633 out->print(" Index:"); _index->print(out); 1634 switch (scale()) { 1635 case times_1: break; 1636 case times_2: out->print(" * 2"); break; 1637 case times_4: out->print(" * 4"); break; 1638 case times_8: out->print(" * 8"); break; 1639 } 1640 } 1641 out->print(" Disp: " INTX_FORMAT, _disp); 1642} 1643 1644// debug output of block header without InstructionPrinter 1645// (because phi functions are not necessary for LIR) 1646static void print_block(BlockBegin* x) { 1647 // print block id 1648 BlockEnd* end = x->end(); 1649 tty->print("B%d ", x->block_id()); 1650 1651 // print flags 1652 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std "); 1653 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr "); 1654 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex "); 1655 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr "); 1656 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb "); 1657 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh "); 1658 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le "); 1659 1660 // print block bci range 1661 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci())); 1662 1663 // print predecessors and successors 1664 if (x->number_of_preds() > 0) { 1665 tty->print("preds: "); 1666 for (int i = 0; i < x->number_of_preds(); i ++) { 1667 tty->print("B%d ", x->pred_at(i)->block_id()); 1668 } 1669 } 1670 1671 if (x->number_of_sux() > 0) { 1672 tty->print("sux: "); 1673 for (int i = 0; i < x->number_of_sux(); i ++) { 1674 tty->print("B%d ", x->sux_at(i)->block_id()); 1675 } 1676 } 1677 1678 // print exception handlers 1679 if (x->number_of_exception_handlers() > 0) { 1680 tty->print("xhandler: "); 1681 for (int i = 0; i < x->number_of_exception_handlers(); i++) { 1682 tty->print("B%d ", x->exception_handler_at(i)->block_id()); 1683 } 1684 } 1685 1686 tty->cr(); 1687} 1688 1689void print_LIR(BlockList* blocks) { 1690 tty->print_cr("LIR:"); 1691 int i; 1692 for (i = 0; i < blocks->length(); i++) { 1693 BlockBegin* bb = blocks->at(i); 1694 print_block(bb); 1695 tty->print("__id_Instruction___________________________________________"); tty->cr(); 1696 bb->lir()->print_instructions(); 1697 } 1698} 1699 1700void LIR_List::print_instructions() { 1701 for (int i = 0; i < _operations.length(); i++) { 1702 _operations.at(i)->print(); tty->cr(); 1703 } 1704 tty->cr(); 1705} 1706 1707// LIR_Ops printing routines 1708// LIR_Op 1709void LIR_Op::print_on(outputStream* out) const { 1710 if (id() != -1 || PrintCFGToFile) { 1711 out->print("%4d ", id()); 1712 } else { 1713 out->print(" "); 1714 } 1715 out->print("%s ", name()); 1716 print_instr(out); 1717 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci()); 1718#ifdef ASSERT 1719 if (Verbose && _file != NULL) { 1720 out->print(" (%s:%d)", _file, _line); 1721 } 1722#endif 1723} 1724 1725const char * LIR_Op::name() const { 1726 const char* s = NULL; 1727 switch(code()) { 1728 // LIR_Op0 1729 case lir_membar: s = "membar"; break; 1730 case lir_membar_acquire: s = "membar_acquire"; break; 1731 case lir_membar_release: s = "membar_release"; break; 1732 case lir_membar_loadload: s = "membar_loadload"; break; 1733 case lir_membar_storestore: s = "membar_storestore"; break; 1734 case lir_membar_loadstore: s = "membar_loadstore"; break; 1735 case lir_membar_storeload: s = "membar_storeload"; break; 1736 case lir_word_align: s = "word_align"; break; 1737 case lir_label: s = "label"; break; 1738 case lir_nop: s = "nop"; break; 1739 case lir_backwardbranch_target: s = "backbranch"; break; 1740 case lir_std_entry: s = "std_entry"; break; 1741 case lir_osr_entry: s = "osr_entry"; break; 1742 case lir_build_frame: s = "build_frm"; break; 1743 case lir_fpop_raw: s = "fpop_raw"; break; 1744 case lir_24bit_FPU: s = "24bit_FPU"; break; 1745 case lir_reset_FPU: s = "reset_FPU"; break; 1746 case lir_breakpoint: s = "breakpoint"; break; 1747 case lir_get_thread: s = "get_thread"; break; 1748 // LIR_Op1 1749 case lir_fxch: s = "fxch"; break; 1750 case lir_fld: s = "fld"; break; 1751 case lir_ffree: s = "ffree"; break; 1752 case lir_push: s = "push"; break; 1753 case lir_pop: s = "pop"; break; 1754 case lir_null_check: s = "null_check"; break; 1755 case lir_return: s = "return"; break; 1756 case lir_safepoint: s = "safepoint"; break; 1757 case lir_neg: s = "neg"; break; 1758 case lir_leal: s = "leal"; break; 1759 case lir_branch: s = "branch"; break; 1760 case lir_cond_float_branch: s = "flt_cond_br"; break; 1761 case lir_move: s = "move"; break; 1762 case lir_roundfp: s = "roundfp"; break; 1763 case lir_rtcall: s = "rtcall"; break; 1764 case lir_throw: s = "throw"; break; 1765 case lir_unwind: s = "unwind"; break; 1766 case lir_convert: s = "convert"; break; 1767 case lir_alloc_object: s = "alloc_obj"; break; 1768 case lir_monaddr: s = "mon_addr"; break; 1769 case lir_pack64: s = "pack64"; break; 1770 case lir_unpack64: s = "unpack64"; break; 1771 // LIR_Op2 1772 case lir_cmp: s = "cmp"; break; 1773 case lir_cmp_l2i: s = "cmp_l2i"; break; 1774 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break; 1775 case lir_cmp_fd2i: s = "comp_fd2i"; break; 1776 case lir_cmove: s = "cmove"; break; 1777 case lir_add: s = "add"; break; 1778 case lir_sub: s = "sub"; break; 1779 case lir_mul: s = "mul"; break; 1780 case lir_mul_strictfp: s = "mul_strictfp"; break; 1781 case lir_div: s = "div"; break; 1782 case lir_div_strictfp: s = "div_strictfp"; break; 1783 case lir_rem: s = "rem"; break; 1784 case lir_abs: s = "abs"; break; 1785 case lir_sqrt: s = "sqrt"; break; 1786 case lir_sin: s = "sin"; break; 1787 case lir_cos: s = "cos"; break; 1788 case lir_tan: s = "tan"; break; 1789 case lir_log: s = "log"; break; 1790 case lir_log10: s = "log10"; break; 1791 case lir_exp: s = "exp"; break; 1792 case lir_pow: s = "pow"; break; 1793 case lir_logic_and: s = "logic_and"; break; 1794 case lir_logic_or: s = "logic_or"; break; 1795 case lir_logic_xor: s = "logic_xor"; break; 1796 case lir_shl: s = "shift_left"; break; 1797 case lir_shr: s = "shift_right"; break; 1798 case lir_ushr: s = "ushift_right"; break; 1799 case lir_alloc_array: s = "alloc_array"; break; 1800 case lir_xadd: s = "xadd"; break; 1801 case lir_xchg: s = "xchg"; break; 1802 // LIR_Op3 1803 case lir_idiv: s = "idiv"; break; 1804 case lir_irem: s = "irem"; break; 1805 // LIR_OpJavaCall 1806 case lir_static_call: s = "static"; break; 1807 case lir_optvirtual_call: s = "optvirtual"; break; 1808 case lir_icvirtual_call: s = "icvirtual"; break; 1809 case lir_virtual_call: s = "virtual"; break; 1810 case lir_dynamic_call: s = "dynamic"; break; 1811 // LIR_OpArrayCopy 1812 case lir_arraycopy: s = "arraycopy"; break; 1813 // LIR_OpUpdateCRC32 1814 case lir_updatecrc32: s = "updatecrc32"; break; 1815 // LIR_OpLock 1816 case lir_lock: s = "lock"; break; 1817 case lir_unlock: s = "unlock"; break; 1818 // LIR_OpDelay 1819 case lir_delay_slot: s = "delay"; break; 1820 // LIR_OpTypeCheck 1821 case lir_instanceof: s = "instanceof"; break; 1822 case lir_checkcast: s = "checkcast"; break; 1823 case lir_store_check: s = "store_check"; break; 1824 // LIR_OpCompareAndSwap 1825 case lir_cas_long: s = "cas_long"; break; 1826 case lir_cas_obj: s = "cas_obj"; break; 1827 case lir_cas_int: s = "cas_int"; break; 1828 // LIR_OpProfileCall 1829 case lir_profile_call: s = "profile_call"; break; 1830 // LIR_OpProfileType 1831 case lir_profile_type: s = "profile_type"; break; 1832 // LIR_OpAssert 1833#ifdef ASSERT 1834 case lir_assert: s = "assert"; break; 1835#endif 1836 case lir_none: ShouldNotReachHere();break; 1837 default: s = "illegal_op"; break; 1838 } 1839 return s; 1840} 1841 1842// LIR_OpJavaCall 1843void LIR_OpJavaCall::print_instr(outputStream* out) const { 1844 out->print("call: "); 1845 out->print("[addr: " INTPTR_FORMAT "]", p2i(address())); 1846 if (receiver()->is_valid()) { 1847 out->print(" [recv: "); receiver()->print(out); out->print("]"); 1848 } 1849 if (result_opr()->is_valid()) { 1850 out->print(" [result: "); result_opr()->print(out); out->print("]"); 1851 } 1852} 1853 1854// LIR_OpLabel 1855void LIR_OpLabel::print_instr(outputStream* out) const { 1856 out->print("[label:" INTPTR_FORMAT "]", p2i(_label)); 1857} 1858 1859// LIR_OpArrayCopy 1860void LIR_OpArrayCopy::print_instr(outputStream* out) const { 1861 src()->print(out); out->print(" "); 1862 src_pos()->print(out); out->print(" "); 1863 dst()->print(out); out->print(" "); 1864 dst_pos()->print(out); out->print(" "); 1865 length()->print(out); out->print(" "); 1866 tmp()->print(out); out->print(" "); 1867} 1868 1869// LIR_OpUpdateCRC32 1870void LIR_OpUpdateCRC32::print_instr(outputStream* out) const { 1871 crc()->print(out); out->print(" "); 1872 val()->print(out); out->print(" "); 1873 result_opr()->print(out); out->print(" "); 1874} 1875 1876// LIR_OpCompareAndSwap 1877void LIR_OpCompareAndSwap::print_instr(outputStream* out) const { 1878 addr()->print(out); out->print(" "); 1879 cmp_value()->print(out); out->print(" "); 1880 new_value()->print(out); out->print(" "); 1881 tmp1()->print(out); out->print(" "); 1882 tmp2()->print(out); out->print(" "); 1883 1884} 1885 1886// LIR_Op0 1887void LIR_Op0::print_instr(outputStream* out) const { 1888 result_opr()->print(out); 1889} 1890 1891// LIR_Op1 1892const char * LIR_Op1::name() const { 1893 if (code() == lir_move) { 1894 switch (move_kind()) { 1895 case lir_move_normal: 1896 return "move"; 1897 case lir_move_unaligned: 1898 return "unaligned move"; 1899 case lir_move_volatile: 1900 return "volatile_move"; 1901 case lir_move_wide: 1902 return "wide_move"; 1903 default: 1904 ShouldNotReachHere(); 1905 return "illegal_op"; 1906 } 1907 } else { 1908 return LIR_Op::name(); 1909 } 1910} 1911 1912 1913void LIR_Op1::print_instr(outputStream* out) const { 1914 _opr->print(out); out->print(" "); 1915 result_opr()->print(out); out->print(" "); 1916 print_patch_code(out, patch_code()); 1917} 1918 1919 1920// LIR_Op1 1921void LIR_OpRTCall::print_instr(outputStream* out) const { 1922 intx a = (intx)addr(); 1923 out->print("%s", Runtime1::name_for_address(addr())); 1924 out->print(" "); 1925 tmp()->print(out); 1926} 1927 1928void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) { 1929 switch(code) { 1930 case lir_patch_none: break; 1931 case lir_patch_low: out->print("[patch_low]"); break; 1932 case lir_patch_high: out->print("[patch_high]"); break; 1933 case lir_patch_normal: out->print("[patch_normal]"); break; 1934 default: ShouldNotReachHere(); 1935 } 1936} 1937 1938// LIR_OpBranch 1939void LIR_OpBranch::print_instr(outputStream* out) const { 1940 print_condition(out, cond()); out->print(" "); 1941 if (block() != NULL) { 1942 out->print("[B%d] ", block()->block_id()); 1943 } else if (stub() != NULL) { 1944 out->print("["); 1945 stub()->print_name(out); 1946 out->print(": " INTPTR_FORMAT "]", p2i(stub())); 1947 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci()); 1948 } else { 1949 out->print("[label:" INTPTR_FORMAT "] ", p2i(label())); 1950 } 1951 if (ublock() != NULL) { 1952 out->print("unordered: [B%d] ", ublock()->block_id()); 1953 } 1954} 1955 1956void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) { 1957 switch(cond) { 1958 case lir_cond_equal: out->print("[EQ]"); break; 1959 case lir_cond_notEqual: out->print("[NE]"); break; 1960 case lir_cond_less: out->print("[LT]"); break; 1961 case lir_cond_lessEqual: out->print("[LE]"); break; 1962 case lir_cond_greaterEqual: out->print("[GE]"); break; 1963 case lir_cond_greater: out->print("[GT]"); break; 1964 case lir_cond_belowEqual: out->print("[BE]"); break; 1965 case lir_cond_aboveEqual: out->print("[AE]"); break; 1966 case lir_cond_always: out->print("[AL]"); break; 1967 default: out->print("[%d]",cond); break; 1968 } 1969} 1970 1971// LIR_OpConvert 1972void LIR_OpConvert::print_instr(outputStream* out) const { 1973 print_bytecode(out, bytecode()); 1974 in_opr()->print(out); out->print(" "); 1975 result_opr()->print(out); out->print(" "); 1976#ifdef PPC 1977 if(tmp1()->is_valid()) { 1978 tmp1()->print(out); out->print(" "); 1979 tmp2()->print(out); out->print(" "); 1980 } 1981#endif 1982} 1983 1984void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) { 1985 switch(code) { 1986 case Bytecodes::_d2f: out->print("[d2f] "); break; 1987 case Bytecodes::_d2i: out->print("[d2i] "); break; 1988 case Bytecodes::_d2l: out->print("[d2l] "); break; 1989 case Bytecodes::_f2d: out->print("[f2d] "); break; 1990 case Bytecodes::_f2i: out->print("[f2i] "); break; 1991 case Bytecodes::_f2l: out->print("[f2l] "); break; 1992 case Bytecodes::_i2b: out->print("[i2b] "); break; 1993 case Bytecodes::_i2c: out->print("[i2c] "); break; 1994 case Bytecodes::_i2d: out->print("[i2d] "); break; 1995 case Bytecodes::_i2f: out->print("[i2f] "); break; 1996 case Bytecodes::_i2l: out->print("[i2l] "); break; 1997 case Bytecodes::_i2s: out->print("[i2s] "); break; 1998 case Bytecodes::_l2i: out->print("[l2i] "); break; 1999 case Bytecodes::_l2f: out->print("[l2f] "); break; 2000 case Bytecodes::_l2d: out->print("[l2d] "); break; 2001 default: 2002 out->print("[?%d]",code); 2003 break; 2004 } 2005} 2006 2007void LIR_OpAllocObj::print_instr(outputStream* out) const { 2008 klass()->print(out); out->print(" "); 2009 obj()->print(out); out->print(" "); 2010 tmp1()->print(out); out->print(" "); 2011 tmp2()->print(out); out->print(" "); 2012 tmp3()->print(out); out->print(" "); 2013 tmp4()->print(out); out->print(" "); 2014 out->print("[hdr:%d]", header_size()); out->print(" "); 2015 out->print("[obj:%d]", object_size()); out->print(" "); 2016 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2017} 2018 2019void LIR_OpRoundFP::print_instr(outputStream* out) const { 2020 _opr->print(out); out->print(" "); 2021 tmp()->print(out); out->print(" "); 2022 result_opr()->print(out); out->print(" "); 2023} 2024 2025// LIR_Op2 2026void LIR_Op2::print_instr(outputStream* out) const { 2027 if (code() == lir_cmove) { 2028 print_condition(out, condition()); out->print(" "); 2029 } 2030 in_opr1()->print(out); out->print(" "); 2031 in_opr2()->print(out); out->print(" "); 2032 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); } 2033 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); } 2034 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); } 2035 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); } 2036 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); } 2037 result_opr()->print(out); 2038} 2039 2040void LIR_OpAllocArray::print_instr(outputStream* out) const { 2041 klass()->print(out); out->print(" "); 2042 len()->print(out); out->print(" "); 2043 obj()->print(out); out->print(" "); 2044 tmp1()->print(out); out->print(" "); 2045 tmp2()->print(out); out->print(" "); 2046 tmp3()->print(out); out->print(" "); 2047 tmp4()->print(out); out->print(" "); 2048 out->print("[type:0x%x]", type()); out->print(" "); 2049 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2050} 2051 2052 2053void LIR_OpTypeCheck::print_instr(outputStream* out) const { 2054 object()->print(out); out->print(" "); 2055 if (code() == lir_store_check) { 2056 array()->print(out); out->print(" "); 2057 } 2058 if (code() != lir_store_check) { 2059 klass()->print_name_on(out); out->print(" "); 2060 if (fast_check()) out->print("fast_check "); 2061 } 2062 tmp1()->print(out); out->print(" "); 2063 tmp2()->print(out); out->print(" "); 2064 tmp3()->print(out); out->print(" "); 2065 result_opr()->print(out); out->print(" "); 2066 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci()); 2067} 2068 2069 2070// LIR_Op3 2071void LIR_Op3::print_instr(outputStream* out) const { 2072 in_opr1()->print(out); out->print(" "); 2073 in_opr2()->print(out); out->print(" "); 2074 in_opr3()->print(out); out->print(" "); 2075 result_opr()->print(out); 2076} 2077 2078 2079void LIR_OpLock::print_instr(outputStream* out) const { 2080 hdr_opr()->print(out); out->print(" "); 2081 obj_opr()->print(out); out->print(" "); 2082 lock_opr()->print(out); out->print(" "); 2083 if (_scratch->is_valid()) { 2084 _scratch->print(out); out->print(" "); 2085 } 2086 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry())); 2087} 2088 2089#ifdef ASSERT 2090void LIR_OpAssert::print_instr(outputStream* out) const { 2091 print_condition(out, condition()); out->print(" "); 2092 in_opr1()->print(out); out->print(" "); 2093 in_opr2()->print(out); out->print(", \""); 2094 out->print("%s", msg()); out->print("\""); 2095} 2096#endif 2097 2098 2099void LIR_OpDelay::print_instr(outputStream* out) const { 2100 _op->print_on(out); 2101} 2102 2103 2104// LIR_OpProfileCall 2105void LIR_OpProfileCall::print_instr(outputStream* out) const { 2106 profiled_method()->name()->print_symbol_on(out); 2107 out->print("."); 2108 profiled_method()->holder()->name()->print_symbol_on(out); 2109 out->print(" @ %d ", profiled_bci()); 2110 mdo()->print(out); out->print(" "); 2111 recv()->print(out); out->print(" "); 2112 tmp1()->print(out); out->print(" "); 2113} 2114 2115// LIR_OpProfileType 2116void LIR_OpProfileType::print_instr(outputStream* out) const { 2117 out->print("exact = "); exact_klass()->print_name_on(out); 2118 out->print("current = "); ciTypeEntries::print_ciklass(out, current_klass()); 2119 mdp()->print(out); out->print(" "); 2120 obj()->print(out); out->print(" "); 2121 tmp()->print(out); out->print(" "); 2122} 2123 2124#endif // PRODUCT 2125 2126// Implementation of LIR_InsertionBuffer 2127 2128void LIR_InsertionBuffer::append(int index, LIR_Op* op) { 2129 assert(_index_and_count.length() % 2 == 0, "must have a count for each index"); 2130 2131 int i = number_of_insertion_points() - 1; 2132 if (i < 0 || index_at(i) < index) { 2133 append_new(index, 1); 2134 } else { 2135 assert(index_at(i) == index, "can append LIR_Ops in ascending order only"); 2136 assert(count_at(i) > 0, "check"); 2137 set_count_at(i, count_at(i) + 1); 2138 } 2139 _ops.push(op); 2140 2141 DEBUG_ONLY(verify()); 2142} 2143 2144#ifdef ASSERT 2145void LIR_InsertionBuffer::verify() { 2146 int sum = 0; 2147 int prev_idx = -1; 2148 2149 for (int i = 0; i < number_of_insertion_points(); i++) { 2150 assert(prev_idx < index_at(i), "index must be ordered ascending"); 2151 sum += count_at(i); 2152 } 2153 assert(sum == number_of_ops(), "wrong total sum"); 2154} 2155#endif 2156