orderAccess_solaris_sparc.inline.hpp revision 11857:d0fbf661cc16 
1/*
2 * Copyright (c) 2003, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
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23 */
24
25#ifndef OS_CPU_SOLARIS_SPARC_VM_ORDERACCESS_SOLARIS_SPARC_INLINE_HPP
26#define OS_CPU_SOLARIS_SPARC_VM_ORDERACCESS_SOLARIS_SPARC_INLINE_HPP
27
28#include "runtime/atomic.hpp"
29#include "runtime/orderAccess.hpp"
30
31// Compiler version last used for testing: solaris studio 12u3
32// Please update this information when this file changes
33
34// Implementation of class OrderAccess.
35
36// Assume TSO.
37
38// A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions
39inline void compiler_barrier() {
40  __asm__ volatile ("" : : : "memory");
41}
42
43inline void OrderAccess::loadload()   { compiler_barrier(); }
44inline void OrderAccess::storestore() { compiler_barrier(); }
45inline void OrderAccess::loadstore()  { compiler_barrier(); }
46inline void OrderAccess::storeload()  { fence();            }
47
48inline void OrderAccess::acquire()    { compiler_barrier(); }
49inline void OrderAccess::release()    { compiler_barrier(); }
50
51inline void OrderAccess::fence() {
52  __asm__ volatile ("membar  #StoreLoad" : : : "memory");
53}
54
55#define VM_HAS_GENERALIZED_ORDER_ACCESS 1
56
57#endif // OS_CPU_SOLARIS_SPARC_VM_ORDERACCESS_SOLARIS_SPARC_INLINE_HPP
58