x86_32.ad revision 235:9c2ecc2ffb12
1// 2// Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved. 3// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4// 5// This code is free software; you can redistribute it and/or modify it 6// under the terms of the GNU General Public License version 2 only, as 7// published by the Free Software Foundation. 8// 9// This code is distributed in the hope that it will be useful, but WITHOUT 10// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12// version 2 for more details (a copy is included in the LICENSE file that 13// accompanied this code). 14// 15// You should have received a copy of the GNU General Public License version 16// 2 along with this work; if not, write to the Free Software Foundation, 17// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18// 19// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20// CA 95054 USA or visit www.sun.com if you need additional information or 21// have any questions. 22// 23// 24 25// X86 Architecture Description File 26 27//----------REGISTER DEFINITION BLOCK------------------------------------------ 28// This information is used by the matcher and the register allocator to 29// describe individual registers and classes of registers within the target 30// archtecture. 31 32register %{ 33//----------Architecture Description Register Definitions---------------------- 34// General Registers 35// "reg_def" name ( register save type, C convention save type, 36// ideal register type, encoding ); 37// Register Save Types: 38// 39// NS = No-Save: The register allocator assumes that these registers 40// can be used without saving upon entry to the method, & 41// that they do not need to be saved at call sites. 42// 43// SOC = Save-On-Call: The register allocator assumes that these registers 44// can be used without saving upon entry to the method, 45// but that they must be saved at call sites. 46// 47// SOE = Save-On-Entry: The register allocator assumes that these registers 48// must be saved before using them upon entry to the 49// method, but they do not need to be saved at call 50// sites. 51// 52// AS = Always-Save: The register allocator assumes that these registers 53// must be saved before using them upon entry to the 54// method, & that they must be saved at call sites. 55// 56// Ideal Register Type is used to determine how to save & restore a 57// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 58// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 59// 60// The encoding number is the actual bit-pattern placed into the opcodes. 61 62// General Registers 63// Previously set EBX, ESI, and EDI as save-on-entry for java code 64// Turn off SOE in java-code due to frequent use of uncommon-traps. 65// Now that allocator is better, turn on ESI and EDI as SOE registers. 66 67reg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); 68reg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); 69reg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); 70reg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); 71// now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code 72reg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); 73reg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); 74reg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); 75reg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); 76 77// Special Registers 78reg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad()); 79 80// Float registers. We treat TOS/FPR0 special. It is invisible to the 81// allocator, and only shows up in the encodings. 82reg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); 83reg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); 84// Ok so here's the trick FPR1 is really st(0) except in the midst 85// of emission of assembly for a machnode. During the emission the fpu stack 86// is pushed making FPR1 == st(1) temporarily. However at any safepoint 87// the stack will not have this element so FPR1 == st(0) from the 88// oopMap viewpoint. This same weirdness with numbering causes 89// instruction encoding to have to play games with the register 90// encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation 91// where it does flt->flt moves to see an example 92// 93reg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); 94reg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); 95reg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); 96reg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); 97reg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); 98reg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); 99reg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); 100reg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); 101reg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); 102reg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); 103reg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); 104reg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); 105reg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); 106reg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); 107 108// XMM registers. 128-bit registers or 4 words each, labeled a-d. 109// Word a in each register holds a Float, words ab hold a Double. 110// We currently do not use the SIMD capabilities, so registers cd 111// are unused at the moment. 112reg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); 113reg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); 114reg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); 115reg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); 116reg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); 117reg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); 118reg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); 119reg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); 120reg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); 121reg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); 122reg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); 123reg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); 124reg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); 125reg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); 126reg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); 127reg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); 128 129// Specify priority of register selection within phases of register 130// allocation. Highest priority is first. A useful heuristic is to 131// give registers a low priority when they are required by machine 132// instructions, like EAX and EDX. Registers which are used as 133// pairs must fall on an even boundry (witness the FPR#L's in this list). 134// For the Intel integer registers, the equivalent Long pairs are 135// EDX:EAX, EBX:ECX, and EDI:EBP. 136alloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, 137 FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, 138 FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, 139 FPR6L, FPR6H, FPR7L, FPR7H ); 140 141alloc_class chunk1( XMM0a, XMM0b, 142 XMM1a, XMM1b, 143 XMM2a, XMM2b, 144 XMM3a, XMM3b, 145 XMM4a, XMM4b, 146 XMM5a, XMM5b, 147 XMM6a, XMM6b, 148 XMM7a, XMM7b, EFLAGS); 149 150 151//----------Architecture Description Register Classes-------------------------- 152// Several register classes are automatically defined based upon information in 153// this architecture description. 154// 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) 155// 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) 156// 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) 157// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 158// 159// Class for all registers 160reg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); 161// Class for general registers 162reg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); 163// Class for general registers which may be used for implicit null checks on win95 164// Also safe for use by tailjump. We don't want to allocate in rbp, 165reg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); 166// Class of "X" registers 167reg_class x_reg(EBX, ECX, EDX, EAX); 168// Class of registers that can appear in an address with no offset. 169// EBP and ESP require an extra instruction byte for zero offset. 170// Used in fast-unlock 171reg_class p_reg(EDX, EDI, ESI, EBX); 172// Class for general registers not including ECX 173reg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); 174// Class for general registers not including EAX 175reg_class nax_reg(EDX, EDI, ESI, ECX, EBX); 176// Class for general registers not including EAX or EBX. 177reg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); 178// Class of EAX (for multiply and divide operations) 179reg_class eax_reg(EAX); 180// Class of EBX (for atomic add) 181reg_class ebx_reg(EBX); 182// Class of ECX (for shift and JCXZ operations and cmpLTMask) 183reg_class ecx_reg(ECX); 184// Class of EDX (for multiply and divide operations) 185reg_class edx_reg(EDX); 186// Class of EDI (for synchronization) 187reg_class edi_reg(EDI); 188// Class of ESI (for synchronization) 189reg_class esi_reg(ESI); 190// Singleton class for interpreter's stack pointer 191reg_class ebp_reg(EBP); 192// Singleton class for stack pointer 193reg_class sp_reg(ESP); 194// Singleton class for instruction pointer 195// reg_class ip_reg(EIP); 196// Singleton class for condition codes 197reg_class int_flags(EFLAGS); 198// Class of integer register pairs 199reg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); 200// Class of integer register pairs that aligns with calling convention 201reg_class eadx_reg( EAX,EDX ); 202reg_class ebcx_reg( ECX,EBX ); 203// Not AX or DX, used in divides 204reg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); 205 206// Floating point registers. Notice FPR0 is not a choice. 207// FPR0 is not ever allocated; we use clever encodings to fake 208// a 2-address instructions out of Intels FP stack. 209reg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); 210 211// make a register class for SSE registers 212reg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a); 213 214// make a double register class for SSE2 registers 215reg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b, 216 XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b ); 217 218reg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, 219 FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, 220 FPR7L,FPR7H ); 221 222reg_class flt_reg0( FPR1L ); 223reg_class dbl_reg0( FPR1L,FPR1H ); 224reg_class dbl_reg1( FPR2L,FPR2H ); 225reg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, 226 FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); 227 228// XMM6 and XMM7 could be used as temporary registers for long, float and 229// double values for SSE2. 230reg_class xdb_reg6( XMM6a,XMM6b ); 231reg_class xdb_reg7( XMM7a,XMM7b ); 232%} 233 234 235//----------SOURCE BLOCK------------------------------------------------------- 236// This is a block of C++ code which provides values, functions, and 237// definitions necessary in the rest of the architecture description 238source %{ 239#define RELOC_IMM32 Assembler::imm32_operand 240#define RELOC_DISP32 Assembler::disp32_operand 241 242#define __ _masm. 243 244// How to find the high register of a Long pair, given the low register 245#define HIGH_FROM_LOW(x) ((x)+2) 246 247// These masks are used to provide 128-bit aligned bitmasks to the XMM 248// instructions, to allow sign-masking or sign-bit flipping. They allow 249// fast versions of NegF/NegD and AbsF/AbsD. 250 251// Note: 'double' and 'long long' have 32-bits alignment on x86. 252static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 253 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 254 // of 128-bits operands for SSE instructions. 255 jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); 256 // Store the value to a 128-bits operand. 257 operand[0] = lo; 258 operand[1] = hi; 259 return operand; 260} 261 262// Buffer for 128-bits masks used by SSE instructions. 263static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 264 265// Static initialization during VM startup. 266static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 267static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 268static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); 269static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); 270 271// !!!!! Special hack to get all type of calls to specify the byte offset 272// from the start of the call to the point where the return address 273// will point. 274int MachCallStaticJavaNode::ret_addr_offset() { 275 return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points 276} 277 278int MachCallDynamicJavaNode::ret_addr_offset() { 279 return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points 280} 281 282static int sizeof_FFree_Float_Stack_All = -1; 283 284int MachCallRuntimeNode::ret_addr_offset() { 285 assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); 286 return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); 287} 288 289// Indicate if the safepoint node needs the polling page as an input. 290// Since x86 does have absolute addressing, it doesn't. 291bool SafePointNode::needs_polling_address_input() { 292 return false; 293} 294 295// 296// Compute padding required for nodes which need alignment 297// 298 299// The address of the call instruction needs to be 4-byte aligned to 300// ensure that it does not span a cache line so that it can be patched. 301int CallStaticJavaDirectNode::compute_padding(int current_offset) const { 302 if (Compile::current()->in_24_bit_fp_mode()) 303 current_offset += 6; // skip fldcw in pre_call_FPU, if any 304 current_offset += 1; // skip call opcode byte 305 return round_to(current_offset, alignment_required()) - current_offset; 306} 307 308// The address of the call instruction needs to be 4-byte aligned to 309// ensure that it does not span a cache line so that it can be patched. 310int CallDynamicJavaDirectNode::compute_padding(int current_offset) const { 311 if (Compile::current()->in_24_bit_fp_mode()) 312 current_offset += 6; // skip fldcw in pre_call_FPU, if any 313 current_offset += 5; // skip MOV instruction 314 current_offset += 1; // skip call opcode byte 315 return round_to(current_offset, alignment_required()) - current_offset; 316} 317 318#ifndef PRODUCT 319void MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const { 320 st->print("INT3"); 321} 322#endif 323 324// EMIT_RM() 325void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { 326 unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); 327 *(cbuf.code_end()) = c; 328 cbuf.set_code_end(cbuf.code_end() + 1); 329} 330 331// EMIT_CC() 332void emit_cc(CodeBuffer &cbuf, int f1, int f2) { 333 unsigned char c = (unsigned char)( f1 | f2 ); 334 *(cbuf.code_end()) = c; 335 cbuf.set_code_end(cbuf.code_end() + 1); 336} 337 338// EMIT_OPCODE() 339void emit_opcode(CodeBuffer &cbuf, int code) { 340 *(cbuf.code_end()) = (unsigned char)code; 341 cbuf.set_code_end(cbuf.code_end() + 1); 342} 343 344// EMIT_OPCODE() w/ relocation information 345void emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { 346 cbuf.relocate(cbuf.inst_mark() + offset, reloc); 347 emit_opcode(cbuf, code); 348} 349 350// EMIT_D8() 351void emit_d8(CodeBuffer &cbuf, int d8) { 352 *(cbuf.code_end()) = (unsigned char)d8; 353 cbuf.set_code_end(cbuf.code_end() + 1); 354} 355 356// EMIT_D16() 357void emit_d16(CodeBuffer &cbuf, int d16) { 358 *((short *)(cbuf.code_end())) = d16; 359 cbuf.set_code_end(cbuf.code_end() + 2); 360} 361 362// EMIT_D32() 363void emit_d32(CodeBuffer &cbuf, int d32) { 364 *((int *)(cbuf.code_end())) = d32; 365 cbuf.set_code_end(cbuf.code_end() + 4); 366} 367 368// emit 32 bit value and construct relocation entry from relocInfo::relocType 369void emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, 370 int format) { 371 cbuf.relocate(cbuf.inst_mark(), reloc, format); 372 373 *((int *)(cbuf.code_end())) = d32; 374 cbuf.set_code_end(cbuf.code_end() + 4); 375} 376 377// emit 32 bit value and construct relocation entry from RelocationHolder 378void emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, 379 int format) { 380#ifdef ASSERT 381 if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { 382 assert(oop(d32)->is_oop() && oop(d32)->is_perm(), "cannot embed non-perm oops in code"); 383 } 384#endif 385 cbuf.relocate(cbuf.inst_mark(), rspec, format); 386 387 *((int *)(cbuf.code_end())) = d32; 388 cbuf.set_code_end(cbuf.code_end() + 4); 389} 390 391// Access stack slot for load or store 392void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { 393 emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) 394 if( -128 <= disp && disp <= 127 ) { 395 emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte 396 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 397 emit_d8 (cbuf, disp); // Displacement // R/M byte 398 } else { 399 emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte 400 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 401 emit_d32(cbuf, disp); // Displacement // R/M byte 402 } 403} 404 405 // eRegI ereg, memory mem) %{ // emit_reg_mem 406void encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) { 407 // There is no index & no scale, use form without SIB byte 408 if ((index == 0x4) && 409 (scale == 0) && (base != ESP_enc)) { 410 // If no displacement, mode is 0x0; unless base is [EBP] 411 if ( (displace == 0) && (base != EBP_enc) ) { 412 emit_rm(cbuf, 0x0, reg_encoding, base); 413 } 414 else { // If 8-bit displacement, mode 0x1 415 if ((displace >= -128) && (displace <= 127) 416 && !(displace_is_oop) ) { 417 emit_rm(cbuf, 0x1, reg_encoding, base); 418 emit_d8(cbuf, displace); 419 } 420 else { // If 32-bit displacement 421 if (base == -1) { // Special flag for absolute address 422 emit_rm(cbuf, 0x0, reg_encoding, 0x5); 423 // (manual lies; no SIB needed here) 424 if ( displace_is_oop ) { 425 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 426 } else { 427 emit_d32 (cbuf, displace); 428 } 429 } 430 else { // Normal base + offset 431 emit_rm(cbuf, 0x2, reg_encoding, base); 432 if ( displace_is_oop ) { 433 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 434 } else { 435 emit_d32 (cbuf, displace); 436 } 437 } 438 } 439 } 440 } 441 else { // Else, encode with the SIB byte 442 // If no displacement, mode is 0x0; unless base is [EBP] 443 if (displace == 0 && (base != EBP_enc)) { // If no displacement 444 emit_rm(cbuf, 0x0, reg_encoding, 0x4); 445 emit_rm(cbuf, scale, index, base); 446 } 447 else { // If 8-bit displacement, mode 0x1 448 if ((displace >= -128) && (displace <= 127) 449 && !(displace_is_oop) ) { 450 emit_rm(cbuf, 0x1, reg_encoding, 0x4); 451 emit_rm(cbuf, scale, index, base); 452 emit_d8(cbuf, displace); 453 } 454 else { // If 32-bit displacement 455 if (base == 0x04 ) { 456 emit_rm(cbuf, 0x2, reg_encoding, 0x4); 457 emit_rm(cbuf, scale, index, 0x04); 458 } else { 459 emit_rm(cbuf, 0x2, reg_encoding, 0x4); 460 emit_rm(cbuf, scale, index, base); 461 } 462 if ( displace_is_oop ) { 463 emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 464 } else { 465 emit_d32 (cbuf, displace); 466 } 467 } 468 } 469 } 470} 471 472 473void encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { 474 if( dst_encoding == src_encoding ) { 475 // reg-reg copy, use an empty encoding 476 } else { 477 emit_opcode( cbuf, 0x8B ); 478 emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); 479 } 480} 481 482void encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { 483 if( dst_encoding == src_encoding ) { 484 // reg-reg copy, use an empty encoding 485 } else { 486 MacroAssembler _masm(&cbuf); 487 488 __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding)); 489 } 490} 491 492 493//============================================================================= 494#ifndef PRODUCT 495void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 496 Compile* C = ra_->C; 497 if( C->in_24_bit_fp_mode() ) { 498 tty->print("FLDCW 24 bit fpu control word"); 499 tty->print_cr(""); tty->print("\t"); 500 } 501 502 int framesize = C->frame_slots() << LogBytesPerInt; 503 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 504 // Remove two words for return addr and rbp, 505 framesize -= 2*wordSize; 506 507 // Calls to C2R adapters often do not accept exceptional returns. 508 // We require that their callers must bang for them. But be careful, because 509 // some VM calls (such as call site linkage) can use several kilobytes of 510 // stack. But the stack safety zone should account for that. 511 // See bugs 4446381, 4468289, 4497237. 512 if (C->need_stack_bang(framesize)) { 513 tty->print_cr("# stack bang"); tty->print("\t"); 514 } 515 tty->print_cr("PUSHL EBP"); tty->print("\t"); 516 517 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth 518 tty->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check"); 519 tty->print_cr(""); tty->print("\t"); 520 framesize -= wordSize; 521 } 522 523 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { 524 if (framesize) { 525 tty->print("SUB ESP,%d\t# Create frame",framesize); 526 } 527 } else { 528 tty->print("SUB ESP,%d\t# Create frame",framesize); 529 } 530} 531#endif 532 533 534void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 535 Compile* C = ra_->C; 536 537 if (UseSSE >= 2 && VerifyFPU) { 538 MacroAssembler masm(&cbuf); 539 masm.verify_FPU(0, "FPU stack must be clean on entry"); 540 } 541 542 // WARNING: Initial instruction MUST be 5 bytes or longer so that 543 // NativeJump::patch_verified_entry will be able to patch out the entry 544 // code safely. The fldcw is ok at 6 bytes, the push to verify stack 545 // depth is ok at 5 bytes, the frame allocation can be either 3 or 546 // 6 bytes. So if we don't do the fldcw or the push then we must 547 // use the 6 byte frame allocation even if we have no frame. :-( 548 // If method sets FPU control word do it now 549 if( C->in_24_bit_fp_mode() ) { 550 MacroAssembler masm(&cbuf); 551 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 552 } 553 554 int framesize = C->frame_slots() << LogBytesPerInt; 555 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 556 // Remove two words for return addr and rbp, 557 framesize -= 2*wordSize; 558 559 // Calls to C2R adapters often do not accept exceptional returns. 560 // We require that their callers must bang for them. But be careful, because 561 // some VM calls (such as call site linkage) can use several kilobytes of 562 // stack. But the stack safety zone should account for that. 563 // See bugs 4446381, 4468289, 4497237. 564 if (C->need_stack_bang(framesize)) { 565 MacroAssembler masm(&cbuf); 566 masm.generate_stack_overflow_check(framesize); 567 } 568 569 // We always push rbp, so that on return to interpreter rbp, will be 570 // restored correctly and we can correct the stack. 571 emit_opcode(cbuf, 0x50 | EBP_enc); 572 573 if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth 574 emit_opcode(cbuf, 0x68); // push 0xbadb100d 575 emit_d32(cbuf, 0xbadb100d); 576 framesize -= wordSize; 577 } 578 579 if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { 580 if (framesize) { 581 emit_opcode(cbuf, 0x83); // sub SP,#framesize 582 emit_rm(cbuf, 0x3, 0x05, ESP_enc); 583 emit_d8(cbuf, framesize); 584 } 585 } else { 586 emit_opcode(cbuf, 0x81); // sub SP,#framesize 587 emit_rm(cbuf, 0x3, 0x05, ESP_enc); 588 emit_d32(cbuf, framesize); 589 } 590 C->set_frame_complete(cbuf.code_end() - cbuf.code_begin()); 591 592#ifdef ASSERT 593 if (VerifyStackAtCalls) { 594 Label L; 595 MacroAssembler masm(&cbuf); 596 masm.pushl(rax); 597 masm.movl(rax, rsp); 598 masm.andl(rax, StackAlignmentInBytes-1); 599 masm.cmpl(rax, StackAlignmentInBytes-wordSize); 600 masm.popl(rax); 601 masm.jcc(Assembler::equal, L); 602 masm.stop("Stack is not properly aligned!"); 603 masm.bind(L); 604 } 605#endif 606 607} 608 609uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 610 return MachNode::size(ra_); // too many variables; just compute it the hard way 611} 612 613int MachPrologNode::reloc() const { 614 return 0; // a large enough number 615} 616 617//============================================================================= 618#ifndef PRODUCT 619void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 620 Compile *C = ra_->C; 621 int framesize = C->frame_slots() << LogBytesPerInt; 622 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 623 // Remove two words for return addr and rbp, 624 framesize -= 2*wordSize; 625 626 if( C->in_24_bit_fp_mode() ) { 627 st->print("FLDCW standard control word"); 628 st->cr(); st->print("\t"); 629 } 630 if( framesize ) { 631 st->print("ADD ESP,%d\t# Destroy frame",framesize); 632 st->cr(); st->print("\t"); 633 } 634 st->print_cr("POPL EBP"); st->print("\t"); 635 if( do_polling() && C->is_method_compilation() ) { 636 st->print("TEST PollPage,EAX\t! Poll Safepoint"); 637 st->cr(); st->print("\t"); 638 } 639} 640#endif 641 642void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 643 Compile *C = ra_->C; 644 645 // If method set FPU control word, restore to standard control word 646 if( C->in_24_bit_fp_mode() ) { 647 MacroAssembler masm(&cbuf); 648 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 649 } 650 651 int framesize = C->frame_slots() << LogBytesPerInt; 652 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 653 // Remove two words for return addr and rbp, 654 framesize -= 2*wordSize; 655 656 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here 657 658 if( framesize >= 128 ) { 659 emit_opcode(cbuf, 0x81); // add SP, #framesize 660 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 661 emit_d32(cbuf, framesize); 662 } 663 else if( framesize ) { 664 emit_opcode(cbuf, 0x83); // add SP, #framesize 665 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 666 emit_d8(cbuf, framesize); 667 } 668 669 emit_opcode(cbuf, 0x58 | EBP_enc); 670 671 if( do_polling() && C->is_method_compilation() ) { 672 cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0); 673 emit_opcode(cbuf,0x85); 674 emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX 675 emit_d32(cbuf, (intptr_t)os::get_polling_page()); 676 } 677} 678 679uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 680 Compile *C = ra_->C; 681 // If method set FPU control word, restore to standard control word 682 int size = C->in_24_bit_fp_mode() ? 6 : 0; 683 if( do_polling() && C->is_method_compilation() ) size += 6; 684 685 int framesize = C->frame_slots() << LogBytesPerInt; 686 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 687 // Remove two words for return addr and rbp, 688 framesize -= 2*wordSize; 689 690 size++; // popl rbp, 691 692 if( framesize >= 128 ) { 693 size += 6; 694 } else { 695 size += framesize ? 3 : 0; 696 } 697 return size; 698} 699 700int MachEpilogNode::reloc() const { 701 return 0; // a large enough number 702} 703 704const Pipeline * MachEpilogNode::pipeline() const { 705 return MachNode::pipeline_class(); 706} 707 708int MachEpilogNode::safepoint_offset() const { return 0; } 709 710//============================================================================= 711 712enum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; 713static enum RC rc_class( OptoReg::Name reg ) { 714 715 if( !OptoReg::is_valid(reg) ) return rc_bad; 716 if (OptoReg::is_stack(reg)) return rc_stack; 717 718 VMReg r = OptoReg::as_VMReg(reg); 719 if (r->is_Register()) return rc_int; 720 if (r->is_FloatRegister()) { 721 assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); 722 return rc_float; 723 } 724 assert(r->is_XMMRegister(), "must be"); 725 return rc_xmm; 726} 727 728static int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size ) { 729 if( cbuf ) { 730 emit_opcode (*cbuf, opcode ); 731 encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false); 732#ifndef PRODUCT 733 } else if( !do_size ) { 734 if( size != 0 ) tty->print("\n\t"); 735 if( opcode == 0x8B || opcode == 0x89 ) { // MOV 736 if( is_load ) tty->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); 737 else tty->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); 738 } else { // FLD, FST, PUSH, POP 739 tty->print("%s [ESP + #%d]",op_str,offset); 740 } 741#endif 742 } 743 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 744 return size+3+offset_size; 745} 746 747// Helper for XMM registers. Extra opcode bits, limited syntax. 748static int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, 749 int offset, int reg_lo, int reg_hi, int size ) { 750 if( cbuf ) { 751 if( reg_lo+1 == reg_hi ) { // double move? 752 if( is_load && !UseXmmLoadAndClearUpper ) 753 emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load 754 else 755 emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise 756 } else { 757 emit_opcode(*cbuf, 0xF3 ); 758 } 759 emit_opcode(*cbuf, 0x0F ); 760 if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper ) 761 emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load 762 else 763 emit_opcode(*cbuf, is_load ? 0x10 : 0x11 ); 764 encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false); 765#ifndef PRODUCT 766 } else if( !do_size ) { 767 if( size != 0 ) tty->print("\n\t"); 768 if( reg_lo+1 == reg_hi ) { // double move? 769 if( is_load ) tty->print("%s %s,[ESP + #%d]", 770 UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", 771 Matcher::regName[reg_lo], offset); 772 else tty->print("MOVSD [ESP + #%d],%s", 773 offset, Matcher::regName[reg_lo]); 774 } else { 775 if( is_load ) tty->print("MOVSS %s,[ESP + #%d]", 776 Matcher::regName[reg_lo], offset); 777 else tty->print("MOVSS [ESP + #%d],%s", 778 offset, Matcher::regName[reg_lo]); 779 } 780#endif 781 } 782 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 783 return size+5+offset_size; 784} 785 786 787static int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, 788 int src_hi, int dst_hi, int size ) { 789 if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers 790 if( cbuf ) { 791 if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) { 792 emit_opcode(*cbuf, 0x66 ); 793 } 794 emit_opcode(*cbuf, 0x0F ); 795 emit_opcode(*cbuf, 0x28 ); 796 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] ); 797#ifndef PRODUCT 798 } else if( !do_size ) { 799 if( size != 0 ) tty->print("\n\t"); 800 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? 801 tty->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 802 } else { 803 tty->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 804 } 805#endif 806 } 807 return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3); 808 } else { 809 if( cbuf ) { 810 emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 ); 811 emit_opcode(*cbuf, 0x0F ); 812 emit_opcode(*cbuf, 0x10 ); 813 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] ); 814#ifndef PRODUCT 815 } else if( !do_size ) { 816 if( size != 0 ) tty->print("\n\t"); 817 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? 818 tty->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 819 } else { 820 tty->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 821 } 822#endif 823 } 824 return size+4; 825 } 826} 827 828static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size ) { 829 if( cbuf ) { 830 emit_opcode(*cbuf, 0x8B ); 831 emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); 832#ifndef PRODUCT 833 } else if( !do_size ) { 834 if( size != 0 ) tty->print("\n\t"); 835 tty->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); 836#endif 837 } 838 return size+2; 839} 840 841static int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, int offset, int size ) { 842 if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there 843 if( cbuf ) { 844 emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) 845 emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); 846#ifndef PRODUCT 847 } else if( !do_size ) { 848 if( size != 0 ) tty->print("\n\t"); 849 tty->print("FLD %s",Matcher::regName[src_lo]); 850#endif 851 } 852 size += 2; 853 } 854 855 int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; 856 const char *op_str; 857 int op; 858 if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? 859 op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; 860 op = 0xDD; 861 } else { // 32-bit store 862 op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; 863 op = 0xD9; 864 assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); 865 } 866 867 return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size); 868} 869 870uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { 871 // Get registers to move 872 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 873 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 874 OptoReg::Name dst_second = ra_->get_reg_second(this ); 875 OptoReg::Name dst_first = ra_->get_reg_first(this ); 876 877 enum RC src_second_rc = rc_class(src_second); 878 enum RC src_first_rc = rc_class(src_first); 879 enum RC dst_second_rc = rc_class(dst_second); 880 enum RC dst_first_rc = rc_class(dst_first); 881 882 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 883 884 // Generate spill code! 885 int size = 0; 886 887 if( src_first == dst_first && src_second == dst_second ) 888 return size; // Self copy, no move 889 890 // -------------------------------------- 891 // Check for mem-mem move. push/pop to move. 892 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 893 if( src_second == dst_first ) { // overlapping stack copy ranges 894 assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); 895 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size); 896 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size); 897 src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits 898 } 899 // move low bits 900 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size); 901 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size); 902 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits 903 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size); 904 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size); 905 } 906 return size; 907 } 908 909 // -------------------------------------- 910 // Check for integer reg-reg copy 911 if( src_first_rc == rc_int && dst_first_rc == rc_int ) 912 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size); 913 914 // Check for integer store 915 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) 916 size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size); 917 918 // Check for integer load 919 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) 920 size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size); 921 922 // -------------------------------------- 923 // Check for float reg-reg copy 924 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 925 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || 926 (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); 927 if( cbuf ) { 928 929 // Note the mucking with the register encode to compensate for the 0/1 930 // indexing issue mentioned in a comment in the reg_def sections 931 // for FPR registers many lines above here. 932 933 if( src_first != FPR1L_num ) { 934 emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) 935 emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); 936 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) 937 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); 938 } else { 939 emit_opcode (*cbuf, 0xDD ); // FST ST(i) 940 emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); 941 } 942#ifndef PRODUCT 943 } else if( !do_size ) { 944 if( size != 0 ) st->print("\n\t"); 945 if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); 946 else st->print( "FST %s", Matcher::regName[dst_first]); 947#endif 948 } 949 return size + ((src_first != FPR1L_num) ? 2+2 : 2); 950 } 951 952 // Check for float store 953 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 954 return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size); 955 } 956 957 // Check for float load 958 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 959 int offset = ra_->reg2offset(src_first); 960 const char *op_str; 961 int op; 962 if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? 963 op_str = "FLD_D"; 964 op = 0xDD; 965 } else { // 32-bit load 966 op_str = "FLD_S"; 967 op = 0xD9; 968 assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); 969 } 970 if( cbuf ) { 971 emit_opcode (*cbuf, op ); 972 encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false); 973 emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) 974 emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); 975#ifndef PRODUCT 976 } else if( !do_size ) { 977 if( size != 0 ) st->print("\n\t"); 978 st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); 979#endif 980 } 981 int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 982 return size + 3+offset_size+2; 983 } 984 985 // Check for xmm reg-reg copy 986 if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { 987 assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || 988 (src_first+1 == src_second && dst_first+1 == dst_second), 989 "no non-adjacent float-moves" ); 990 return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size); 991 } 992 993 // Check for xmm store 994 if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { 995 return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size); 996 } 997 998 // Check for float xmm load 999 if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { 1000 return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size); 1001 } 1002 1003 // Copy from float reg to xmm reg 1004 if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { 1005 // copy to the top of stack from floating point reg 1006 // and use LEA to preserve flags 1007 if( cbuf ) { 1008 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] 1009 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); 1010 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); 1011 emit_d8(*cbuf,0xF8); 1012#ifndef PRODUCT 1013 } else if( !do_size ) { 1014 if( size != 0 ) st->print("\n\t"); 1015 st->print("LEA ESP,[ESP-8]"); 1016#endif 1017 } 1018 size += 4; 1019 1020 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size); 1021 1022 // Copy from the temp memory to the xmm reg. 1023 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size); 1024 1025 if( cbuf ) { 1026 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] 1027 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); 1028 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); 1029 emit_d8(*cbuf,0x08); 1030#ifndef PRODUCT 1031 } else if( !do_size ) { 1032 if( size != 0 ) st->print("\n\t"); 1033 st->print("LEA ESP,[ESP+8]"); 1034#endif 1035 } 1036 size += 4; 1037 return size; 1038 } 1039 1040 assert( size > 0, "missed a case" ); 1041 1042 // -------------------------------------------------------------------- 1043 // Check for second bits still needing moving. 1044 if( src_second == dst_second ) 1045 return size; // Self copy; no move 1046 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1047 1048 // Check for second word int-int move 1049 if( src_second_rc == rc_int && dst_second_rc == rc_int ) 1050 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size); 1051 1052 // Check for second word integer store 1053 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1054 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size); 1055 1056 // Check for second word integer load 1057 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1058 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size); 1059 1060 1061 Unimplemented(); 1062} 1063 1064#ifndef PRODUCT 1065void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1066 implementation( NULL, ra_, false, st ); 1067} 1068#endif 1069 1070void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1071 implementation( &cbuf, ra_, false, NULL ); 1072} 1073 1074uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1075 return implementation( NULL, ra_, true, NULL ); 1076} 1077 1078//============================================================================= 1079#ifndef PRODUCT 1080void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const { 1081 st->print("NOP \t# %d bytes pad for loops and calls", _count); 1082} 1083#endif 1084 1085void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { 1086 MacroAssembler _masm(&cbuf); 1087 __ nop(_count); 1088} 1089 1090uint MachNopNode::size(PhaseRegAlloc *) const { 1091 return _count; 1092} 1093 1094 1095//============================================================================= 1096#ifndef PRODUCT 1097void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1098 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1099 int reg = ra_->get_reg_first(this); 1100 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); 1101} 1102#endif 1103 1104void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1105 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1106 int reg = ra_->get_encode(this); 1107 if( offset >= 128 ) { 1108 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] 1109 emit_rm(cbuf, 0x2, reg, 0x04); 1110 emit_rm(cbuf, 0x0, 0x04, ESP_enc); 1111 emit_d32(cbuf, offset); 1112 } 1113 else { 1114 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] 1115 emit_rm(cbuf, 0x1, reg, 0x04); 1116 emit_rm(cbuf, 0x0, 0x04, ESP_enc); 1117 emit_d8(cbuf, offset); 1118 } 1119} 1120 1121uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1122 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1123 if( offset >= 128 ) { 1124 return 7; 1125 } 1126 else { 1127 return 4; 1128 } 1129} 1130 1131//============================================================================= 1132 1133// emit call stub, compiled java to interpreter 1134void emit_java_to_interp(CodeBuffer &cbuf ) { 1135 // Stub is fixed up when the corresponding call is converted from calling 1136 // compiled code to calling interpreted code. 1137 // mov rbx,0 1138 // jmp -1 1139 1140 address mark = cbuf.inst_mark(); // get mark within main instrs section 1141 1142 // Note that the code buffer's inst_mark is always relative to insts. 1143 // That's why we must use the macroassembler to generate a stub. 1144 MacroAssembler _masm(&cbuf); 1145 1146 address base = 1147 __ start_a_stub(Compile::MAX_stubs_size); 1148 if (base == NULL) return; // CodeBuffer::expand failed 1149 // static stub relocation stores the instruction address of the call 1150 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32); 1151 // static stub relocation also tags the methodOop in the code-stream. 1152 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time 1153 __ jump(RuntimeAddress((address)-1)); 1154 1155 __ end_a_stub(); 1156 // Update current stubs pointer and restore code_end. 1157} 1158// size of call stub, compiled java to interpretor 1159uint size_java_to_interp() { 1160 return 10; // movl; jmp 1161} 1162// relocation entries for call stub, compiled java to interpretor 1163uint reloc_java_to_interp() { 1164 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call 1165} 1166 1167//============================================================================= 1168#ifndef PRODUCT 1169void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1170 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); 1171 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); 1172 st->print_cr("\tNOP"); 1173 st->print_cr("\tNOP"); 1174 if( !OptoBreakpoint ) 1175 st->print_cr("\tNOP"); 1176} 1177#endif 1178 1179void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1180 MacroAssembler masm(&cbuf); 1181#ifdef ASSERT 1182 uint code_size = cbuf.code_size(); 1183#endif 1184 masm.cmpl(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); 1185 masm.jump_cc(Assembler::notEqual, 1186 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 1187 /* WARNING these NOPs are critical so that verified entry point is properly 1188 aligned for patching by NativeJump::patch_verified_entry() */ 1189 int nops_cnt = 2; 1190 if( !OptoBreakpoint ) // Leave space for int3 1191 nops_cnt += 1; 1192 masm.nop(nops_cnt); 1193 1194 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node"); 1195} 1196 1197uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1198 return OptoBreakpoint ? 11 : 12; 1199} 1200 1201 1202//============================================================================= 1203uint size_exception_handler() { 1204 // NativeCall instruction size is the same as NativeJump. 1205 // exception handler starts out as jump and can be patched to 1206 // a call be deoptimization. (4932387) 1207 // Note that this value is also credited (in output.cpp) to 1208 // the size of the code section. 1209 return NativeJump::instruction_size; 1210} 1211 1212// Emit exception handler code. Stuff framesize into a register 1213// and call a VM stub routine. 1214int emit_exception_handler(CodeBuffer& cbuf) { 1215 1216 // Note that the code buffer's inst_mark is always relative to insts. 1217 // That's why we must use the macroassembler to generate a handler. 1218 MacroAssembler _masm(&cbuf); 1219 address base = 1220 __ start_a_stub(size_exception_handler()); 1221 if (base == NULL) return 0; // CodeBuffer::expand failed 1222 int offset = __ offset(); 1223 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin())); 1224 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1225 __ end_a_stub(); 1226 return offset; 1227} 1228 1229uint size_deopt_handler() { 1230 // NativeCall instruction size is the same as NativeJump. 1231 // exception handler starts out as jump and can be patched to 1232 // a call be deoptimization. (4932387) 1233 // Note that this value is also credited (in output.cpp) to 1234 // the size of the code section. 1235 return 5 + NativeJump::instruction_size; // pushl(); jmp; 1236} 1237 1238// Emit deopt handler code. 1239int emit_deopt_handler(CodeBuffer& cbuf) { 1240 1241 // Note that the code buffer's inst_mark is always relative to insts. 1242 // That's why we must use the macroassembler to generate a handler. 1243 MacroAssembler _masm(&cbuf); 1244 address base = 1245 __ start_a_stub(size_exception_handler()); 1246 if (base == NULL) return 0; // CodeBuffer::expand failed 1247 int offset = __ offset(); 1248 InternalAddress here(__ pc()); 1249 __ pushptr(here.addr()); 1250 1251 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 1252 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1253 __ end_a_stub(); 1254 return offset; 1255} 1256 1257 1258static void emit_double_constant(CodeBuffer& cbuf, double x) { 1259 int mark = cbuf.insts()->mark_off(); 1260 MacroAssembler _masm(&cbuf); 1261 address double_address = __ double_constant(x); 1262 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift 1263 emit_d32_reloc(cbuf, 1264 (int)double_address, 1265 internal_word_Relocation::spec(double_address), 1266 RELOC_DISP32); 1267} 1268 1269static void emit_float_constant(CodeBuffer& cbuf, float x) { 1270 int mark = cbuf.insts()->mark_off(); 1271 MacroAssembler _masm(&cbuf); 1272 address float_address = __ float_constant(x); 1273 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift 1274 emit_d32_reloc(cbuf, 1275 (int)float_address, 1276 internal_word_Relocation::spec(float_address), 1277 RELOC_DISP32); 1278} 1279 1280 1281int Matcher::regnum_to_fpu_offset(int regnum) { 1282 return regnum - 32; // The FP registers are in the second chunk 1283} 1284 1285bool is_positive_zero_float(jfloat f) { 1286 return jint_cast(f) == jint_cast(0.0F); 1287} 1288 1289bool is_positive_one_float(jfloat f) { 1290 return jint_cast(f) == jint_cast(1.0F); 1291} 1292 1293bool is_positive_zero_double(jdouble d) { 1294 return jlong_cast(d) == jlong_cast(0.0); 1295} 1296 1297bool is_positive_one_double(jdouble d) { 1298 return jlong_cast(d) == jlong_cast(1.0); 1299} 1300 1301// This is UltraSparc specific, true just means we have fast l2f conversion 1302const bool Matcher::convL2FSupported(void) { 1303 return true; 1304} 1305 1306// Vector width in bytes 1307const uint Matcher::vector_width_in_bytes(void) { 1308 return UseSSE >= 2 ? 8 : 0; 1309} 1310 1311// Vector ideal reg 1312const uint Matcher::vector_ideal_reg(void) { 1313 return Op_RegD; 1314} 1315 1316// Is this branch offset short enough that a short branch can be used? 1317// 1318// NOTE: If the platform does not provide any short branch variants, then 1319// this method should return false for offset 0. 1320bool Matcher::is_short_branch_offset(int offset) { 1321 return (-128 <= offset && offset <= 127); 1322} 1323 1324const bool Matcher::isSimpleConstant64(jlong value) { 1325 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1326 return false; 1327} 1328 1329// The ecx parameter to rep stos for the ClearArray node is in dwords. 1330const bool Matcher::init_array_count_is_in_bytes = false; 1331 1332// Threshold size for cleararray. 1333const int Matcher::init_array_short_size = 8 * BytesPerLong; 1334 1335// Should the Matcher clone shifts on addressing modes, expecting them to 1336// be subsumed into complex addressing expressions or compute them into 1337// registers? True for Intel but false for most RISCs 1338const bool Matcher::clone_shift_expressions = true; 1339 1340// Is it better to copy float constants, or load them directly from memory? 1341// Intel can load a float constant from a direct address, requiring no 1342// extra registers. Most RISCs will have to materialize an address into a 1343// register first, so they would do better to copy the constant from stack. 1344const bool Matcher::rematerialize_float_constants = true; 1345 1346// If CPU can load and store mis-aligned doubles directly then no fixup is 1347// needed. Else we split the double into 2 integer pieces and move it 1348// piece-by-piece. Only happens when passing doubles into C code as the 1349// Java calling convention forces doubles to be aligned. 1350const bool Matcher::misaligned_doubles_ok = true; 1351 1352 1353void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1354 // Get the memory operand from the node 1355 uint numopnds = node->num_opnds(); // Virtual call for number of operands 1356 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far 1357 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); 1358 uint opcnt = 1; // First operand 1359 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand 1360 while( idx >= skipped+num_edges ) { 1361 skipped += num_edges; 1362 opcnt++; // Bump operand count 1363 assert( opcnt < numopnds, "Accessing non-existent operand" ); 1364 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand 1365 } 1366 1367 MachOper *memory = node->_opnds[opcnt]; 1368 MachOper *new_memory = NULL; 1369 switch (memory->opcode()) { 1370 case DIRECT: 1371 case INDOFFSET32X: 1372 // No transformation necessary. 1373 return; 1374 case INDIRECT: 1375 new_memory = new (C) indirect_win95_safeOper( ); 1376 break; 1377 case INDOFFSET8: 1378 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); 1379 break; 1380 case INDOFFSET32: 1381 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); 1382 break; 1383 case INDINDEXOFFSET: 1384 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); 1385 break; 1386 case INDINDEXSCALE: 1387 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); 1388 break; 1389 case INDINDEXSCALEOFFSET: 1390 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); 1391 break; 1392 case LOAD_LONG_INDIRECT: 1393 case LOAD_LONG_INDOFFSET32: 1394 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} 1395 return; 1396 default: 1397 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); 1398 return; 1399 } 1400 node->_opnds[opcnt] = new_memory; 1401} 1402 1403// Advertise here if the CPU requires explicit rounding operations 1404// to implement the UseStrictFP mode. 1405const bool Matcher::strict_fp_requires_explicit_rounding = true; 1406 1407// Do floats take an entire double register or just half? 1408const bool Matcher::float_in_double = true; 1409// Do ints take an entire long register or just half? 1410const bool Matcher::int_in_long = false; 1411 1412// Return whether or not this register is ever used as an argument. This 1413// function is used on startup to build the trampoline stubs in generateOptoStub. 1414// Registers not mentioned will be killed by the VM call in the trampoline, and 1415// arguments in those registers not be available to the callee. 1416bool Matcher::can_be_java_arg( int reg ) { 1417 if( reg == ECX_num || reg == EDX_num ) return true; 1418 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true; 1419 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; 1420 return false; 1421} 1422 1423bool Matcher::is_spillable_arg( int reg ) { 1424 return can_be_java_arg(reg); 1425} 1426 1427// Register for DIVI projection of divmodI 1428RegMask Matcher::divI_proj_mask() { 1429 return EAX_REG_mask; 1430} 1431 1432// Register for MODI projection of divmodI 1433RegMask Matcher::modI_proj_mask() { 1434 return EDX_REG_mask; 1435} 1436 1437// Register for DIVL projection of divmodL 1438RegMask Matcher::divL_proj_mask() { 1439 ShouldNotReachHere(); 1440 return RegMask(); 1441} 1442 1443// Register for MODL projection of divmodL 1444RegMask Matcher::modL_proj_mask() { 1445 ShouldNotReachHere(); 1446 return RegMask(); 1447} 1448 1449%} 1450 1451//----------ENCODING BLOCK----------------------------------------------------- 1452// This block specifies the encoding classes used by the compiler to output 1453// byte streams. Encoding classes generate functions which are called by 1454// Machine Instruction Nodes in order to generate the bit encoding of the 1455// instruction. Operands specify their base encoding interface with the 1456// interface keyword. There are currently supported four interfaces, 1457// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1458// operand to generate a function which returns its register number when 1459// queried. CONST_INTER causes an operand to generate a function which 1460// returns the value of the constant when queried. MEMORY_INTER causes an 1461// operand to generate four functions which return the Base Register, the 1462// Index Register, the Scale Value, and the Offset Value of the operand when 1463// queried. COND_INTER causes an operand to generate six functions which 1464// return the encoding code (ie - encoding bits for the instruction) 1465// associated with each basic boolean condition for a conditional instruction. 1466// Instructions specify two basic values for encoding. They use the 1467// ins_encode keyword to specify their encoding class (which must be one of 1468// the class names specified in the encoding block), and they use the 1469// opcode keyword to specify, in order, their primary, secondary, and 1470// tertiary opcode. Only the opcode sections which a particular instruction 1471// needs for encoding need to be specified. 1472encode %{ 1473 // Build emit functions for each basic byte or larger field in the intel 1474 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ 1475 // code in the enc_class source block. Emit functions will live in the 1476 // main source block for now. In future, we can generalize this by 1477 // adding a syntax that specifies the sizes of fields in an order, 1478 // so that the adlc can build the emit functions automagically 1479 enc_class OpcP %{ // Emit opcode 1480 emit_opcode(cbuf,$primary); 1481 %} 1482 1483 enc_class OpcS %{ // Emit opcode 1484 emit_opcode(cbuf,$secondary); 1485 %} 1486 1487 enc_class Opcode(immI d8 ) %{ // Emit opcode 1488 emit_opcode(cbuf,$d8$$constant); 1489 %} 1490 1491 enc_class SizePrefix %{ 1492 emit_opcode(cbuf,0x66); 1493 %} 1494 1495 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) 1496 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1497 %} 1498 1499 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many) 1500 emit_opcode(cbuf,$opcode$$constant); 1501 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1502 %} 1503 1504 enc_class mov_r32_imm0( eRegI dst ) %{ 1505 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 1506 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 1507 %} 1508 1509 enc_class cdq_enc %{ 1510 // Full implementation of Java idiv and irem; checks for 1511 // special case as described in JVM spec., p.243 & p.271. 1512 // 1513 // normal case special case 1514 // 1515 // input : rax,: dividend min_int 1516 // reg: divisor -1 1517 // 1518 // output: rax,: quotient (= rax, idiv reg) min_int 1519 // rdx: remainder (= rax, irem reg) 0 1520 // 1521 // Code sequnce: 1522 // 1523 // 81 F8 00 00 00 80 cmp rax,80000000h 1524 // 0F 85 0B 00 00 00 jne normal_case 1525 // 33 D2 xor rdx,edx 1526 // 83 F9 FF cmp rcx,0FFh 1527 // 0F 84 03 00 00 00 je done 1528 // normal_case: 1529 // 99 cdq 1530 // F7 F9 idiv rax,ecx 1531 // done: 1532 // 1533 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); 1534 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); 1535 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h 1536 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); 1537 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); 1538 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case 1539 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx 1540 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh 1541 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); 1542 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); 1543 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done 1544 // normal_case: 1545 emit_opcode(cbuf,0x99); // cdq 1546 // idiv (note: must be emitted by the user of this rule) 1547 // normal: 1548 %} 1549 1550 // Dense encoding for older common ops 1551 enc_class Opc_plus(immI opcode, eRegI reg) %{ 1552 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); 1553 %} 1554 1555 1556 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension 1557 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit 1558 // Check for 8-bit immediate, and set sign extend bit in opcode 1559 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1560 emit_opcode(cbuf, $primary | 0x02); 1561 } 1562 else { // If 32-bit immediate 1563 emit_opcode(cbuf, $primary); 1564 } 1565 %} 1566 1567 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m 1568 // Emit primary opcode and set sign-extend bit 1569 // Check for 8-bit immediate, and set sign extend bit in opcode 1570 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1571 emit_opcode(cbuf, $primary | 0x02); } 1572 else { // If 32-bit immediate 1573 emit_opcode(cbuf, $primary); 1574 } 1575 // Emit r/m byte with secondary opcode, after primary opcode. 1576 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1577 %} 1578 1579 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits 1580 // Check for 8-bit immediate, and set sign extend bit in opcode 1581 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1582 $$$emit8$imm$$constant; 1583 } 1584 else { // If 32-bit immediate 1585 // Output immediate 1586 $$$emit32$imm$$constant; 1587 } 1588 %} 1589 1590 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ 1591 // Emit primary opcode and set sign-extend bit 1592 // Check for 8-bit immediate, and set sign extend bit in opcode 1593 int con = (int)$imm$$constant; // Throw away top bits 1594 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); 1595 // Emit r/m byte with secondary opcode, after primary opcode. 1596 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1597 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); 1598 else emit_d32(cbuf,con); 1599 %} 1600 1601 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ 1602 // Emit primary opcode and set sign-extend bit 1603 // Check for 8-bit immediate, and set sign extend bit in opcode 1604 int con = (int)($imm$$constant >> 32); // Throw away bottom bits 1605 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); 1606 // Emit r/m byte with tertiary opcode, after primary opcode. 1607 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); 1608 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); 1609 else emit_d32(cbuf,con); 1610 %} 1611 1612 enc_class Lbl (label labl) %{ // JMP, CALL 1613 Label *l = $labl$$label; 1614 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0); 1615 %} 1616 1617 enc_class LblShort (label labl) %{ // JMP, CALL 1618 Label *l = $labl$$label; 1619 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0; 1620 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); 1621 emit_d8(cbuf, disp); 1622 %} 1623 1624 enc_class OpcSReg (eRegI dst) %{ // BSWAP 1625 emit_cc(cbuf, $secondary, $dst$$reg ); 1626 %} 1627 1628 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP 1629 int destlo = $dst$$reg; 1630 int desthi = HIGH_FROM_LOW(destlo); 1631 // bswap lo 1632 emit_opcode(cbuf, 0x0F); 1633 emit_cc(cbuf, 0xC8, destlo); 1634 // bswap hi 1635 emit_opcode(cbuf, 0x0F); 1636 emit_cc(cbuf, 0xC8, desthi); 1637 // xchg lo and hi 1638 emit_opcode(cbuf, 0x87); 1639 emit_rm(cbuf, 0x3, destlo, desthi); 1640 %} 1641 1642 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ... 1643 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); 1644 %} 1645 1646 enc_class Jcc (cmpOp cop, label labl) %{ // JCC 1647 Label *l = $labl$$label; 1648 $$$emit8$primary; 1649 emit_cc(cbuf, $secondary, $cop$$cmpcode); 1650 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0); 1651 %} 1652 1653 enc_class JccShort (cmpOp cop, label labl) %{ // JCC 1654 Label *l = $labl$$label; 1655 emit_cc(cbuf, $primary, $cop$$cmpcode); 1656 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0; 1657 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); 1658 emit_d8(cbuf, disp); 1659 %} 1660 1661 enc_class enc_cmov(cmpOp cop ) %{ // CMOV 1662 $$$emit8$primary; 1663 emit_cc(cbuf, $secondary, $cop$$cmpcode); 1664 %} 1665 1666 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV 1667 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); 1668 emit_d8(cbuf, op >> 8 ); 1669 emit_d8(cbuf, op & 255); 1670 %} 1671 1672 // emulate a CMOV with a conditional branch around a MOV 1673 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV 1674 // Invert sense of branch from sense of CMOV 1675 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); 1676 emit_d8( cbuf, $brOffs$$constant ); 1677 %} 1678 1679 enc_class enc_PartialSubtypeCheck( ) %{ 1680 Register Redi = as_Register(EDI_enc); // result register 1681 Register Reax = as_Register(EAX_enc); // super class 1682 Register Recx = as_Register(ECX_enc); // killed 1683 Register Resi = as_Register(ESI_enc); // sub class 1684 Label hit, miss; 1685 1686 MacroAssembler _masm(&cbuf); 1687 // Compare super with sub directly, since super is not in its own SSA. 1688 // The compiler used to emit this test, but we fold it in here, 1689 // to allow platform-specific tweaking on sparc. 1690 __ cmpl(Reax, Resi); 1691 __ jcc(Assembler::equal, hit); 1692#ifndef PRODUCT 1693 __ increment(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr)); 1694#endif //PRODUCT 1695 __ movl(Redi,Address(Resi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())); 1696 __ movl(Recx,Address(Redi,arrayOopDesc::length_offset_in_bytes())); 1697 __ addl(Redi,arrayOopDesc::base_offset_in_bytes(T_OBJECT)); 1698 __ repne_scan(); 1699 __ jcc(Assembler::notEqual, miss); 1700 __ movl(Address(Resi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()),Reax); 1701 __ bind(hit); 1702 if( $primary ) 1703 __ xorl(Redi,Redi); 1704 __ bind(miss); 1705 %} 1706 1707 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All 1708 MacroAssembler masm(&cbuf); 1709 int start = masm.offset(); 1710 if (UseSSE >= 2) { 1711 if (VerifyFPU) { 1712 masm.verify_FPU(0, "must be empty in SSE2+ mode"); 1713 } 1714 } else { 1715 // External c_calling_convention expects the FPU stack to be 'clean'. 1716 // Compiled code leaves it dirty. Do cleanup now. 1717 masm.empty_FPU_stack(); 1718 } 1719 if (sizeof_FFree_Float_Stack_All == -1) { 1720 sizeof_FFree_Float_Stack_All = masm.offset() - start; 1721 } else { 1722 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); 1723 } 1724 %} 1725 1726 enc_class Verify_FPU_For_Leaf %{ 1727 if( VerifyFPU ) { 1728 MacroAssembler masm(&cbuf); 1729 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); 1730 } 1731 %} 1732 1733 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf 1734 // This is the instruction starting address for relocation info. 1735 cbuf.set_inst_mark(); 1736 $$$emit8$primary; 1737 // CALL directly to the runtime 1738 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1739 runtime_call_Relocation::spec(), RELOC_IMM32 ); 1740 1741 if (UseSSE >= 2) { 1742 MacroAssembler _masm(&cbuf); 1743 BasicType rt = tf()->return_type(); 1744 1745 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { 1746 // A C runtime call where the return value is unused. In SSE2+ 1747 // mode the result needs to be removed from the FPU stack. It's 1748 // likely that this function call could be removed by the 1749 // optimizer if the C function is a pure function. 1750 __ ffree(0); 1751 } else if (rt == T_FLOAT) { 1752 __ leal(rsp, Address(rsp, -4)); 1753 __ fstp_s(Address(rsp, 0)); 1754 __ movflt(xmm0, Address(rsp, 0)); 1755 __ leal(rsp, Address(rsp, 4)); 1756 } else if (rt == T_DOUBLE) { 1757 __ leal(rsp, Address(rsp, -8)); 1758 __ fstp_d(Address(rsp, 0)); 1759 __ movdbl(xmm0, Address(rsp, 0)); 1760 __ leal(rsp, Address(rsp, 8)); 1761 } 1762 } 1763 %} 1764 1765 1766 enc_class pre_call_FPU %{ 1767 // If method sets FPU control word restore it here 1768 if( Compile::current()->in_24_bit_fp_mode() ) { 1769 MacroAssembler masm(&cbuf); 1770 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1771 } 1772 %} 1773 1774 enc_class post_call_FPU %{ 1775 // If method sets FPU control word do it here also 1776 if( Compile::current()->in_24_bit_fp_mode() ) { 1777 MacroAssembler masm(&cbuf); 1778 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 1779 } 1780 %} 1781 1782 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 1783 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 1784 // who we intended to call. 1785 cbuf.set_inst_mark(); 1786 $$$emit8$primary; 1787 if ( !_method ) { 1788 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1789 runtime_call_Relocation::spec(), RELOC_IMM32 ); 1790 } else if(_optimized_virtual) { 1791 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1792 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); 1793 } else { 1794 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1795 static_call_Relocation::spec(), RELOC_IMM32 ); 1796 } 1797 if( _method ) { // Emit stub for static call 1798 emit_java_to_interp(cbuf); 1799 } 1800 %} 1801 1802 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 1803 // !!!!! 1804 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info 1805 // emit_call_dynamic_prologue( cbuf ); 1806 cbuf.set_inst_mark(); 1807 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1 1808 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32); 1809 address virtual_call_oop_addr = cbuf.inst_mark(); 1810 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 1811 // who we intended to call. 1812 cbuf.set_inst_mark(); 1813 $$$emit8$primary; 1814 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1815 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 ); 1816 %} 1817 1818 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 1819 int disp = in_bytes(methodOopDesc::from_compiled_offset()); 1820 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); 1821 1822 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())] 1823 cbuf.set_inst_mark(); 1824 $$$emit8$primary; 1825 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte 1826 emit_d8(cbuf, disp); // Displacement 1827 1828 %} 1829 1830 enc_class Xor_Reg (eRegI dst) %{ 1831 emit_opcode(cbuf, 0x33); 1832 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); 1833 %} 1834 1835// Following encoding is no longer used, but may be restored if calling 1836// convention changes significantly. 1837// Became: Xor_Reg(EBP), Java_To_Runtime( labl ) 1838// 1839// enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL 1840// // int ic_reg = Matcher::inline_cache_reg(); 1841// // int ic_encode = Matcher::_regEncode[ic_reg]; 1842// // int imo_reg = Matcher::interpreter_method_oop_reg(); 1843// // int imo_encode = Matcher::_regEncode[imo_reg]; 1844// 1845// // // Interpreter expects method_oop in EBX, currently a callee-saved register, 1846// // // so we load it immediately before the call 1847// // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop 1848// // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte 1849// 1850// // xor rbp,ebp 1851// emit_opcode(cbuf, 0x33); 1852// emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); 1853// 1854// // CALL to interpreter. 1855// cbuf.set_inst_mark(); 1856// $$$emit8$primary; 1857// emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4), 1858// runtime_call_Relocation::spec(), RELOC_IMM32 ); 1859// %} 1860 1861 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR 1862 $$$emit8$primary; 1863 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1864 $$$emit8$shift$$constant; 1865 %} 1866 1867 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate 1868 // Load immediate does not have a zero or sign extended version 1869 // for 8-bit immediates 1870 emit_opcode(cbuf, 0xB8 + $dst$$reg); 1871 $$$emit32$src$$constant; 1872 %} 1873 1874 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate 1875 // Load immediate does not have a zero or sign extended version 1876 // for 8-bit immediates 1877 emit_opcode(cbuf, $primary + $dst$$reg); 1878 $$$emit32$src$$constant; 1879 %} 1880 1881 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate 1882 // Load immediate does not have a zero or sign extended version 1883 // for 8-bit immediates 1884 int dst_enc = $dst$$reg; 1885 int src_con = $src$$constant & 0x0FFFFFFFFL; 1886 if (src_con == 0) { 1887 // xor dst, dst 1888 emit_opcode(cbuf, 0x33); 1889 emit_rm(cbuf, 0x3, dst_enc, dst_enc); 1890 } else { 1891 emit_opcode(cbuf, $primary + dst_enc); 1892 emit_d32(cbuf, src_con); 1893 } 1894 %} 1895 1896 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate 1897 // Load immediate does not have a zero or sign extended version 1898 // for 8-bit immediates 1899 int dst_enc = $dst$$reg + 2; 1900 int src_con = ((julong)($src$$constant)) >> 32; 1901 if (src_con == 0) { 1902 // xor dst, dst 1903 emit_opcode(cbuf, 0x33); 1904 emit_rm(cbuf, 0x3, dst_enc, dst_enc); 1905 } else { 1906 emit_opcode(cbuf, $primary + dst_enc); 1907 emit_d32(cbuf, src_con); 1908 } 1909 %} 1910 1911 1912 enc_class LdImmD (immD src) %{ // Load Immediate 1913 if( is_positive_zero_double($src$$constant)) { 1914 // FLDZ 1915 emit_opcode(cbuf,0xD9); 1916 emit_opcode(cbuf,0xEE); 1917 } else if( is_positive_one_double($src$$constant)) { 1918 // FLD1 1919 emit_opcode(cbuf,0xD9); 1920 emit_opcode(cbuf,0xE8); 1921 } else { 1922 emit_opcode(cbuf,0xDD); 1923 emit_rm(cbuf, 0x0, 0x0, 0x5); 1924 emit_double_constant(cbuf, $src$$constant); 1925 } 1926 %} 1927 1928 1929 enc_class LdImmF (immF src) %{ // Load Immediate 1930 if( is_positive_zero_float($src$$constant)) { 1931 emit_opcode(cbuf,0xD9); 1932 emit_opcode(cbuf,0xEE); 1933 } else if( is_positive_one_float($src$$constant)) { 1934 emit_opcode(cbuf,0xD9); 1935 emit_opcode(cbuf,0xE8); 1936 } else { 1937 $$$emit8$primary; 1938 // Load immediate does not have a zero or sign extended version 1939 // for 8-bit immediates 1940 // First load to TOS, then move to dst 1941 emit_rm(cbuf, 0x0, 0x0, 0x5); 1942 emit_float_constant(cbuf, $src$$constant); 1943 } 1944 %} 1945 1946 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate 1947 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 1948 emit_float_constant(cbuf, $con$$constant); 1949 %} 1950 1951 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate 1952 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 1953 emit_double_constant(cbuf, $con$$constant); 1954 %} 1955 1956 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant 1957 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con) 1958 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 1959 emit_opcode(cbuf, 0x0F); 1960 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); 1961 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 1962 emit_double_constant(cbuf, $con$$constant); 1963 %} 1964 1965 enc_class Opc_MemImm_F(immF src) %{ 1966 cbuf.set_inst_mark(); 1967 $$$emit8$primary; 1968 emit_rm(cbuf, 0x0, $secondary, 0x5); 1969 emit_float_constant(cbuf, $src$$constant); 1970 %} 1971 1972 1973 enc_class MovI2X_reg(regX dst, eRegI src) %{ 1974 emit_opcode(cbuf, 0x66 ); // MOVD dst,src 1975 emit_opcode(cbuf, 0x0F ); 1976 emit_opcode(cbuf, 0x6E ); 1977 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1978 %} 1979 1980 enc_class MovX2I_reg(eRegI dst, regX src) %{ 1981 emit_opcode(cbuf, 0x66 ); // MOVD dst,src 1982 emit_opcode(cbuf, 0x0F ); 1983 emit_opcode(cbuf, 0x7E ); 1984 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg); 1985 %} 1986 1987 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{ 1988 { // MOVD $dst,$src.lo 1989 emit_opcode(cbuf,0x66); 1990 emit_opcode(cbuf,0x0F); 1991 emit_opcode(cbuf,0x6E); 1992 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1993 } 1994 { // MOVD $tmp,$src.hi 1995 emit_opcode(cbuf,0x66); 1996 emit_opcode(cbuf,0x0F); 1997 emit_opcode(cbuf,0x6E); 1998 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); 1999 } 2000 { // PUNPCKLDQ $dst,$tmp 2001 emit_opcode(cbuf,0x66); 2002 emit_opcode(cbuf,0x0F); 2003 emit_opcode(cbuf,0x62); 2004 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg); 2005 } 2006 %} 2007 2008 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{ 2009 { // MOVD $dst.lo,$src 2010 emit_opcode(cbuf,0x66); 2011 emit_opcode(cbuf,0x0F); 2012 emit_opcode(cbuf,0x7E); 2013 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg); 2014 } 2015 { // PSHUFLW $tmp,$src,0x4E (01001110b) 2016 emit_opcode(cbuf,0xF2); 2017 emit_opcode(cbuf,0x0F); 2018 emit_opcode(cbuf,0x70); 2019 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); 2020 emit_d8(cbuf, 0x4E); 2021 } 2022 { // MOVD $dst.hi,$tmp 2023 emit_opcode(cbuf,0x66); 2024 emit_opcode(cbuf,0x0F); 2025 emit_opcode(cbuf,0x7E); 2026 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg)); 2027 } 2028 %} 2029 2030 2031 // Encode a reg-reg copy. If it is useless, then empty encoding. 2032 enc_class enc_Copy( eRegI dst, eRegI src ) %{ 2033 encode_Copy( cbuf, $dst$$reg, $src$$reg ); 2034 %} 2035 2036 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{ 2037 encode_Copy( cbuf, $dst$$reg, $src$$reg ); 2038 %} 2039 2040 // Encode xmm reg-reg copy. If it is useless, then empty encoding. 2041 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{ 2042 encode_CopyXD( cbuf, $dst$$reg, $src$$reg ); 2043 %} 2044 2045 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) 2046 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2047 %} 2048 2049 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) 2050 $$$emit8$primary; 2051 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2052 %} 2053 2054 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) 2055 $$$emit8$secondary; 2056 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); 2057 %} 2058 2059 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) 2060 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2061 %} 2062 2063 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) 2064 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); 2065 %} 2066 2067 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{ 2068 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); 2069 %} 2070 2071 enc_class Con32 (immI src) %{ // Con32(storeImmI) 2072 // Output immediate 2073 $$$emit32$src$$constant; 2074 %} 2075 2076 enc_class Con32F_as_bits(immF src) %{ // storeF_imm 2077 // Output Float immediate bits 2078 jfloat jf = $src$$constant; 2079 int jf_as_bits = jint_cast( jf ); 2080 emit_d32(cbuf, jf_as_bits); 2081 %} 2082 2083 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm 2084 // Output Float immediate bits 2085 jfloat jf = $src$$constant; 2086 int jf_as_bits = jint_cast( jf ); 2087 emit_d32(cbuf, jf_as_bits); 2088 %} 2089 2090 enc_class Con16 (immI src) %{ // Con16(storeImmI) 2091 // Output immediate 2092 $$$emit16$src$$constant; 2093 %} 2094 2095 enc_class Con_d32(immI src) %{ 2096 emit_d32(cbuf,$src$$constant); 2097 %} 2098 2099 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) 2100 // Output immediate memory reference 2101 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); 2102 emit_d32(cbuf, 0x00); 2103 %} 2104 2105 enc_class lock_prefix( ) %{ 2106 if( os::is_MP() ) 2107 emit_opcode(cbuf,0xF0); // [Lock] 2108 %} 2109 2110 // Cmp-xchg long value. 2111 // Note: we need to swap rbx, and rcx before and after the 2112 // cmpxchg8 instruction because the instruction uses 2113 // rcx as the high order word of the new value to store but 2114 // our register encoding uses rbx,. 2115 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ 2116 2117 // XCHG rbx,ecx 2118 emit_opcode(cbuf,0x87); 2119 emit_opcode(cbuf,0xD9); 2120 // [Lock] 2121 if( os::is_MP() ) 2122 emit_opcode(cbuf,0xF0); 2123 // CMPXCHG8 [Eptr] 2124 emit_opcode(cbuf,0x0F); 2125 emit_opcode(cbuf,0xC7); 2126 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); 2127 // XCHG rbx,ecx 2128 emit_opcode(cbuf,0x87); 2129 emit_opcode(cbuf,0xD9); 2130 %} 2131 2132 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ 2133 // [Lock] 2134 if( os::is_MP() ) 2135 emit_opcode(cbuf,0xF0); 2136 2137 // CMPXCHG [Eptr] 2138 emit_opcode(cbuf,0x0F); 2139 emit_opcode(cbuf,0xB1); 2140 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); 2141 %} 2142 2143 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ 2144 int res_encoding = $res$$reg; 2145 2146 // MOV res,0 2147 emit_opcode( cbuf, 0xB8 + res_encoding); 2148 emit_d32( cbuf, 0 ); 2149 // JNE,s fail 2150 emit_opcode(cbuf,0x75); 2151 emit_d8(cbuf, 5 ); 2152 // MOV res,1 2153 emit_opcode( cbuf, 0xB8 + res_encoding); 2154 emit_d32( cbuf, 1 ); 2155 // fail: 2156 %} 2157 2158 enc_class set_instruction_start( ) %{ 2159 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand 2160 %} 2161 2162 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem 2163 int reg_encoding = $ereg$$reg; 2164 int base = $mem$$base; 2165 int index = $mem$$index; 2166 int scale = $mem$$scale; 2167 int displace = $mem$$disp; 2168 bool disp_is_oop = $mem->disp_is_oop(); 2169 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2170 %} 2171 2172 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem 2173 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo 2174 int base = $mem$$base; 2175 int index = $mem$$index; 2176 int scale = $mem$$scale; 2177 int displace = $mem$$disp + 4; // Offset is 4 further in memory 2178 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" ); 2179 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/); 2180 %} 2181 2182 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ 2183 int r1, r2; 2184 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } 2185 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } 2186 emit_opcode(cbuf,0x0F); 2187 emit_opcode(cbuf,$tertiary); 2188 emit_rm(cbuf, 0x3, r1, r2); 2189 emit_d8(cbuf,$cnt$$constant); 2190 emit_d8(cbuf,$primary); 2191 emit_rm(cbuf, 0x3, $secondary, r1); 2192 emit_d8(cbuf,$cnt$$constant); 2193 %} 2194 2195 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ 2196 emit_opcode( cbuf, 0x8B ); // Move 2197 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); 2198 emit_d8(cbuf,$primary); 2199 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 2200 emit_d8(cbuf,$cnt$$constant-32); 2201 emit_d8(cbuf,$primary); 2202 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); 2203 emit_d8(cbuf,31); 2204 %} 2205 2206 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ 2207 int r1, r2; 2208 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } 2209 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } 2210 2211 emit_opcode( cbuf, 0x8B ); // Move r1,r2 2212 emit_rm(cbuf, 0x3, r1, r2); 2213 if( $cnt$$constant > 32 ) { // Shift, if not by zero 2214 emit_opcode(cbuf,$primary); 2215 emit_rm(cbuf, 0x3, $secondary, r1); 2216 emit_d8(cbuf,$cnt$$constant-32); 2217 } 2218 emit_opcode(cbuf,0x33); // XOR r2,r2 2219 emit_rm(cbuf, 0x3, r2, r2); 2220 %} 2221 2222 // Clone of RegMem but accepts an extra parameter to access each 2223 // half of a double in memory; it never needs relocation info. 2224 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{ 2225 emit_opcode(cbuf,$opcode$$constant); 2226 int reg_encoding = $rm_reg$$reg; 2227 int base = $mem$$base; 2228 int index = $mem$$index; 2229 int scale = $mem$$scale; 2230 int displace = $mem$$disp + $disp_for_half$$constant; 2231 bool disp_is_oop = false; 2232 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2233 %} 2234 2235 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! 2236 // 2237 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant 2238 // and it never needs relocation information. 2239 // Frequently used to move data between FPU's Stack Top and memory. 2240 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ 2241 int rm_byte_opcode = $rm_opcode$$constant; 2242 int base = $mem$$base; 2243 int index = $mem$$index; 2244 int scale = $mem$$scale; 2245 int displace = $mem$$disp; 2246 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" ); 2247 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false); 2248 %} 2249 2250 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ 2251 int rm_byte_opcode = $rm_opcode$$constant; 2252 int base = $mem$$base; 2253 int index = $mem$$index; 2254 int scale = $mem$$scale; 2255 int displace = $mem$$disp; 2256 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 2257 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 2258 %} 2259 2260 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea 2261 int reg_encoding = $dst$$reg; 2262 int base = $src0$$reg; // 0xFFFFFFFF indicates no base 2263 int index = 0x04; // 0x04 indicates no index 2264 int scale = 0x00; // 0x00 indicates no scale 2265 int displace = $src1$$constant; // 0x00 indicates no displacement 2266 bool disp_is_oop = false; 2267 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2268 %} 2269 2270 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN 2271 // Compare dst,src 2272 emit_opcode(cbuf,0x3B); 2273 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2274 // jmp dst < src around move 2275 emit_opcode(cbuf,0x7C); 2276 emit_d8(cbuf,2); 2277 // move dst,src 2278 emit_opcode(cbuf,0x8B); 2279 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2280 %} 2281 2282 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX 2283 // Compare dst,src 2284 emit_opcode(cbuf,0x3B); 2285 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2286 // jmp dst > src around move 2287 emit_opcode(cbuf,0x7F); 2288 emit_d8(cbuf,2); 2289 // move dst,src 2290 emit_opcode(cbuf,0x8B); 2291 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2292 %} 2293 2294 enc_class enc_FP_store(memory mem, regD src) %{ 2295 // If src is FPR1, we can just FST to store it. 2296 // Else we need to FLD it to FPR1, then FSTP to store/pop it. 2297 int reg_encoding = 0x2; // Just store 2298 int base = $mem$$base; 2299 int index = $mem$$index; 2300 int scale = $mem$$scale; 2301 int displace = $mem$$disp; 2302 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 2303 if( $src$$reg != FPR1L_enc ) { 2304 reg_encoding = 0x3; // Store & pop 2305 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) 2306 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2307 } 2308 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand 2309 emit_opcode(cbuf,$primary); 2310 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2311 %} 2312 2313 enc_class neg_reg(eRegI dst) %{ 2314 // NEG $dst 2315 emit_opcode(cbuf,0xF7); 2316 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); 2317 %} 2318 2319 enc_class setLT_reg(eCXRegI dst) %{ 2320 // SETLT $dst 2321 emit_opcode(cbuf,0x0F); 2322 emit_opcode(cbuf,0x9C); 2323 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); 2324 %} 2325 2326 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT 2327 int tmpReg = $tmp$$reg; 2328 2329 // SUB $p,$q 2330 emit_opcode(cbuf,0x2B); 2331 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); 2332 // SBB $tmp,$tmp 2333 emit_opcode(cbuf,0x1B); 2334 emit_rm(cbuf, 0x3, tmpReg, tmpReg); 2335 // AND $tmp,$y 2336 emit_opcode(cbuf,0x23); 2337 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); 2338 // ADD $p,$tmp 2339 emit_opcode(cbuf,0x03); 2340 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); 2341 %} 2342 2343 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT 2344 int tmpReg = $tmp$$reg; 2345 2346 // SUB $p,$q 2347 emit_opcode(cbuf,0x2B); 2348 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); 2349 // SBB $tmp,$tmp 2350 emit_opcode(cbuf,0x1B); 2351 emit_rm(cbuf, 0x3, tmpReg, tmpReg); 2352 // AND $tmp,$y 2353 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand 2354 emit_opcode(cbuf,0x23); 2355 int reg_encoding = tmpReg; 2356 int base = $mem$$base; 2357 int index = $mem$$index; 2358 int scale = $mem$$scale; 2359 int displace = $mem$$disp; 2360 bool disp_is_oop = $mem->disp_is_oop(); 2361 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2362 // ADD $p,$tmp 2363 emit_opcode(cbuf,0x03); 2364 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); 2365 %} 2366 2367 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ 2368 // TEST shift,32 2369 emit_opcode(cbuf,0xF7); 2370 emit_rm(cbuf, 0x3, 0, ECX_enc); 2371 emit_d32(cbuf,0x20); 2372 // JEQ,s small 2373 emit_opcode(cbuf, 0x74); 2374 emit_d8(cbuf, 0x04); 2375 // MOV $dst.hi,$dst.lo 2376 emit_opcode( cbuf, 0x8B ); 2377 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); 2378 // CLR $dst.lo 2379 emit_opcode(cbuf, 0x33); 2380 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); 2381// small: 2382 // SHLD $dst.hi,$dst.lo,$shift 2383 emit_opcode(cbuf,0x0F); 2384 emit_opcode(cbuf,0xA5); 2385 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); 2386 // SHL $dst.lo,$shift" 2387 emit_opcode(cbuf,0xD3); 2388 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); 2389 %} 2390 2391 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ 2392 // TEST shift,32 2393 emit_opcode(cbuf,0xF7); 2394 emit_rm(cbuf, 0x3, 0, ECX_enc); 2395 emit_d32(cbuf,0x20); 2396 // JEQ,s small 2397 emit_opcode(cbuf, 0x74); 2398 emit_d8(cbuf, 0x04); 2399 // MOV $dst.lo,$dst.hi 2400 emit_opcode( cbuf, 0x8B ); 2401 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); 2402 // CLR $dst.hi 2403 emit_opcode(cbuf, 0x33); 2404 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); 2405// small: 2406 // SHRD $dst.lo,$dst.hi,$shift 2407 emit_opcode(cbuf,0x0F); 2408 emit_opcode(cbuf,0xAD); 2409 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); 2410 // SHR $dst.hi,$shift" 2411 emit_opcode(cbuf,0xD3); 2412 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); 2413 %} 2414 2415 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ 2416 // TEST shift,32 2417 emit_opcode(cbuf,0xF7); 2418 emit_rm(cbuf, 0x3, 0, ECX_enc); 2419 emit_d32(cbuf,0x20); 2420 // JEQ,s small 2421 emit_opcode(cbuf, 0x74); 2422 emit_d8(cbuf, 0x05); 2423 // MOV $dst.lo,$dst.hi 2424 emit_opcode( cbuf, 0x8B ); 2425 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); 2426 // SAR $dst.hi,31 2427 emit_opcode(cbuf, 0xC1); 2428 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); 2429 emit_d8(cbuf, 0x1F ); 2430// small: 2431 // SHRD $dst.lo,$dst.hi,$shift 2432 emit_opcode(cbuf,0x0F); 2433 emit_opcode(cbuf,0xAD); 2434 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); 2435 // SAR $dst.hi,$shift" 2436 emit_opcode(cbuf,0xD3); 2437 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); 2438 %} 2439 2440 2441 // ----------------- Encodings for floating point unit ----------------- 2442 // May leave result in FPU-TOS or FPU reg depending on opcodes 2443 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV 2444 $$$emit8$primary; 2445 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); 2446 %} 2447 2448 // Pop argument in FPR0 with FSTP ST(0) 2449 enc_class PopFPU() %{ 2450 emit_opcode( cbuf, 0xDD ); 2451 emit_d8( cbuf, 0xD8 ); 2452 %} 2453 2454 // !!!!! equivalent to Pop_Reg_F 2455 enc_class Pop_Reg_D( regD dst ) %{ 2456 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) 2457 emit_d8( cbuf, 0xD8+$dst$$reg ); 2458 %} 2459 2460 enc_class Push_Reg_D( regD dst ) %{ 2461 emit_opcode( cbuf, 0xD9 ); 2462 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) 2463 %} 2464 2465 enc_class strictfp_bias1( regD dst ) %{ 2466 emit_opcode( cbuf, 0xDB ); // FLD m80real 2467 emit_opcode( cbuf, 0x2D ); 2468 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); 2469 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 2470 emit_opcode( cbuf, 0xC8+$dst$$reg ); 2471 %} 2472 2473 enc_class strictfp_bias2( regD dst ) %{ 2474 emit_opcode( cbuf, 0xDB ); // FLD m80real 2475 emit_opcode( cbuf, 0x2D ); 2476 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); 2477 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 2478 emit_opcode( cbuf, 0xC8+$dst$$reg ); 2479 %} 2480 2481 // Special case for moving an integer register to a stack slot. 2482 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS 2483 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); 2484 %} 2485 2486 // Special case for moving a register to a stack slot. 2487 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS 2488 // Opcode already emitted 2489 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte 2490 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 2491 emit_d32(cbuf, $dst$$disp); // Displacement 2492 %} 2493 2494 // Push the integer in stackSlot 'src' onto FP-stack 2495 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] 2496 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); 2497 %} 2498 2499 // Push the float in stackSlot 'src' onto FP-stack 2500 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src] 2501 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp ); 2502 %} 2503 2504 // Push the double in stackSlot 'src' onto FP-stack 2505 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src] 2506 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp ); 2507 %} 2508 2509 // Push FPU's TOS float to a stack-slot, and pop FPU-stack 2510 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst] 2511 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); 2512 %} 2513 2514 // Same as Pop_Mem_F except for opcode 2515 // Push FPU's TOS double to a stack-slot, and pop FPU-stack 2516 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst] 2517 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); 2518 %} 2519 2520 enc_class Pop_Reg_F( regF dst ) %{ 2521 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) 2522 emit_d8( cbuf, 0xD8+$dst$$reg ); 2523 %} 2524 2525 enc_class Push_Reg_F( regF dst ) %{ 2526 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2527 emit_d8( cbuf, 0xC0-1+$dst$$reg ); 2528 %} 2529 2530 // Push FPU's float to a stack-slot, and pop FPU-stack 2531 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{ 2532 int pop = 0x02; 2533 if ($src$$reg != FPR1L_enc) { 2534 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2535 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2536 pop = 0x03; 2537 } 2538 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] 2539 %} 2540 2541 // Push FPU's double to a stack-slot, and pop FPU-stack 2542 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{ 2543 int pop = 0x02; 2544 if ($src$$reg != FPR1L_enc) { 2545 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2546 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2547 pop = 0x03; 2548 } 2549 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] 2550 %} 2551 2552 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack 2553 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{ 2554 int pop = 0xD0 - 1; // -1 since we skip FLD 2555 if ($src$$reg != FPR1L_enc) { 2556 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) 2557 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2558 pop = 0xD8; 2559 } 2560 emit_opcode( cbuf, 0xDD ); 2561 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) 2562 %} 2563 2564 2565 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{ 2566 MacroAssembler masm(&cbuf); 2567 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg 2568 masm.fmul( $src2$$reg+0); // value at TOS 2569 masm.fadd( $src$$reg+0); // value at TOS 2570 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store 2571 %} 2572 2573 2574 enc_class Push_Reg_Mod_D( regD dst, regD src) %{ 2575 // load dst in FPR0 2576 emit_opcode( cbuf, 0xD9 ); 2577 emit_d8( cbuf, 0xC0-1+$dst$$reg ); 2578 if ($src$$reg != FPR1L_enc) { 2579 // fincstp 2580 emit_opcode (cbuf, 0xD9); 2581 emit_opcode (cbuf, 0xF7); 2582 // swap src with FPR1: 2583 // FXCH FPR1 with src 2584 emit_opcode(cbuf, 0xD9); 2585 emit_d8(cbuf, 0xC8-1+$src$$reg ); 2586 // fdecstp 2587 emit_opcode (cbuf, 0xD9); 2588 emit_opcode (cbuf, 0xF6); 2589 } 2590 %} 2591 2592 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{ 2593 // Allocate a word 2594 emit_opcode(cbuf,0x83); // SUB ESP,8 2595 emit_opcode(cbuf,0xEC); 2596 emit_d8(cbuf,0x08); 2597 2598 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1 2599 emit_opcode (cbuf, 0x0F ); 2600 emit_opcode (cbuf, 0x11 ); 2601 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false); 2602 2603 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 2604 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2605 2606 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0 2607 emit_opcode (cbuf, 0x0F ); 2608 emit_opcode (cbuf, 0x11 ); 2609 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false); 2610 2611 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 2612 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2613 2614 %} 2615 2616 enc_class Push_ModX_encoding( regX src0, regX src1) %{ 2617 // Allocate a word 2618 emit_opcode(cbuf,0x83); // SUB ESP,4 2619 emit_opcode(cbuf,0xEC); 2620 emit_d8(cbuf,0x04); 2621 2622 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1 2623 emit_opcode (cbuf, 0x0F ); 2624 emit_opcode (cbuf, 0x11 ); 2625 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false); 2626 2627 emit_opcode(cbuf,0xD9 ); // FLD [ESP] 2628 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2629 2630 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0 2631 emit_opcode (cbuf, 0x0F ); 2632 emit_opcode (cbuf, 0x11 ); 2633 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false); 2634 2635 emit_opcode(cbuf,0xD9 ); // FLD [ESP] 2636 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2637 2638 %} 2639 2640 enc_class Push_ResultXD(regXD dst) %{ 2641 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP] 2642 2643 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp] 2644 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 2645 emit_opcode (cbuf, 0x0F ); 2646 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); 2647 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); 2648 2649 emit_opcode(cbuf,0x83); // ADD ESP,8 2650 emit_opcode(cbuf,0xC4); 2651 emit_d8(cbuf,0x08); 2652 %} 2653 2654 enc_class Push_ResultX(regX dst, immI d8) %{ 2655 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP] 2656 2657 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP] 2658 emit_opcode (cbuf, 0x0F ); 2659 emit_opcode (cbuf, 0x10 ); 2660 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); 2661 2662 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8) 2663 emit_opcode(cbuf,0xC4); 2664 emit_d8(cbuf,$d8$$constant); 2665 %} 2666 2667 enc_class Push_SrcXD(regXD src) %{ 2668 // Allocate a word 2669 emit_opcode(cbuf,0x83); // SUB ESP,8 2670 emit_opcode(cbuf,0xEC); 2671 emit_d8(cbuf,0x08); 2672 2673 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src 2674 emit_opcode (cbuf, 0x0F ); 2675 emit_opcode (cbuf, 0x11 ); 2676 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 2677 2678 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 2679 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2680 %} 2681 2682 enc_class push_stack_temp_qword() %{ 2683 emit_opcode(cbuf,0x83); // SUB ESP,8 2684 emit_opcode(cbuf,0xEC); 2685 emit_d8 (cbuf,0x08); 2686 %} 2687 2688 enc_class pop_stack_temp_qword() %{ 2689 emit_opcode(cbuf,0x83); // ADD ESP,8 2690 emit_opcode(cbuf,0xC4); 2691 emit_d8 (cbuf,0x08); 2692 %} 2693 2694 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{ 2695 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src 2696 emit_opcode (cbuf, 0x0F ); 2697 emit_opcode (cbuf, 0x11 ); 2698 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false); 2699 2700 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 2701 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2702 %} 2703 2704 // Compute X^Y using Intel's fast hardware instructions, if possible. 2705 // Otherwise return a NaN. 2706 enc_class pow_exp_core_encoding %{ 2707 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X)) 2708 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q 2709 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q 2710 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q) 2711 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q) 2712 emit_opcode(cbuf,0x1C); 2713 emit_d8(cbuf,0x24); 2714 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1 2715 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1 2716 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q) 2717 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q) 2718 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false); 2719 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask 2720 emit_rm(cbuf, 0x3, 0x0, ECX_enc); 2721 emit_d32(cbuf,0xFFFFF800); 2722 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias 2723 emit_rm(cbuf, 0x3, 0x0, EAX_enc); 2724 emit_d32(cbuf,1023); 2725 emit_opcode(cbuf,0x8B); // mov rbx,eax 2726 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc); 2727 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position 2728 emit_rm(cbuf,0x3,0x4,EAX_enc); 2729 emit_d8(cbuf,20); 2730 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow 2731 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc); 2732 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX 2733 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc); 2734 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word 2735 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false); 2736 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q) 2737 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2738 emit_d32(cbuf,0); 2739 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q 2740 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false); 2741 %} 2742 2743// enc_class Pop_Reg_Mod_D( regD dst, regD src) 2744// was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X() 2745 2746 enc_class Push_Result_Mod_D( regD src) %{ 2747 if ($src$$reg != FPR1L_enc) { 2748 // fincstp 2749 emit_opcode (cbuf, 0xD9); 2750 emit_opcode (cbuf, 0xF7); 2751 // FXCH FPR1 with src 2752 emit_opcode(cbuf, 0xD9); 2753 emit_d8(cbuf, 0xC8-1+$src$$reg ); 2754 // fdecstp 2755 emit_opcode (cbuf, 0xD9); 2756 emit_opcode (cbuf, 0xF6); 2757 } 2758 // // following asm replaced with Pop_Reg_F or Pop_Mem_F 2759 // // FSTP FPR$dst$$reg 2760 // emit_opcode( cbuf, 0xDD ); 2761 // emit_d8( cbuf, 0xD8+$dst$$reg ); 2762 %} 2763 2764 enc_class fnstsw_sahf_skip_parity() %{ 2765 // fnstsw ax 2766 emit_opcode( cbuf, 0xDF ); 2767 emit_opcode( cbuf, 0xE0 ); 2768 // sahf 2769 emit_opcode( cbuf, 0x9E ); 2770 // jnp ::skip 2771 emit_opcode( cbuf, 0x7B ); 2772 emit_opcode( cbuf, 0x05 ); 2773 %} 2774 2775 enc_class emitModD() %{ 2776 // fprem must be iterative 2777 // :: loop 2778 // fprem 2779 emit_opcode( cbuf, 0xD9 ); 2780 emit_opcode( cbuf, 0xF8 ); 2781 // wait 2782 emit_opcode( cbuf, 0x9b ); 2783 // fnstsw ax 2784 emit_opcode( cbuf, 0xDF ); 2785 emit_opcode( cbuf, 0xE0 ); 2786 // sahf 2787 emit_opcode( cbuf, 0x9E ); 2788 // jp ::loop 2789 emit_opcode( cbuf, 0x0F ); 2790 emit_opcode( cbuf, 0x8A ); 2791 emit_opcode( cbuf, 0xF4 ); 2792 emit_opcode( cbuf, 0xFF ); 2793 emit_opcode( cbuf, 0xFF ); 2794 emit_opcode( cbuf, 0xFF ); 2795 %} 2796 2797 enc_class fpu_flags() %{ 2798 // fnstsw_ax 2799 emit_opcode( cbuf, 0xDF); 2800 emit_opcode( cbuf, 0xE0); 2801 // test ax,0x0400 2802 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate 2803 emit_opcode( cbuf, 0xA9 ); 2804 emit_d16 ( cbuf, 0x0400 ); 2805 // // // This sequence works, but stalls for 12-16 cycles on PPro 2806 // // test rax,0x0400 2807 // emit_opcode( cbuf, 0xA9 ); 2808 // emit_d32 ( cbuf, 0x00000400 ); 2809 // 2810 // jz exit (no unordered comparison) 2811 emit_opcode( cbuf, 0x74 ); 2812 emit_d8 ( cbuf, 0x02 ); 2813 // mov ah,1 - treat as LT case (set carry flag) 2814 emit_opcode( cbuf, 0xB4 ); 2815 emit_d8 ( cbuf, 0x01 ); 2816 // sahf 2817 emit_opcode( cbuf, 0x9E); 2818 %} 2819 2820 enc_class cmpF_P6_fixup() %{ 2821 // Fixup the integer flags in case comparison involved a NaN 2822 // 2823 // JNP exit (no unordered comparison, P-flag is set by NaN) 2824 emit_opcode( cbuf, 0x7B ); 2825 emit_d8 ( cbuf, 0x03 ); 2826 // MOV AH,1 - treat as LT case (set carry flag) 2827 emit_opcode( cbuf, 0xB4 ); 2828 emit_d8 ( cbuf, 0x01 ); 2829 // SAHF 2830 emit_opcode( cbuf, 0x9E); 2831 // NOP // target for branch to avoid branch to branch 2832 emit_opcode( cbuf, 0x90); 2833 %} 2834 2835// fnstsw_ax(); 2836// sahf(); 2837// movl(dst, nan_result); 2838// jcc(Assembler::parity, exit); 2839// movl(dst, less_result); 2840// jcc(Assembler::below, exit); 2841// movl(dst, equal_result); 2842// jcc(Assembler::equal, exit); 2843// movl(dst, greater_result); 2844 2845// less_result = 1; 2846// greater_result = -1; 2847// equal_result = 0; 2848// nan_result = -1; 2849 2850 enc_class CmpF_Result(eRegI dst) %{ 2851 // fnstsw_ax(); 2852 emit_opcode( cbuf, 0xDF); 2853 emit_opcode( cbuf, 0xE0); 2854 // sahf 2855 emit_opcode( cbuf, 0x9E); 2856 // movl(dst, nan_result); 2857 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2858 emit_d32( cbuf, -1 ); 2859 // jcc(Assembler::parity, exit); 2860 emit_opcode( cbuf, 0x7A ); 2861 emit_d8 ( cbuf, 0x13 ); 2862 // movl(dst, less_result); 2863 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2864 emit_d32( cbuf, -1 ); 2865 // jcc(Assembler::below, exit); 2866 emit_opcode( cbuf, 0x72 ); 2867 emit_d8 ( cbuf, 0x0C ); 2868 // movl(dst, equal_result); 2869 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2870 emit_d32( cbuf, 0 ); 2871 // jcc(Assembler::equal, exit); 2872 emit_opcode( cbuf, 0x74 ); 2873 emit_d8 ( cbuf, 0x05 ); 2874 // movl(dst, greater_result); 2875 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2876 emit_d32( cbuf, 1 ); 2877 %} 2878 2879 2880 // XMM version of CmpF_Result. Because the XMM compare 2881 // instructions set the EFLAGS directly. It becomes simpler than 2882 // the float version above. 2883 enc_class CmpX_Result(eRegI dst) %{ 2884 MacroAssembler _masm(&cbuf); 2885 Label nan, inc, done; 2886 2887 __ jccb(Assembler::parity, nan); 2888 __ jccb(Assembler::equal, done); 2889 __ jccb(Assembler::above, inc); 2890 __ bind(nan); 2891 __ decrement(as_Register($dst$$reg)); 2892 __ jmpb(done); 2893 __ bind(inc); 2894 __ increment(as_Register($dst$$reg)); 2895 __ bind(done); 2896 %} 2897 2898 // Compare the longs and set flags 2899 // BROKEN! Do Not use as-is 2900 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ 2901 // CMP $src1.hi,$src2.hi 2902 emit_opcode( cbuf, 0x3B ); 2903 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); 2904 // JNE,s done 2905 emit_opcode(cbuf,0x75); 2906 emit_d8(cbuf, 2 ); 2907 // CMP $src1.lo,$src2.lo 2908 emit_opcode( cbuf, 0x3B ); 2909 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 2910// done: 2911 %} 2912 2913 enc_class convert_int_long( regL dst, eRegI src ) %{ 2914 // mov $dst.lo,$src 2915 int dst_encoding = $dst$$reg; 2916 int src_encoding = $src$$reg; 2917 encode_Copy( cbuf, dst_encoding , src_encoding ); 2918 // mov $dst.hi,$src 2919 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); 2920 // sar $dst.hi,31 2921 emit_opcode( cbuf, 0xC1 ); 2922 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); 2923 emit_d8(cbuf, 0x1F ); 2924 %} 2925 2926 enc_class convert_long_double( eRegL src ) %{ 2927 // push $src.hi 2928 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); 2929 // push $src.lo 2930 emit_opcode(cbuf, 0x50+$src$$reg ); 2931 // fild 64-bits at [SP] 2932 emit_opcode(cbuf,0xdf); 2933 emit_d8(cbuf, 0x6C); 2934 emit_d8(cbuf, 0x24); 2935 emit_d8(cbuf, 0x00); 2936 // pop stack 2937 emit_opcode(cbuf, 0x83); // add SP, #8 2938 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 2939 emit_d8(cbuf, 0x8); 2940 %} 2941 2942 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ 2943 // IMUL EDX:EAX,$src1 2944 emit_opcode( cbuf, 0xF7 ); 2945 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); 2946 // SAR EDX,$cnt-32 2947 int shift_count = ((int)$cnt$$constant) - 32; 2948 if (shift_count > 0) { 2949 emit_opcode(cbuf, 0xC1); 2950 emit_rm(cbuf, 0x3, 7, $dst$$reg ); 2951 emit_d8(cbuf, shift_count); 2952 } 2953 %} 2954 2955 // this version doesn't have add sp, 8 2956 enc_class convert_long_double2( eRegL src ) %{ 2957 // push $src.hi 2958 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); 2959 // push $src.lo 2960 emit_opcode(cbuf, 0x50+$src$$reg ); 2961 // fild 64-bits at [SP] 2962 emit_opcode(cbuf,0xdf); 2963 emit_d8(cbuf, 0x6C); 2964 emit_d8(cbuf, 0x24); 2965 emit_d8(cbuf, 0x00); 2966 %} 2967 2968 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ 2969 // Basic idea: long = (long)int * (long)int 2970 // IMUL EDX:EAX, src 2971 emit_opcode( cbuf, 0xF7 ); 2972 emit_rm( cbuf, 0x3, 0x5, $src$$reg); 2973 %} 2974 2975 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ 2976 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) 2977 // MUL EDX:EAX, src 2978 emit_opcode( cbuf, 0xF7 ); 2979 emit_rm( cbuf, 0x3, 0x4, $src$$reg); 2980 %} 2981 2982 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{ 2983 // Basic idea: lo(result) = lo(x_lo * y_lo) 2984 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 2985 // MOV $tmp,$src.lo 2986 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); 2987 // IMUL $tmp,EDX 2988 emit_opcode( cbuf, 0x0F ); 2989 emit_opcode( cbuf, 0xAF ); 2990 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 2991 // MOV EDX,$src.hi 2992 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); 2993 // IMUL EDX,EAX 2994 emit_opcode( cbuf, 0x0F ); 2995 emit_opcode( cbuf, 0xAF ); 2996 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); 2997 // ADD $tmp,EDX 2998 emit_opcode( cbuf, 0x03 ); 2999 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 3000 // MUL EDX:EAX,$src.lo 3001 emit_opcode( cbuf, 0xF7 ); 3002 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); 3003 // ADD EDX,ESI 3004 emit_opcode( cbuf, 0x03 ); 3005 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); 3006 %} 3007 3008 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{ 3009 // Basic idea: lo(result) = lo(src * y_lo) 3010 // hi(result) = hi(src * y_lo) + lo(src * y_hi) 3011 // IMUL $tmp,EDX,$src 3012 emit_opcode( cbuf, 0x6B ); 3013 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 3014 emit_d8( cbuf, (int)$src$$constant ); 3015 // MOV EDX,$src 3016 emit_opcode(cbuf, 0xB8 + EDX_enc); 3017 emit_d32( cbuf, (int)$src$$constant ); 3018 // MUL EDX:EAX,EDX 3019 emit_opcode( cbuf, 0xF7 ); 3020 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); 3021 // ADD EDX,ESI 3022 emit_opcode( cbuf, 0x03 ); 3023 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); 3024 %} 3025 3026 enc_class long_div( eRegL src1, eRegL src2 ) %{ 3027 // PUSH src1.hi 3028 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); 3029 // PUSH src1.lo 3030 emit_opcode(cbuf, 0x50+$src1$$reg ); 3031 // PUSH src2.hi 3032 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); 3033 // PUSH src2.lo 3034 emit_opcode(cbuf, 0x50+$src2$$reg ); 3035 // CALL directly to the runtime 3036 cbuf.set_inst_mark(); 3037 emit_opcode(cbuf,0xE8); // Call into runtime 3038 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3039 // Restore stack 3040 emit_opcode(cbuf, 0x83); // add SP, #framesize 3041 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 3042 emit_d8(cbuf, 4*4); 3043 %} 3044 3045 enc_class long_mod( eRegL src1, eRegL src2 ) %{ 3046 // PUSH src1.hi 3047 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); 3048 // PUSH src1.lo 3049 emit_opcode(cbuf, 0x50+$src1$$reg ); 3050 // PUSH src2.hi 3051 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); 3052 // PUSH src2.lo 3053 emit_opcode(cbuf, 0x50+$src2$$reg ); 3054 // CALL directly to the runtime 3055 cbuf.set_inst_mark(); 3056 emit_opcode(cbuf,0xE8); // Call into runtime 3057 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3058 // Restore stack 3059 emit_opcode(cbuf, 0x83); // add SP, #framesize 3060 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 3061 emit_d8(cbuf, 4*4); 3062 %} 3063 3064 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{ 3065 // MOV $tmp,$src.lo 3066 emit_opcode(cbuf, 0x8B); 3067 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); 3068 // OR $tmp,$src.hi 3069 emit_opcode(cbuf, 0x0B); 3070 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); 3071 %} 3072 3073 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ 3074 // CMP $src1.lo,$src2.lo 3075 emit_opcode( cbuf, 0x3B ); 3076 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 3077 // JNE,s skip 3078 emit_cc(cbuf, 0x70, 0x5); 3079 emit_d8(cbuf,2); 3080 // CMP $src1.hi,$src2.hi 3081 emit_opcode( cbuf, 0x3B ); 3082 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); 3083 %} 3084 3085 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{ 3086 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits 3087 emit_opcode( cbuf, 0x3B ); 3088 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 3089 // MOV $tmp,$src1.hi 3090 emit_opcode( cbuf, 0x8B ); 3091 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); 3092 // SBB $tmp,$src2.hi\t! Compute flags for long compare 3093 emit_opcode( cbuf, 0x1B ); 3094 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); 3095 %} 3096 3097 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{ 3098 // XOR $tmp,$tmp 3099 emit_opcode(cbuf,0x33); // XOR 3100 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); 3101 // CMP $tmp,$src.lo 3102 emit_opcode( cbuf, 0x3B ); 3103 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); 3104 // SBB $tmp,$src.hi 3105 emit_opcode( cbuf, 0x1B ); 3106 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); 3107 %} 3108 3109 // Sniff, sniff... smells like Gnu Superoptimizer 3110 enc_class neg_long( eRegL dst ) %{ 3111 emit_opcode(cbuf,0xF7); // NEG hi 3112 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); 3113 emit_opcode(cbuf,0xF7); // NEG lo 3114 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); 3115 emit_opcode(cbuf,0x83); // SBB hi,0 3116 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); 3117 emit_d8 (cbuf,0 ); 3118 %} 3119 3120 enc_class movq_ld(regXD dst, memory mem) %{ 3121 MacroAssembler _masm(&cbuf); 3122 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); 3123 __ movq(as_XMMRegister($dst$$reg), madr); 3124 %} 3125 3126 enc_class movq_st(memory mem, regXD src) %{ 3127 MacroAssembler _masm(&cbuf); 3128 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); 3129 __ movq(madr, as_XMMRegister($src$$reg)); 3130 %} 3131 3132 enc_class pshufd_8x8(regX dst, regX src) %{ 3133 MacroAssembler _masm(&cbuf); 3134 3135 encode_CopyXD(cbuf, $dst$$reg, $src$$reg); 3136 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg)); 3137 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00); 3138 %} 3139 3140 enc_class pshufd_4x16(regX dst, regX src) %{ 3141 MacroAssembler _masm(&cbuf); 3142 3143 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00); 3144 %} 3145 3146 enc_class pshufd(regXD dst, regXD src, int mode) %{ 3147 MacroAssembler _masm(&cbuf); 3148 3149 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode); 3150 %} 3151 3152 enc_class pxor(regXD dst, regXD src) %{ 3153 MacroAssembler _masm(&cbuf); 3154 3155 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg)); 3156 %} 3157 3158 enc_class mov_i2x(regXD dst, eRegI src) %{ 3159 MacroAssembler _masm(&cbuf); 3160 3161 __ movd(as_XMMRegister($dst$$reg), as_Register($src$$reg)); 3162 %} 3163 3164 3165 // Because the transitions from emitted code to the runtime 3166 // monitorenter/exit helper stubs are so slow it's critical that 3167 // we inline both the stack-locking fast-path and the inflated fast path. 3168 // 3169 // See also: cmpFastLock and cmpFastUnlock. 3170 // 3171 // What follows is a specialized inline transliteration of the code 3172 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 3173 // another option would be to emit TrySlowEnter and TrySlowExit methods 3174 // at startup-time. These methods would accept arguments as 3175 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 3176 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 3177 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 3178 // In practice, however, the # of lock sites is bounded and is usually small. 3179 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 3180 // if the processor uses simple bimodal branch predictors keyed by EIP 3181 // Since the helper routines would be called from multiple synchronization 3182 // sites. 3183 // 3184 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 3185 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 3186 // to those specialized methods. That'd give us a mostly platform-independent 3187 // implementation that the JITs could optimize and inline at their pleasure. 3188 // Done correctly, the only time we'd need to cross to native could would be 3189 // to park() or unpark() threads. We'd also need a few more unsafe operators 3190 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 3191 // (b) explicit barriers or fence operations. 3192 // 3193 // TODO: 3194 // 3195 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 3196 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 3197 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 3198 // the lock operators would typically be faster than reifying Self. 3199 // 3200 // * Ideally I'd define the primitives as: 3201 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 3202 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 3203 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 3204 // Instead, we're stuck with a rather awkward and brittle register assignments below. 3205 // Furthermore the register assignments are overconstrained, possibly resulting in 3206 // sub-optimal code near the synchronization site. 3207 // 3208 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 3209 // Alternately, use a better sp-proximity test. 3210 // 3211 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 3212 // Either one is sufficient to uniquely identify a thread. 3213 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 3214 // 3215 // * Intrinsify notify() and notifyAll() for the common cases where the 3216 // object is locked by the calling thread but the waitlist is empty. 3217 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 3218 // 3219 // * use jccb and jmpb instead of jcc and jmp to improve code density. 3220 // But beware of excessive branch density on AMD Opterons. 3221 // 3222 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 3223 // or failure of the fast-path. If the fast-path fails then we pass 3224 // control to the slow-path, typically in C. In Fast_Lock and 3225 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 3226 // will emit a conditional branch immediately after the node. 3227 // So we have branches to branches and lots of ICC.ZF games. 3228 // Instead, it might be better to have C2 pass a "FailureLabel" 3229 // into Fast_Lock and Fast_Unlock. In the case of success, control 3230 // will drop through the node. ICC.ZF is undefined at exit. 3231 // In the case of failure, the node will branch directly to the 3232 // FailureLabel 3233 3234 3235 // obj: object to lock 3236 // box: on-stack box address (displaced header location) - KILLED 3237 // rax,: tmp -- KILLED 3238 // scr: tmp -- KILLED 3239 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{ 3240 3241 Register objReg = as_Register($obj$$reg); 3242 Register boxReg = as_Register($box$$reg); 3243 Register tmpReg = as_Register($tmp$$reg); 3244 Register scrReg = as_Register($scr$$reg); 3245 3246 // Ensure the register assignents are disjoint 3247 guarantee (objReg != boxReg, "") ; 3248 guarantee (objReg != tmpReg, "") ; 3249 guarantee (objReg != scrReg, "") ; 3250 guarantee (boxReg != tmpReg, "") ; 3251 guarantee (boxReg != scrReg, "") ; 3252 guarantee (tmpReg == as_Register(EAX_enc), "") ; 3253 3254 MacroAssembler masm(&cbuf); 3255 3256 if (_counters != NULL) { 3257 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); 3258 } 3259 if (EmitSync & 1) { 3260 // set box->dhw = unused_mark (3) 3261 // Force all sync thru slow-path: slow_enter() and slow_exit() 3262 masm.movl (Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())) ; 3263 masm.cmpl (rsp, 0) ; 3264 } else 3265 if (EmitSync & 2) { 3266 Label DONE_LABEL ; 3267 if (UseBiasedLocking) { 3268 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. 3269 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); 3270 } 3271 3272 masm.movl (tmpReg, Address(objReg, 0)) ; // fetch markword 3273 masm.orl (tmpReg, 0x1); 3274 masm.movl (Address(boxReg, 0), tmpReg); // Anticipate successful CAS 3275 if (os::is_MP()) { masm.lock(); } 3276 masm.cmpxchg(boxReg, Address(objReg, 0)); // Updates tmpReg 3277 masm.jcc(Assembler::equal, DONE_LABEL); 3278 // Recursive locking 3279 masm.subl(tmpReg, rsp); 3280 masm.andl(tmpReg, 0xFFFFF003 ); 3281 masm.movl(Address(boxReg, 0), tmpReg); 3282 masm.bind(DONE_LABEL) ; 3283 } else { 3284 // Possible cases that we'll encounter in fast_lock 3285 // ------------------------------------------------ 3286 // * Inflated 3287 // -- unlocked 3288 // -- Locked 3289 // = by self 3290 // = by other 3291 // * biased 3292 // -- by Self 3293 // -- by other 3294 // * neutral 3295 // * stack-locked 3296 // -- by self 3297 // = sp-proximity test hits 3298 // = sp-proximity test generates false-negative 3299 // -- by other 3300 // 3301 3302 Label IsInflated, DONE_LABEL, PopDone ; 3303 3304 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 3305 // order to reduce the number of conditional branches in the most common cases. 3306 // Beware -- there's a subtle invariant that fetch of the markword 3307 // at [FETCH], below, will never observe a biased encoding (*101b). 3308 // If this invariant is not held we risk exclusion (safety) failure. 3309 if (UseBiasedLocking) { 3310 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); 3311 } 3312 3313 masm.movl (tmpReg, Address(objReg, 0)) ; // [FETCH] 3314 masm.testl (tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral) 3315 masm.jccb (Assembler::notZero, IsInflated) ; 3316 3317 // Attempt stack-locking ... 3318 masm.orl (tmpReg, 0x1); 3319 masm.movl (Address(boxReg, 0), tmpReg); // Anticipate successful CAS 3320 if (os::is_MP()) { masm.lock(); } 3321 masm.cmpxchg(boxReg, Address(objReg, 0)); // Updates tmpReg 3322 if (_counters != NULL) { 3323 masm.cond_inc32(Assembler::equal, 3324 ExternalAddress((address)_counters->fast_path_entry_count_addr())); 3325 } 3326 masm.jccb (Assembler::equal, DONE_LABEL); 3327 3328 // Recursive locking 3329 masm.subl(tmpReg, rsp); 3330 masm.andl(tmpReg, 0xFFFFF003 ); 3331 masm.movl(Address(boxReg, 0), tmpReg); 3332 if (_counters != NULL) { 3333 masm.cond_inc32(Assembler::equal, 3334 ExternalAddress((address)_counters->fast_path_entry_count_addr())); 3335 } 3336 masm.jmp (DONE_LABEL) ; 3337 3338 masm.bind (IsInflated) ; 3339 3340 // The object is inflated. 3341 // 3342 // TODO-FIXME: eliminate the ugly use of manifest constants: 3343 // Use markOopDesc::monitor_value instead of "2". 3344 // use markOop::unused_mark() instead of "3". 3345 // The tmpReg value is an objectMonitor reference ORed with 3346 // markOopDesc::monitor_value (2). We can either convert tmpReg to an 3347 // objectmonitor pointer by masking off the "2" bit or we can just 3348 // use tmpReg as an objectmonitor pointer but bias the objectmonitor 3349 // field offsets with "-2" to compensate for and annul the low-order tag bit. 3350 // 3351 // I use the latter as it avoids AGI stalls. 3352 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]" 3353 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]". 3354 // 3355 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2) 3356 3357 // boxReg refers to the on-stack BasicLock in the current frame. 3358 // We'd like to write: 3359 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices. 3360 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 3361 // additional latency as we have another ST in the store buffer that must drain. 3362 3363 if (EmitSync & 8192) { 3364 masm.movl (Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty 3365 masm.get_thread (scrReg) ; 3366 masm.movl (boxReg, tmpReg); // consider: LEA box, [tmp-2] 3367 masm.movl (tmpReg, 0); // consider: xor vs mov 3368 if (os::is_MP()) { masm.lock(); } 3369 masm.cmpxchg (scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3370 } else 3371 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 3372 masm.movl (scrReg, boxReg) ; 3373 masm.movl (boxReg, tmpReg); // consider: LEA box, [tmp-2] 3374 3375 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 3376 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) { 3377 // prefetchw [eax + Offset(_owner)-2] 3378 masm.emit_raw (0x0F) ; 3379 masm.emit_raw (0x0D) ; 3380 masm.emit_raw (0x48) ; 3381 masm.emit_raw (ObjectMonitor::owner_offset_in_bytes()-2) ; 3382 } 3383 3384 if ((EmitSync & 64) == 0) { 3385 // Optimistic form: consider XORL tmpReg,tmpReg 3386 masm.movl (tmpReg, 0 ) ; 3387 } else { 3388 // Can suffer RTS->RTO upgrades on shared or cold $ lines 3389 // Test-And-CAS instead of CAS 3390 masm.movl (tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner 3391 masm.testl (tmpReg, tmpReg) ; // Locked ? 3392 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3393 } 3394 3395 // Appears unlocked - try to swing _owner from null to non-null. 3396 // Ideally, I'd manifest "Self" with get_thread and then attempt 3397 // to CAS the register containing Self into m->Owner. 3398 // But we don't have enough registers, so instead we can either try to CAS 3399 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 3400 // we later store "Self" into m->Owner. Transiently storing a stack address 3401 // (rsp or the address of the box) into m->owner is harmless. 3402 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 3403 if (os::is_MP()) { masm.lock(); } 3404 masm.cmpxchg (scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3405 masm.movl (Address(scrReg, 0), 3) ; // box->_displaced_header = 3 3406 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3407 masm.get_thread (scrReg) ; // beware: clobbers ICCs 3408 masm.movl (Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; 3409 masm.xorl (boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success 3410 3411 // If the CAS fails we can either retry or pass control to the slow-path. 3412 // We use the latter tactic. 3413 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 3414 // If the CAS was successful ... 3415 // Self has acquired the lock 3416 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 3417 // Intentional fall-through into DONE_LABEL ... 3418 } else { 3419 masm.movl (Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty 3420 masm.movl (boxReg, tmpReg) ; 3421 3422 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 3423 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) { 3424 // prefetchw [eax + Offset(_owner)-2] 3425 masm.emit_raw (0x0F) ; 3426 masm.emit_raw (0x0D) ; 3427 masm.emit_raw (0x48) ; 3428 masm.emit_raw (ObjectMonitor::owner_offset_in_bytes()-2) ; 3429 } 3430 3431 if ((EmitSync & 64) == 0) { 3432 // Optimistic form 3433 masm.xorl (tmpReg, tmpReg) ; 3434 } else { 3435 // Can suffer RTS->RTO upgrades on shared or cold $ lines 3436 masm.movl (tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner 3437 masm.testl (tmpReg, tmpReg) ; // Locked ? 3438 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3439 } 3440 3441 // Appears unlocked - try to swing _owner from null to non-null. 3442 // Use either "Self" (in scr) or rsp as thread identity in _owner. 3443 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 3444 masm.get_thread (scrReg) ; 3445 if (os::is_MP()) { masm.lock(); } 3446 masm.cmpxchg (scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3447 3448 // If the CAS fails we can either retry or pass control to the slow-path. 3449 // We use the latter tactic. 3450 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 3451 // If the CAS was successful ... 3452 // Self has acquired the lock 3453 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 3454 // Intentional fall-through into DONE_LABEL ... 3455 } 3456 3457 // DONE_LABEL is a hot target - we'd really like to place it at the 3458 // start of cache line by padding with NOPs. 3459 // See the AMD and Intel software optimization manuals for the 3460 // most efficient "long" NOP encodings. 3461 // Unfortunately none of our alignment mechanisms suffice. 3462 masm.bind(DONE_LABEL); 3463 3464 // Avoid branch-to-branch on AMD processors 3465 // This appears to be superstition. 3466 if (EmitSync & 32) masm.nop() ; 3467 3468 3469 // At DONE_LABEL the icc ZFlag is set as follows ... 3470 // Fast_Unlock uses the same protocol. 3471 // ZFlag == 1 -> Success 3472 // ZFlag == 0 -> Failure - force control through the slow-path 3473 } 3474 %} 3475 3476 // obj: object to unlock 3477 // box: box address (displaced header location), killed. Must be EAX. 3478 // rbx,: killed tmp; cannot be obj nor box. 3479 // 3480 // Some commentary on balanced locking: 3481 // 3482 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 3483 // Methods that don't have provably balanced locking are forced to run in the 3484 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 3485 // The interpreter provides two properties: 3486 // I1: At return-time the interpreter automatically and quietly unlocks any 3487 // objects acquired the current activation (frame). Recall that the 3488 // interpreter maintains an on-stack list of locks currently held by 3489 // a frame. 3490 // I2: If a method attempts to unlock an object that is not held by the 3491 // the frame the interpreter throws IMSX. 3492 // 3493 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 3494 // B() doesn't have provably balanced locking so it runs in the interpreter. 3495 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 3496 // is still locked by A(). 3497 // 3498 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 3499 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 3500 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 3501 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 3502 3503 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{ 3504 3505 Register objReg = as_Register($obj$$reg); 3506 Register boxReg = as_Register($box$$reg); 3507 Register tmpReg = as_Register($tmp$$reg); 3508 3509 guarantee (objReg != boxReg, "") ; 3510 guarantee (objReg != tmpReg, "") ; 3511 guarantee (boxReg != tmpReg, "") ; 3512 guarantee (boxReg == as_Register(EAX_enc), "") ; 3513 MacroAssembler masm(&cbuf); 3514 3515 if (EmitSync & 4) { 3516 // Disable - inhibit all inlining. Force control through the slow-path 3517 masm.cmpl (rsp, 0) ; 3518 } else 3519 if (EmitSync & 8) { 3520 Label DONE_LABEL ; 3521 if (UseBiasedLocking) { 3522 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); 3523 } 3524 // classic stack-locking code ... 3525 masm.movl (tmpReg, Address(boxReg, 0)) ; 3526 masm.testl (tmpReg, tmpReg) ; 3527 masm.jcc (Assembler::zero, DONE_LABEL) ; 3528 if (os::is_MP()) { masm.lock(); } 3529 masm.cmpxchg(tmpReg, Address(objReg, 0)); // Uses EAX which is box 3530 masm.bind(DONE_LABEL); 3531 } else { 3532 Label DONE_LABEL, Stacked, CheckSucc, Inflated ; 3533 3534 // Critically, the biased locking test must have precedence over 3535 // and appear before the (box->dhw == 0) recursive stack-lock test. 3536 if (UseBiasedLocking) { 3537 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); 3538 } 3539 3540 masm.cmpl (Address(boxReg, 0), 0) ; // Examine the displaced header 3541 masm.movl (tmpReg, Address(objReg, 0)) ; // Examine the object's markword 3542 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock 3543 3544 masm.testl (tmpReg, 0x02) ; // Inflated? 3545 masm.jccb (Assembler::zero, Stacked) ; 3546 3547 masm.bind (Inflated) ; 3548 // It's inflated. 3549 // Despite our balanced locking property we still check that m->_owner == Self 3550 // as java routines or native JNI code called by this thread might 3551 // have released the lock. 3552 // Refer to the comments in synchronizer.cpp for how we might encode extra 3553 // state in _succ so we can avoid fetching EntryList|cxq. 3554 // 3555 // I'd like to add more cases in fast_lock() and fast_unlock() -- 3556 // such as recursive enter and exit -- but we have to be wary of 3557 // I$ bloat, T$ effects and BP$ effects. 3558 // 3559 // If there's no contention try a 1-0 exit. That is, exit without 3560 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 3561 // we detect and recover from the race that the 1-0 exit admits. 3562 // 3563 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 3564 // before it STs null into _owner, releasing the lock. Updates 3565 // to data protected by the critical section must be visible before 3566 // we drop the lock (and thus before any other thread could acquire 3567 // the lock and observe the fields protected by the lock). 3568 // IA32's memory-model is SPO, so STs are ordered with respect to 3569 // each other and there's no need for an explicit barrier (fence). 3570 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 3571 3572 masm.get_thread (boxReg) ; 3573 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) { 3574 // prefetchw [ebx + Offset(_owner)-2] 3575 masm.emit_raw (0x0F) ; 3576 masm.emit_raw (0x0D) ; 3577 masm.emit_raw (0x4B) ; 3578 masm.emit_raw (ObjectMonitor::owner_offset_in_bytes()-2) ; 3579 } 3580 3581 // Note that we could employ various encoding schemes to reduce 3582 // the number of loads below (currently 4) to just 2 or 3. 3583 // Refer to the comments in synchronizer.cpp. 3584 // In practice the chain of fetches doesn't seem to impact performance, however. 3585 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 3586 // Attempt to reduce branch density - AMD's branch predictor. 3587 masm.xorl (boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3588 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; 3589 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 3590 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 3591 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3592 masm.movl (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ; 3593 masm.jmpb (DONE_LABEL) ; 3594 } else { 3595 masm.xorl (boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3596 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; 3597 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3598 masm.movl (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 3599 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 3600 masm.jccb (Assembler::notZero, CheckSucc) ; 3601 masm.movl (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ; 3602 masm.jmpb (DONE_LABEL) ; 3603 } 3604 3605 // The Following code fragment (EmitSync & 65536) improves the performance of 3606 // contended applications and contended synchronization microbenchmarks. 3607 // Unfortunately the emission of the code - even though not executed - causes regressions 3608 // in scimark and jetstream, evidently because of $ effects. Replacing the code 3609 // with an equal number of never-executed NOPs results in the same regression. 3610 // We leave it off by default. 3611 3612 if ((EmitSync & 65536) != 0) { 3613 Label LSuccess, LGoSlowPath ; 3614 3615 masm.bind (CheckSucc) ; 3616 3617 // Optional pre-test ... it's safe to elide this 3618 if ((EmitSync & 16) == 0) { 3619 masm.cmpl (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 3620 masm.jccb (Assembler::zero, LGoSlowPath) ; 3621 } 3622 3623 // We have a classic Dekker-style idiom: 3624 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 3625 // There are a number of ways to implement the barrier: 3626 // (1) lock:andl &m->_owner, 0 3627 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 3628 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 3629 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 3630 // (2) If supported, an explicit MFENCE is appealing. 3631 // In older IA32 processors MFENCE is slower than lock:add or xchg 3632 // particularly if the write-buffer is full as might be the case if 3633 // if stores closely precede the fence or fence-equivalent instruction. 3634 // In more modern implementations MFENCE appears faster, however. 3635 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 3636 // The $lines underlying the top-of-stack should be in M-state. 3637 // The locked add instruction is serializing, of course. 3638 // (4) Use xchg, which is serializing 3639 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 3640 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 3641 // The integer condition codes will tell us if succ was 0. 3642 // Since _succ and _owner should reside in the same $line and 3643 // we just stored into _owner, it's likely that the $line 3644 // remains in M-state for the lock:orl. 3645 // 3646 // We currently use (3), although it's likely that switching to (2) 3647 // is correct for the future. 3648 3649 masm.movl (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ; 3650 if (os::is_MP()) { 3651 if (VM_Version::supports_sse2() && 1 == FenceInstruction) { 3652 masm.emit_raw (0x0F) ; // MFENCE ... 3653 masm.emit_raw (0xAE) ; 3654 masm.emit_raw (0xF0) ; 3655 } else { 3656 masm.lock () ; masm.addl (Address(rsp, 0), 0) ; 3657 } 3658 } 3659 // Ratify _succ remains non-null 3660 masm.cmpl (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 3661 masm.jccb (Assembler::notZero, LSuccess) ; 3662 3663 masm.xorl (boxReg, boxReg) ; // box is really EAX 3664 if (os::is_MP()) { masm.lock(); } 3665 masm.cmpxchg(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); 3666 masm.jccb (Assembler::notEqual, LSuccess) ; 3667 // Since we're low on registers we installed rsp as a placeholding in _owner. 3668 // Now install Self over rsp. This is safe as we're transitioning from 3669 // non-null to non=null 3670 masm.get_thread (boxReg) ; 3671 masm.movl (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ; 3672 // Intentional fall-through into LGoSlowPath ... 3673 3674 masm.bind (LGoSlowPath) ; 3675 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure 3676 masm.jmpb (DONE_LABEL) ; 3677 3678 masm.bind (LSuccess) ; 3679 masm.xorl (boxReg, boxReg) ; // set ICC.ZF=1 to indicate success 3680 masm.jmpb (DONE_LABEL) ; 3681 } 3682 3683 masm.bind (Stacked) ; 3684 // It's not inflated and it's not recursively stack-locked and it's not biased. 3685 // It must be stack-locked. 3686 // Try to reset the header to displaced header. 3687 // The "box" value on the stack is stable, so we can reload 3688 // and be assured we observe the same value as above. 3689 masm.movl (tmpReg, Address(boxReg, 0)) ; 3690 if (os::is_MP()) { masm.lock(); } 3691 masm.cmpxchg(tmpReg, Address(objReg, 0)); // Uses EAX which is box 3692 // Intention fall-thru into DONE_LABEL 3693 3694 3695 // DONE_LABEL is a hot target - we'd really like to place it at the 3696 // start of cache line by padding with NOPs. 3697 // See the AMD and Intel software optimization manuals for the 3698 // most efficient "long" NOP encodings. 3699 // Unfortunately none of our alignment mechanisms suffice. 3700 if ((EmitSync & 65536) == 0) { 3701 masm.bind (CheckSucc) ; 3702 } 3703 masm.bind(DONE_LABEL); 3704 3705 // Avoid branch to branch on AMD processors 3706 if (EmitSync & 32768) { masm.nop() ; } 3707 } 3708 %} 3709 3710 enc_class enc_String_Compare() %{ 3711 Label ECX_GOOD_LABEL, LENGTH_DIFF_LABEL, 3712 POP_LABEL, DONE_LABEL, CONT_LABEL, 3713 WHILE_HEAD_LABEL; 3714 MacroAssembler masm(&cbuf); 3715 3716 // Get the first character position in both strings 3717 // [8] char array, [12] offset, [16] count 3718 int value_offset = java_lang_String::value_offset_in_bytes(); 3719 int offset_offset = java_lang_String::offset_offset_in_bytes(); 3720 int count_offset = java_lang_String::count_offset_in_bytes(); 3721 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 3722 3723 masm.movl(rax, Address(rsi, value_offset)); 3724 masm.movl(rcx, Address(rsi, offset_offset)); 3725 masm.leal(rax, Address(rax, rcx, Address::times_2, base_offset)); 3726 masm.movl(rbx, Address(rdi, value_offset)); 3727 masm.movl(rcx, Address(rdi, offset_offset)); 3728 masm.leal(rbx, Address(rbx, rcx, Address::times_2, base_offset)); 3729 3730 // Compute the minimum of the string lengths(rsi) and the 3731 // difference of the string lengths (stack) 3732 3733 3734 if (VM_Version::supports_cmov()) { 3735 masm.movl(rdi, Address(rdi, count_offset)); 3736 masm.movl(rsi, Address(rsi, count_offset)); 3737 masm.movl(rcx, rdi); 3738 masm.subl(rdi, rsi); 3739 masm.pushl(rdi); 3740 masm.cmovl(Assembler::lessEqual, rsi, rcx); 3741 } else { 3742 masm.movl(rdi, Address(rdi, count_offset)); 3743 masm.movl(rcx, Address(rsi, count_offset)); 3744 masm.movl(rsi, rdi); 3745 masm.subl(rdi, rcx); 3746 masm.pushl(rdi); 3747 masm.jcc(Assembler::lessEqual, ECX_GOOD_LABEL); 3748 masm.movl(rsi, rcx); 3749 // rsi holds min, rcx is unused 3750 } 3751 3752 // Is the minimum length zero? 3753 masm.bind(ECX_GOOD_LABEL); 3754 masm.testl(rsi, rsi); 3755 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL); 3756 3757 // Load first characters 3758 masm.load_unsigned_word(rcx, Address(rbx, 0)); 3759 masm.load_unsigned_word(rdi, Address(rax, 0)); 3760 3761 // Compare first characters 3762 masm.subl(rcx, rdi); 3763 masm.jcc(Assembler::notZero, POP_LABEL); 3764 masm.decrement(rsi); 3765 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL); 3766 3767 { 3768 // Check after comparing first character to see if strings are equivalent 3769 Label LSkip2; 3770 // Check if the strings start at same location 3771 masm.cmpl(rbx,rax); 3772 masm.jcc(Assembler::notEqual, LSkip2); 3773 3774 // Check if the length difference is zero (from stack) 3775 masm.cmpl(Address(rsp, 0), 0x0); 3776 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL); 3777 3778 // Strings might not be equivalent 3779 masm.bind(LSkip2); 3780 } 3781 3782 // Shift rax, and rbx, to the end of the arrays, negate min 3783 masm.leal(rax, Address(rax, rsi, Address::times_2, 2)); 3784 masm.leal(rbx, Address(rbx, rsi, Address::times_2, 2)); 3785 masm.negl(rsi); 3786 3787 // Compare the rest of the characters 3788 masm.bind(WHILE_HEAD_LABEL); 3789 masm.load_unsigned_word(rcx, Address(rbx, rsi, Address::times_2, 0)); 3790 masm.load_unsigned_word(rdi, Address(rax, rsi, Address::times_2, 0)); 3791 masm.subl(rcx, rdi); 3792 masm.jcc(Assembler::notZero, POP_LABEL); 3793 masm.increment(rsi); 3794 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL); 3795 3796 // Strings are equal up to min length. Return the length difference. 3797 masm.bind(LENGTH_DIFF_LABEL); 3798 masm.popl(rcx); 3799 masm.jmp(DONE_LABEL); 3800 3801 // Discard the stored length difference 3802 masm.bind(POP_LABEL); 3803 masm.addl(rsp, 4); 3804 3805 // That's it 3806 masm.bind(DONE_LABEL); 3807 %} 3808 3809 enc_class enc_Array_Equals(eDIRegP ary1, eSIRegP ary2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result) %{ 3810 Label TRUE_LABEL, FALSE_LABEL, DONE_LABEL, COMPARE_LOOP_HDR, COMPARE_LOOP; 3811 MacroAssembler masm(&cbuf); 3812 3813 Register ary1Reg = as_Register($ary1$$reg); 3814 Register ary2Reg = as_Register($ary2$$reg); 3815 Register tmp1Reg = as_Register($tmp1$$reg); 3816 Register tmp2Reg = as_Register($tmp2$$reg); 3817 Register resultReg = as_Register($result$$reg); 3818 3819 int length_offset = arrayOopDesc::length_offset_in_bytes(); 3820 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 3821 3822 // Check the input args 3823 masm.cmpl(ary1Reg, ary2Reg); 3824 masm.jcc(Assembler::equal, TRUE_LABEL); 3825 masm.testl(ary1Reg, ary1Reg); 3826 masm.jcc(Assembler::zero, FALSE_LABEL); 3827 masm.testl(ary2Reg, ary2Reg); 3828 masm.jcc(Assembler::zero, FALSE_LABEL); 3829 3830 // Check the lengths 3831 masm.movl(tmp2Reg, Address(ary1Reg, length_offset)); 3832 masm.movl(resultReg, Address(ary2Reg, length_offset)); 3833 masm.cmpl(tmp2Reg, resultReg); 3834 masm.jcc(Assembler::notEqual, FALSE_LABEL); 3835 masm.testl(resultReg, resultReg); 3836 masm.jcc(Assembler::zero, TRUE_LABEL); 3837 3838 // Get the number of 4 byte vectors to compare 3839 masm.shrl(resultReg, 1); 3840 3841 // Check for odd-length arrays 3842 masm.andl(tmp2Reg, 1); 3843 masm.testl(tmp2Reg, tmp2Reg); 3844 masm.jcc(Assembler::zero, COMPARE_LOOP_HDR); 3845 3846 // Compare 2-byte "tail" at end of arrays 3847 masm.load_unsigned_word(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset)); 3848 masm.load_unsigned_word(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset)); 3849 masm.cmpl(tmp1Reg, tmp2Reg); 3850 masm.jcc(Assembler::notEqual, FALSE_LABEL); 3851 masm.testl(resultReg, resultReg); 3852 masm.jcc(Assembler::zero, TRUE_LABEL); 3853 3854 // Setup compare loop 3855 masm.bind(COMPARE_LOOP_HDR); 3856 // Shift tmp1Reg and tmp2Reg to the last 4-byte boundary of the arrays 3857 masm.leal(tmp1Reg, Address(ary1Reg, resultReg, Address::times_4, base_offset)); 3858 masm.leal(tmp2Reg, Address(ary2Reg, resultReg, Address::times_4, base_offset)); 3859 masm.negl(resultReg); 3860 3861 // 4-byte-wide compare loop 3862 masm.bind(COMPARE_LOOP); 3863 masm.movl(ary1Reg, Address(tmp1Reg, resultReg, Address::times_4, 0)); 3864 masm.movl(ary2Reg, Address(tmp2Reg, resultReg, Address::times_4, 0)); 3865 masm.cmpl(ary1Reg, ary2Reg); 3866 masm.jcc(Assembler::notEqual, FALSE_LABEL); 3867 masm.increment(resultReg); 3868 masm.jcc(Assembler::notZero, COMPARE_LOOP); 3869 3870 masm.bind(TRUE_LABEL); 3871 masm.movl(resultReg, 1); // return true 3872 masm.jmp(DONE_LABEL); 3873 3874 masm.bind(FALSE_LABEL); 3875 masm.xorl(resultReg, resultReg); // return false 3876 3877 // That's it 3878 masm.bind(DONE_LABEL); 3879 %} 3880 3881 enc_class enc_pop_rdx() %{ 3882 emit_opcode(cbuf,0x5A); 3883 %} 3884 3885 enc_class enc_rethrow() %{ 3886 cbuf.set_inst_mark(); 3887 emit_opcode(cbuf, 0xE9); // jmp entry 3888 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4, 3889 runtime_call_Relocation::spec(), RELOC_IMM32 ); 3890 %} 3891 3892 3893 // Convert a double to an int. Java semantics require we do complex 3894 // manglelations in the corner cases. So we set the rounding mode to 3895 // 'zero', store the darned double down as an int, and reset the 3896 // rounding mode to 'nearest'. The hardware throws an exception which 3897 // patches up the correct value directly to the stack. 3898 enc_class D2I_encoding( regD src ) %{ 3899 // Flip to round-to-zero mode. We attempted to allow invalid-op 3900 // exceptions here, so that a NAN or other corner-case value will 3901 // thrown an exception (but normal values get converted at full speed). 3902 // However, I2C adapters and other float-stack manglers leave pending 3903 // invalid-op exceptions hanging. We would have to clear them before 3904 // enabling them and that is more expensive than just testing for the 3905 // invalid value Intel stores down in the corner cases. 3906 emit_opcode(cbuf,0xD9); // FLDCW trunc 3907 emit_opcode(cbuf,0x2D); 3908 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 3909 // Allocate a word 3910 emit_opcode(cbuf,0x83); // SUB ESP,4 3911 emit_opcode(cbuf,0xEC); 3912 emit_d8(cbuf,0x04); 3913 // Encoding assumes a double has been pushed into FPR0. 3914 // Store down the double as an int, popping the FPU stack 3915 emit_opcode(cbuf,0xDB); // FISTP [ESP] 3916 emit_opcode(cbuf,0x1C); 3917 emit_d8(cbuf,0x24); 3918 // Restore the rounding mode; mask the exception 3919 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 3920 emit_opcode(cbuf,0x2D); 3921 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 3922 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 3923 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 3924 3925 // Load the converted int; adjust CPU stack 3926 emit_opcode(cbuf,0x58); // POP EAX 3927 emit_opcode(cbuf,0x3D); // CMP EAX,imm 3928 emit_d32 (cbuf,0x80000000); // 0x80000000 3929 emit_opcode(cbuf,0x75); // JNE around_slow_call 3930 emit_d8 (cbuf,0x07); // Size of slow_call 3931 // Push src onto stack slow-path 3932 emit_opcode(cbuf,0xD9 ); // FLD ST(i) 3933 emit_d8 (cbuf,0xC0-1+$src$$reg ); 3934 // CALL directly to the runtime 3935 cbuf.set_inst_mark(); 3936 emit_opcode(cbuf,0xE8); // Call into runtime 3937 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3938 // Carry on here... 3939 %} 3940 3941 enc_class D2L_encoding( regD src ) %{ 3942 emit_opcode(cbuf,0xD9); // FLDCW trunc 3943 emit_opcode(cbuf,0x2D); 3944 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 3945 // Allocate a word 3946 emit_opcode(cbuf,0x83); // SUB ESP,8 3947 emit_opcode(cbuf,0xEC); 3948 emit_d8(cbuf,0x08); 3949 // Encoding assumes a double has been pushed into FPR0. 3950 // Store down the double as a long, popping the FPU stack 3951 emit_opcode(cbuf,0xDF); // FISTP [ESP] 3952 emit_opcode(cbuf,0x3C); 3953 emit_d8(cbuf,0x24); 3954 // Restore the rounding mode; mask the exception 3955 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 3956 emit_opcode(cbuf,0x2D); 3957 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 3958 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 3959 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 3960 3961 // Load the converted int; adjust CPU stack 3962 emit_opcode(cbuf,0x58); // POP EAX 3963 emit_opcode(cbuf,0x5A); // POP EDX 3964 emit_opcode(cbuf,0x81); // CMP EDX,imm 3965 emit_d8 (cbuf,0xFA); // rdx 3966 emit_d32 (cbuf,0x80000000); // 0x80000000 3967 emit_opcode(cbuf,0x75); // JNE around_slow_call 3968 emit_d8 (cbuf,0x07+4); // Size of slow_call 3969 emit_opcode(cbuf,0x85); // TEST EAX,EAX 3970 emit_opcode(cbuf,0xC0); // 2/rax,/rax, 3971 emit_opcode(cbuf,0x75); // JNE around_slow_call 3972 emit_d8 (cbuf,0x07); // Size of slow_call 3973 // Push src onto stack slow-path 3974 emit_opcode(cbuf,0xD9 ); // FLD ST(i) 3975 emit_d8 (cbuf,0xC0-1+$src$$reg ); 3976 // CALL directly to the runtime 3977 cbuf.set_inst_mark(); 3978 emit_opcode(cbuf,0xE8); // Call into runtime 3979 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3980 // Carry on here... 3981 %} 3982 3983 enc_class X2L_encoding( regX src ) %{ 3984 // Allocate a word 3985 emit_opcode(cbuf,0x83); // SUB ESP,8 3986 emit_opcode(cbuf,0xEC); 3987 emit_d8(cbuf,0x08); 3988 3989 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src 3990 emit_opcode (cbuf, 0x0F ); 3991 emit_opcode (cbuf, 0x11 ); 3992 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 3993 3994 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] 3995 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 3996 3997 emit_opcode(cbuf,0xD9); // FLDCW trunc 3998 emit_opcode(cbuf,0x2D); 3999 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 4000 4001 // Encoding assumes a double has been pushed into FPR0. 4002 // Store down the double as a long, popping the FPU stack 4003 emit_opcode(cbuf,0xDF); // FISTP [ESP] 4004 emit_opcode(cbuf,0x3C); 4005 emit_d8(cbuf,0x24); 4006 4007 // Restore the rounding mode; mask the exception 4008 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 4009 emit_opcode(cbuf,0x2D); 4010 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 4011 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 4012 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 4013 4014 // Load the converted int; adjust CPU stack 4015 emit_opcode(cbuf,0x58); // POP EAX 4016 4017 emit_opcode(cbuf,0x5A); // POP EDX 4018 4019 emit_opcode(cbuf,0x81); // CMP EDX,imm 4020 emit_d8 (cbuf,0xFA); // rdx 4021 emit_d32 (cbuf,0x80000000);// 0x80000000 4022 4023 emit_opcode(cbuf,0x75); // JNE around_slow_call 4024 emit_d8 (cbuf,0x13+4); // Size of slow_call 4025 4026 emit_opcode(cbuf,0x85); // TEST EAX,EAX 4027 emit_opcode(cbuf,0xC0); // 2/rax,/rax, 4028 4029 emit_opcode(cbuf,0x75); // JNE around_slow_call 4030 emit_d8 (cbuf,0x13); // Size of slow_call 4031 4032 // Allocate a word 4033 emit_opcode(cbuf,0x83); // SUB ESP,4 4034 emit_opcode(cbuf,0xEC); 4035 emit_d8(cbuf,0x04); 4036 4037 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src 4038 emit_opcode (cbuf, 0x0F ); 4039 emit_opcode (cbuf, 0x11 ); 4040 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 4041 4042 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] 4043 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 4044 4045 emit_opcode(cbuf,0x83); // ADD ESP,4 4046 emit_opcode(cbuf,0xC4); 4047 emit_d8(cbuf,0x04); 4048 4049 // CALL directly to the runtime 4050 cbuf.set_inst_mark(); 4051 emit_opcode(cbuf,0xE8); // Call into runtime 4052 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 4053 // Carry on here... 4054 %} 4055 4056 enc_class XD2L_encoding( regXD src ) %{ 4057 // Allocate a word 4058 emit_opcode(cbuf,0x83); // SUB ESP,8 4059 emit_opcode(cbuf,0xEC); 4060 emit_d8(cbuf,0x08); 4061 4062 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src 4063 emit_opcode (cbuf, 0x0F ); 4064 emit_opcode (cbuf, 0x11 ); 4065 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 4066 4067 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 4068 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 4069 4070 emit_opcode(cbuf,0xD9); // FLDCW trunc 4071 emit_opcode(cbuf,0x2D); 4072 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 4073 4074 // Encoding assumes a double has been pushed into FPR0. 4075 // Store down the double as a long, popping the FPU stack 4076 emit_opcode(cbuf,0xDF); // FISTP [ESP] 4077 emit_opcode(cbuf,0x3C); 4078 emit_d8(cbuf,0x24); 4079 4080 // Restore the rounding mode; mask the exception 4081 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 4082 emit_opcode(cbuf,0x2D); 4083 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 4084 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 4085 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 4086 4087 // Load the converted int; adjust CPU stack 4088 emit_opcode(cbuf,0x58); // POP EAX 4089 4090 emit_opcode(cbuf,0x5A); // POP EDX 4091 4092 emit_opcode(cbuf,0x81); // CMP EDX,imm 4093 emit_d8 (cbuf,0xFA); // rdx 4094 emit_d32 (cbuf,0x80000000); // 0x80000000 4095 4096 emit_opcode(cbuf,0x75); // JNE around_slow_call 4097 emit_d8 (cbuf,0x13+4); // Size of slow_call 4098 4099 emit_opcode(cbuf,0x85); // TEST EAX,EAX 4100 emit_opcode(cbuf,0xC0); // 2/rax,/rax, 4101 4102 emit_opcode(cbuf,0x75); // JNE around_slow_call 4103 emit_d8 (cbuf,0x13); // Size of slow_call 4104 4105 // Push src onto stack slow-path 4106 // Allocate a word 4107 emit_opcode(cbuf,0x83); // SUB ESP,8 4108 emit_opcode(cbuf,0xEC); 4109 emit_d8(cbuf,0x08); 4110 4111 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src 4112 emit_opcode (cbuf, 0x0F ); 4113 emit_opcode (cbuf, 0x11 ); 4114 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 4115 4116 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 4117 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 4118 4119 emit_opcode(cbuf,0x83); // ADD ESP,8 4120 emit_opcode(cbuf,0xC4); 4121 emit_d8(cbuf,0x08); 4122 4123 // CALL directly to the runtime 4124 cbuf.set_inst_mark(); 4125 emit_opcode(cbuf,0xE8); // Call into runtime 4126 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 4127 // Carry on here... 4128 %} 4129 4130 enc_class D2X_encoding( regX dst, regD src ) %{ 4131 // Allocate a word 4132 emit_opcode(cbuf,0x83); // SUB ESP,4 4133 emit_opcode(cbuf,0xEC); 4134 emit_d8(cbuf,0x04); 4135 int pop = 0x02; 4136 if ($src$$reg != FPR1L_enc) { 4137 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 4138 emit_d8( cbuf, 0xC0-1+$src$$reg ); 4139 pop = 0x03; 4140 } 4141 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP] 4142 4143 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP] 4144 emit_opcode (cbuf, 0x0F ); 4145 emit_opcode (cbuf, 0x10 ); 4146 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); 4147 4148 emit_opcode(cbuf,0x83); // ADD ESP,4 4149 emit_opcode(cbuf,0xC4); 4150 emit_d8(cbuf,0x04); 4151 // Carry on here... 4152 %} 4153 4154 enc_class FX2I_encoding( regX src, eRegI dst ) %{ 4155 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 4156 4157 // Compare the result to see if we need to go to the slow path 4158 emit_opcode(cbuf,0x81); // CMP dst,imm 4159 emit_rm (cbuf,0x3,0x7,$dst$$reg); 4160 emit_d32 (cbuf,0x80000000); // 0x80000000 4161 4162 emit_opcode(cbuf,0x75); // JNE around_slow_call 4163 emit_d8 (cbuf,0x13); // Size of slow_call 4164 // Store xmm to a temp memory 4165 // location and push it onto stack. 4166 4167 emit_opcode(cbuf,0x83); // SUB ESP,4 4168 emit_opcode(cbuf,0xEC); 4169 emit_d8(cbuf, $primary ? 0x8 : 0x4); 4170 4171 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm 4172 emit_opcode (cbuf, 0x0F ); 4173 emit_opcode (cbuf, 0x11 ); 4174 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 4175 4176 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP] 4177 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 4178 4179 emit_opcode(cbuf,0x83); // ADD ESP,4 4180 emit_opcode(cbuf,0xC4); 4181 emit_d8(cbuf, $primary ? 0x8 : 0x4); 4182 4183 // CALL directly to the runtime 4184 cbuf.set_inst_mark(); 4185 emit_opcode(cbuf,0xE8); // Call into runtime 4186 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 4187 4188 // Carry on here... 4189 %} 4190 4191 enc_class X2D_encoding( regD dst, regX src ) %{ 4192 // Allocate a word 4193 emit_opcode(cbuf,0x83); // SUB ESP,4 4194 emit_opcode(cbuf,0xEC); 4195 emit_d8(cbuf,0x04); 4196 4197 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm 4198 emit_opcode (cbuf, 0x0F ); 4199 emit_opcode (cbuf, 0x11 ); 4200 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 4201 4202 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] 4203 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 4204 4205 emit_opcode(cbuf,0x83); // ADD ESP,4 4206 emit_opcode(cbuf,0xC4); 4207 emit_d8(cbuf,0x04); 4208 4209 // Carry on here... 4210 %} 4211 4212 enc_class AbsXF_encoding(regX dst) %{ 4213 address signmask_address=(address)float_signmask_pool; 4214 // andpd:\tANDPS $dst,[signconst] 4215 emit_opcode(cbuf, 0x0F); 4216 emit_opcode(cbuf, 0x54); 4217 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 4218 emit_d32(cbuf, (int)signmask_address); 4219 %} 4220 4221 enc_class AbsXD_encoding(regXD dst) %{ 4222 address signmask_address=(address)double_signmask_pool; 4223 // andpd:\tANDPD $dst,[signconst] 4224 emit_opcode(cbuf, 0x66); 4225 emit_opcode(cbuf, 0x0F); 4226 emit_opcode(cbuf, 0x54); 4227 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 4228 emit_d32(cbuf, (int)signmask_address); 4229 %} 4230 4231 enc_class NegXF_encoding(regX dst) %{ 4232 address signmask_address=(address)float_signflip_pool; 4233 // andpd:\tXORPS $dst,[signconst] 4234 emit_opcode(cbuf, 0x0F); 4235 emit_opcode(cbuf, 0x57); 4236 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 4237 emit_d32(cbuf, (int)signmask_address); 4238 %} 4239 4240 enc_class NegXD_encoding(regXD dst) %{ 4241 address signmask_address=(address)double_signflip_pool; 4242 // andpd:\tXORPD $dst,[signconst] 4243 emit_opcode(cbuf, 0x66); 4244 emit_opcode(cbuf, 0x0F); 4245 emit_opcode(cbuf, 0x57); 4246 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 4247 emit_d32(cbuf, (int)signmask_address); 4248 %} 4249 4250 enc_class FMul_ST_reg( eRegF src1 ) %{ 4251 // Operand was loaded from memory into fp ST (stack top) 4252 // FMUL ST,$src /* D8 C8+i */ 4253 emit_opcode(cbuf, 0xD8); 4254 emit_opcode(cbuf, 0xC8 + $src1$$reg); 4255 %} 4256 4257 enc_class FAdd_ST_reg( eRegF src2 ) %{ 4258 // FADDP ST,src2 /* D8 C0+i */ 4259 emit_opcode(cbuf, 0xD8); 4260 emit_opcode(cbuf, 0xC0 + $src2$$reg); 4261 //could use FADDP src2,fpST /* DE C0+i */ 4262 %} 4263 4264 enc_class FAddP_reg_ST( eRegF src2 ) %{ 4265 // FADDP src2,ST /* DE C0+i */ 4266 emit_opcode(cbuf, 0xDE); 4267 emit_opcode(cbuf, 0xC0 + $src2$$reg); 4268 %} 4269 4270 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{ 4271 // Operand has been loaded into fp ST (stack top) 4272 // FSUB ST,$src1 4273 emit_opcode(cbuf, 0xD8); 4274 emit_opcode(cbuf, 0xE0 + $src1$$reg); 4275 4276 // FDIV 4277 emit_opcode(cbuf, 0xD8); 4278 emit_opcode(cbuf, 0xF0 + $src2$$reg); 4279 %} 4280 4281 enc_class MulFAddF (eRegF src1, eRegF src2) %{ 4282 // Operand was loaded from memory into fp ST (stack top) 4283 // FADD ST,$src /* D8 C0+i */ 4284 emit_opcode(cbuf, 0xD8); 4285 emit_opcode(cbuf, 0xC0 + $src1$$reg); 4286 4287 // FMUL ST,src2 /* D8 C*+i */ 4288 emit_opcode(cbuf, 0xD8); 4289 emit_opcode(cbuf, 0xC8 + $src2$$reg); 4290 %} 4291 4292 4293 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{ 4294 // Operand was loaded from memory into fp ST (stack top) 4295 // FADD ST,$src /* D8 C0+i */ 4296 emit_opcode(cbuf, 0xD8); 4297 emit_opcode(cbuf, 0xC0 + $src1$$reg); 4298 4299 // FMULP src2,ST /* DE C8+i */ 4300 emit_opcode(cbuf, 0xDE); 4301 emit_opcode(cbuf, 0xC8 + $src2$$reg); 4302 %} 4303 4304 enc_class enc_membar_acquire %{ 4305 // Doug Lea believes this is not needed with current Sparcs and TSO. 4306 // MacroAssembler masm(&cbuf); 4307 // masm.membar(); 4308 %} 4309 4310 enc_class enc_membar_release %{ 4311 // Doug Lea believes this is not needed with current Sparcs and TSO. 4312 // MacroAssembler masm(&cbuf); 4313 // masm.membar(); 4314 %} 4315 4316 enc_class enc_membar_volatile %{ 4317 MacroAssembler masm(&cbuf); 4318 masm.membar(); 4319 %} 4320 4321 // Atomically load the volatile long 4322 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ 4323 emit_opcode(cbuf,0xDF); 4324 int rm_byte_opcode = 0x05; 4325 int base = $mem$$base; 4326 int index = $mem$$index; 4327 int scale = $mem$$scale; 4328 int displace = $mem$$disp; 4329 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4330 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 4331 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); 4332 %} 4333 4334 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{ 4335 { // Atomic long load 4336 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem 4337 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 4338 emit_opcode(cbuf,0x0F); 4339 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); 4340 int base = $mem$$base; 4341 int index = $mem$$index; 4342 int scale = $mem$$scale; 4343 int displace = $mem$$disp; 4344 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4345 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4346 } 4347 { // MOVSD $dst,$tmp ! atomic long store 4348 emit_opcode(cbuf,0xF2); 4349 emit_opcode(cbuf,0x0F); 4350 emit_opcode(cbuf,0x11); 4351 int base = $dst$$base; 4352 int index = $dst$$index; 4353 int scale = $dst$$scale; 4354 int displace = $dst$$disp; 4355 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals 4356 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4357 } 4358 %} 4359 4360 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{ 4361 { // Atomic long load 4362 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem 4363 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 4364 emit_opcode(cbuf,0x0F); 4365 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); 4366 int base = $mem$$base; 4367 int index = $mem$$index; 4368 int scale = $mem$$scale; 4369 int displace = $mem$$disp; 4370 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4371 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4372 } 4373 { // MOVD $dst.lo,$tmp 4374 emit_opcode(cbuf,0x66); 4375 emit_opcode(cbuf,0x0F); 4376 emit_opcode(cbuf,0x7E); 4377 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg); 4378 } 4379 { // PSRLQ $tmp,32 4380 emit_opcode(cbuf,0x66); 4381 emit_opcode(cbuf,0x0F); 4382 emit_opcode(cbuf,0x73); 4383 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg); 4384 emit_d8(cbuf, 0x20); 4385 } 4386 { // MOVD $dst.hi,$tmp 4387 emit_opcode(cbuf,0x66); 4388 emit_opcode(cbuf,0x0F); 4389 emit_opcode(cbuf,0x7E); 4390 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg)); 4391 } 4392 %} 4393 4394 // Volatile Store Long. Must be atomic, so move it into 4395 // the FP TOS and then do a 64-bit FIST. Has to probe the 4396 // target address before the store (for null-ptr checks) 4397 // so the memory operand is used twice in the encoding. 4398 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ 4399 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); 4400 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop 4401 emit_opcode(cbuf,0xDF); 4402 int rm_byte_opcode = 0x07; 4403 int base = $mem$$base; 4404 int index = $mem$$index; 4405 int scale = $mem$$scale; 4406 int displace = $mem$$disp; 4407 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4408 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 4409 %} 4410 4411 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{ 4412 { // Atomic long load 4413 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src] 4414 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 4415 emit_opcode(cbuf,0x0F); 4416 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); 4417 int base = $src$$base; 4418 int index = $src$$index; 4419 int scale = $src$$scale; 4420 int displace = $src$$disp; 4421 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals 4422 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4423 } 4424 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop 4425 { // MOVSD $mem,$tmp ! atomic long store 4426 emit_opcode(cbuf,0xF2); 4427 emit_opcode(cbuf,0x0F); 4428 emit_opcode(cbuf,0x11); 4429 int base = $mem$$base; 4430 int index = $mem$$index; 4431 int scale = $mem$$scale; 4432 int displace = $mem$$disp; 4433 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4434 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4435 } 4436 %} 4437 4438 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{ 4439 { // MOVD $tmp,$src.lo 4440 emit_opcode(cbuf,0x66); 4441 emit_opcode(cbuf,0x0F); 4442 emit_opcode(cbuf,0x6E); 4443 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); 4444 } 4445 { // MOVD $tmp2,$src.hi 4446 emit_opcode(cbuf,0x66); 4447 emit_opcode(cbuf,0x0F); 4448 emit_opcode(cbuf,0x6E); 4449 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg)); 4450 } 4451 { // PUNPCKLDQ $tmp,$tmp2 4452 emit_opcode(cbuf,0x66); 4453 emit_opcode(cbuf,0x0F); 4454 emit_opcode(cbuf,0x62); 4455 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg); 4456 } 4457 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop 4458 { // MOVSD $mem,$tmp ! atomic long store 4459 emit_opcode(cbuf,0xF2); 4460 emit_opcode(cbuf,0x0F); 4461 emit_opcode(cbuf,0x11); 4462 int base = $mem$$base; 4463 int index = $mem$$index; 4464 int scale = $mem$$scale; 4465 int displace = $mem$$disp; 4466 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4467 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4468 } 4469 %} 4470 4471 // Safepoint Poll. This polls the safepoint page, and causes an 4472 // exception if it is not readable. Unfortunately, it kills the condition code 4473 // in the process 4474 // We current use TESTL [spp],EDI 4475 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 4476 4477 enc_class Safepoint_Poll() %{ 4478 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0); 4479 emit_opcode(cbuf,0x85); 4480 emit_rm (cbuf, 0x0, 0x7, 0x5); 4481 emit_d32(cbuf, (intptr_t)os::get_polling_page()); 4482 %} 4483%} 4484 4485 4486//----------FRAME-------------------------------------------------------------- 4487// Definition of frame structure and management information. 4488// 4489// S T A C K L A Y O U T Allocators stack-slot number 4490// | (to get allocators register number 4491// G Owned by | | v add OptoReg::stack0()) 4492// r CALLER | | 4493// o | +--------+ pad to even-align allocators stack-slot 4494// w V | pad0 | numbers; owned by CALLER 4495// t -----------+--------+----> Matcher::_in_arg_limit, unaligned 4496// h ^ | in | 5 4497// | | args | 4 Holes in incoming args owned by SELF 4498// | | | | 3 4499// | | +--------+ 4500// V | | old out| Empty on Intel, window on Sparc 4501// | old |preserve| Must be even aligned. 4502// | SP-+--------+----> Matcher::_old_SP, even aligned 4503// | | in | 3 area for Intel ret address 4504// Owned by |preserve| Empty on Sparc. 4505// SELF +--------+ 4506// | | pad2 | 2 pad to align old SP 4507// | +--------+ 1 4508// | | locks | 0 4509// | +--------+----> OptoReg::stack0(), even aligned 4510// | | pad1 | 11 pad to align new SP 4511// | +--------+ 4512// | | | 10 4513// | | spills | 9 spills 4514// V | | 8 (pad0 slot for callee) 4515// -----------+--------+----> Matcher::_out_arg_limit, unaligned 4516// ^ | out | 7 4517// | | args | 6 Holes in outgoing args owned by CALLEE 4518// Owned by +--------+ 4519// CALLEE | new out| 6 Empty on Intel, window on Sparc 4520// | new |preserve| Must be even-aligned. 4521// | SP-+--------+----> Matcher::_new_SP, even aligned 4522// | | | 4523// 4524// Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 4525// known from SELF's arguments and the Java calling convention. 4526// Region 6-7 is determined per call site. 4527// Note 2: If the calling convention leaves holes in the incoming argument 4528// area, those holes are owned by SELF. Holes in the outgoing area 4529// are owned by the CALLEE. Holes should not be nessecary in the 4530// incoming area, as the Java calling convention is completely under 4531// the control of the AD file. Doubles can be sorted and packed to 4532// avoid holes. Holes in the outgoing arguments may be nessecary for 4533// varargs C calling conventions. 4534// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 4535// even aligned with pad0 as needed. 4536// Region 6 is even aligned. Region 6-7 is NOT even aligned; 4537// region 6-11 is even aligned; it may be padded out more so that 4538// the region from SP to FP meets the minimum stack alignment. 4539 4540frame %{ 4541 // What direction does stack grow in (assumed to be same for C & Java) 4542 stack_direction(TOWARDS_LOW); 4543 4544 // These three registers define part of the calling convention 4545 // between compiled code and the interpreter. 4546 inline_cache_reg(EAX); // Inline Cache Register 4547 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter 4548 4549 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 4550 cisc_spilling_operand_name(indOffset32); 4551 4552 // Number of stack slots consumed by locking an object 4553 sync_stack_slots(1); 4554 4555 // Compiled code's Frame Pointer 4556 frame_pointer(ESP); 4557 // Interpreter stores its frame pointer in a register which is 4558 // stored to the stack by I2CAdaptors. 4559 // I2CAdaptors convert from interpreted java to compiled java. 4560 interpreter_frame_pointer(EBP); 4561 4562 // Stack alignment requirement 4563 // Alignment size in bytes (128-bit -> 16 bytes) 4564 stack_alignment(StackAlignmentInBytes); 4565 4566 // Number of stack slots between incoming argument block and the start of 4567 // a new frame. The PROLOG must add this many slots to the stack. The 4568 // EPILOG must remove this many slots. Intel needs one slot for 4569 // return address and one for rbp, (must save rbp) 4570 in_preserve_stack_slots(2+VerifyStackAtCalls); 4571 4572 // Number of outgoing stack slots killed above the out_preserve_stack_slots 4573 // for calls to C. Supports the var-args backing area for register parms. 4574 varargs_C_out_slots_killed(0); 4575 4576 // The after-PROLOG location of the return address. Location of 4577 // return address specifies a type (REG or STACK) and a number 4578 // representing the register number (i.e. - use a register name) or 4579 // stack slot. 4580 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. 4581 // Otherwise, it is above the locks and verification slot and alignment word 4582 return_addr(STACK - 1 + 4583 round_to(1+VerifyStackAtCalls+ 4584 Compile::current()->fixed_slots(), 4585 (StackAlignmentInBytes/wordSize))); 4586 4587 // Body of function which returns an integer array locating 4588 // arguments either in registers or in stack slots. Passed an array 4589 // of ideal registers called "sig" and a "length" count. Stack-slot 4590 // offsets are based on outgoing arguments, i.e. a CALLER setting up 4591 // arguments for a CALLEE. Incoming stack arguments are 4592 // automatically biased by the preserve_stack_slots field above. 4593 calling_convention %{ 4594 // No difference between ingoing/outgoing just pass false 4595 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 4596 %} 4597 4598 4599 // Body of function which returns an integer array locating 4600 // arguments either in registers or in stack slots. Passed an array 4601 // of ideal registers called "sig" and a "length" count. Stack-slot 4602 // offsets are based on outgoing arguments, i.e. a CALLER setting up 4603 // arguments for a CALLEE. Incoming stack arguments are 4604 // automatically biased by the preserve_stack_slots field above. 4605 c_calling_convention %{ 4606 // This is obviously always outgoing 4607 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); 4608 %} 4609 4610 // Location of C & interpreter return values 4611 c_return_value %{ 4612 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 4613 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; 4614 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; 4615 4616 // in SSE2+ mode we want to keep the FPU stack clean so pretend 4617 // that C functions return float and double results in XMM0. 4618 if( ideal_reg == Op_RegD && UseSSE>=2 ) 4619 return OptoRegPair(XMM0b_num,XMM0a_num); 4620 if( ideal_reg == Op_RegF && UseSSE>=2 ) 4621 return OptoRegPair(OptoReg::Bad,XMM0a_num); 4622 4623 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); 4624 %} 4625 4626 // Location of return values 4627 return_value %{ 4628 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 4629 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; 4630 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; 4631 if( ideal_reg == Op_RegD && UseSSE>=2 ) 4632 return OptoRegPair(XMM0b_num,XMM0a_num); 4633 if( ideal_reg == Op_RegF && UseSSE>=1 ) 4634 return OptoRegPair(OptoReg::Bad,XMM0a_num); 4635 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); 4636 %} 4637 4638%} 4639 4640//----------ATTRIBUTES--------------------------------------------------------- 4641//----------Operand Attributes------------------------------------------------- 4642op_attrib op_cost(0); // Required cost attribute 4643 4644//----------Instruction Attributes--------------------------------------------- 4645ins_attrib ins_cost(100); // Required cost attribute 4646ins_attrib ins_size(8); // Required size attribute (in bits) 4647ins_attrib ins_pc_relative(0); // Required PC Relative flag 4648ins_attrib ins_short_branch(0); // Required flag: is this instruction a 4649 // non-matching short branch variant of some 4650 // long branch? 4651ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) 4652 // specifies the alignment that some part of the instruction (not 4653 // necessarily the start) requires. If > 1, a compute_padding() 4654 // function must be provided for the instruction 4655 4656//----------OPERANDS----------------------------------------------------------- 4657// Operand definitions must precede instruction definitions for correct parsing 4658// in the ADLC because operands constitute user defined types which are used in 4659// instruction definitions. 4660 4661//----------Simple Operands---------------------------------------------------- 4662// Immediate Operands 4663// Integer Immediate 4664operand immI() %{ 4665 match(ConI); 4666 4667 op_cost(10); 4668 format %{ %} 4669 interface(CONST_INTER); 4670%} 4671 4672// Constant for test vs zero 4673operand immI0() %{ 4674 predicate(n->get_int() == 0); 4675 match(ConI); 4676 4677 op_cost(0); 4678 format %{ %} 4679 interface(CONST_INTER); 4680%} 4681 4682// Constant for increment 4683operand immI1() %{ 4684 predicate(n->get_int() == 1); 4685 match(ConI); 4686 4687 op_cost(0); 4688 format %{ %} 4689 interface(CONST_INTER); 4690%} 4691 4692// Constant for decrement 4693operand immI_M1() %{ 4694 predicate(n->get_int() == -1); 4695 match(ConI); 4696 4697 op_cost(0); 4698 format %{ %} 4699 interface(CONST_INTER); 4700%} 4701 4702// Valid scale values for addressing modes 4703operand immI2() %{ 4704 predicate(0 <= n->get_int() && (n->get_int() <= 3)); 4705 match(ConI); 4706 4707 format %{ %} 4708 interface(CONST_INTER); 4709%} 4710 4711operand immI8() %{ 4712 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); 4713 match(ConI); 4714 4715 op_cost(5); 4716 format %{ %} 4717 interface(CONST_INTER); 4718%} 4719 4720operand immI16() %{ 4721 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); 4722 match(ConI); 4723 4724 op_cost(10); 4725 format %{ %} 4726 interface(CONST_INTER); 4727%} 4728 4729// Constant for long shifts 4730operand immI_32() %{ 4731 predicate( n->get_int() == 32 ); 4732 match(ConI); 4733 4734 op_cost(0); 4735 format %{ %} 4736 interface(CONST_INTER); 4737%} 4738 4739operand immI_1_31() %{ 4740 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); 4741 match(ConI); 4742 4743 op_cost(0); 4744 format %{ %} 4745 interface(CONST_INTER); 4746%} 4747 4748operand immI_32_63() %{ 4749 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); 4750 match(ConI); 4751 op_cost(0); 4752 4753 format %{ %} 4754 interface(CONST_INTER); 4755%} 4756 4757operand immI_1() %{ 4758 predicate( n->get_int() == 1 ); 4759 match(ConI); 4760 4761 op_cost(0); 4762 format %{ %} 4763 interface(CONST_INTER); 4764%} 4765 4766operand immI_2() %{ 4767 predicate( n->get_int() == 2 ); 4768 match(ConI); 4769 4770 op_cost(0); 4771 format %{ %} 4772 interface(CONST_INTER); 4773%} 4774 4775operand immI_3() %{ 4776 predicate( n->get_int() == 3 ); 4777 match(ConI); 4778 4779 op_cost(0); 4780 format %{ %} 4781 interface(CONST_INTER); 4782%} 4783 4784// Pointer Immediate 4785operand immP() %{ 4786 match(ConP); 4787 4788 op_cost(10); 4789 format %{ %} 4790 interface(CONST_INTER); 4791%} 4792 4793// NULL Pointer Immediate 4794operand immP0() %{ 4795 predicate( n->get_ptr() == 0 ); 4796 match(ConP); 4797 op_cost(0); 4798 4799 format %{ %} 4800 interface(CONST_INTER); 4801%} 4802 4803// Long Immediate 4804operand immL() %{ 4805 match(ConL); 4806 4807 op_cost(20); 4808 format %{ %} 4809 interface(CONST_INTER); 4810%} 4811 4812// Long Immediate zero 4813operand immL0() %{ 4814 predicate( n->get_long() == 0L ); 4815 match(ConL); 4816 op_cost(0); 4817 4818 format %{ %} 4819 interface(CONST_INTER); 4820%} 4821 4822// Long immediate from 0 to 127. 4823// Used for a shorter form of long mul by 10. 4824operand immL_127() %{ 4825 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); 4826 match(ConL); 4827 op_cost(0); 4828 4829 format %{ %} 4830 interface(CONST_INTER); 4831%} 4832 4833// Long Immediate: low 32-bit mask 4834operand immL_32bits() %{ 4835 predicate(n->get_long() == 0xFFFFFFFFL); 4836 match(ConL); 4837 op_cost(0); 4838 4839 format %{ %} 4840 interface(CONST_INTER); 4841%} 4842 4843// Long Immediate: low 32-bit mask 4844operand immL32() %{ 4845 predicate(n->get_long() == (int)(n->get_long())); 4846 match(ConL); 4847 op_cost(20); 4848 4849 format %{ %} 4850 interface(CONST_INTER); 4851%} 4852 4853//Double Immediate zero 4854operand immD0() %{ 4855 // Do additional (and counter-intuitive) test against NaN to work around VC++ 4856 // bug that generates code such that NaNs compare equal to 0.0 4857 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); 4858 match(ConD); 4859 4860 op_cost(5); 4861 format %{ %} 4862 interface(CONST_INTER); 4863%} 4864 4865// Double Immediate 4866operand immD1() %{ 4867 predicate( UseSSE<=1 && n->getd() == 1.0 ); 4868 match(ConD); 4869 4870 op_cost(5); 4871 format %{ %} 4872 interface(CONST_INTER); 4873%} 4874 4875// Double Immediate 4876operand immD() %{ 4877 predicate(UseSSE<=1); 4878 match(ConD); 4879 4880 op_cost(5); 4881 format %{ %} 4882 interface(CONST_INTER); 4883%} 4884 4885operand immXD() %{ 4886 predicate(UseSSE>=2); 4887 match(ConD); 4888 4889 op_cost(5); 4890 format %{ %} 4891 interface(CONST_INTER); 4892%} 4893 4894// Double Immediate zero 4895operand immXD0() %{ 4896 // Do additional (and counter-intuitive) test against NaN to work around VC++ 4897 // bug that generates code such that NaNs compare equal to 0.0 AND do not 4898 // compare equal to -0.0. 4899 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); 4900 match(ConD); 4901 4902 format %{ %} 4903 interface(CONST_INTER); 4904%} 4905 4906// Float Immediate zero 4907operand immF0() %{ 4908 predicate( UseSSE == 0 && n->getf() == 0.0 ); 4909 match(ConF); 4910 4911 op_cost(5); 4912 format %{ %} 4913 interface(CONST_INTER); 4914%} 4915 4916// Float Immediate 4917operand immF() %{ 4918 predicate( UseSSE == 0 ); 4919 match(ConF); 4920 4921 op_cost(5); 4922 format %{ %} 4923 interface(CONST_INTER); 4924%} 4925 4926// Float Immediate 4927operand immXF() %{ 4928 predicate(UseSSE >= 1); 4929 match(ConF); 4930 4931 op_cost(5); 4932 format %{ %} 4933 interface(CONST_INTER); 4934%} 4935 4936// Float Immediate zero. Zero and not -0.0 4937operand immXF0() %{ 4938 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); 4939 match(ConF); 4940 4941 op_cost(5); 4942 format %{ %} 4943 interface(CONST_INTER); 4944%} 4945 4946// Immediates for special shifts (sign extend) 4947 4948// Constants for increment 4949operand immI_16() %{ 4950 predicate( n->get_int() == 16 ); 4951 match(ConI); 4952 4953 format %{ %} 4954 interface(CONST_INTER); 4955%} 4956 4957operand immI_24() %{ 4958 predicate( n->get_int() == 24 ); 4959 match(ConI); 4960 4961 format %{ %} 4962 interface(CONST_INTER); 4963%} 4964 4965// Constant for byte-wide masking 4966operand immI_255() %{ 4967 predicate( n->get_int() == 255 ); 4968 match(ConI); 4969 4970 format %{ %} 4971 interface(CONST_INTER); 4972%} 4973 4974// Register Operands 4975// Integer Register 4976operand eRegI() %{ 4977 constraint(ALLOC_IN_RC(e_reg)); 4978 match(RegI); 4979 match(xRegI); 4980 match(eAXRegI); 4981 match(eBXRegI); 4982 match(eCXRegI); 4983 match(eDXRegI); 4984 match(eDIRegI); 4985 match(eSIRegI); 4986 4987 format %{ %} 4988 interface(REG_INTER); 4989%} 4990 4991// Subset of Integer Register 4992operand xRegI(eRegI reg) %{ 4993 constraint(ALLOC_IN_RC(x_reg)); 4994 match(reg); 4995 match(eAXRegI); 4996 match(eBXRegI); 4997 match(eCXRegI); 4998 match(eDXRegI); 4999 5000 format %{ %} 5001 interface(REG_INTER); 5002%} 5003 5004// Special Registers 5005operand eAXRegI(xRegI reg) %{ 5006 constraint(ALLOC_IN_RC(eax_reg)); 5007 match(reg); 5008 match(eRegI); 5009 5010 format %{ "EAX" %} 5011 interface(REG_INTER); 5012%} 5013 5014// Special Registers 5015operand eBXRegI(xRegI reg) %{ 5016 constraint(ALLOC_IN_RC(ebx_reg)); 5017 match(reg); 5018 match(eRegI); 5019 5020 format %{ "EBX" %} 5021 interface(REG_INTER); 5022%} 5023 5024operand eCXRegI(xRegI reg) %{ 5025 constraint(ALLOC_IN_RC(ecx_reg)); 5026 match(reg); 5027 match(eRegI); 5028 5029 format %{ "ECX" %} 5030 interface(REG_INTER); 5031%} 5032 5033operand eDXRegI(xRegI reg) %{ 5034 constraint(ALLOC_IN_RC(edx_reg)); 5035 match(reg); 5036 match(eRegI); 5037 5038 format %{ "EDX" %} 5039 interface(REG_INTER); 5040%} 5041 5042operand eDIRegI(xRegI reg) %{ 5043 constraint(ALLOC_IN_RC(edi_reg)); 5044 match(reg); 5045 match(eRegI); 5046 5047 format %{ "EDI" %} 5048 interface(REG_INTER); 5049%} 5050 5051operand naxRegI() %{ 5052 constraint(ALLOC_IN_RC(nax_reg)); 5053 match(RegI); 5054 match(eCXRegI); 5055 match(eDXRegI); 5056 match(eSIRegI); 5057 match(eDIRegI); 5058 5059 format %{ %} 5060 interface(REG_INTER); 5061%} 5062 5063operand nadxRegI() %{ 5064 constraint(ALLOC_IN_RC(nadx_reg)); 5065 match(RegI); 5066 match(eBXRegI); 5067 match(eCXRegI); 5068 match(eSIRegI); 5069 match(eDIRegI); 5070 5071 format %{ %} 5072 interface(REG_INTER); 5073%} 5074 5075operand ncxRegI() %{ 5076 constraint(ALLOC_IN_RC(ncx_reg)); 5077 match(RegI); 5078 match(eAXRegI); 5079 match(eDXRegI); 5080 match(eSIRegI); 5081 match(eDIRegI); 5082 5083 format %{ %} 5084 interface(REG_INTER); 5085%} 5086 5087// // This operand was used by cmpFastUnlock, but conflicted with 'object' reg 5088// // 5089operand eSIRegI(xRegI reg) %{ 5090 constraint(ALLOC_IN_RC(esi_reg)); 5091 match(reg); 5092 match(eRegI); 5093 5094 format %{ "ESI" %} 5095 interface(REG_INTER); 5096%} 5097 5098// Pointer Register 5099operand anyRegP() %{ 5100 constraint(ALLOC_IN_RC(any_reg)); 5101 match(RegP); 5102 match(eAXRegP); 5103 match(eBXRegP); 5104 match(eCXRegP); 5105 match(eDIRegP); 5106 match(eRegP); 5107 5108 format %{ %} 5109 interface(REG_INTER); 5110%} 5111 5112operand eRegP() %{ 5113 constraint(ALLOC_IN_RC(e_reg)); 5114 match(RegP); 5115 match(eAXRegP); 5116 match(eBXRegP); 5117 match(eCXRegP); 5118 match(eDIRegP); 5119 5120 format %{ %} 5121 interface(REG_INTER); 5122%} 5123 5124// On windows95, EBP is not safe to use for implicit null tests. 5125operand eRegP_no_EBP() %{ 5126 constraint(ALLOC_IN_RC(e_reg_no_rbp)); 5127 match(RegP); 5128 match(eAXRegP); 5129 match(eBXRegP); 5130 match(eCXRegP); 5131 match(eDIRegP); 5132 5133 op_cost(100); 5134 format %{ %} 5135 interface(REG_INTER); 5136%} 5137 5138operand naxRegP() %{ 5139 constraint(ALLOC_IN_RC(nax_reg)); 5140 match(RegP); 5141 match(eBXRegP); 5142 match(eDXRegP); 5143 match(eCXRegP); 5144 match(eSIRegP); 5145 match(eDIRegP); 5146 5147 format %{ %} 5148 interface(REG_INTER); 5149%} 5150 5151operand nabxRegP() %{ 5152 constraint(ALLOC_IN_RC(nabx_reg)); 5153 match(RegP); 5154 match(eCXRegP); 5155 match(eDXRegP); 5156 match(eSIRegP); 5157 match(eDIRegP); 5158 5159 format %{ %} 5160 interface(REG_INTER); 5161%} 5162 5163operand pRegP() %{ 5164 constraint(ALLOC_IN_RC(p_reg)); 5165 match(RegP); 5166 match(eBXRegP); 5167 match(eDXRegP); 5168 match(eSIRegP); 5169 match(eDIRegP); 5170 5171 format %{ %} 5172 interface(REG_INTER); 5173%} 5174 5175// Special Registers 5176// Return a pointer value 5177operand eAXRegP(eRegP reg) %{ 5178 constraint(ALLOC_IN_RC(eax_reg)); 5179 match(reg); 5180 format %{ "EAX" %} 5181 interface(REG_INTER); 5182%} 5183 5184// Used in AtomicAdd 5185operand eBXRegP(eRegP reg) %{ 5186 constraint(ALLOC_IN_RC(ebx_reg)); 5187 match(reg); 5188 format %{ "EBX" %} 5189 interface(REG_INTER); 5190%} 5191 5192// Tail-call (interprocedural jump) to interpreter 5193operand eCXRegP(eRegP reg) %{ 5194 constraint(ALLOC_IN_RC(ecx_reg)); 5195 match(reg); 5196 format %{ "ECX" %} 5197 interface(REG_INTER); 5198%} 5199 5200operand eSIRegP(eRegP reg) %{ 5201 constraint(ALLOC_IN_RC(esi_reg)); 5202 match(reg); 5203 format %{ "ESI" %} 5204 interface(REG_INTER); 5205%} 5206 5207// Used in rep stosw 5208operand eDIRegP(eRegP reg) %{ 5209 constraint(ALLOC_IN_RC(edi_reg)); 5210 match(reg); 5211 format %{ "EDI" %} 5212 interface(REG_INTER); 5213%} 5214 5215operand eBPRegP() %{ 5216 constraint(ALLOC_IN_RC(ebp_reg)); 5217 match(RegP); 5218 format %{ "EBP" %} 5219 interface(REG_INTER); 5220%} 5221 5222operand eRegL() %{ 5223 constraint(ALLOC_IN_RC(long_reg)); 5224 match(RegL); 5225 match(eADXRegL); 5226 5227 format %{ %} 5228 interface(REG_INTER); 5229%} 5230 5231operand eADXRegL( eRegL reg ) %{ 5232 constraint(ALLOC_IN_RC(eadx_reg)); 5233 match(reg); 5234 5235 format %{ "EDX:EAX" %} 5236 interface(REG_INTER); 5237%} 5238 5239operand eBCXRegL( eRegL reg ) %{ 5240 constraint(ALLOC_IN_RC(ebcx_reg)); 5241 match(reg); 5242 5243 format %{ "EBX:ECX" %} 5244 interface(REG_INTER); 5245%} 5246 5247// Special case for integer high multiply 5248operand eADXRegL_low_only() %{ 5249 constraint(ALLOC_IN_RC(eadx_reg)); 5250 match(RegL); 5251 5252 format %{ "EAX" %} 5253 interface(REG_INTER); 5254%} 5255 5256// Flags register, used as output of compare instructions 5257operand eFlagsReg() %{ 5258 constraint(ALLOC_IN_RC(int_flags)); 5259 match(RegFlags); 5260 5261 format %{ "EFLAGS" %} 5262 interface(REG_INTER); 5263%} 5264 5265// Flags register, used as output of FLOATING POINT compare instructions 5266operand eFlagsRegU() %{ 5267 constraint(ALLOC_IN_RC(int_flags)); 5268 match(RegFlags); 5269 5270 format %{ "EFLAGS_U" %} 5271 interface(REG_INTER); 5272%} 5273 5274// Condition Code Register used by long compare 5275operand flagsReg_long_LTGE() %{ 5276 constraint(ALLOC_IN_RC(int_flags)); 5277 match(RegFlags); 5278 format %{ "FLAGS_LTGE" %} 5279 interface(REG_INTER); 5280%} 5281operand flagsReg_long_EQNE() %{ 5282 constraint(ALLOC_IN_RC(int_flags)); 5283 match(RegFlags); 5284 format %{ "FLAGS_EQNE" %} 5285 interface(REG_INTER); 5286%} 5287operand flagsReg_long_LEGT() %{ 5288 constraint(ALLOC_IN_RC(int_flags)); 5289 match(RegFlags); 5290 format %{ "FLAGS_LEGT" %} 5291 interface(REG_INTER); 5292%} 5293 5294// Float register operands 5295operand regD() %{ 5296 predicate( UseSSE < 2 ); 5297 constraint(ALLOC_IN_RC(dbl_reg)); 5298 match(RegD); 5299 match(regDPR1); 5300 match(regDPR2); 5301 format %{ %} 5302 interface(REG_INTER); 5303%} 5304 5305operand regDPR1(regD reg) %{ 5306 predicate( UseSSE < 2 ); 5307 constraint(ALLOC_IN_RC(dbl_reg0)); 5308 match(reg); 5309 format %{ "FPR1" %} 5310 interface(REG_INTER); 5311%} 5312 5313operand regDPR2(regD reg) %{ 5314 predicate( UseSSE < 2 ); 5315 constraint(ALLOC_IN_RC(dbl_reg1)); 5316 match(reg); 5317 format %{ "FPR2" %} 5318 interface(REG_INTER); 5319%} 5320 5321operand regnotDPR1(regD reg) %{ 5322 predicate( UseSSE < 2 ); 5323 constraint(ALLOC_IN_RC(dbl_notreg0)); 5324 match(reg); 5325 format %{ %} 5326 interface(REG_INTER); 5327%} 5328 5329// XMM Double register operands 5330operand regXD() %{ 5331 predicate( UseSSE>=2 ); 5332 constraint(ALLOC_IN_RC(xdb_reg)); 5333 match(RegD); 5334 match(regXD6); 5335 match(regXD7); 5336 format %{ %} 5337 interface(REG_INTER); 5338%} 5339 5340// XMM6 double register operands 5341operand regXD6(regXD reg) %{ 5342 predicate( UseSSE>=2 ); 5343 constraint(ALLOC_IN_RC(xdb_reg6)); 5344 match(reg); 5345 format %{ "XMM6" %} 5346 interface(REG_INTER); 5347%} 5348 5349// XMM7 double register operands 5350operand regXD7(regXD reg) %{ 5351 predicate( UseSSE>=2 ); 5352 constraint(ALLOC_IN_RC(xdb_reg7)); 5353 match(reg); 5354 format %{ "XMM7" %} 5355 interface(REG_INTER); 5356%} 5357 5358// Float register operands 5359operand regF() %{ 5360 predicate( UseSSE < 2 ); 5361 constraint(ALLOC_IN_RC(flt_reg)); 5362 match(RegF); 5363 match(regFPR1); 5364 format %{ %} 5365 interface(REG_INTER); 5366%} 5367 5368// Float register operands 5369operand regFPR1(regF reg) %{ 5370 predicate( UseSSE < 2 ); 5371 constraint(ALLOC_IN_RC(flt_reg0)); 5372 match(reg); 5373 format %{ "FPR1" %} 5374 interface(REG_INTER); 5375%} 5376 5377// XMM register operands 5378operand regX() %{ 5379 predicate( UseSSE>=1 ); 5380 constraint(ALLOC_IN_RC(xmm_reg)); 5381 match(RegF); 5382 format %{ %} 5383 interface(REG_INTER); 5384%} 5385 5386 5387//----------Memory Operands---------------------------------------------------- 5388// Direct Memory Operand 5389operand direct(immP addr) %{ 5390 match(addr); 5391 5392 format %{ "[$addr]" %} 5393 interface(MEMORY_INTER) %{ 5394 base(0xFFFFFFFF); 5395 index(0x4); 5396 scale(0x0); 5397 disp($addr); 5398 %} 5399%} 5400 5401// Indirect Memory Operand 5402operand indirect(eRegP reg) %{ 5403 constraint(ALLOC_IN_RC(e_reg)); 5404 match(reg); 5405 5406 format %{ "[$reg]" %} 5407 interface(MEMORY_INTER) %{ 5408 base($reg); 5409 index(0x4); 5410 scale(0x0); 5411 disp(0x0); 5412 %} 5413%} 5414 5415// Indirect Memory Plus Short Offset Operand 5416operand indOffset8(eRegP reg, immI8 off) %{ 5417 match(AddP reg off); 5418 5419 format %{ "[$reg + $off]" %} 5420 interface(MEMORY_INTER) %{ 5421 base($reg); 5422 index(0x4); 5423 scale(0x0); 5424 disp($off); 5425 %} 5426%} 5427 5428// Indirect Memory Plus Long Offset Operand 5429operand indOffset32(eRegP reg, immI off) %{ 5430 match(AddP reg off); 5431 5432 format %{ "[$reg + $off]" %} 5433 interface(MEMORY_INTER) %{ 5434 base($reg); 5435 index(0x4); 5436 scale(0x0); 5437 disp($off); 5438 %} 5439%} 5440 5441// Indirect Memory Plus Long Offset Operand 5442operand indOffset32X(eRegI reg, immP off) %{ 5443 match(AddP off reg); 5444 5445 format %{ "[$reg + $off]" %} 5446 interface(MEMORY_INTER) %{ 5447 base($reg); 5448 index(0x4); 5449 scale(0x0); 5450 disp($off); 5451 %} 5452%} 5453 5454// Indirect Memory Plus Index Register Plus Offset Operand 5455operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{ 5456 match(AddP (AddP reg ireg) off); 5457 5458 op_cost(10); 5459 format %{"[$reg + $off + $ireg]" %} 5460 interface(MEMORY_INTER) %{ 5461 base($reg); 5462 index($ireg); 5463 scale(0x0); 5464 disp($off); 5465 %} 5466%} 5467 5468// Indirect Memory Plus Index Register Plus Offset Operand 5469operand indIndex(eRegP reg, eRegI ireg) %{ 5470 match(AddP reg ireg); 5471 5472 op_cost(10); 5473 format %{"[$reg + $ireg]" %} 5474 interface(MEMORY_INTER) %{ 5475 base($reg); 5476 index($ireg); 5477 scale(0x0); 5478 disp(0x0); 5479 %} 5480%} 5481 5482// // ------------------------------------------------------------------------- 5483// // 486 architecture doesn't support "scale * index + offset" with out a base 5484// // ------------------------------------------------------------------------- 5485// // Scaled Memory Operands 5486// // Indirect Memory Times Scale Plus Offset Operand 5487// operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{ 5488// match(AddP off (LShiftI ireg scale)); 5489// 5490// op_cost(10); 5491// format %{"[$off + $ireg << $scale]" %} 5492// interface(MEMORY_INTER) %{ 5493// base(0x4); 5494// index($ireg); 5495// scale($scale); 5496// disp($off); 5497// %} 5498// %} 5499 5500// Indirect Memory Times Scale Plus Index Register 5501operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{ 5502 match(AddP reg (LShiftI ireg scale)); 5503 5504 op_cost(10); 5505 format %{"[$reg + $ireg << $scale]" %} 5506 interface(MEMORY_INTER) %{ 5507 base($reg); 5508 index($ireg); 5509 scale($scale); 5510 disp(0x0); 5511 %} 5512%} 5513 5514// Indirect Memory Times Scale Plus Index Register Plus Offset Operand 5515operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{ 5516 match(AddP (AddP reg (LShiftI ireg scale)) off); 5517 5518 op_cost(10); 5519 format %{"[$reg + $off + $ireg << $scale]" %} 5520 interface(MEMORY_INTER) %{ 5521 base($reg); 5522 index($ireg); 5523 scale($scale); 5524 disp($off); 5525 %} 5526%} 5527 5528//----------Load Long Memory Operands------------------------------------------ 5529// The load-long idiom will use it's address expression again after loading 5530// the first word of the long. If the load-long destination overlaps with 5531// registers used in the addressing expression, the 2nd half will be loaded 5532// from a clobbered address. Fix this by requiring that load-long use 5533// address registers that do not overlap with the load-long target. 5534 5535// load-long support 5536operand load_long_RegP() %{ 5537 constraint(ALLOC_IN_RC(esi_reg)); 5538 match(RegP); 5539 match(eSIRegP); 5540 op_cost(100); 5541 format %{ %} 5542 interface(REG_INTER); 5543%} 5544 5545// Indirect Memory Operand Long 5546operand load_long_indirect(load_long_RegP reg) %{ 5547 constraint(ALLOC_IN_RC(esi_reg)); 5548 match(reg); 5549 5550 format %{ "[$reg]" %} 5551 interface(MEMORY_INTER) %{ 5552 base($reg); 5553 index(0x4); 5554 scale(0x0); 5555 disp(0x0); 5556 %} 5557%} 5558 5559// Indirect Memory Plus Long Offset Operand 5560operand load_long_indOffset32(load_long_RegP reg, immI off) %{ 5561 match(AddP reg off); 5562 5563 format %{ "[$reg + $off]" %} 5564 interface(MEMORY_INTER) %{ 5565 base($reg); 5566 index(0x4); 5567 scale(0x0); 5568 disp($off); 5569 %} 5570%} 5571 5572opclass load_long_memory(load_long_indirect, load_long_indOffset32); 5573 5574 5575//----------Special Memory Operands-------------------------------------------- 5576// Stack Slot Operand - This operand is used for loading and storing temporary 5577// values on the stack where a match requires a value to 5578// flow through memory. 5579operand stackSlotP(sRegP reg) %{ 5580 constraint(ALLOC_IN_RC(stack_slots)); 5581 // No match rule because this operand is only generated in matching 5582 format %{ "[$reg]" %} 5583 interface(MEMORY_INTER) %{ 5584 base(0x4); // ESP 5585 index(0x4); // No Index 5586 scale(0x0); // No Scale 5587 disp($reg); // Stack Offset 5588 %} 5589%} 5590 5591operand stackSlotI(sRegI reg) %{ 5592 constraint(ALLOC_IN_RC(stack_slots)); 5593 // No match rule because this operand is only generated in matching 5594 format %{ "[$reg]" %} 5595 interface(MEMORY_INTER) %{ 5596 base(0x4); // ESP 5597 index(0x4); // No Index 5598 scale(0x0); // No Scale 5599 disp($reg); // Stack Offset 5600 %} 5601%} 5602 5603operand stackSlotF(sRegF reg) %{ 5604 constraint(ALLOC_IN_RC(stack_slots)); 5605 // No match rule because this operand is only generated in matching 5606 format %{ "[$reg]" %} 5607 interface(MEMORY_INTER) %{ 5608 base(0x4); // ESP 5609 index(0x4); // No Index 5610 scale(0x0); // No Scale 5611 disp($reg); // Stack Offset 5612 %} 5613%} 5614 5615operand stackSlotD(sRegD reg) %{ 5616 constraint(ALLOC_IN_RC(stack_slots)); 5617 // No match rule because this operand is only generated in matching 5618 format %{ "[$reg]" %} 5619 interface(MEMORY_INTER) %{ 5620 base(0x4); // ESP 5621 index(0x4); // No Index 5622 scale(0x0); // No Scale 5623 disp($reg); // Stack Offset 5624 %} 5625%} 5626 5627operand stackSlotL(sRegL reg) %{ 5628 constraint(ALLOC_IN_RC(stack_slots)); 5629 // No match rule because this operand is only generated in matching 5630 format %{ "[$reg]" %} 5631 interface(MEMORY_INTER) %{ 5632 base(0x4); // ESP 5633 index(0x4); // No Index 5634 scale(0x0); // No Scale 5635 disp($reg); // Stack Offset 5636 %} 5637%} 5638 5639//----------Memory Operands - Win95 Implicit Null Variants---------------- 5640// Indirect Memory Operand 5641operand indirect_win95_safe(eRegP_no_EBP reg) 5642%{ 5643 constraint(ALLOC_IN_RC(e_reg)); 5644 match(reg); 5645 5646 op_cost(100); 5647 format %{ "[$reg]" %} 5648 interface(MEMORY_INTER) %{ 5649 base($reg); 5650 index(0x4); 5651 scale(0x0); 5652 disp(0x0); 5653 %} 5654%} 5655 5656// Indirect Memory Plus Short Offset Operand 5657operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) 5658%{ 5659 match(AddP reg off); 5660 5661 op_cost(100); 5662 format %{ "[$reg + $off]" %} 5663 interface(MEMORY_INTER) %{ 5664 base($reg); 5665 index(0x4); 5666 scale(0x0); 5667 disp($off); 5668 %} 5669%} 5670 5671// Indirect Memory Plus Long Offset Operand 5672operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) 5673%{ 5674 match(AddP reg off); 5675 5676 op_cost(100); 5677 format %{ "[$reg + $off]" %} 5678 interface(MEMORY_INTER) %{ 5679 base($reg); 5680 index(0x4); 5681 scale(0x0); 5682 disp($off); 5683 %} 5684%} 5685 5686// Indirect Memory Plus Index Register Plus Offset Operand 5687operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off) 5688%{ 5689 match(AddP (AddP reg ireg) off); 5690 5691 op_cost(100); 5692 format %{"[$reg + $off + $ireg]" %} 5693 interface(MEMORY_INTER) %{ 5694 base($reg); 5695 index($ireg); 5696 scale(0x0); 5697 disp($off); 5698 %} 5699%} 5700 5701// Indirect Memory Times Scale Plus Index Register 5702operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale) 5703%{ 5704 match(AddP reg (LShiftI ireg scale)); 5705 5706 op_cost(100); 5707 format %{"[$reg + $ireg << $scale]" %} 5708 interface(MEMORY_INTER) %{ 5709 base($reg); 5710 index($ireg); 5711 scale($scale); 5712 disp(0x0); 5713 %} 5714%} 5715 5716// Indirect Memory Times Scale Plus Index Register Plus Offset Operand 5717operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale) 5718%{ 5719 match(AddP (AddP reg (LShiftI ireg scale)) off); 5720 5721 op_cost(100); 5722 format %{"[$reg + $off + $ireg << $scale]" %} 5723 interface(MEMORY_INTER) %{ 5724 base($reg); 5725 index($ireg); 5726 scale($scale); 5727 disp($off); 5728 %} 5729%} 5730 5731//----------Conditional Branch Operands---------------------------------------- 5732// Comparison Op - This is the operation of the comparison, and is limited to 5733// the following set of codes: 5734// L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 5735// 5736// Other attributes of the comparison, such as unsignedness, are specified 5737// by the comparison instruction that sets a condition code flags register. 5738// That result is represented by a flags operand whose subtype is appropriate 5739// to the unsignedness (etc.) of the comparison. 5740// 5741// Later, the instruction which matches both the Comparison Op (a Bool) and 5742// the flags (produced by the Cmp) specifies the coding of the comparison op 5743// by matching a specific subtype of Bool operand below, such as cmpOpU. 5744 5745// Comparision Code 5746operand cmpOp() %{ 5747 match(Bool); 5748 5749 format %{ "" %} 5750 interface(COND_INTER) %{ 5751 equal(0x4); 5752 not_equal(0x5); 5753 less(0xC); 5754 greater_equal(0xD); 5755 less_equal(0xE); 5756 greater(0xF); 5757 %} 5758%} 5759 5760// Comparison Code, unsigned compare. Used by FP also, with 5761// C2 (unordered) turned into GT or LT already. The other bits 5762// C0 and C3 are turned into Carry & Zero flags. 5763operand cmpOpU() %{ 5764 match(Bool); 5765 5766 format %{ "" %} 5767 interface(COND_INTER) %{ 5768 equal(0x4); 5769 not_equal(0x5); 5770 less(0x2); 5771 greater_equal(0x3); 5772 less_equal(0x6); 5773 greater(0x7); 5774 %} 5775%} 5776 5777// Comparison Code for FP conditional move 5778operand cmpOp_fcmov() %{ 5779 match(Bool); 5780 5781 format %{ "" %} 5782 interface(COND_INTER) %{ 5783 equal (0x0C8); 5784 not_equal (0x1C8); 5785 less (0x0C0); 5786 greater_equal(0x1C0); 5787 less_equal (0x0D0); 5788 greater (0x1D0); 5789 %} 5790%} 5791 5792// Comparision Code used in long compares 5793operand cmpOp_commute() %{ 5794 match(Bool); 5795 5796 format %{ "" %} 5797 interface(COND_INTER) %{ 5798 equal(0x4); 5799 not_equal(0x5); 5800 less(0xF); 5801 greater_equal(0xE); 5802 less_equal(0xD); 5803 greater(0xC); 5804 %} 5805%} 5806 5807//----------OPERAND CLASSES---------------------------------------------------- 5808// Operand Classes are groups of operands that are used as to simplify 5809// instruction definitions by not requiring the AD writer to specify seperate 5810// instructions for every form of operand when the instruction accepts 5811// multiple operand types with the same basic encoding and format. The classic 5812// case of this is memory operands. 5813 5814opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, 5815 indIndex, indIndexScale, indIndexScaleOffset); 5816 5817// Long memory operations are encoded in 2 instructions and a +4 offset. 5818// This means some kind of offset is always required and you cannot use 5819// an oop as the offset (done when working on static globals). 5820opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, 5821 indIndex, indIndexScale, indIndexScaleOffset); 5822 5823 5824//----------PIPELINE----------------------------------------------------------- 5825// Rules which define the behavior of the target architectures pipeline. 5826pipeline %{ 5827 5828//----------ATTRIBUTES--------------------------------------------------------- 5829attributes %{ 5830 variable_size_instructions; // Fixed size instructions 5831 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle 5832 instruction_unit_size = 1; // An instruction is 1 bytes long 5833 instruction_fetch_unit_size = 16; // The processor fetches one line 5834 instruction_fetch_units = 1; // of 16 bytes 5835 5836 // List of nop instructions 5837 nops( MachNop ); 5838%} 5839 5840//----------RESOURCES---------------------------------------------------------- 5841// Resources are the functional units available to the machine 5842 5843// Generic P2/P3 pipeline 5844// 3 decoders, only D0 handles big operands; a "bundle" is the limit of 5845// 3 instructions decoded per cycle. 5846// 2 load/store ops per cycle, 1 branch, 1 FPU, 5847// 2 ALU op, only ALU0 handles mul/div instructions. 5848resources( D0, D1, D2, DECODE = D0 | D1 | D2, 5849 MS0, MS1, MEM = MS0 | MS1, 5850 BR, FPU, 5851 ALU0, ALU1, ALU = ALU0 | ALU1 ); 5852 5853//----------PIPELINE DESCRIPTION----------------------------------------------- 5854// Pipeline Description specifies the stages in the machine's pipeline 5855 5856// Generic P2/P3 pipeline 5857pipe_desc(S0, S1, S2, S3, S4, S5); 5858 5859//----------PIPELINE CLASSES--------------------------------------------------- 5860// Pipeline Classes describe the stages in which input and output are 5861// referenced by the hardware pipeline. 5862 5863// Naming convention: ialu or fpu 5864// Then: _reg 5865// Then: _reg if there is a 2nd register 5866// Then: _long if it's a pair of instructions implementing a long 5867// Then: _fat if it requires the big decoder 5868// Or: _mem if it requires the big decoder and a memory unit. 5869 5870// Integer ALU reg operation 5871pipe_class ialu_reg(eRegI dst) %{ 5872 single_instruction; 5873 dst : S4(write); 5874 dst : S3(read); 5875 DECODE : S0; // any decoder 5876 ALU : S3; // any alu 5877%} 5878 5879// Long ALU reg operation 5880pipe_class ialu_reg_long(eRegL dst) %{ 5881 instruction_count(2); 5882 dst : S4(write); 5883 dst : S3(read); 5884 DECODE : S0(2); // any 2 decoders 5885 ALU : S3(2); // both alus 5886%} 5887 5888// Integer ALU reg operation using big decoder 5889pipe_class ialu_reg_fat(eRegI dst) %{ 5890 single_instruction; 5891 dst : S4(write); 5892 dst : S3(read); 5893 D0 : S0; // big decoder only 5894 ALU : S3; // any alu 5895%} 5896 5897// Long ALU reg operation using big decoder 5898pipe_class ialu_reg_long_fat(eRegL dst) %{ 5899 instruction_count(2); 5900 dst : S4(write); 5901 dst : S3(read); 5902 D0 : S0(2); // big decoder only; twice 5903 ALU : S3(2); // any 2 alus 5904%} 5905 5906// Integer ALU reg-reg operation 5907pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{ 5908 single_instruction; 5909 dst : S4(write); 5910 src : S3(read); 5911 DECODE : S0; // any decoder 5912 ALU : S3; // any alu 5913%} 5914 5915// Long ALU reg-reg operation 5916pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ 5917 instruction_count(2); 5918 dst : S4(write); 5919 src : S3(read); 5920 DECODE : S0(2); // any 2 decoders 5921 ALU : S3(2); // both alus 5922%} 5923 5924// Integer ALU reg-reg operation 5925pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{ 5926 single_instruction; 5927 dst : S4(write); 5928 src : S3(read); 5929 D0 : S0; // big decoder only 5930 ALU : S3; // any alu 5931%} 5932 5933// Long ALU reg-reg operation 5934pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ 5935 instruction_count(2); 5936 dst : S4(write); 5937 src : S3(read); 5938 D0 : S0(2); // big decoder only; twice 5939 ALU : S3(2); // both alus 5940%} 5941 5942// Integer ALU reg-mem operation 5943pipe_class ialu_reg_mem(eRegI dst, memory mem) %{ 5944 single_instruction; 5945 dst : S5(write); 5946 mem : S3(read); 5947 D0 : S0; // big decoder only 5948 ALU : S4; // any alu 5949 MEM : S3; // any mem 5950%} 5951 5952// Long ALU reg-mem operation 5953pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ 5954 instruction_count(2); 5955 dst : S5(write); 5956 mem : S3(read); 5957 D0 : S0(2); // big decoder only; twice 5958 ALU : S4(2); // any 2 alus 5959 MEM : S3(2); // both mems 5960%} 5961 5962// Integer mem operation (prefetch) 5963pipe_class ialu_mem(memory mem) 5964%{ 5965 single_instruction; 5966 mem : S3(read); 5967 D0 : S0; // big decoder only 5968 MEM : S3; // any mem 5969%} 5970 5971// Integer Store to Memory 5972pipe_class ialu_mem_reg(memory mem, eRegI src) %{ 5973 single_instruction; 5974 mem : S3(read); 5975 src : S5(read); 5976 D0 : S0; // big decoder only 5977 ALU : S4; // any alu 5978 MEM : S3; 5979%} 5980 5981// Long Store to Memory 5982pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ 5983 instruction_count(2); 5984 mem : S3(read); 5985 src : S5(read); 5986 D0 : S0(2); // big decoder only; twice 5987 ALU : S4(2); // any 2 alus 5988 MEM : S3(2); // Both mems 5989%} 5990 5991// Integer Store to Memory 5992pipe_class ialu_mem_imm(memory mem) %{ 5993 single_instruction; 5994 mem : S3(read); 5995 D0 : S0; // big decoder only 5996 ALU : S4; // any alu 5997 MEM : S3; 5998%} 5999 6000// Integer ALU0 reg-reg operation 6001pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{ 6002 single_instruction; 6003 dst : S4(write); 6004 src : S3(read); 6005 D0 : S0; // Big decoder only 6006 ALU0 : S3; // only alu0 6007%} 6008 6009// Integer ALU0 reg-mem operation 6010pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{ 6011 single_instruction; 6012 dst : S5(write); 6013 mem : S3(read); 6014 D0 : S0; // big decoder only 6015 ALU0 : S4; // ALU0 only 6016 MEM : S3; // any mem 6017%} 6018 6019// Integer ALU reg-reg operation 6020pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{ 6021 single_instruction; 6022 cr : S4(write); 6023 src1 : S3(read); 6024 src2 : S3(read); 6025 DECODE : S0; // any decoder 6026 ALU : S3; // any alu 6027%} 6028 6029// Integer ALU reg-imm operation 6030pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{ 6031 single_instruction; 6032 cr : S4(write); 6033 src1 : S3(read); 6034 DECODE : S0; // any decoder 6035 ALU : S3; // any alu 6036%} 6037 6038// Integer ALU reg-mem operation 6039pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{ 6040 single_instruction; 6041 cr : S4(write); 6042 src1 : S3(read); 6043 src2 : S3(read); 6044 D0 : S0; // big decoder only 6045 ALU : S4; // any alu 6046 MEM : S3; 6047%} 6048 6049// Conditional move reg-reg 6050pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{ 6051 instruction_count(4); 6052 y : S4(read); 6053 q : S3(read); 6054 p : S3(read); 6055 DECODE : S0(4); // any decoder 6056%} 6057 6058// Conditional move reg-reg 6059pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{ 6060 single_instruction; 6061 dst : S4(write); 6062 src : S3(read); 6063 cr : S3(read); 6064 DECODE : S0; // any decoder 6065%} 6066 6067// Conditional move reg-mem 6068pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{ 6069 single_instruction; 6070 dst : S4(write); 6071 src : S3(read); 6072 cr : S3(read); 6073 DECODE : S0; // any decoder 6074 MEM : S3; 6075%} 6076 6077// Conditional move reg-reg long 6078pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ 6079 single_instruction; 6080 dst : S4(write); 6081 src : S3(read); 6082 cr : S3(read); 6083 DECODE : S0(2); // any 2 decoders 6084%} 6085 6086// Conditional move double reg-reg 6087pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{ 6088 single_instruction; 6089 dst : S4(write); 6090 src : S3(read); 6091 cr : S3(read); 6092 DECODE : S0; // any decoder 6093%} 6094 6095// Float reg-reg operation 6096pipe_class fpu_reg(regD dst) %{ 6097 instruction_count(2); 6098 dst : S3(read); 6099 DECODE : S0(2); // any 2 decoders 6100 FPU : S3; 6101%} 6102 6103// Float reg-reg operation 6104pipe_class fpu_reg_reg(regD dst, regD src) %{ 6105 instruction_count(2); 6106 dst : S4(write); 6107 src : S3(read); 6108 DECODE : S0(2); // any 2 decoders 6109 FPU : S3; 6110%} 6111 6112// Float reg-reg operation 6113pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{ 6114 instruction_count(3); 6115 dst : S4(write); 6116 src1 : S3(read); 6117 src2 : S3(read); 6118 DECODE : S0(3); // any 3 decoders 6119 FPU : S3(2); 6120%} 6121 6122// Float reg-reg operation 6123pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{ 6124 instruction_count(4); 6125 dst : S4(write); 6126 src1 : S3(read); 6127 src2 : S3(read); 6128 src3 : S3(read); 6129 DECODE : S0(4); // any 3 decoders 6130 FPU : S3(2); 6131%} 6132 6133// Float reg-reg operation 6134pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{ 6135 instruction_count(4); 6136 dst : S4(write); 6137 src1 : S3(read); 6138 src2 : S3(read); 6139 src3 : S3(read); 6140 DECODE : S1(3); // any 3 decoders 6141 D0 : S0; // Big decoder only 6142 FPU : S3(2); 6143 MEM : S3; 6144%} 6145 6146// Float reg-mem operation 6147pipe_class fpu_reg_mem(regD dst, memory mem) %{ 6148 instruction_count(2); 6149 dst : S5(write); 6150 mem : S3(read); 6151 D0 : S0; // big decoder only 6152 DECODE : S1; // any decoder for FPU POP 6153 FPU : S4; 6154 MEM : S3; // any mem 6155%} 6156 6157// Float reg-mem operation 6158pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{ 6159 instruction_count(3); 6160 dst : S5(write); 6161 src1 : S3(read); 6162 mem : S3(read); 6163 D0 : S0; // big decoder only 6164 DECODE : S1(2); // any decoder for FPU POP 6165 FPU : S4; 6166 MEM : S3; // any mem 6167%} 6168 6169// Float mem-reg operation 6170pipe_class fpu_mem_reg(memory mem, regD src) %{ 6171 instruction_count(2); 6172 src : S5(read); 6173 mem : S3(read); 6174 DECODE : S0; // any decoder for FPU PUSH 6175 D0 : S1; // big decoder only 6176 FPU : S4; 6177 MEM : S3; // any mem 6178%} 6179 6180pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{ 6181 instruction_count(3); 6182 src1 : S3(read); 6183 src2 : S3(read); 6184 mem : S3(read); 6185 DECODE : S0(2); // any decoder for FPU PUSH 6186 D0 : S1; // big decoder only 6187 FPU : S4; 6188 MEM : S3; // any mem 6189%} 6190 6191pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{ 6192 instruction_count(3); 6193 src1 : S3(read); 6194 src2 : S3(read); 6195 mem : S4(read); 6196 DECODE : S0; // any decoder for FPU PUSH 6197 D0 : S0(2); // big decoder only 6198 FPU : S4; 6199 MEM : S3(2); // any mem 6200%} 6201 6202pipe_class fpu_mem_mem(memory dst, memory src1) %{ 6203 instruction_count(2); 6204 src1 : S3(read); 6205 dst : S4(read); 6206 D0 : S0(2); // big decoder only 6207 MEM : S3(2); // any mem 6208%} 6209 6210pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ 6211 instruction_count(3); 6212 src1 : S3(read); 6213 src2 : S3(read); 6214 dst : S4(read); 6215 D0 : S0(3); // big decoder only 6216 FPU : S4; 6217 MEM : S3(3); // any mem 6218%} 6219 6220pipe_class fpu_mem_reg_con(memory mem, regD src1) %{ 6221 instruction_count(3); 6222 src1 : S4(read); 6223 mem : S4(read); 6224 DECODE : S0; // any decoder for FPU PUSH 6225 D0 : S0(2); // big decoder only 6226 FPU : S4; 6227 MEM : S3(2); // any mem 6228%} 6229 6230// Float load constant 6231pipe_class fpu_reg_con(regD dst) %{ 6232 instruction_count(2); 6233 dst : S5(write); 6234 D0 : S0; // big decoder only for the load 6235 DECODE : S1; // any decoder for FPU POP 6236 FPU : S4; 6237 MEM : S3; // any mem 6238%} 6239 6240// Float load constant 6241pipe_class fpu_reg_reg_con(regD dst, regD src) %{ 6242 instruction_count(3); 6243 dst : S5(write); 6244 src : S3(read); 6245 D0 : S0; // big decoder only for the load 6246 DECODE : S1(2); // any decoder for FPU POP 6247 FPU : S4; 6248 MEM : S3; // any mem 6249%} 6250 6251// UnConditional branch 6252pipe_class pipe_jmp( label labl ) %{ 6253 single_instruction; 6254 BR : S3; 6255%} 6256 6257// Conditional branch 6258pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ 6259 single_instruction; 6260 cr : S1(read); 6261 BR : S3; 6262%} 6263 6264// Allocation idiom 6265pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ 6266 instruction_count(1); force_serialization; 6267 fixed_latency(6); 6268 heap_ptr : S3(read); 6269 DECODE : S0(3); 6270 D0 : S2; 6271 MEM : S3; 6272 ALU : S3(2); 6273 dst : S5(write); 6274 BR : S5; 6275%} 6276 6277// Generic big/slow expanded idiom 6278pipe_class pipe_slow( ) %{ 6279 instruction_count(10); multiple_bundles; force_serialization; 6280 fixed_latency(100); 6281 D0 : S0(2); 6282 MEM : S3(2); 6283%} 6284 6285// The real do-nothing guy 6286pipe_class empty( ) %{ 6287 instruction_count(0); 6288%} 6289 6290// Define the class for the Nop node 6291define %{ 6292 MachNop = empty; 6293%} 6294 6295%} 6296 6297//----------INSTRUCTIONS------------------------------------------------------- 6298// 6299// match -- States which machine-independent subtree may be replaced 6300// by this instruction. 6301// ins_cost -- The estimated cost of this instruction is used by instruction 6302// selection to identify a minimum cost tree of machine 6303// instructions that matches a tree of machine-independent 6304// instructions. 6305// format -- A string providing the disassembly for this instruction. 6306// The value of an instruction's operand may be inserted 6307// by referring to it with a '$' prefix. 6308// opcode -- Three instruction opcodes may be provided. These are referred 6309// to within an encode class as $primary, $secondary, and $tertiary 6310// respectively. The primary opcode is commonly used to 6311// indicate the type of machine instruction, while secondary 6312// and tertiary are often used for prefix options or addressing 6313// modes. 6314// ins_encode -- A list of encode classes with parameters. The encode class 6315// name must have been defined in an 'enc_class' specification 6316// in the encode section of the architecture description. 6317 6318//----------BSWAP-Instruction-------------------------------------------------- 6319instruct bytes_reverse_int(eRegI dst) %{ 6320 match(Set dst (ReverseBytesI dst)); 6321 6322 format %{ "BSWAP $dst" %} 6323 opcode(0x0F, 0xC8); 6324 ins_encode( OpcP, OpcSReg(dst) ); 6325 ins_pipe( ialu_reg ); 6326%} 6327 6328instruct bytes_reverse_long(eRegL dst) %{ 6329 match(Set dst (ReverseBytesL dst)); 6330 6331 format %{ "BSWAP $dst.lo\n\t" 6332 "BSWAP $dst.hi\n\t" 6333 "XCHG $dst.lo $dst.hi" %} 6334 6335 ins_cost(125); 6336 ins_encode( bswap_long_bytes(dst) ); 6337 ins_pipe( ialu_reg_reg); 6338%} 6339 6340 6341//----------Load/Store/Move Instructions--------------------------------------- 6342//----------Load Instructions-------------------------------------------------- 6343// Load Byte (8bit signed) 6344instruct loadB(xRegI dst, memory mem) %{ 6345 match(Set dst (LoadB mem)); 6346 6347 ins_cost(125); 6348 format %{ "MOVSX8 $dst,$mem" %} 6349 opcode(0xBE, 0x0F); 6350 ins_encode( OpcS, OpcP, RegMem(dst,mem)); 6351 ins_pipe( ialu_reg_mem ); 6352%} 6353 6354// Load Byte (8bit UNsigned) 6355instruct loadUB(xRegI dst, memory mem, immI_255 bytemask) %{ 6356 match(Set dst (AndI (LoadB mem) bytemask)); 6357 6358 ins_cost(125); 6359 format %{ "MOVZX8 $dst,$mem" %} 6360 opcode(0xB6, 0x0F); 6361 ins_encode( OpcS, OpcP, RegMem(dst,mem)); 6362 ins_pipe( ialu_reg_mem ); 6363%} 6364 6365// Load Char (16bit unsigned) 6366instruct loadC(eRegI dst, memory mem) %{ 6367 match(Set dst (LoadC mem)); 6368 6369 ins_cost(125); 6370 format %{ "MOVZX $dst,$mem" %} 6371 opcode(0xB7, 0x0F); 6372 ins_encode( OpcS, OpcP, RegMem(dst,mem)); 6373 ins_pipe( ialu_reg_mem ); 6374%} 6375 6376// Load Integer 6377instruct loadI(eRegI dst, memory mem) %{ 6378 match(Set dst (LoadI mem)); 6379 6380 ins_cost(125); 6381 format %{ "MOV $dst,$mem" %} 6382 opcode(0x8B); 6383 ins_encode( OpcP, RegMem(dst,mem)); 6384 ins_pipe( ialu_reg_mem ); 6385%} 6386 6387// Load Long. Cannot clobber address while loading, so restrict address 6388// register to ESI 6389instruct loadL(eRegL dst, load_long_memory mem) %{ 6390 predicate(!((LoadLNode*)n)->require_atomic_access()); 6391 match(Set dst (LoadL mem)); 6392 6393 ins_cost(250); 6394 format %{ "MOV $dst.lo,$mem\n\t" 6395 "MOV $dst.hi,$mem+4" %} 6396 opcode(0x8B, 0x8B); 6397 ins_encode( OpcP, RegMem(dst,mem), OpcS, RegMem_Hi(dst,mem)); 6398 ins_pipe( ialu_reg_long_mem ); 6399%} 6400 6401// Volatile Load Long. Must be atomic, so do 64-bit FILD 6402// then store it down to the stack and reload on the int 6403// side. 6404instruct loadL_volatile(stackSlotL dst, memory mem) %{ 6405 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); 6406 match(Set dst (LoadL mem)); 6407 6408 ins_cost(200); 6409 format %{ "FILD $mem\t# Atomic volatile long load\n\t" 6410 "FISTp $dst" %} 6411 ins_encode(enc_loadL_volatile(mem,dst)); 6412 ins_pipe( fpu_reg_mem ); 6413%} 6414 6415instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{ 6416 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); 6417 match(Set dst (LoadL mem)); 6418 effect(TEMP tmp); 6419 ins_cost(180); 6420 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 6421 "MOVSD $dst,$tmp" %} 6422 ins_encode(enc_loadLX_volatile(mem, dst, tmp)); 6423 ins_pipe( pipe_slow ); 6424%} 6425 6426instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{ 6427 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); 6428 match(Set dst (LoadL mem)); 6429 effect(TEMP tmp); 6430 ins_cost(160); 6431 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 6432 "MOVD $dst.lo,$tmp\n\t" 6433 "PSRLQ $tmp,32\n\t" 6434 "MOVD $dst.hi,$tmp" %} 6435 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp)); 6436 ins_pipe( pipe_slow ); 6437%} 6438 6439// Load Range 6440instruct loadRange(eRegI dst, memory mem) %{ 6441 match(Set dst (LoadRange mem)); 6442 6443 ins_cost(125); 6444 format %{ "MOV $dst,$mem" %} 6445 opcode(0x8B); 6446 ins_encode( OpcP, RegMem(dst,mem)); 6447 ins_pipe( ialu_reg_mem ); 6448%} 6449 6450 6451// Load Pointer 6452instruct loadP(eRegP dst, memory mem) %{ 6453 match(Set dst (LoadP mem)); 6454 6455 ins_cost(125); 6456 format %{ "MOV $dst,$mem" %} 6457 opcode(0x8B); 6458 ins_encode( OpcP, RegMem(dst,mem)); 6459 ins_pipe( ialu_reg_mem ); 6460%} 6461 6462// Load Klass Pointer 6463instruct loadKlass(eRegP dst, memory mem) %{ 6464 match(Set dst (LoadKlass mem)); 6465 6466 ins_cost(125); 6467 format %{ "MOV $dst,$mem" %} 6468 opcode(0x8B); 6469 ins_encode( OpcP, RegMem(dst,mem)); 6470 ins_pipe( ialu_reg_mem ); 6471%} 6472 6473// Load Short (16bit signed) 6474instruct loadS(eRegI dst, memory mem) %{ 6475 match(Set dst (LoadS mem)); 6476 6477 ins_cost(125); 6478 format %{ "MOVSX $dst,$mem" %} 6479 opcode(0xBF, 0x0F); 6480 ins_encode( OpcS, OpcP, RegMem(dst,mem)); 6481 ins_pipe( ialu_reg_mem ); 6482%} 6483 6484// Load Double 6485instruct loadD(regD dst, memory mem) %{ 6486 predicate(UseSSE<=1); 6487 match(Set dst (LoadD mem)); 6488 6489 ins_cost(150); 6490 format %{ "FLD_D ST,$mem\n\t" 6491 "FSTP $dst" %} 6492 opcode(0xDD); /* DD /0 */ 6493 ins_encode( OpcP, RMopc_Mem(0x00,mem), 6494 Pop_Reg_D(dst) ); 6495 ins_pipe( fpu_reg_mem ); 6496%} 6497 6498// Load Double to XMM 6499instruct loadXD(regXD dst, memory mem) %{ 6500 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); 6501 match(Set dst (LoadD mem)); 6502 ins_cost(145); 6503 format %{ "MOVSD $dst,$mem" %} 6504 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem)); 6505 ins_pipe( pipe_slow ); 6506%} 6507 6508instruct loadXD_partial(regXD dst, memory mem) %{ 6509 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); 6510 match(Set dst (LoadD mem)); 6511 ins_cost(145); 6512 format %{ "MOVLPD $dst,$mem" %} 6513 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem)); 6514 ins_pipe( pipe_slow ); 6515%} 6516 6517// Load to XMM register (single-precision floating point) 6518// MOVSS instruction 6519instruct loadX(regX dst, memory mem) %{ 6520 predicate(UseSSE>=1); 6521 match(Set dst (LoadF mem)); 6522 ins_cost(145); 6523 format %{ "MOVSS $dst,$mem" %} 6524 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem)); 6525 ins_pipe( pipe_slow ); 6526%} 6527 6528// Load Float 6529instruct loadF(regF dst, memory mem) %{ 6530 predicate(UseSSE==0); 6531 match(Set dst (LoadF mem)); 6532 6533 ins_cost(150); 6534 format %{ "FLD_S ST,$mem\n\t" 6535 "FSTP $dst" %} 6536 opcode(0xD9); /* D9 /0 */ 6537 ins_encode( OpcP, RMopc_Mem(0x00,mem), 6538 Pop_Reg_F(dst) ); 6539 ins_pipe( fpu_reg_mem ); 6540%} 6541 6542// Load Aligned Packed Byte to XMM register 6543instruct loadA8B(regXD dst, memory mem) %{ 6544 predicate(UseSSE>=1); 6545 match(Set dst (Load8B mem)); 6546 ins_cost(125); 6547 format %{ "MOVQ $dst,$mem\t! packed8B" %} 6548 ins_encode( movq_ld(dst, mem)); 6549 ins_pipe( pipe_slow ); 6550%} 6551 6552// Load Aligned Packed Short to XMM register 6553instruct loadA4S(regXD dst, memory mem) %{ 6554 predicate(UseSSE>=1); 6555 match(Set dst (Load4S mem)); 6556 ins_cost(125); 6557 format %{ "MOVQ $dst,$mem\t! packed4S" %} 6558 ins_encode( movq_ld(dst, mem)); 6559 ins_pipe( pipe_slow ); 6560%} 6561 6562// Load Aligned Packed Char to XMM register 6563instruct loadA4C(regXD dst, memory mem) %{ 6564 predicate(UseSSE>=1); 6565 match(Set dst (Load4C mem)); 6566 ins_cost(125); 6567 format %{ "MOVQ $dst,$mem\t! packed4C" %} 6568 ins_encode( movq_ld(dst, mem)); 6569 ins_pipe( pipe_slow ); 6570%} 6571 6572// Load Aligned Packed Integer to XMM register 6573instruct load2IU(regXD dst, memory mem) %{ 6574 predicate(UseSSE>=1); 6575 match(Set dst (Load2I mem)); 6576 ins_cost(125); 6577 format %{ "MOVQ $dst,$mem\t! packed2I" %} 6578 ins_encode( movq_ld(dst, mem)); 6579 ins_pipe( pipe_slow ); 6580%} 6581 6582// Load Aligned Packed Single to XMM 6583instruct loadA2F(regXD dst, memory mem) %{ 6584 predicate(UseSSE>=1); 6585 match(Set dst (Load2F mem)); 6586 ins_cost(145); 6587 format %{ "MOVQ $dst,$mem\t! packed2F" %} 6588 ins_encode( movq_ld(dst, mem)); 6589 ins_pipe( pipe_slow ); 6590%} 6591 6592// Load Effective Address 6593instruct leaP8(eRegP dst, indOffset8 mem) %{ 6594 match(Set dst mem); 6595 6596 ins_cost(110); 6597 format %{ "LEA $dst,$mem" %} 6598 opcode(0x8D); 6599 ins_encode( OpcP, RegMem(dst,mem)); 6600 ins_pipe( ialu_reg_reg_fat ); 6601%} 6602 6603instruct leaP32(eRegP dst, indOffset32 mem) %{ 6604 match(Set dst mem); 6605 6606 ins_cost(110); 6607 format %{ "LEA $dst,$mem" %} 6608 opcode(0x8D); 6609 ins_encode( OpcP, RegMem(dst,mem)); 6610 ins_pipe( ialu_reg_reg_fat ); 6611%} 6612 6613instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ 6614 match(Set dst mem); 6615 6616 ins_cost(110); 6617 format %{ "LEA $dst,$mem" %} 6618 opcode(0x8D); 6619 ins_encode( OpcP, RegMem(dst,mem)); 6620 ins_pipe( ialu_reg_reg_fat ); 6621%} 6622 6623instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ 6624 match(Set dst mem); 6625 6626 ins_cost(110); 6627 format %{ "LEA $dst,$mem" %} 6628 opcode(0x8D); 6629 ins_encode( OpcP, RegMem(dst,mem)); 6630 ins_pipe( ialu_reg_reg_fat ); 6631%} 6632 6633instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ 6634 match(Set dst mem); 6635 6636 ins_cost(110); 6637 format %{ "LEA $dst,$mem" %} 6638 opcode(0x8D); 6639 ins_encode( OpcP, RegMem(dst,mem)); 6640 ins_pipe( ialu_reg_reg_fat ); 6641%} 6642 6643// Load Constant 6644instruct loadConI(eRegI dst, immI src) %{ 6645 match(Set dst src); 6646 6647 format %{ "MOV $dst,$src" %} 6648 ins_encode( LdImmI(dst, src) ); 6649 ins_pipe( ialu_reg_fat ); 6650%} 6651 6652// Load Constant zero 6653instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{ 6654 match(Set dst src); 6655 effect(KILL cr); 6656 6657 ins_cost(50); 6658 format %{ "XOR $dst,$dst" %} 6659 opcode(0x33); /* + rd */ 6660 ins_encode( OpcP, RegReg( dst, dst ) ); 6661 ins_pipe( ialu_reg ); 6662%} 6663 6664instruct loadConP(eRegP dst, immP src) %{ 6665 match(Set dst src); 6666 6667 format %{ "MOV $dst,$src" %} 6668 opcode(0xB8); /* + rd */ 6669 ins_encode( LdImmP(dst, src) ); 6670 ins_pipe( ialu_reg_fat ); 6671%} 6672 6673instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ 6674 match(Set dst src); 6675 effect(KILL cr); 6676 ins_cost(200); 6677 format %{ "MOV $dst.lo,$src.lo\n\t" 6678 "MOV $dst.hi,$src.hi" %} 6679 opcode(0xB8); 6680 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); 6681 ins_pipe( ialu_reg_long_fat ); 6682%} 6683 6684instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ 6685 match(Set dst src); 6686 effect(KILL cr); 6687 ins_cost(150); 6688 format %{ "XOR $dst.lo,$dst.lo\n\t" 6689 "XOR $dst.hi,$dst.hi" %} 6690 opcode(0x33,0x33); 6691 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); 6692 ins_pipe( ialu_reg_long ); 6693%} 6694 6695// The instruction usage is guarded by predicate in operand immF(). 6696instruct loadConF(regF dst, immF src) %{ 6697 match(Set dst src); 6698 ins_cost(125); 6699 6700 format %{ "FLD_S ST,$src\n\t" 6701 "FSTP $dst" %} 6702 opcode(0xD9, 0x00); /* D9 /0 */ 6703 ins_encode(LdImmF(src), Pop_Reg_F(dst) ); 6704 ins_pipe( fpu_reg_con ); 6705%} 6706 6707// The instruction usage is guarded by predicate in operand immXF(). 6708instruct loadConX(regX dst, immXF con) %{ 6709 match(Set dst con); 6710 ins_cost(125); 6711 format %{ "MOVSS $dst,[$con]" %} 6712 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con)); 6713 ins_pipe( pipe_slow ); 6714%} 6715 6716// The instruction usage is guarded by predicate in operand immXF0(). 6717instruct loadConX0(regX dst, immXF0 src) %{ 6718 match(Set dst src); 6719 ins_cost(100); 6720 format %{ "XORPS $dst,$dst\t# float 0.0" %} 6721 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst)); 6722 ins_pipe( pipe_slow ); 6723%} 6724 6725// The instruction usage is guarded by predicate in operand immD(). 6726instruct loadConD(regD dst, immD src) %{ 6727 match(Set dst src); 6728 ins_cost(125); 6729 6730 format %{ "FLD_D ST,$src\n\t" 6731 "FSTP $dst" %} 6732 ins_encode(LdImmD(src), Pop_Reg_D(dst) ); 6733 ins_pipe( fpu_reg_con ); 6734%} 6735 6736// The instruction usage is guarded by predicate in operand immXD(). 6737instruct loadConXD(regXD dst, immXD con) %{ 6738 match(Set dst con); 6739 ins_cost(125); 6740 format %{ "MOVSD $dst,[$con]" %} 6741 ins_encode(load_conXD(dst, con)); 6742 ins_pipe( pipe_slow ); 6743%} 6744 6745// The instruction usage is guarded by predicate in operand immXD0(). 6746instruct loadConXD0(regXD dst, immXD0 src) %{ 6747 match(Set dst src); 6748 ins_cost(100); 6749 format %{ "XORPD $dst,$dst\t# double 0.0" %} 6750 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst)); 6751 ins_pipe( pipe_slow ); 6752%} 6753 6754// Load Stack Slot 6755instruct loadSSI(eRegI dst, stackSlotI src) %{ 6756 match(Set dst src); 6757 ins_cost(125); 6758 6759 format %{ "MOV $dst,$src" %} 6760 opcode(0x8B); 6761 ins_encode( OpcP, RegMem(dst,src)); 6762 ins_pipe( ialu_reg_mem ); 6763%} 6764 6765instruct loadSSL(eRegL dst, stackSlotL src) %{ 6766 match(Set dst src); 6767 6768 ins_cost(200); 6769 format %{ "MOV $dst,$src.lo\n\t" 6770 "MOV $dst+4,$src.hi" %} 6771 opcode(0x8B, 0x8B); 6772 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); 6773 ins_pipe( ialu_mem_long_reg ); 6774%} 6775 6776// Load Stack Slot 6777instruct loadSSP(eRegP dst, stackSlotP src) %{ 6778 match(Set dst src); 6779 ins_cost(125); 6780 6781 format %{ "MOV $dst,$src" %} 6782 opcode(0x8B); 6783 ins_encode( OpcP, RegMem(dst,src)); 6784 ins_pipe( ialu_reg_mem ); 6785%} 6786 6787// Load Stack Slot 6788instruct loadSSF(regF dst, stackSlotF src) %{ 6789 match(Set dst src); 6790 ins_cost(125); 6791 6792 format %{ "FLD_S $src\n\t" 6793 "FSTP $dst" %} 6794 opcode(0xD9); /* D9 /0, FLD m32real */ 6795 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 6796 Pop_Reg_F(dst) ); 6797 ins_pipe( fpu_reg_mem ); 6798%} 6799 6800// Load Stack Slot 6801instruct loadSSD(regD dst, stackSlotD src) %{ 6802 match(Set dst src); 6803 ins_cost(125); 6804 6805 format %{ "FLD_D $src\n\t" 6806 "FSTP $dst" %} 6807 opcode(0xDD); /* DD /0, FLD m64real */ 6808 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 6809 Pop_Reg_D(dst) ); 6810 ins_pipe( fpu_reg_mem ); 6811%} 6812 6813// Prefetch instructions. 6814// Must be safe to execute with invalid address (cannot fault). 6815 6816instruct prefetchr0( memory mem ) %{ 6817 predicate(UseSSE==0 && !VM_Version::supports_3dnow()); 6818 match(PrefetchRead mem); 6819 ins_cost(0); 6820 size(0); 6821 format %{ "PREFETCHR (non-SSE is empty encoding)" %} 6822 ins_encode(); 6823 ins_pipe(empty); 6824%} 6825 6826instruct prefetchr( memory mem ) %{ 6827 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3); 6828 match(PrefetchRead mem); 6829 ins_cost(100); 6830 6831 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} 6832 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */ 6833 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); 6834 ins_pipe(ialu_mem); 6835%} 6836 6837instruct prefetchrNTA( memory mem ) %{ 6838 predicate(UseSSE>=1 && ReadPrefetchInstr==0); 6839 match(PrefetchRead mem); 6840 ins_cost(100); 6841 6842 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} 6843 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ 6844 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); 6845 ins_pipe(ialu_mem); 6846%} 6847 6848instruct prefetchrT0( memory mem ) %{ 6849 predicate(UseSSE>=1 && ReadPrefetchInstr==1); 6850 match(PrefetchRead mem); 6851 ins_cost(100); 6852 6853 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} 6854 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ 6855 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); 6856 ins_pipe(ialu_mem); 6857%} 6858 6859instruct prefetchrT2( memory mem ) %{ 6860 predicate(UseSSE>=1 && ReadPrefetchInstr==2); 6861 match(PrefetchRead mem); 6862 ins_cost(100); 6863 6864 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} 6865 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ 6866 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); 6867 ins_pipe(ialu_mem); 6868%} 6869 6870instruct prefetchw0( memory mem ) %{ 6871 predicate(UseSSE==0 && !VM_Version::supports_3dnow()); 6872 match(PrefetchWrite mem); 6873 ins_cost(0); 6874 size(0); 6875 format %{ "Prefetch (non-SSE is empty encoding)" %} 6876 ins_encode(); 6877 ins_pipe(empty); 6878%} 6879 6880instruct prefetchw( memory mem ) %{ 6881 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3); 6882 match( PrefetchWrite mem ); 6883 ins_cost(100); 6884 6885 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} 6886 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ 6887 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); 6888 ins_pipe(ialu_mem); 6889%} 6890 6891instruct prefetchwNTA( memory mem ) %{ 6892 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); 6893 match(PrefetchWrite mem); 6894 ins_cost(100); 6895 6896 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} 6897 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ 6898 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); 6899 ins_pipe(ialu_mem); 6900%} 6901 6902instruct prefetchwT0( memory mem ) %{ 6903 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); 6904 match(PrefetchWrite mem); 6905 ins_cost(100); 6906 6907 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %} 6908 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ 6909 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); 6910 ins_pipe(ialu_mem); 6911%} 6912 6913instruct prefetchwT2( memory mem ) %{ 6914 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); 6915 match(PrefetchWrite mem); 6916 ins_cost(100); 6917 6918 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %} 6919 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ 6920 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); 6921 ins_pipe(ialu_mem); 6922%} 6923 6924//----------Store Instructions------------------------------------------------- 6925 6926// Store Byte 6927instruct storeB(memory mem, xRegI src) %{ 6928 match(Set mem (StoreB mem src)); 6929 6930 ins_cost(125); 6931 format %{ "MOV8 $mem,$src" %} 6932 opcode(0x88); 6933 ins_encode( OpcP, RegMem( src, mem ) ); 6934 ins_pipe( ialu_mem_reg ); 6935%} 6936 6937// Store Char/Short 6938instruct storeC(memory mem, eRegI src) %{ 6939 match(Set mem (StoreC mem src)); 6940 6941 ins_cost(125); 6942 format %{ "MOV16 $mem,$src" %} 6943 opcode(0x89, 0x66); 6944 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); 6945 ins_pipe( ialu_mem_reg ); 6946%} 6947 6948// Store Integer 6949instruct storeI(memory mem, eRegI src) %{ 6950 match(Set mem (StoreI mem src)); 6951 6952 ins_cost(125); 6953 format %{ "MOV $mem,$src" %} 6954 opcode(0x89); 6955 ins_encode( OpcP, RegMem( src, mem ) ); 6956 ins_pipe( ialu_mem_reg ); 6957%} 6958 6959// Store Long 6960instruct storeL(long_memory mem, eRegL src) %{ 6961 predicate(!((StoreLNode*)n)->require_atomic_access()); 6962 match(Set mem (StoreL mem src)); 6963 6964 ins_cost(200); 6965 format %{ "MOV $mem,$src.lo\n\t" 6966 "MOV $mem+4,$src.hi" %} 6967 opcode(0x89, 0x89); 6968 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); 6969 ins_pipe( ialu_mem_long_reg ); 6970%} 6971 6972// Volatile Store Long. Must be atomic, so move it into 6973// the FP TOS and then do a 64-bit FIST. Has to probe the 6974// target address before the store (for null-ptr checks) 6975// so the memory operand is used twice in the encoding. 6976instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ 6977 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); 6978 match(Set mem (StoreL mem src)); 6979 effect( KILL cr ); 6980 ins_cost(400); 6981 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 6982 "FILD $src\n\t" 6983 "FISTp $mem\t # 64-bit atomic volatile long store" %} 6984 opcode(0x3B); 6985 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); 6986 ins_pipe( fpu_reg_mem ); 6987%} 6988 6989instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{ 6990 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); 6991 match(Set mem (StoreL mem src)); 6992 effect( TEMP tmp, KILL cr ); 6993 ins_cost(380); 6994 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 6995 "MOVSD $tmp,$src\n\t" 6996 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} 6997 opcode(0x3B); 6998 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp)); 6999 ins_pipe( pipe_slow ); 7000%} 7001 7002instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{ 7003 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); 7004 match(Set mem (StoreL mem src)); 7005 effect( TEMP tmp2 , TEMP tmp, KILL cr ); 7006 ins_cost(360); 7007 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 7008 "MOVD $tmp,$src.lo\n\t" 7009 "MOVD $tmp2,$src.hi\n\t" 7010 "PUNPCKLDQ $tmp,$tmp2\n\t" 7011 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} 7012 opcode(0x3B); 7013 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2)); 7014 ins_pipe( pipe_slow ); 7015%} 7016 7017// Store Pointer; for storing unknown oops and raw pointers 7018instruct storeP(memory mem, anyRegP src) %{ 7019 match(Set mem (StoreP mem src)); 7020 7021 ins_cost(125); 7022 format %{ "MOV $mem,$src" %} 7023 opcode(0x89); 7024 ins_encode( OpcP, RegMem( src, mem ) ); 7025 ins_pipe( ialu_mem_reg ); 7026%} 7027 7028// Store Integer Immediate 7029instruct storeImmI(memory mem, immI src) %{ 7030 match(Set mem (StoreI mem src)); 7031 7032 ins_cost(150); 7033 format %{ "MOV $mem,$src" %} 7034 opcode(0xC7); /* C7 /0 */ 7035 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); 7036 ins_pipe( ialu_mem_imm ); 7037%} 7038 7039// Store Short/Char Immediate 7040instruct storeImmI16(memory mem, immI16 src) %{ 7041 predicate(UseStoreImmI16); 7042 match(Set mem (StoreC mem src)); 7043 7044 ins_cost(150); 7045 format %{ "MOV16 $mem,$src" %} 7046 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ 7047 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); 7048 ins_pipe( ialu_mem_imm ); 7049%} 7050 7051// Store Pointer Immediate; null pointers or constant oops that do not 7052// need card-mark barriers. 7053instruct storeImmP(memory mem, immP src) %{ 7054 match(Set mem (StoreP mem src)); 7055 7056 ins_cost(150); 7057 format %{ "MOV $mem,$src" %} 7058 opcode(0xC7); /* C7 /0 */ 7059 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); 7060 ins_pipe( ialu_mem_imm ); 7061%} 7062 7063// Store Byte Immediate 7064instruct storeImmB(memory mem, immI8 src) %{ 7065 match(Set mem (StoreB mem src)); 7066 7067 ins_cost(150); 7068 format %{ "MOV8 $mem,$src" %} 7069 opcode(0xC6); /* C6 /0 */ 7070 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); 7071 ins_pipe( ialu_mem_imm ); 7072%} 7073 7074// Store Aligned Packed Byte XMM register to memory 7075instruct storeA8B(memory mem, regXD src) %{ 7076 predicate(UseSSE>=1); 7077 match(Set mem (Store8B mem src)); 7078 ins_cost(145); 7079 format %{ "MOVQ $mem,$src\t! packed8B" %} 7080 ins_encode( movq_st(mem, src)); 7081 ins_pipe( pipe_slow ); 7082%} 7083 7084// Store Aligned Packed Char/Short XMM register to memory 7085instruct storeA4C(memory mem, regXD src) %{ 7086 predicate(UseSSE>=1); 7087 match(Set mem (Store4C mem src)); 7088 ins_cost(145); 7089 format %{ "MOVQ $mem,$src\t! packed4C" %} 7090 ins_encode( movq_st(mem, src)); 7091 ins_pipe( pipe_slow ); 7092%} 7093 7094// Store Aligned Packed Integer XMM register to memory 7095instruct storeA2I(memory mem, regXD src) %{ 7096 predicate(UseSSE>=1); 7097 match(Set mem (Store2I mem src)); 7098 ins_cost(145); 7099 format %{ "MOVQ $mem,$src\t! packed2I" %} 7100 ins_encode( movq_st(mem, src)); 7101 ins_pipe( pipe_slow ); 7102%} 7103 7104// Store CMS card-mark Immediate 7105instruct storeImmCM(memory mem, immI8 src) %{ 7106 match(Set mem (StoreCM mem src)); 7107 7108 ins_cost(150); 7109 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} 7110 opcode(0xC6); /* C6 /0 */ 7111 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); 7112 ins_pipe( ialu_mem_imm ); 7113%} 7114 7115// Store Double 7116instruct storeD( memory mem, regDPR1 src) %{ 7117 predicate(UseSSE<=1); 7118 match(Set mem (StoreD mem src)); 7119 7120 ins_cost(100); 7121 format %{ "FST_D $mem,$src" %} 7122 opcode(0xDD); /* DD /2 */ 7123 ins_encode( enc_FP_store(mem,src) ); 7124 ins_pipe( fpu_mem_reg ); 7125%} 7126 7127// Store double does rounding on x86 7128instruct storeD_rounded( memory mem, regDPR1 src) %{ 7129 predicate(UseSSE<=1); 7130 match(Set mem (StoreD mem (RoundDouble src))); 7131 7132 ins_cost(100); 7133 format %{ "FST_D $mem,$src\t# round" %} 7134 opcode(0xDD); /* DD /2 */ 7135 ins_encode( enc_FP_store(mem,src) ); 7136 ins_pipe( fpu_mem_reg ); 7137%} 7138 7139// Store XMM register to memory (double-precision floating points) 7140// MOVSD instruction 7141instruct storeXD(memory mem, regXD src) %{ 7142 predicate(UseSSE>=2); 7143 match(Set mem (StoreD mem src)); 7144 ins_cost(95); 7145 format %{ "MOVSD $mem,$src" %} 7146 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem)); 7147 ins_pipe( pipe_slow ); 7148%} 7149 7150// Store XMM register to memory (single-precision floating point) 7151// MOVSS instruction 7152instruct storeX(memory mem, regX src) %{ 7153 predicate(UseSSE>=1); 7154 match(Set mem (StoreF mem src)); 7155 ins_cost(95); 7156 format %{ "MOVSS $mem,$src" %} 7157 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem)); 7158 ins_pipe( pipe_slow ); 7159%} 7160 7161// Store Aligned Packed Single Float XMM register to memory 7162instruct storeA2F(memory mem, regXD src) %{ 7163 predicate(UseSSE>=1); 7164 match(Set mem (Store2F mem src)); 7165 ins_cost(145); 7166 format %{ "MOVQ $mem,$src\t! packed2F" %} 7167 ins_encode( movq_st(mem, src)); 7168 ins_pipe( pipe_slow ); 7169%} 7170 7171// Store Float 7172instruct storeF( memory mem, regFPR1 src) %{ 7173 predicate(UseSSE==0); 7174 match(Set mem (StoreF mem src)); 7175 7176 ins_cost(100); 7177 format %{ "FST_S $mem,$src" %} 7178 opcode(0xD9); /* D9 /2 */ 7179 ins_encode( enc_FP_store(mem,src) ); 7180 ins_pipe( fpu_mem_reg ); 7181%} 7182 7183// Store Float does rounding on x86 7184instruct storeF_rounded( memory mem, regFPR1 src) %{ 7185 predicate(UseSSE==0); 7186 match(Set mem (StoreF mem (RoundFloat src))); 7187 7188 ins_cost(100); 7189 format %{ "FST_S $mem,$src\t# round" %} 7190 opcode(0xD9); /* D9 /2 */ 7191 ins_encode( enc_FP_store(mem,src) ); 7192 ins_pipe( fpu_mem_reg ); 7193%} 7194 7195// Store Float does rounding on x86 7196instruct storeF_Drounded( memory mem, regDPR1 src) %{ 7197 predicate(UseSSE<=1); 7198 match(Set mem (StoreF mem (ConvD2F src))); 7199 7200 ins_cost(100); 7201 format %{ "FST_S $mem,$src\t# D-round" %} 7202 opcode(0xD9); /* D9 /2 */ 7203 ins_encode( enc_FP_store(mem,src) ); 7204 ins_pipe( fpu_mem_reg ); 7205%} 7206 7207// Store immediate Float value (it is faster than store from FPU register) 7208// The instruction usage is guarded by predicate in operand immF(). 7209instruct storeF_imm( memory mem, immF src) %{ 7210 match(Set mem (StoreF mem src)); 7211 7212 ins_cost(50); 7213 format %{ "MOV $mem,$src\t# store float" %} 7214 opcode(0xC7); /* C7 /0 */ 7215 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); 7216 ins_pipe( ialu_mem_imm ); 7217%} 7218 7219// Store immediate Float value (it is faster than store from XMM register) 7220// The instruction usage is guarded by predicate in operand immXF(). 7221instruct storeX_imm( memory mem, immXF src) %{ 7222 match(Set mem (StoreF mem src)); 7223 7224 ins_cost(50); 7225 format %{ "MOV $mem,$src\t# store float" %} 7226 opcode(0xC7); /* C7 /0 */ 7227 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src )); 7228 ins_pipe( ialu_mem_imm ); 7229%} 7230 7231// Store Integer to stack slot 7232instruct storeSSI(stackSlotI dst, eRegI src) %{ 7233 match(Set dst src); 7234 7235 ins_cost(100); 7236 format %{ "MOV $dst,$src" %} 7237 opcode(0x89); 7238 ins_encode( OpcPRegSS( dst, src ) ); 7239 ins_pipe( ialu_mem_reg ); 7240%} 7241 7242// Store Integer to stack slot 7243instruct storeSSP(stackSlotP dst, eRegP src) %{ 7244 match(Set dst src); 7245 7246 ins_cost(100); 7247 format %{ "MOV $dst,$src" %} 7248 opcode(0x89); 7249 ins_encode( OpcPRegSS( dst, src ) ); 7250 ins_pipe( ialu_mem_reg ); 7251%} 7252 7253// Store Long to stack slot 7254instruct storeSSL(stackSlotL dst, eRegL src) %{ 7255 match(Set dst src); 7256 7257 ins_cost(200); 7258 format %{ "MOV $dst,$src.lo\n\t" 7259 "MOV $dst+4,$src.hi" %} 7260 opcode(0x89, 0x89); 7261 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); 7262 ins_pipe( ialu_mem_long_reg ); 7263%} 7264 7265//----------MemBar Instructions----------------------------------------------- 7266// Memory barrier flavors 7267 7268instruct membar_acquire() %{ 7269 match(MemBarAcquire); 7270 ins_cost(400); 7271 7272 size(0); 7273 format %{ "MEMBAR-acquire" %} 7274 ins_encode( enc_membar_acquire ); 7275 ins_pipe(pipe_slow); 7276%} 7277 7278instruct membar_acquire_lock() %{ 7279 match(MemBarAcquire); 7280 predicate(Matcher::prior_fast_lock(n)); 7281 ins_cost(0); 7282 7283 size(0); 7284 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} 7285 ins_encode( ); 7286 ins_pipe(empty); 7287%} 7288 7289instruct membar_release() %{ 7290 match(MemBarRelease); 7291 ins_cost(400); 7292 7293 size(0); 7294 format %{ "MEMBAR-release" %} 7295 ins_encode( enc_membar_release ); 7296 ins_pipe(pipe_slow); 7297%} 7298 7299instruct membar_release_lock() %{ 7300 match(MemBarRelease); 7301 predicate(Matcher::post_fast_unlock(n)); 7302 ins_cost(0); 7303 7304 size(0); 7305 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} 7306 ins_encode( ); 7307 ins_pipe(empty); 7308%} 7309 7310instruct membar_volatile() %{ 7311 match(MemBarVolatile); 7312 ins_cost(400); 7313 7314 format %{ "MEMBAR-volatile" %} 7315 ins_encode( enc_membar_volatile ); 7316 ins_pipe(pipe_slow); 7317%} 7318 7319instruct unnecessary_membar_volatile() %{ 7320 match(MemBarVolatile); 7321 predicate(Matcher::post_store_load_barrier(n)); 7322 ins_cost(0); 7323 7324 size(0); 7325 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} 7326 ins_encode( ); 7327 ins_pipe(empty); 7328%} 7329 7330//----------Move Instructions-------------------------------------------------- 7331instruct castX2P(eAXRegP dst, eAXRegI src) %{ 7332 match(Set dst (CastX2P src)); 7333 format %{ "# X2P $dst, $src" %} 7334 ins_encode( /*empty encoding*/ ); 7335 ins_cost(0); 7336 ins_pipe(empty); 7337%} 7338 7339instruct castP2X(eRegI dst, eRegP src ) %{ 7340 match(Set dst (CastP2X src)); 7341 ins_cost(50); 7342 format %{ "MOV $dst, $src\t# CastP2X" %} 7343 ins_encode( enc_Copy( dst, src) ); 7344 ins_pipe( ialu_reg_reg ); 7345%} 7346 7347//----------Conditional Move--------------------------------------------------- 7348// Conditional move 7349instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{ 7350 predicate(VM_Version::supports_cmov() ); 7351 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7352 ins_cost(200); 7353 format %{ "CMOV$cop $dst,$src" %} 7354 opcode(0x0F,0x40); 7355 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7356 ins_pipe( pipe_cmov_reg ); 7357%} 7358 7359instruct cmovI_regU( eRegI dst, eRegI src, eFlagsRegU cr, cmpOpU cop ) %{ 7360 predicate(VM_Version::supports_cmov() ); 7361 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7362 ins_cost(200); 7363 format %{ "CMOV$cop $dst,$src" %} 7364 opcode(0x0F,0x40); 7365 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7366 ins_pipe( pipe_cmov_reg ); 7367%} 7368 7369// Conditional move 7370instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{ 7371 predicate(VM_Version::supports_cmov() ); 7372 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 7373 ins_cost(250); 7374 format %{ "CMOV$cop $dst,$src" %} 7375 opcode(0x0F,0x40); 7376 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7377 ins_pipe( pipe_cmov_mem ); 7378%} 7379 7380// Conditional move 7381instruct cmovI_memu(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{ 7382 predicate(VM_Version::supports_cmov() ); 7383 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 7384 ins_cost(250); 7385 format %{ "CMOV$cop $dst,$src" %} 7386 opcode(0x0F,0x40); 7387 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7388 ins_pipe( pipe_cmov_mem ); 7389%} 7390 7391// Conditional move 7392instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ 7393 predicate(VM_Version::supports_cmov() ); 7394 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7395 ins_cost(200); 7396 format %{ "CMOV$cop $dst,$src\t# ptr" %} 7397 opcode(0x0F,0x40); 7398 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7399 ins_pipe( pipe_cmov_reg ); 7400%} 7401 7402// Conditional move (non-P6 version) 7403// Note: a CMoveP is generated for stubs and native wrappers 7404// regardless of whether we are on a P6, so we 7405// emulate a cmov here 7406instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ 7407 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7408 ins_cost(300); 7409 format %{ "Jn$cop skip\n\t" 7410 "MOV $dst,$src\t# pointer\n" 7411 "skip:" %} 7412 opcode(0x8b); 7413 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); 7414 ins_pipe( pipe_cmov_reg ); 7415%} 7416 7417// Conditional move 7418instruct cmovP_regU(eRegP dst, eRegP src, eFlagsRegU cr, cmpOpU cop ) %{ 7419 predicate(VM_Version::supports_cmov() ); 7420 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7421 ins_cost(200); 7422 format %{ "CMOV$cop $dst,$src\t# ptr" %} 7423 opcode(0x0F,0x40); 7424 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7425 ins_pipe( pipe_cmov_reg ); 7426%} 7427 7428// DISABLED: Requires the ADLC to emit a bottom_type call that 7429// correctly meets the two pointer arguments; one is an incoming 7430// register but the other is a memory operand. ALSO appears to 7431// be buggy with implicit null checks. 7432// 7433//// Conditional move 7434//instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ 7435// predicate(VM_Version::supports_cmov() ); 7436// match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); 7437// ins_cost(250); 7438// format %{ "CMOV$cop $dst,$src\t# ptr" %} 7439// opcode(0x0F,0x40); 7440// ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7441// ins_pipe( pipe_cmov_mem ); 7442//%} 7443// 7444//// Conditional move 7445//instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ 7446// predicate(VM_Version::supports_cmov() ); 7447// match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); 7448// ins_cost(250); 7449// format %{ "CMOV$cop $dst,$src\t# ptr" %} 7450// opcode(0x0F,0x40); 7451// ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7452// ins_pipe( pipe_cmov_mem ); 7453//%} 7454 7455// Conditional move 7456instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{ 7457 predicate(UseSSE<=1); 7458 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7459 ins_cost(200); 7460 format %{ "FCMOV$cop $dst,$src\t# double" %} 7461 opcode(0xDA); 7462 ins_encode( enc_cmov_d(cop,src) ); 7463 ins_pipe( pipe_cmovD_reg ); 7464%} 7465 7466// Conditional move 7467instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{ 7468 predicate(UseSSE==0); 7469 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7470 ins_cost(200); 7471 format %{ "FCMOV$cop $dst,$src\t# float" %} 7472 opcode(0xDA); 7473 ins_encode( enc_cmov_d(cop,src) ); 7474 ins_pipe( pipe_cmovD_reg ); 7475%} 7476 7477// Float CMOV on Intel doesn't handle *signed* compares, only unsigned. 7478instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ 7479 predicate(UseSSE<=1); 7480 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7481 ins_cost(200); 7482 format %{ "Jn$cop skip\n\t" 7483 "MOV $dst,$src\t# double\n" 7484 "skip:" %} 7485 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ 7486 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) ); 7487 ins_pipe( pipe_cmovD_reg ); 7488%} 7489 7490// Float CMOV on Intel doesn't handle *signed* compares, only unsigned. 7491instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ 7492 predicate(UseSSE==0); 7493 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7494 ins_cost(200); 7495 format %{ "Jn$cop skip\n\t" 7496 "MOV $dst,$src\t# float\n" 7497 "skip:" %} 7498 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ 7499 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) ); 7500 ins_pipe( pipe_cmovD_reg ); 7501%} 7502 7503// No CMOVE with SSE/SSE2 7504instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{ 7505 predicate (UseSSE>=1); 7506 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7507 ins_cost(200); 7508 format %{ "Jn$cop skip\n\t" 7509 "MOVSS $dst,$src\t# float\n" 7510 "skip:" %} 7511 ins_encode %{ 7512 Label skip; 7513 // Invert sense of branch from sense of CMOV 7514 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7515 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 7516 __ bind(skip); 7517 %} 7518 ins_pipe( pipe_slow ); 7519%} 7520 7521// No CMOVE with SSE/SSE2 7522instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{ 7523 predicate (UseSSE>=2); 7524 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7525 ins_cost(200); 7526 format %{ "Jn$cop skip\n\t" 7527 "MOVSD $dst,$src\t# float\n" 7528 "skip:" %} 7529 ins_encode %{ 7530 Label skip; 7531 // Invert sense of branch from sense of CMOV 7532 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7533 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 7534 __ bind(skip); 7535 %} 7536 ins_pipe( pipe_slow ); 7537%} 7538 7539// unsigned version 7540instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{ 7541 predicate (UseSSE>=1); 7542 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7543 ins_cost(200); 7544 format %{ "Jn$cop skip\n\t" 7545 "MOVSS $dst,$src\t# float\n" 7546 "skip:" %} 7547 ins_encode %{ 7548 Label skip; 7549 // Invert sense of branch from sense of CMOV 7550 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7551 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 7552 __ bind(skip); 7553 %} 7554 ins_pipe( pipe_slow ); 7555%} 7556 7557// unsigned version 7558instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{ 7559 predicate (UseSSE>=2); 7560 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7561 ins_cost(200); 7562 format %{ "Jn$cop skip\n\t" 7563 "MOVSD $dst,$src\t# float\n" 7564 "skip:" %} 7565 ins_encode %{ 7566 Label skip; 7567 // Invert sense of branch from sense of CMOV 7568 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7569 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 7570 __ bind(skip); 7571 %} 7572 ins_pipe( pipe_slow ); 7573%} 7574 7575instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ 7576 predicate(VM_Version::supports_cmov() ); 7577 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 7578 ins_cost(200); 7579 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" 7580 "CMOV$cop $dst.hi,$src.hi" %} 7581 opcode(0x0F,0x40); 7582 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); 7583 ins_pipe( pipe_cmov_reg_long ); 7584%} 7585 7586instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ 7587 predicate(VM_Version::supports_cmov() ); 7588 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 7589 ins_cost(200); 7590 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" 7591 "CMOV$cop $dst.hi,$src.hi" %} 7592 opcode(0x0F,0x40); 7593 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); 7594 ins_pipe( pipe_cmov_reg_long ); 7595%} 7596 7597//----------Arithmetic Instructions-------------------------------------------- 7598//----------Addition Instructions---------------------------------------------- 7599// Integer Addition Instructions 7600instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 7601 match(Set dst (AddI dst src)); 7602 effect(KILL cr); 7603 7604 size(2); 7605 format %{ "ADD $dst,$src" %} 7606 opcode(0x03); 7607 ins_encode( OpcP, RegReg( dst, src) ); 7608 ins_pipe( ialu_reg_reg ); 7609%} 7610 7611instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 7612 match(Set dst (AddI dst src)); 7613 effect(KILL cr); 7614 7615 format %{ "ADD $dst,$src" %} 7616 opcode(0x81, 0x00); /* /0 id */ 7617 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 7618 ins_pipe( ialu_reg ); 7619%} 7620 7621instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 7622 predicate(UseIncDec); 7623 match(Set dst (AddI dst src)); 7624 effect(KILL cr); 7625 7626 size(1); 7627 format %{ "INC $dst" %} 7628 opcode(0x40); /* */ 7629 ins_encode( Opc_plus( primary, dst ) ); 7630 ins_pipe( ialu_reg ); 7631%} 7632 7633instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{ 7634 match(Set dst (AddI src0 src1)); 7635 ins_cost(110); 7636 7637 format %{ "LEA $dst,[$src0 + $src1]" %} 7638 opcode(0x8D); /* 0x8D /r */ 7639 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); 7640 ins_pipe( ialu_reg_reg ); 7641%} 7642 7643instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ 7644 match(Set dst (AddP src0 src1)); 7645 ins_cost(110); 7646 7647 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} 7648 opcode(0x8D); /* 0x8D /r */ 7649 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); 7650 ins_pipe( ialu_reg_reg ); 7651%} 7652 7653instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{ 7654 predicate(UseIncDec); 7655 match(Set dst (AddI dst src)); 7656 effect(KILL cr); 7657 7658 size(1); 7659 format %{ "DEC $dst" %} 7660 opcode(0x48); /* */ 7661 ins_encode( Opc_plus( primary, dst ) ); 7662 ins_pipe( ialu_reg ); 7663%} 7664 7665instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{ 7666 match(Set dst (AddP dst src)); 7667 effect(KILL cr); 7668 7669 size(2); 7670 format %{ "ADD $dst,$src" %} 7671 opcode(0x03); 7672 ins_encode( OpcP, RegReg( dst, src) ); 7673 ins_pipe( ialu_reg_reg ); 7674%} 7675 7676instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ 7677 match(Set dst (AddP dst src)); 7678 effect(KILL cr); 7679 7680 format %{ "ADD $dst,$src" %} 7681 opcode(0x81,0x00); /* Opcode 81 /0 id */ 7682 // ins_encode( RegImm( dst, src) ); 7683 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 7684 ins_pipe( ialu_reg ); 7685%} 7686 7687instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 7688 match(Set dst (AddI dst (LoadI src))); 7689 effect(KILL cr); 7690 7691 ins_cost(125); 7692 format %{ "ADD $dst,$src" %} 7693 opcode(0x03); 7694 ins_encode( OpcP, RegMem( dst, src) ); 7695 ins_pipe( ialu_reg_mem ); 7696%} 7697 7698instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 7699 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7700 effect(KILL cr); 7701 7702 ins_cost(150); 7703 format %{ "ADD $dst,$src" %} 7704 opcode(0x01); /* Opcode 01 /r */ 7705 ins_encode( OpcP, RegMem( src, dst ) ); 7706 ins_pipe( ialu_mem_reg ); 7707%} 7708 7709// Add Memory with Immediate 7710instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 7711 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7712 effect(KILL cr); 7713 7714 ins_cost(125); 7715 format %{ "ADD $dst,$src" %} 7716 opcode(0x81); /* Opcode 81 /0 id */ 7717 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); 7718 ins_pipe( ialu_mem_imm ); 7719%} 7720 7721instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ 7722 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7723 effect(KILL cr); 7724 7725 ins_cost(125); 7726 format %{ "INC $dst" %} 7727 opcode(0xFF); /* Opcode FF /0 */ 7728 ins_encode( OpcP, RMopc_Mem(0x00,dst)); 7729 ins_pipe( ialu_mem_imm ); 7730%} 7731 7732instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ 7733 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7734 effect(KILL cr); 7735 7736 ins_cost(125); 7737 format %{ "DEC $dst" %} 7738 opcode(0xFF); /* Opcode FF /1 */ 7739 ins_encode( OpcP, RMopc_Mem(0x01,dst)); 7740 ins_pipe( ialu_mem_imm ); 7741%} 7742 7743 7744instruct checkCastPP( eRegP dst ) %{ 7745 match(Set dst (CheckCastPP dst)); 7746 7747 size(0); 7748 format %{ "#checkcastPP of $dst" %} 7749 ins_encode( /*empty encoding*/ ); 7750 ins_pipe( empty ); 7751%} 7752 7753instruct castPP( eRegP dst ) %{ 7754 match(Set dst (CastPP dst)); 7755 format %{ "#castPP of $dst" %} 7756 ins_encode( /*empty encoding*/ ); 7757 ins_pipe( empty ); 7758%} 7759 7760instruct castII( eRegI dst ) %{ 7761 match(Set dst (CastII dst)); 7762 format %{ "#castII of $dst" %} 7763 ins_encode( /*empty encoding*/ ); 7764 ins_cost(0); 7765 ins_pipe( empty ); 7766%} 7767 7768 7769// Load-locked - same as a regular pointer load when used with compare-swap 7770instruct loadPLocked(eRegP dst, memory mem) %{ 7771 match(Set dst (LoadPLocked mem)); 7772 7773 ins_cost(125); 7774 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} 7775 opcode(0x8B); 7776 ins_encode( OpcP, RegMem(dst,mem)); 7777 ins_pipe( ialu_reg_mem ); 7778%} 7779 7780// LoadLong-locked - same as a volatile long load when used with compare-swap 7781instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{ 7782 predicate(UseSSE<=1); 7783 match(Set dst (LoadLLocked mem)); 7784 7785 ins_cost(200); 7786 format %{ "FILD $mem\t# Atomic volatile long load\n\t" 7787 "FISTp $dst" %} 7788 ins_encode(enc_loadL_volatile(mem,dst)); 7789 ins_pipe( fpu_reg_mem ); 7790%} 7791 7792instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{ 7793 predicate(UseSSE>=2); 7794 match(Set dst (LoadLLocked mem)); 7795 effect(TEMP tmp); 7796 ins_cost(180); 7797 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 7798 "MOVSD $dst,$tmp" %} 7799 ins_encode(enc_loadLX_volatile(mem, dst, tmp)); 7800 ins_pipe( pipe_slow ); 7801%} 7802 7803instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{ 7804 predicate(UseSSE>=2); 7805 match(Set dst (LoadLLocked mem)); 7806 effect(TEMP tmp); 7807 ins_cost(160); 7808 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 7809 "MOVD $dst.lo,$tmp\n\t" 7810 "PSRLQ $tmp,32\n\t" 7811 "MOVD $dst.hi,$tmp" %} 7812 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp)); 7813 ins_pipe( pipe_slow ); 7814%} 7815 7816// Conditional-store of the updated heap-top. 7817// Used during allocation of the shared heap. 7818// Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. 7819instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ 7820 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); 7821 // EAX is killed if there is contention, but then it's also unused. 7822 // In the common case of no contention, EAX holds the new oop address. 7823 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} 7824 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); 7825 ins_pipe( pipe_cmpxchg ); 7826%} 7827 7828// Conditional-store of a long value 7829// Returns a boolean value (0/1) on success. Implemented with a CMPXCHG8 on Intel. 7830// mem_ptr can actually be in either ESI or EDI 7831instruct storeLConditional( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ 7832 match(Set res (StoreLConditional mem_ptr (Binary oldval newval))); 7833 effect(KILL cr); 7834 // EDX:EAX is killed if there is contention, but then it's also unused. 7835 // In the common case of no contention, EDX:EAX holds the new oop address. 7836 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 7837 "MOV $res,0\n\t" 7838 "JNE,s fail\n\t" 7839 "MOV $res,1\n" 7840 "fail:" %} 7841 ins_encode( enc_cmpxchg8(mem_ptr), 7842 enc_flags_ne_to_boolean(res) ); 7843 ins_pipe( pipe_cmpxchg ); 7844%} 7845 7846// Conditional-store of a long value 7847// ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. 7848// mem_ptr can actually be in either ESI or EDI 7849instruct storeLConditional_flags( eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr, immI0 zero ) %{ 7850 match(Set cr (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero)); 7851 // EDX:EAX is killed if there is contention, but then it's also unused. 7852 // In the common case of no contention, EDX:EAX holds the new oop address. 7853 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" %} 7854 ins_encode( enc_cmpxchg8(mem_ptr) ); 7855 ins_pipe( pipe_cmpxchg ); 7856%} 7857 7858// No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7859 7860instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ 7861 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 7862 effect(KILL cr, KILL oldval); 7863 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 7864 "MOV $res,0\n\t" 7865 "JNE,s fail\n\t" 7866 "MOV $res,1\n" 7867 "fail:" %} 7868 ins_encode( enc_cmpxchg8(mem_ptr), 7869 enc_flags_ne_to_boolean(res) ); 7870 ins_pipe( pipe_cmpxchg ); 7871%} 7872 7873instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ 7874 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 7875 effect(KILL cr, KILL oldval); 7876 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 7877 "MOV $res,0\n\t" 7878 "JNE,s fail\n\t" 7879 "MOV $res,1\n" 7880 "fail:" %} 7881 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); 7882 ins_pipe( pipe_cmpxchg ); 7883%} 7884 7885instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ 7886 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 7887 effect(KILL cr, KILL oldval); 7888 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 7889 "MOV $res,0\n\t" 7890 "JNE,s fail\n\t" 7891 "MOV $res,1\n" 7892 "fail:" %} 7893 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); 7894 ins_pipe( pipe_cmpxchg ); 7895%} 7896 7897//----------Subtraction Instructions------------------------------------------- 7898// Integer Subtraction Instructions 7899instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 7900 match(Set dst (SubI dst src)); 7901 effect(KILL cr); 7902 7903 size(2); 7904 format %{ "SUB $dst,$src" %} 7905 opcode(0x2B); 7906 ins_encode( OpcP, RegReg( dst, src) ); 7907 ins_pipe( ialu_reg_reg ); 7908%} 7909 7910instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 7911 match(Set dst (SubI dst src)); 7912 effect(KILL cr); 7913 7914 format %{ "SUB $dst,$src" %} 7915 opcode(0x81,0x05); /* Opcode 81 /5 */ 7916 // ins_encode( RegImm( dst, src) ); 7917 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 7918 ins_pipe( ialu_reg ); 7919%} 7920 7921instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 7922 match(Set dst (SubI dst (LoadI src))); 7923 effect(KILL cr); 7924 7925 ins_cost(125); 7926 format %{ "SUB $dst,$src" %} 7927 opcode(0x2B); 7928 ins_encode( OpcP, RegMem( dst, src) ); 7929 ins_pipe( ialu_reg_mem ); 7930%} 7931 7932instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 7933 match(Set dst (StoreI dst (SubI (LoadI dst) src))); 7934 effect(KILL cr); 7935 7936 ins_cost(150); 7937 format %{ "SUB $dst,$src" %} 7938 opcode(0x29); /* Opcode 29 /r */ 7939 ins_encode( OpcP, RegMem( src, dst ) ); 7940 ins_pipe( ialu_mem_reg ); 7941%} 7942 7943// Subtract from a pointer 7944instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{ 7945 match(Set dst (AddP dst (SubI zero src))); 7946 effect(KILL cr); 7947 7948 size(2); 7949 format %{ "SUB $dst,$src" %} 7950 opcode(0x2B); 7951 ins_encode( OpcP, RegReg( dst, src) ); 7952 ins_pipe( ialu_reg_reg ); 7953%} 7954 7955instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{ 7956 match(Set dst (SubI zero dst)); 7957 effect(KILL cr); 7958 7959 size(2); 7960 format %{ "NEG $dst" %} 7961 opcode(0xF7,0x03); // Opcode F7 /3 7962 ins_encode( OpcP, RegOpc( dst ) ); 7963 ins_pipe( ialu_reg ); 7964%} 7965 7966 7967//----------Multiplication/Division Instructions------------------------------- 7968// Integer Multiplication Instructions 7969// Multiply Register 7970instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 7971 match(Set dst (MulI dst src)); 7972 effect(KILL cr); 7973 7974 size(3); 7975 ins_cost(300); 7976 format %{ "IMUL $dst,$src" %} 7977 opcode(0xAF, 0x0F); 7978 ins_encode( OpcS, OpcP, RegReg( dst, src) ); 7979 ins_pipe( ialu_reg_reg_alu0 ); 7980%} 7981 7982// Multiply 32-bit Immediate 7983instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{ 7984 match(Set dst (MulI src imm)); 7985 effect(KILL cr); 7986 7987 ins_cost(300); 7988 format %{ "IMUL $dst,$src,$imm" %} 7989 opcode(0x69); /* 69 /r id */ 7990 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); 7991 ins_pipe( ialu_reg_reg_alu0 ); 7992%} 7993 7994instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ 7995 match(Set dst src); 7996 effect(KILL cr); 7997 7998 // Note that this is artificially increased to make it more expensive than loadConL 7999 ins_cost(250); 8000 format %{ "MOV EAX,$src\t// low word only" %} 8001 opcode(0xB8); 8002 ins_encode( LdImmL_Lo(dst, src) ); 8003 ins_pipe( ialu_reg_fat ); 8004%} 8005 8006// Multiply by 32-bit Immediate, taking the shifted high order results 8007// (special case for shift by 32) 8008instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ 8009 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); 8010 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && 8011 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && 8012 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); 8013 effect(USE src1, KILL cr); 8014 8015 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only 8016 ins_cost(0*100 + 1*400 - 150); 8017 format %{ "IMUL EDX:EAX,$src1" %} 8018 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); 8019 ins_pipe( pipe_slow ); 8020%} 8021 8022// Multiply by 32-bit Immediate, taking the shifted high order results 8023instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ 8024 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); 8025 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && 8026 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && 8027 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); 8028 effect(USE src1, KILL cr); 8029 8030 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only 8031 ins_cost(1*100 + 1*400 - 150); 8032 format %{ "IMUL EDX:EAX,$src1\n\t" 8033 "SAR EDX,$cnt-32" %} 8034 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); 8035 ins_pipe( pipe_slow ); 8036%} 8037 8038// Multiply Memory 32-bit Immediate 8039instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{ 8040 match(Set dst (MulI (LoadI src) imm)); 8041 effect(KILL cr); 8042 8043 ins_cost(300); 8044 format %{ "IMUL $dst,$src,$imm" %} 8045 opcode(0x69); /* 69 /r id */ 8046 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); 8047 ins_pipe( ialu_reg_mem_alu0 ); 8048%} 8049 8050// Multiply Memory 8051instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{ 8052 match(Set dst (MulI dst (LoadI src))); 8053 effect(KILL cr); 8054 8055 ins_cost(350); 8056 format %{ "IMUL $dst,$src" %} 8057 opcode(0xAF, 0x0F); 8058 ins_encode( OpcS, OpcP, RegMem( dst, src) ); 8059 ins_pipe( ialu_reg_mem_alu0 ); 8060%} 8061 8062// Multiply Register Int to Long 8063instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ 8064 // Basic Idea: long = (long)int * (long)int 8065 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); 8066 effect(DEF dst, USE src, USE src1, KILL flags); 8067 8068 ins_cost(300); 8069 format %{ "IMUL $dst,$src1" %} 8070 8071 ins_encode( long_int_multiply( dst, src1 ) ); 8072 ins_pipe( ialu_reg_reg_alu0 ); 8073%} 8074 8075instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ 8076 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) 8077 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); 8078 effect(KILL flags); 8079 8080 ins_cost(300); 8081 format %{ "MUL $dst,$src1" %} 8082 8083 ins_encode( long_uint_multiply(dst, src1) ); 8084 ins_pipe( ialu_reg_reg_alu0 ); 8085%} 8086 8087// Multiply Register Long 8088instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 8089 match(Set dst (MulL dst src)); 8090 effect(KILL cr, TEMP tmp); 8091 ins_cost(4*100+3*400); 8092// Basic idea: lo(result) = lo(x_lo * y_lo) 8093// hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 8094 format %{ "MOV $tmp,$src.lo\n\t" 8095 "IMUL $tmp,EDX\n\t" 8096 "MOV EDX,$src.hi\n\t" 8097 "IMUL EDX,EAX\n\t" 8098 "ADD $tmp,EDX\n\t" 8099 "MUL EDX:EAX,$src.lo\n\t" 8100 "ADD EDX,$tmp" %} 8101 ins_encode( long_multiply( dst, src, tmp ) ); 8102 ins_pipe( pipe_slow ); 8103%} 8104 8105// Multiply Register Long by small constant 8106instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{ 8107 match(Set dst (MulL dst src)); 8108 effect(KILL cr, TEMP tmp); 8109 ins_cost(2*100+2*400); 8110 size(12); 8111// Basic idea: lo(result) = lo(src * EAX) 8112// hi(result) = hi(src * EAX) + lo(src * EDX) 8113 format %{ "IMUL $tmp,EDX,$src\n\t" 8114 "MOV EDX,$src\n\t" 8115 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" 8116 "ADD EDX,$tmp" %} 8117 ins_encode( long_multiply_con( dst, src, tmp ) ); 8118 ins_pipe( pipe_slow ); 8119%} 8120 8121// Integer DIV with Register 8122instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ 8123 match(Set rax (DivI rax div)); 8124 effect(KILL rdx, KILL cr); 8125 size(26); 8126 ins_cost(30*100+10*100); 8127 format %{ "CMP EAX,0x80000000\n\t" 8128 "JNE,s normal\n\t" 8129 "XOR EDX,EDX\n\t" 8130 "CMP ECX,-1\n\t" 8131 "JE,s done\n" 8132 "normal: CDQ\n\t" 8133 "IDIV $div\n\t" 8134 "done:" %} 8135 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8136 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8137 ins_pipe( ialu_reg_reg_alu0 ); 8138%} 8139 8140// Divide Register Long 8141instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ 8142 match(Set dst (DivL src1 src2)); 8143 effect( KILL cr, KILL cx, KILL bx ); 8144 ins_cost(10000); 8145 format %{ "PUSH $src1.hi\n\t" 8146 "PUSH $src1.lo\n\t" 8147 "PUSH $src2.hi\n\t" 8148 "PUSH $src2.lo\n\t" 8149 "CALL SharedRuntime::ldiv\n\t" 8150 "ADD ESP,16" %} 8151 ins_encode( long_div(src1,src2) ); 8152 ins_pipe( pipe_slow ); 8153%} 8154 8155// Integer DIVMOD with Register, both quotient and mod results 8156instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ 8157 match(DivModI rax div); 8158 effect(KILL cr); 8159 size(26); 8160 ins_cost(30*100+10*100); 8161 format %{ "CMP EAX,0x80000000\n\t" 8162 "JNE,s normal\n\t" 8163 "XOR EDX,EDX\n\t" 8164 "CMP ECX,-1\n\t" 8165 "JE,s done\n" 8166 "normal: CDQ\n\t" 8167 "IDIV $div\n\t" 8168 "done:" %} 8169 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8170 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8171 ins_pipe( pipe_slow ); 8172%} 8173 8174// Integer MOD with Register 8175instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ 8176 match(Set rdx (ModI rax div)); 8177 effect(KILL rax, KILL cr); 8178 8179 size(26); 8180 ins_cost(300); 8181 format %{ "CDQ\n\t" 8182 "IDIV $div" %} 8183 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8184 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8185 ins_pipe( ialu_reg_reg_alu0 ); 8186%} 8187 8188// Remainder Register Long 8189instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ 8190 match(Set dst (ModL src1 src2)); 8191 effect( KILL cr, KILL cx, KILL bx ); 8192 ins_cost(10000); 8193 format %{ "PUSH $src1.hi\n\t" 8194 "PUSH $src1.lo\n\t" 8195 "PUSH $src2.hi\n\t" 8196 "PUSH $src2.lo\n\t" 8197 "CALL SharedRuntime::lrem\n\t" 8198 "ADD ESP,16" %} 8199 ins_encode( long_mod(src1,src2) ); 8200 ins_pipe( pipe_slow ); 8201%} 8202 8203// Integer Shift Instructions 8204// Shift Left by one 8205instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8206 match(Set dst (LShiftI dst shift)); 8207 effect(KILL cr); 8208 8209 size(2); 8210 format %{ "SHL $dst,$shift" %} 8211 opcode(0xD1, 0x4); /* D1 /4 */ 8212 ins_encode( OpcP, RegOpc( dst ) ); 8213 ins_pipe( ialu_reg ); 8214%} 8215 8216// Shift Left by 8-bit immediate 8217instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8218 match(Set dst (LShiftI dst shift)); 8219 effect(KILL cr); 8220 8221 size(3); 8222 format %{ "SHL $dst,$shift" %} 8223 opcode(0xC1, 0x4); /* C1 /4 ib */ 8224 ins_encode( RegOpcImm( dst, shift) ); 8225 ins_pipe( ialu_reg ); 8226%} 8227 8228// Shift Left by variable 8229instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8230 match(Set dst (LShiftI dst shift)); 8231 effect(KILL cr); 8232 8233 size(2); 8234 format %{ "SHL $dst,$shift" %} 8235 opcode(0xD3, 0x4); /* D3 /4 */ 8236 ins_encode( OpcP, RegOpc( dst ) ); 8237 ins_pipe( ialu_reg_reg ); 8238%} 8239 8240// Arithmetic shift right by one 8241instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8242 match(Set dst (RShiftI dst shift)); 8243 effect(KILL cr); 8244 8245 size(2); 8246 format %{ "SAR $dst,$shift" %} 8247 opcode(0xD1, 0x7); /* D1 /7 */ 8248 ins_encode( OpcP, RegOpc( dst ) ); 8249 ins_pipe( ialu_reg ); 8250%} 8251 8252// Arithmetic shift right by one 8253instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ 8254 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); 8255 effect(KILL cr); 8256 format %{ "SAR $dst,$shift" %} 8257 opcode(0xD1, 0x7); /* D1 /7 */ 8258 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); 8259 ins_pipe( ialu_mem_imm ); 8260%} 8261 8262// Arithmetic Shift Right by 8-bit immediate 8263instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8264 match(Set dst (RShiftI dst shift)); 8265 effect(KILL cr); 8266 8267 size(3); 8268 format %{ "SAR $dst,$shift" %} 8269 opcode(0xC1, 0x7); /* C1 /7 ib */ 8270 ins_encode( RegOpcImm( dst, shift ) ); 8271 ins_pipe( ialu_mem_imm ); 8272%} 8273 8274// Arithmetic Shift Right by 8-bit immediate 8275instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ 8276 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); 8277 effect(KILL cr); 8278 8279 format %{ "SAR $dst,$shift" %} 8280 opcode(0xC1, 0x7); /* C1 /7 ib */ 8281 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); 8282 ins_pipe( ialu_mem_imm ); 8283%} 8284 8285// Arithmetic Shift Right by variable 8286instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8287 match(Set dst (RShiftI dst shift)); 8288 effect(KILL cr); 8289 8290 size(2); 8291 format %{ "SAR $dst,$shift" %} 8292 opcode(0xD3, 0x7); /* D3 /7 */ 8293 ins_encode( OpcP, RegOpc( dst ) ); 8294 ins_pipe( ialu_reg_reg ); 8295%} 8296 8297// Logical shift right by one 8298instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8299 match(Set dst (URShiftI dst shift)); 8300 effect(KILL cr); 8301 8302 size(2); 8303 format %{ "SHR $dst,$shift" %} 8304 opcode(0xD1, 0x5); /* D1 /5 */ 8305 ins_encode( OpcP, RegOpc( dst ) ); 8306 ins_pipe( ialu_reg ); 8307%} 8308 8309// Logical Shift Right by 8-bit immediate 8310instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8311 match(Set dst (URShiftI dst shift)); 8312 effect(KILL cr); 8313 8314 size(3); 8315 format %{ "SHR $dst,$shift" %} 8316 opcode(0xC1, 0x5); /* C1 /5 ib */ 8317 ins_encode( RegOpcImm( dst, shift) ); 8318 ins_pipe( ialu_reg ); 8319%} 8320 8321// Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. 8322// This idiom is used by the compiler for the i2b bytecode. 8323instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour, eFlagsReg cr) %{ 8324 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); 8325 effect(KILL cr); 8326 8327 size(3); 8328 format %{ "MOVSX $dst,$src :8" %} 8329 opcode(0xBE, 0x0F); 8330 ins_encode( OpcS, OpcP, RegReg( dst, src)); 8331 ins_pipe( ialu_reg_reg ); 8332%} 8333 8334// Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. 8335// This idiom is used by the compiler the i2s bytecode. 8336instruct i2s(eRegI dst, xRegI src, immI_16 sixteen, eFlagsReg cr) %{ 8337 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); 8338 effect(KILL cr); 8339 8340 size(3); 8341 format %{ "MOVSX $dst,$src :16" %} 8342 opcode(0xBF, 0x0F); 8343 ins_encode( OpcS, OpcP, RegReg( dst, src)); 8344 ins_pipe( ialu_reg_reg ); 8345%} 8346 8347 8348// Logical Shift Right by variable 8349instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8350 match(Set dst (URShiftI dst shift)); 8351 effect(KILL cr); 8352 8353 size(2); 8354 format %{ "SHR $dst,$shift" %} 8355 opcode(0xD3, 0x5); /* D3 /5 */ 8356 ins_encode( OpcP, RegOpc( dst ) ); 8357 ins_pipe( ialu_reg_reg ); 8358%} 8359 8360 8361//----------Logical Instructions----------------------------------------------- 8362//----------Integer Logical Instructions--------------------------------------- 8363// And Instructions 8364// And Register with Register 8365instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8366 match(Set dst (AndI dst src)); 8367 effect(KILL cr); 8368 8369 size(2); 8370 format %{ "AND $dst,$src" %} 8371 opcode(0x23); 8372 ins_encode( OpcP, RegReg( dst, src) ); 8373 ins_pipe( ialu_reg_reg ); 8374%} 8375 8376// And Register with Immediate 8377instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8378 match(Set dst (AndI dst src)); 8379 effect(KILL cr); 8380 8381 format %{ "AND $dst,$src" %} 8382 opcode(0x81,0x04); /* Opcode 81 /4 */ 8383 // ins_encode( RegImm( dst, src) ); 8384 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8385 ins_pipe( ialu_reg ); 8386%} 8387 8388// And Register with Memory 8389instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 8390 match(Set dst (AndI dst (LoadI src))); 8391 effect(KILL cr); 8392 8393 ins_cost(125); 8394 format %{ "AND $dst,$src" %} 8395 opcode(0x23); 8396 ins_encode( OpcP, RegMem( dst, src) ); 8397 ins_pipe( ialu_reg_mem ); 8398%} 8399 8400// And Memory with Register 8401instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 8402 match(Set dst (StoreI dst (AndI (LoadI dst) src))); 8403 effect(KILL cr); 8404 8405 ins_cost(150); 8406 format %{ "AND $dst,$src" %} 8407 opcode(0x21); /* Opcode 21 /r */ 8408 ins_encode( OpcP, RegMem( src, dst ) ); 8409 ins_pipe( ialu_mem_reg ); 8410%} 8411 8412// And Memory with Immediate 8413instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 8414 match(Set dst (StoreI dst (AndI (LoadI dst) src))); 8415 effect(KILL cr); 8416 8417 ins_cost(125); 8418 format %{ "AND $dst,$src" %} 8419 opcode(0x81, 0x4); /* Opcode 81 /4 id */ 8420 // ins_encode( MemImm( dst, src) ); 8421 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 8422 ins_pipe( ialu_mem_imm ); 8423%} 8424 8425// Or Instructions 8426// Or Register with Register 8427instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8428 match(Set dst (OrI dst src)); 8429 effect(KILL cr); 8430 8431 size(2); 8432 format %{ "OR $dst,$src" %} 8433 opcode(0x0B); 8434 ins_encode( OpcP, RegReg( dst, src) ); 8435 ins_pipe( ialu_reg_reg ); 8436%} 8437 8438// Or Register with Immediate 8439instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8440 match(Set dst (OrI dst src)); 8441 effect(KILL cr); 8442 8443 format %{ "OR $dst,$src" %} 8444 opcode(0x81,0x01); /* Opcode 81 /1 id */ 8445 // ins_encode( RegImm( dst, src) ); 8446 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8447 ins_pipe( ialu_reg ); 8448%} 8449 8450// Or Register with Memory 8451instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 8452 match(Set dst (OrI dst (LoadI src))); 8453 effect(KILL cr); 8454 8455 ins_cost(125); 8456 format %{ "OR $dst,$src" %} 8457 opcode(0x0B); 8458 ins_encode( OpcP, RegMem( dst, src) ); 8459 ins_pipe( ialu_reg_mem ); 8460%} 8461 8462// Or Memory with Register 8463instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 8464 match(Set dst (StoreI dst (OrI (LoadI dst) src))); 8465 effect(KILL cr); 8466 8467 ins_cost(150); 8468 format %{ "OR $dst,$src" %} 8469 opcode(0x09); /* Opcode 09 /r */ 8470 ins_encode( OpcP, RegMem( src, dst ) ); 8471 ins_pipe( ialu_mem_reg ); 8472%} 8473 8474// Or Memory with Immediate 8475instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 8476 match(Set dst (StoreI dst (OrI (LoadI dst) src))); 8477 effect(KILL cr); 8478 8479 ins_cost(125); 8480 format %{ "OR $dst,$src" %} 8481 opcode(0x81,0x1); /* Opcode 81 /1 id */ 8482 // ins_encode( MemImm( dst, src) ); 8483 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 8484 ins_pipe( ialu_mem_imm ); 8485%} 8486 8487// ROL/ROR 8488// ROL expand 8489instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8490 effect(USE_DEF dst, USE shift, KILL cr); 8491 8492 format %{ "ROL $dst, $shift" %} 8493 opcode(0xD1, 0x0); /* Opcode D1 /0 */ 8494 ins_encode( OpcP, RegOpc( dst )); 8495 ins_pipe( ialu_reg ); 8496%} 8497 8498instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8499 effect(USE_DEF dst, USE shift, KILL cr); 8500 8501 format %{ "ROL $dst, $shift" %} 8502 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ 8503 ins_encode( RegOpcImm(dst, shift) ); 8504 ins_pipe(ialu_reg); 8505%} 8506 8507instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8508 effect(USE_DEF dst, USE shift, KILL cr); 8509 8510 format %{ "ROL $dst, $shift" %} 8511 opcode(0xD3, 0x0); /* Opcode D3 /0 */ 8512 ins_encode(OpcP, RegOpc(dst)); 8513 ins_pipe( ialu_reg_reg ); 8514%} 8515// end of ROL expand 8516 8517// ROL 32bit by one once 8518instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ 8519 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); 8520 8521 expand %{ 8522 rolI_eReg_imm1(dst, lshift, cr); 8523 %} 8524%} 8525 8526// ROL 32bit var by imm8 once 8527instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ 8528 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8529 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); 8530 8531 expand %{ 8532 rolI_eReg_imm8(dst, lshift, cr); 8533 %} 8534%} 8535 8536// ROL 32bit var by var once 8537instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ 8538 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); 8539 8540 expand %{ 8541 rolI_eReg_CL(dst, shift, cr); 8542 %} 8543%} 8544 8545// ROL 32bit var by var once 8546instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ 8547 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); 8548 8549 expand %{ 8550 rolI_eReg_CL(dst, shift, cr); 8551 %} 8552%} 8553 8554// ROR expand 8555instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8556 effect(USE_DEF dst, USE shift, KILL cr); 8557 8558 format %{ "ROR $dst, $shift" %} 8559 opcode(0xD1,0x1); /* Opcode D1 /1 */ 8560 ins_encode( OpcP, RegOpc( dst ) ); 8561 ins_pipe( ialu_reg ); 8562%} 8563 8564instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8565 effect (USE_DEF dst, USE shift, KILL cr); 8566 8567 format %{ "ROR $dst, $shift" %} 8568 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ 8569 ins_encode( RegOpcImm(dst, shift) ); 8570 ins_pipe( ialu_reg ); 8571%} 8572 8573instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ 8574 effect(USE_DEF dst, USE shift, KILL cr); 8575 8576 format %{ "ROR $dst, $shift" %} 8577 opcode(0xD3, 0x1); /* Opcode D3 /1 */ 8578 ins_encode(OpcP, RegOpc(dst)); 8579 ins_pipe( ialu_reg_reg ); 8580%} 8581// end of ROR expand 8582 8583// ROR right once 8584instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ 8585 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); 8586 8587 expand %{ 8588 rorI_eReg_imm1(dst, rshift, cr); 8589 %} 8590%} 8591 8592// ROR 32bit by immI8 once 8593instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ 8594 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8595 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); 8596 8597 expand %{ 8598 rorI_eReg_imm8(dst, rshift, cr); 8599 %} 8600%} 8601 8602// ROR 32bit var by var once 8603instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ 8604 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); 8605 8606 expand %{ 8607 rorI_eReg_CL(dst, shift, cr); 8608 %} 8609%} 8610 8611// ROR 32bit var by var once 8612instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ 8613 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); 8614 8615 expand %{ 8616 rorI_eReg_CL(dst, shift, cr); 8617 %} 8618%} 8619 8620// Xor Instructions 8621// Xor Register with Register 8622instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8623 match(Set dst (XorI dst src)); 8624 effect(KILL cr); 8625 8626 size(2); 8627 format %{ "XOR $dst,$src" %} 8628 opcode(0x33); 8629 ins_encode( OpcP, RegReg( dst, src) ); 8630 ins_pipe( ialu_reg_reg ); 8631%} 8632 8633// Xor Register with Immediate 8634instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8635 match(Set dst (XorI dst src)); 8636 effect(KILL cr); 8637 8638 format %{ "XOR $dst,$src" %} 8639 opcode(0x81,0x06); /* Opcode 81 /6 id */ 8640 // ins_encode( RegImm( dst, src) ); 8641 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8642 ins_pipe( ialu_reg ); 8643%} 8644 8645// Xor Register with Memory 8646instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 8647 match(Set dst (XorI dst (LoadI src))); 8648 effect(KILL cr); 8649 8650 ins_cost(125); 8651 format %{ "XOR $dst,$src" %} 8652 opcode(0x33); 8653 ins_encode( OpcP, RegMem(dst, src) ); 8654 ins_pipe( ialu_reg_mem ); 8655%} 8656 8657// Xor Memory with Register 8658instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 8659 match(Set dst (StoreI dst (XorI (LoadI dst) src))); 8660 effect(KILL cr); 8661 8662 ins_cost(150); 8663 format %{ "XOR $dst,$src" %} 8664 opcode(0x31); /* Opcode 31 /r */ 8665 ins_encode( OpcP, RegMem( src, dst ) ); 8666 ins_pipe( ialu_mem_reg ); 8667%} 8668 8669// Xor Memory with Immediate 8670instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 8671 match(Set dst (StoreI dst (XorI (LoadI dst) src))); 8672 effect(KILL cr); 8673 8674 ins_cost(125); 8675 format %{ "XOR $dst,$src" %} 8676 opcode(0x81,0x6); /* Opcode 81 /6 id */ 8677 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 8678 ins_pipe( ialu_mem_imm ); 8679%} 8680 8681//----------Convert Int to Boolean--------------------------------------------- 8682 8683instruct movI_nocopy(eRegI dst, eRegI src) %{ 8684 effect( DEF dst, USE src ); 8685 format %{ "MOV $dst,$src" %} 8686 ins_encode( enc_Copy( dst, src) ); 8687 ins_pipe( ialu_reg_reg ); 8688%} 8689 8690instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{ 8691 effect( USE_DEF dst, USE src, KILL cr ); 8692 8693 size(4); 8694 format %{ "NEG $dst\n\t" 8695 "ADC $dst,$src" %} 8696 ins_encode( neg_reg(dst), 8697 OpcRegReg(0x13,dst,src) ); 8698 ins_pipe( ialu_reg_reg_long ); 8699%} 8700 8701instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{ 8702 match(Set dst (Conv2B src)); 8703 8704 expand %{ 8705 movI_nocopy(dst,src); 8706 ci2b(dst,src,cr); 8707 %} 8708%} 8709 8710instruct movP_nocopy(eRegI dst, eRegP src) %{ 8711 effect( DEF dst, USE src ); 8712 format %{ "MOV $dst,$src" %} 8713 ins_encode( enc_Copy( dst, src) ); 8714 ins_pipe( ialu_reg_reg ); 8715%} 8716 8717instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{ 8718 effect( USE_DEF dst, USE src, KILL cr ); 8719 format %{ "NEG $dst\n\t" 8720 "ADC $dst,$src" %} 8721 ins_encode( neg_reg(dst), 8722 OpcRegReg(0x13,dst,src) ); 8723 ins_pipe( ialu_reg_reg_long ); 8724%} 8725 8726instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{ 8727 match(Set dst (Conv2B src)); 8728 8729 expand %{ 8730 movP_nocopy(dst,src); 8731 cp2b(dst,src,cr); 8732 %} 8733%} 8734 8735instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{ 8736 match(Set dst (CmpLTMask p q)); 8737 effect( KILL cr ); 8738 ins_cost(400); 8739 8740 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination 8741 format %{ "XOR $dst,$dst\n\t" 8742 "CMP $p,$q\n\t" 8743 "SETlt $dst\n\t" 8744 "NEG $dst" %} 8745 ins_encode( OpcRegReg(0x33,dst,dst), 8746 OpcRegReg(0x3B,p,q), 8747 setLT_reg(dst), neg_reg(dst) ); 8748 ins_pipe( pipe_slow ); 8749%} 8750 8751instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{ 8752 match(Set dst (CmpLTMask dst zero)); 8753 effect( DEF dst, KILL cr ); 8754 ins_cost(100); 8755 8756 format %{ "SAR $dst,31" %} 8757 opcode(0xC1, 0x7); /* C1 /7 ib */ 8758 ins_encode( RegOpcImm( dst, 0x1F ) ); 8759 ins_pipe( ialu_reg ); 8760%} 8761 8762 8763instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{ 8764 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 8765 effect( KILL tmp, KILL cr ); 8766 ins_cost(400); 8767 // annoyingly, $tmp has no edges so you cant ask for it in 8768 // any format or encoding 8769 format %{ "SUB $p,$q\n\t" 8770 "SBB ECX,ECX\n\t" 8771 "AND ECX,$y\n\t" 8772 "ADD $p,ECX" %} 8773 ins_encode( enc_cmpLTP(p,q,y,tmp) ); 8774 ins_pipe( pipe_cmplt ); 8775%} 8776 8777/* If I enable this, I encourage spilling in the inner loop of compress. 8778instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{ 8779 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); 8780 effect( USE_KILL tmp, KILL cr ); 8781 ins_cost(400); 8782 8783 format %{ "SUB $p,$q\n\t" 8784 "SBB ECX,ECX\n\t" 8785 "AND ECX,$y\n\t" 8786 "ADD $p,ECX" %} 8787 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); 8788%} 8789*/ 8790 8791//----------Long Instructions------------------------------------------------ 8792// Add Long Register with Register 8793instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 8794 match(Set dst (AddL dst src)); 8795 effect(KILL cr); 8796 ins_cost(200); 8797 format %{ "ADD $dst.lo,$src.lo\n\t" 8798 "ADC $dst.hi,$src.hi" %} 8799 opcode(0x03, 0x13); 8800 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); 8801 ins_pipe( ialu_reg_reg_long ); 8802%} 8803 8804// Add Long Register with Immediate 8805instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 8806 match(Set dst (AddL dst src)); 8807 effect(KILL cr); 8808 format %{ "ADD $dst.lo,$src.lo\n\t" 8809 "ADC $dst.hi,$src.hi" %} 8810 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ 8811 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 8812 ins_pipe( ialu_reg_long ); 8813%} 8814 8815// Add Long Register with Memory 8816instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 8817 match(Set dst (AddL dst (LoadL mem))); 8818 effect(KILL cr); 8819 ins_cost(125); 8820 format %{ "ADD $dst.lo,$mem\n\t" 8821 "ADC $dst.hi,$mem+4" %} 8822 opcode(0x03, 0x13); 8823 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 8824 ins_pipe( ialu_reg_long_mem ); 8825%} 8826 8827// Subtract Long Register with Register. 8828instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 8829 match(Set dst (SubL dst src)); 8830 effect(KILL cr); 8831 ins_cost(200); 8832 format %{ "SUB $dst.lo,$src.lo\n\t" 8833 "SBB $dst.hi,$src.hi" %} 8834 opcode(0x2B, 0x1B); 8835 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); 8836 ins_pipe( ialu_reg_reg_long ); 8837%} 8838 8839// Subtract Long Register with Immediate 8840instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 8841 match(Set dst (SubL dst src)); 8842 effect(KILL cr); 8843 format %{ "SUB $dst.lo,$src.lo\n\t" 8844 "SBB $dst.hi,$src.hi" %} 8845 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ 8846 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 8847 ins_pipe( ialu_reg_long ); 8848%} 8849 8850// Subtract Long Register with Memory 8851instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 8852 match(Set dst (SubL dst (LoadL mem))); 8853 effect(KILL cr); 8854 ins_cost(125); 8855 format %{ "SUB $dst.lo,$mem\n\t" 8856 "SBB $dst.hi,$mem+4" %} 8857 opcode(0x2B, 0x1B); 8858 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 8859 ins_pipe( ialu_reg_long_mem ); 8860%} 8861 8862instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ 8863 match(Set dst (SubL zero dst)); 8864 effect(KILL cr); 8865 ins_cost(300); 8866 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} 8867 ins_encode( neg_long(dst) ); 8868 ins_pipe( ialu_reg_reg_long ); 8869%} 8870 8871// And Long Register with Register 8872instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 8873 match(Set dst (AndL dst src)); 8874 effect(KILL cr); 8875 format %{ "AND $dst.lo,$src.lo\n\t" 8876 "AND $dst.hi,$src.hi" %} 8877 opcode(0x23,0x23); 8878 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 8879 ins_pipe( ialu_reg_reg_long ); 8880%} 8881 8882// And Long Register with Immediate 8883instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 8884 match(Set dst (AndL dst src)); 8885 effect(KILL cr); 8886 format %{ "AND $dst.lo,$src.lo\n\t" 8887 "AND $dst.hi,$src.hi" %} 8888 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ 8889 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 8890 ins_pipe( ialu_reg_long ); 8891%} 8892 8893// And Long Register with Memory 8894instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 8895 match(Set dst (AndL dst (LoadL mem))); 8896 effect(KILL cr); 8897 ins_cost(125); 8898 format %{ "AND $dst.lo,$mem\n\t" 8899 "AND $dst.hi,$mem+4" %} 8900 opcode(0x23, 0x23); 8901 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 8902 ins_pipe( ialu_reg_long_mem ); 8903%} 8904 8905// Or Long Register with Register 8906instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 8907 match(Set dst (OrL dst src)); 8908 effect(KILL cr); 8909 format %{ "OR $dst.lo,$src.lo\n\t" 8910 "OR $dst.hi,$src.hi" %} 8911 opcode(0x0B,0x0B); 8912 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 8913 ins_pipe( ialu_reg_reg_long ); 8914%} 8915 8916// Or Long Register with Immediate 8917instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 8918 match(Set dst (OrL dst src)); 8919 effect(KILL cr); 8920 format %{ "OR $dst.lo,$src.lo\n\t" 8921 "OR $dst.hi,$src.hi" %} 8922 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ 8923 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 8924 ins_pipe( ialu_reg_long ); 8925%} 8926 8927// Or Long Register with Memory 8928instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 8929 match(Set dst (OrL dst (LoadL mem))); 8930 effect(KILL cr); 8931 ins_cost(125); 8932 format %{ "OR $dst.lo,$mem\n\t" 8933 "OR $dst.hi,$mem+4" %} 8934 opcode(0x0B,0x0B); 8935 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 8936 ins_pipe( ialu_reg_long_mem ); 8937%} 8938 8939// Xor Long Register with Register 8940instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 8941 match(Set dst (XorL dst src)); 8942 effect(KILL cr); 8943 format %{ "XOR $dst.lo,$src.lo\n\t" 8944 "XOR $dst.hi,$src.hi" %} 8945 opcode(0x33,0x33); 8946 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 8947 ins_pipe( ialu_reg_reg_long ); 8948%} 8949 8950// Xor Long Register with Immediate 8951instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 8952 match(Set dst (XorL dst src)); 8953 effect(KILL cr); 8954 format %{ "XOR $dst.lo,$src.lo\n\t" 8955 "XOR $dst.hi,$src.hi" %} 8956 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ 8957 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 8958 ins_pipe( ialu_reg_long ); 8959%} 8960 8961// Xor Long Register with Memory 8962instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 8963 match(Set dst (XorL dst (LoadL mem))); 8964 effect(KILL cr); 8965 ins_cost(125); 8966 format %{ "XOR $dst.lo,$mem\n\t" 8967 "XOR $dst.hi,$mem+4" %} 8968 opcode(0x33,0x33); 8969 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 8970 ins_pipe( ialu_reg_long_mem ); 8971%} 8972 8973// Shift Left Long by 1 8974instruct shlL_eReg_1(eRegL dst, immI_1 cnt, eFlagsReg cr) %{ 8975 predicate(UseNewLongLShift); 8976 match(Set dst (LShiftL dst cnt)); 8977 effect(KILL cr); 8978 ins_cost(100); 8979 format %{ "ADD $dst.lo,$dst.lo\n\t" 8980 "ADC $dst.hi,$dst.hi" %} 8981 ins_encode %{ 8982 __ addl($dst$$Register,$dst$$Register); 8983 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 8984 %} 8985 ins_pipe( ialu_reg_long ); 8986%} 8987 8988// Shift Left Long by 2 8989instruct shlL_eReg_2(eRegL dst, immI_2 cnt, eFlagsReg cr) %{ 8990 predicate(UseNewLongLShift); 8991 match(Set dst (LShiftL dst cnt)); 8992 effect(KILL cr); 8993 ins_cost(100); 8994 format %{ "ADD $dst.lo,$dst.lo\n\t" 8995 "ADC $dst.hi,$dst.hi\n\t" 8996 "ADD $dst.lo,$dst.lo\n\t" 8997 "ADC $dst.hi,$dst.hi" %} 8998 ins_encode %{ 8999 __ addl($dst$$Register,$dst$$Register); 9000 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9001 __ addl($dst$$Register,$dst$$Register); 9002 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9003 %} 9004 ins_pipe( ialu_reg_long ); 9005%} 9006 9007// Shift Left Long by 3 9008instruct shlL_eReg_3(eRegL dst, immI_3 cnt, eFlagsReg cr) %{ 9009 predicate(UseNewLongLShift); 9010 match(Set dst (LShiftL dst cnt)); 9011 effect(KILL cr); 9012 ins_cost(100); 9013 format %{ "ADD $dst.lo,$dst.lo\n\t" 9014 "ADC $dst.hi,$dst.hi\n\t" 9015 "ADD $dst.lo,$dst.lo\n\t" 9016 "ADC $dst.hi,$dst.hi\n\t" 9017 "ADD $dst.lo,$dst.lo\n\t" 9018 "ADC $dst.hi,$dst.hi" %} 9019 ins_encode %{ 9020 __ addl($dst$$Register,$dst$$Register); 9021 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9022 __ addl($dst$$Register,$dst$$Register); 9023 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9024 __ addl($dst$$Register,$dst$$Register); 9025 __ adcl(HIGH_FROM_LOW($dst$$Register),HIGH_FROM_LOW($dst$$Register)); 9026 %} 9027 ins_pipe( ialu_reg_long ); 9028%} 9029 9030// Shift Left Long by 1-31 9031instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 9032 match(Set dst (LShiftL dst cnt)); 9033 effect(KILL cr); 9034 ins_cost(200); 9035 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" 9036 "SHL $dst.lo,$cnt" %} 9037 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ 9038 ins_encode( move_long_small_shift(dst,cnt) ); 9039 ins_pipe( ialu_reg_long ); 9040%} 9041 9042// Shift Left Long by 32-63 9043instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 9044 match(Set dst (LShiftL dst cnt)); 9045 effect(KILL cr); 9046 ins_cost(300); 9047 format %{ "MOV $dst.hi,$dst.lo\n" 9048 "\tSHL $dst.hi,$cnt-32\n" 9049 "\tXOR $dst.lo,$dst.lo" %} 9050 opcode(0xC1, 0x4); /* C1 /4 ib */ 9051 ins_encode( move_long_big_shift_clr(dst,cnt) ); 9052 ins_pipe( ialu_reg_long ); 9053%} 9054 9055// Shift Left Long by variable 9056instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 9057 match(Set dst (LShiftL dst shift)); 9058 effect(KILL cr); 9059 ins_cost(500+200); 9060 size(17); 9061 format %{ "TEST $shift,32\n\t" 9062 "JEQ,s small\n\t" 9063 "MOV $dst.hi,$dst.lo\n\t" 9064 "XOR $dst.lo,$dst.lo\n" 9065 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" 9066 "SHL $dst.lo,$shift" %} 9067 ins_encode( shift_left_long( dst, shift ) ); 9068 ins_pipe( pipe_slow ); 9069%} 9070 9071// Shift Right Long by 1-31 9072instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 9073 match(Set dst (URShiftL dst cnt)); 9074 effect(KILL cr); 9075 ins_cost(200); 9076 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" 9077 "SHR $dst.hi,$cnt" %} 9078 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ 9079 ins_encode( move_long_small_shift(dst,cnt) ); 9080 ins_pipe( ialu_reg_long ); 9081%} 9082 9083// Shift Right Long by 32-63 9084instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 9085 match(Set dst (URShiftL dst cnt)); 9086 effect(KILL cr); 9087 ins_cost(300); 9088 format %{ "MOV $dst.lo,$dst.hi\n" 9089 "\tSHR $dst.lo,$cnt-32\n" 9090 "\tXOR $dst.hi,$dst.hi" %} 9091 opcode(0xC1, 0x5); /* C1 /5 ib */ 9092 ins_encode( move_long_big_shift_clr(dst,cnt) ); 9093 ins_pipe( ialu_reg_long ); 9094%} 9095 9096// Shift Right Long by variable 9097instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 9098 match(Set dst (URShiftL dst shift)); 9099 effect(KILL cr); 9100 ins_cost(600); 9101 size(17); 9102 format %{ "TEST $shift,32\n\t" 9103 "JEQ,s small\n\t" 9104 "MOV $dst.lo,$dst.hi\n\t" 9105 "XOR $dst.hi,$dst.hi\n" 9106 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" 9107 "SHR $dst.hi,$shift" %} 9108 ins_encode( shift_right_long( dst, shift ) ); 9109 ins_pipe( pipe_slow ); 9110%} 9111 9112// Shift Right Long by 1-31 9113instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 9114 match(Set dst (RShiftL dst cnt)); 9115 effect(KILL cr); 9116 ins_cost(200); 9117 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" 9118 "SAR $dst.hi,$cnt" %} 9119 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ 9120 ins_encode( move_long_small_shift(dst,cnt) ); 9121 ins_pipe( ialu_reg_long ); 9122%} 9123 9124// Shift Right Long by 32-63 9125instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 9126 match(Set dst (RShiftL dst cnt)); 9127 effect(KILL cr); 9128 ins_cost(300); 9129 format %{ "MOV $dst.lo,$dst.hi\n" 9130 "\tSAR $dst.lo,$cnt-32\n" 9131 "\tSAR $dst.hi,31" %} 9132 opcode(0xC1, 0x7); /* C1 /7 ib */ 9133 ins_encode( move_long_big_shift_sign(dst,cnt) ); 9134 ins_pipe( ialu_reg_long ); 9135%} 9136 9137// Shift Right arithmetic Long by variable 9138instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 9139 match(Set dst (RShiftL dst shift)); 9140 effect(KILL cr); 9141 ins_cost(600); 9142 size(18); 9143 format %{ "TEST $shift,32\n\t" 9144 "JEQ,s small\n\t" 9145 "MOV $dst.lo,$dst.hi\n\t" 9146 "SAR $dst.hi,31\n" 9147 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" 9148 "SAR $dst.hi,$shift" %} 9149 ins_encode( shift_right_arith_long( dst, shift ) ); 9150 ins_pipe( pipe_slow ); 9151%} 9152 9153 9154//----------Double Instructions------------------------------------------------ 9155// Double Math 9156 9157// Compare & branch 9158 9159// P6 version of float compare, sets condition codes in EFLAGS 9160instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{ 9161 predicate(VM_Version::supports_cmov() && UseSSE <=1); 9162 match(Set cr (CmpD src1 src2)); 9163 effect(KILL rax); 9164 ins_cost(150); 9165 format %{ "FLD $src1\n\t" 9166 "FUCOMIP ST,$src2 // P6 instruction\n\t" 9167 "JNP exit\n\t" 9168 "MOV ah,1 // saw a NaN, set CF\n\t" 9169 "SAHF\n" 9170 "exit:\tNOP // avoid branch to branch" %} 9171 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 9172 ins_encode( Push_Reg_D(src1), 9173 OpcP, RegOpc(src2), 9174 cmpF_P6_fixup ); 9175 ins_pipe( pipe_slow ); 9176%} 9177 9178// Compare & branch 9179instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{ 9180 predicate(UseSSE<=1); 9181 match(Set cr (CmpD src1 src2)); 9182 effect(KILL rax); 9183 ins_cost(200); 9184 format %{ "FLD $src1\n\t" 9185 "FCOMp $src2\n\t" 9186 "FNSTSW AX\n\t" 9187 "TEST AX,0x400\n\t" 9188 "JZ,s flags\n\t" 9189 "MOV AH,1\t# unordered treat as LT\n" 9190 "flags:\tSAHF" %} 9191 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 9192 ins_encode( Push_Reg_D(src1), 9193 OpcP, RegOpc(src2), 9194 fpu_flags); 9195 ins_pipe( pipe_slow ); 9196%} 9197 9198// Compare vs zero into -1,0,1 9199instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{ 9200 predicate(UseSSE<=1); 9201 match(Set dst (CmpD3 src1 zero)); 9202 effect(KILL cr, KILL rax); 9203 ins_cost(280); 9204 format %{ "FTSTD $dst,$src1" %} 9205 opcode(0xE4, 0xD9); 9206 ins_encode( Push_Reg_D(src1), 9207 OpcS, OpcP, PopFPU, 9208 CmpF_Result(dst)); 9209 ins_pipe( pipe_slow ); 9210%} 9211 9212// Compare into -1,0,1 9213instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{ 9214 predicate(UseSSE<=1); 9215 match(Set dst (CmpD3 src1 src2)); 9216 effect(KILL cr, KILL rax); 9217 ins_cost(300); 9218 format %{ "FCMPD $dst,$src1,$src2" %} 9219 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 9220 ins_encode( Push_Reg_D(src1), 9221 OpcP, RegOpc(src2), 9222 CmpF_Result(dst)); 9223 ins_pipe( pipe_slow ); 9224%} 9225 9226// float compare and set condition codes in EFLAGS by XMM regs 9227instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{ 9228 predicate(UseSSE>=2); 9229 match(Set cr (CmpD dst src)); 9230 effect(KILL rax); 9231 ins_cost(125); 9232 format %{ "COMISD $dst,$src\n" 9233 "\tJNP exit\n" 9234 "\tMOV ah,1 // saw a NaN, set CF\n" 9235 "\tSAHF\n" 9236 "exit:\tNOP // avoid branch to branch" %} 9237 opcode(0x66, 0x0F, 0x2F); 9238 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup); 9239 ins_pipe( pipe_slow ); 9240%} 9241 9242// float compare and set condition codes in EFLAGS by XMM regs 9243instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{ 9244 predicate(UseSSE>=2); 9245 match(Set cr (CmpD dst (LoadD src))); 9246 effect(KILL rax); 9247 ins_cost(145); 9248 format %{ "COMISD $dst,$src\n" 9249 "\tJNP exit\n" 9250 "\tMOV ah,1 // saw a NaN, set CF\n" 9251 "\tSAHF\n" 9252 "exit:\tNOP // avoid branch to branch" %} 9253 opcode(0x66, 0x0F, 0x2F); 9254 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup); 9255 ins_pipe( pipe_slow ); 9256%} 9257 9258// Compare into -1,0,1 in XMM 9259instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{ 9260 predicate(UseSSE>=2); 9261 match(Set dst (CmpD3 src1 src2)); 9262 effect(KILL cr); 9263 ins_cost(255); 9264 format %{ "XOR $dst,$dst\n" 9265 "\tCOMISD $src1,$src2\n" 9266 "\tJP,s nan\n" 9267 "\tJEQ,s exit\n" 9268 "\tJA,s inc\n" 9269 "nan:\tDEC $dst\n" 9270 "\tJMP,s exit\n" 9271 "inc:\tINC $dst\n" 9272 "exit:" 9273 %} 9274 opcode(0x66, 0x0F, 0x2F); 9275 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2), 9276 CmpX_Result(dst)); 9277 ins_pipe( pipe_slow ); 9278%} 9279 9280// Compare into -1,0,1 in XMM and memory 9281instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{ 9282 predicate(UseSSE>=2); 9283 match(Set dst (CmpD3 src1 (LoadD mem))); 9284 effect(KILL cr); 9285 ins_cost(275); 9286 format %{ "COMISD $src1,$mem\n" 9287 "\tMOV $dst,0\t\t# do not blow flags\n" 9288 "\tJP,s nan\n" 9289 "\tJEQ,s exit\n" 9290 "\tJA,s inc\n" 9291 "nan:\tDEC $dst\n" 9292 "\tJMP,s exit\n" 9293 "inc:\tINC $dst\n" 9294 "exit:" 9295 %} 9296 opcode(0x66, 0x0F, 0x2F); 9297 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem), 9298 LdImmI(dst,0x0), CmpX_Result(dst)); 9299 ins_pipe( pipe_slow ); 9300%} 9301 9302 9303instruct subD_reg(regD dst, regD src) %{ 9304 predicate (UseSSE <=1); 9305 match(Set dst (SubD dst src)); 9306 9307 format %{ "FLD $src\n\t" 9308 "DSUBp $dst,ST" %} 9309 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ 9310 ins_cost(150); 9311 ins_encode( Push_Reg_D(src), 9312 OpcP, RegOpc(dst) ); 9313 ins_pipe( fpu_reg_reg ); 9314%} 9315 9316instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{ 9317 predicate (UseSSE <=1); 9318 match(Set dst (RoundDouble (SubD src1 src2))); 9319 ins_cost(250); 9320 9321 format %{ "FLD $src2\n\t" 9322 "DSUB ST,$src1\n\t" 9323 "FSTP_D $dst\t# D-round" %} 9324 opcode(0xD8, 0x5); 9325 ins_encode( Push_Reg_D(src2), 9326 OpcP, RegOpc(src1), Pop_Mem_D(dst) ); 9327 ins_pipe( fpu_mem_reg_reg ); 9328%} 9329 9330 9331instruct subD_reg_mem(regD dst, memory src) %{ 9332 predicate (UseSSE <=1); 9333 match(Set dst (SubD dst (LoadD src))); 9334 ins_cost(150); 9335 9336 format %{ "FLD $src\n\t" 9337 "DSUBp $dst,ST" %} 9338 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ 9339 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 9340 OpcP, RegOpc(dst) ); 9341 ins_pipe( fpu_reg_mem ); 9342%} 9343 9344instruct absD_reg(regDPR1 dst, regDPR1 src) %{ 9345 predicate (UseSSE<=1); 9346 match(Set dst (AbsD src)); 9347 ins_cost(100); 9348 format %{ "FABS" %} 9349 opcode(0xE1, 0xD9); 9350 ins_encode( OpcS, OpcP ); 9351 ins_pipe( fpu_reg_reg ); 9352%} 9353 9354instruct absXD_reg( regXD dst ) %{ 9355 predicate(UseSSE>=2); 9356 match(Set dst (AbsD dst)); 9357 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %} 9358 ins_encode( AbsXD_encoding(dst)); 9359 ins_pipe( pipe_slow ); 9360%} 9361 9362instruct negD_reg(regDPR1 dst, regDPR1 src) %{ 9363 predicate(UseSSE<=1); 9364 match(Set dst (NegD src)); 9365 ins_cost(100); 9366 format %{ "FCHS" %} 9367 opcode(0xE0, 0xD9); 9368 ins_encode( OpcS, OpcP ); 9369 ins_pipe( fpu_reg_reg ); 9370%} 9371 9372instruct negXD_reg( regXD dst ) %{ 9373 predicate(UseSSE>=2); 9374 match(Set dst (NegD dst)); 9375 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %} 9376 ins_encode %{ 9377 __ xorpd($dst$$XMMRegister, 9378 ExternalAddress((address)double_signflip_pool)); 9379 %} 9380 ins_pipe( pipe_slow ); 9381%} 9382 9383instruct addD_reg(regD dst, regD src) %{ 9384 predicate(UseSSE<=1); 9385 match(Set dst (AddD dst src)); 9386 format %{ "FLD $src\n\t" 9387 "DADD $dst,ST" %} 9388 size(4); 9389 ins_cost(150); 9390 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ 9391 ins_encode( Push_Reg_D(src), 9392 OpcP, RegOpc(dst) ); 9393 ins_pipe( fpu_reg_reg ); 9394%} 9395 9396 9397instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{ 9398 predicate(UseSSE<=1); 9399 match(Set dst (RoundDouble (AddD src1 src2))); 9400 ins_cost(250); 9401 9402 format %{ "FLD $src2\n\t" 9403 "DADD ST,$src1\n\t" 9404 "FSTP_D $dst\t# D-round" %} 9405 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ 9406 ins_encode( Push_Reg_D(src2), 9407 OpcP, RegOpc(src1), Pop_Mem_D(dst) ); 9408 ins_pipe( fpu_mem_reg_reg ); 9409%} 9410 9411 9412instruct addD_reg_mem(regD dst, memory src) %{ 9413 predicate(UseSSE<=1); 9414 match(Set dst (AddD dst (LoadD src))); 9415 ins_cost(150); 9416 9417 format %{ "FLD $src\n\t" 9418 "DADDp $dst,ST" %} 9419 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ 9420 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 9421 OpcP, RegOpc(dst) ); 9422 ins_pipe( fpu_reg_mem ); 9423%} 9424 9425// add-to-memory 9426instruct addD_mem_reg(memory dst, regD src) %{ 9427 predicate(UseSSE<=1); 9428 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); 9429 ins_cost(150); 9430 9431 format %{ "FLD_D $dst\n\t" 9432 "DADD ST,$src\n\t" 9433 "FST_D $dst" %} 9434 opcode(0xDD, 0x0); 9435 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), 9436 Opcode(0xD8), RegOpc(src), 9437 set_instruction_start, 9438 Opcode(0xDD), RMopc_Mem(0x03,dst) ); 9439 ins_pipe( fpu_reg_mem ); 9440%} 9441 9442instruct addD_reg_imm1(regD dst, immD1 src) %{ 9443 predicate(UseSSE<=1); 9444 match(Set dst (AddD dst src)); 9445 ins_cost(125); 9446 format %{ "FLD1\n\t" 9447 "DADDp $dst,ST" %} 9448 opcode(0xDE, 0x00); 9449 ins_encode( LdImmD(src), 9450 OpcP, RegOpc(dst) ); 9451 ins_pipe( fpu_reg ); 9452%} 9453 9454instruct addD_reg_imm(regD dst, immD src) %{ 9455 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); 9456 match(Set dst (AddD dst src)); 9457 ins_cost(200); 9458 format %{ "FLD_D [$src]\n\t" 9459 "DADDp $dst,ST" %} 9460 opcode(0xDE, 0x00); /* DE /0 */ 9461 ins_encode( LdImmD(src), 9462 OpcP, RegOpc(dst)); 9463 ins_pipe( fpu_reg_mem ); 9464%} 9465 9466instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{ 9467 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); 9468 match(Set dst (RoundDouble (AddD src con))); 9469 ins_cost(200); 9470 format %{ "FLD_D [$con]\n\t" 9471 "DADD ST,$src\n\t" 9472 "FSTP_D $dst\t# D-round" %} 9473 opcode(0xD8, 0x00); /* D8 /0 */ 9474 ins_encode( LdImmD(con), 9475 OpcP, RegOpc(src), Pop_Mem_D(dst)); 9476 ins_pipe( fpu_mem_reg_con ); 9477%} 9478 9479// Add two double precision floating point values in xmm 9480instruct addXD_reg(regXD dst, regXD src) %{ 9481 predicate(UseSSE>=2); 9482 match(Set dst (AddD dst src)); 9483 format %{ "ADDSD $dst,$src" %} 9484 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src)); 9485 ins_pipe( pipe_slow ); 9486%} 9487 9488instruct addXD_imm(regXD dst, immXD con) %{ 9489 predicate(UseSSE>=2); 9490 match(Set dst (AddD dst con)); 9491 format %{ "ADDSD $dst,[$con]" %} 9492 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) ); 9493 ins_pipe( pipe_slow ); 9494%} 9495 9496instruct addXD_mem(regXD dst, memory mem) %{ 9497 predicate(UseSSE>=2); 9498 match(Set dst (AddD dst (LoadD mem))); 9499 format %{ "ADDSD $dst,$mem" %} 9500 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem)); 9501 ins_pipe( pipe_slow ); 9502%} 9503 9504// Sub two double precision floating point values in xmm 9505instruct subXD_reg(regXD dst, regXD src) %{ 9506 predicate(UseSSE>=2); 9507 match(Set dst (SubD dst src)); 9508 format %{ "SUBSD $dst,$src" %} 9509 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src)); 9510 ins_pipe( pipe_slow ); 9511%} 9512 9513instruct subXD_imm(regXD dst, immXD con) %{ 9514 predicate(UseSSE>=2); 9515 match(Set dst (SubD dst con)); 9516 format %{ "SUBSD $dst,[$con]" %} 9517 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) ); 9518 ins_pipe( pipe_slow ); 9519%} 9520 9521instruct subXD_mem(regXD dst, memory mem) %{ 9522 predicate(UseSSE>=2); 9523 match(Set dst (SubD dst (LoadD mem))); 9524 format %{ "SUBSD $dst,$mem" %} 9525 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem)); 9526 ins_pipe( pipe_slow ); 9527%} 9528 9529// Mul two double precision floating point values in xmm 9530instruct mulXD_reg(regXD dst, regXD src) %{ 9531 predicate(UseSSE>=2); 9532 match(Set dst (MulD dst src)); 9533 format %{ "MULSD $dst,$src" %} 9534 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src)); 9535 ins_pipe( pipe_slow ); 9536%} 9537 9538instruct mulXD_imm(regXD dst, immXD con) %{ 9539 predicate(UseSSE>=2); 9540 match(Set dst (MulD dst con)); 9541 format %{ "MULSD $dst,[$con]" %} 9542 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) ); 9543 ins_pipe( pipe_slow ); 9544%} 9545 9546instruct mulXD_mem(regXD dst, memory mem) %{ 9547 predicate(UseSSE>=2); 9548 match(Set dst (MulD dst (LoadD mem))); 9549 format %{ "MULSD $dst,$mem" %} 9550 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem)); 9551 ins_pipe( pipe_slow ); 9552%} 9553 9554// Div two double precision floating point values in xmm 9555instruct divXD_reg(regXD dst, regXD src) %{ 9556 predicate(UseSSE>=2); 9557 match(Set dst (DivD dst src)); 9558 format %{ "DIVSD $dst,$src" %} 9559 opcode(0xF2, 0x0F, 0x5E); 9560 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src)); 9561 ins_pipe( pipe_slow ); 9562%} 9563 9564instruct divXD_imm(regXD dst, immXD con) %{ 9565 predicate(UseSSE>=2); 9566 match(Set dst (DivD dst con)); 9567 format %{ "DIVSD $dst,[$con]" %} 9568 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con)); 9569 ins_pipe( pipe_slow ); 9570%} 9571 9572instruct divXD_mem(regXD dst, memory mem) %{ 9573 predicate(UseSSE>=2); 9574 match(Set dst (DivD dst (LoadD mem))); 9575 format %{ "DIVSD $dst,$mem" %} 9576 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem)); 9577 ins_pipe( pipe_slow ); 9578%} 9579 9580 9581instruct mulD_reg(regD dst, regD src) %{ 9582 predicate(UseSSE<=1); 9583 match(Set dst (MulD dst src)); 9584 format %{ "FLD $src\n\t" 9585 "DMULp $dst,ST" %} 9586 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ 9587 ins_cost(150); 9588 ins_encode( Push_Reg_D(src), 9589 OpcP, RegOpc(dst) ); 9590 ins_pipe( fpu_reg_reg ); 9591%} 9592 9593// Strict FP instruction biases argument before multiply then 9594// biases result to avoid double rounding of subnormals. 9595// 9596// scale arg1 by multiplying arg1 by 2^(-15360) 9597// load arg2 9598// multiply scaled arg1 by arg2 9599// rescale product by 2^(15360) 9600// 9601instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{ 9602 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); 9603 match(Set dst (MulD dst src)); 9604 ins_cost(1); // Select this instruction for all strict FP double multiplies 9605 9606 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" 9607 "DMULp $dst,ST\n\t" 9608 "FLD $src\n\t" 9609 "DMULp $dst,ST\n\t" 9610 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" 9611 "DMULp $dst,ST\n\t" %} 9612 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ 9613 ins_encode( strictfp_bias1(dst), 9614 Push_Reg_D(src), 9615 OpcP, RegOpc(dst), 9616 strictfp_bias2(dst) ); 9617 ins_pipe( fpu_reg_reg ); 9618%} 9619 9620instruct mulD_reg_imm(regD dst, immD src) %{ 9621 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); 9622 match(Set dst (MulD dst src)); 9623 ins_cost(200); 9624 format %{ "FLD_D [$src]\n\t" 9625 "DMULp $dst,ST" %} 9626 opcode(0xDE, 0x1); /* DE /1 */ 9627 ins_encode( LdImmD(src), 9628 OpcP, RegOpc(dst) ); 9629 ins_pipe( fpu_reg_mem ); 9630%} 9631 9632 9633instruct mulD_reg_mem(regD dst, memory src) %{ 9634 predicate( UseSSE<=1 ); 9635 match(Set dst (MulD dst (LoadD src))); 9636 ins_cost(200); 9637 format %{ "FLD_D $src\n\t" 9638 "DMULp $dst,ST" %} 9639 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ 9640 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 9641 OpcP, RegOpc(dst) ); 9642 ins_pipe( fpu_reg_mem ); 9643%} 9644 9645// 9646// Cisc-alternate to reg-reg multiply 9647instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{ 9648 predicate( UseSSE<=1 ); 9649 match(Set dst (MulD src (LoadD mem))); 9650 ins_cost(250); 9651 format %{ "FLD_D $mem\n\t" 9652 "DMUL ST,$src\n\t" 9653 "FSTP_D $dst" %} 9654 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ 9655 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), 9656 OpcReg_F(src), 9657 Pop_Reg_D(dst) ); 9658 ins_pipe( fpu_reg_reg_mem ); 9659%} 9660 9661 9662// MACRO3 -- addD a mulD 9663// This instruction is a '2-address' instruction in that the result goes 9664// back to src2. This eliminates a move from the macro; possibly the 9665// register allocator will have to add it back (and maybe not). 9666instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{ 9667 predicate( UseSSE<=1 ); 9668 match(Set src2 (AddD (MulD src0 src1) src2)); 9669 format %{ "FLD $src0\t# ===MACRO3d===\n\t" 9670 "DMUL ST,$src1\n\t" 9671 "DADDp $src2,ST" %} 9672 ins_cost(250); 9673 opcode(0xDD); /* LoadD DD /0 */ 9674 ins_encode( Push_Reg_F(src0), 9675 FMul_ST_reg(src1), 9676 FAddP_reg_ST(src2) ); 9677 ins_pipe( fpu_reg_reg_reg ); 9678%} 9679 9680 9681// MACRO3 -- subD a mulD 9682instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{ 9683 predicate( UseSSE<=1 ); 9684 match(Set src2 (SubD (MulD src0 src1) src2)); 9685 format %{ "FLD $src0\t# ===MACRO3d===\n\t" 9686 "DMUL ST,$src1\n\t" 9687 "DSUBRp $src2,ST" %} 9688 ins_cost(250); 9689 ins_encode( Push_Reg_F(src0), 9690 FMul_ST_reg(src1), 9691 Opcode(0xDE), Opc_plus(0xE0,src2)); 9692 ins_pipe( fpu_reg_reg_reg ); 9693%} 9694 9695 9696instruct divD_reg(regD dst, regD src) %{ 9697 predicate( UseSSE<=1 ); 9698 match(Set dst (DivD dst src)); 9699 9700 format %{ "FLD $src\n\t" 9701 "FDIVp $dst,ST" %} 9702 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 9703 ins_cost(150); 9704 ins_encode( Push_Reg_D(src), 9705 OpcP, RegOpc(dst) ); 9706 ins_pipe( fpu_reg_reg ); 9707%} 9708 9709// Strict FP instruction biases argument before division then 9710// biases result, to avoid double rounding of subnormals. 9711// 9712// scale dividend by multiplying dividend by 2^(-15360) 9713// load divisor 9714// divide scaled dividend by divisor 9715// rescale quotient by 2^(15360) 9716// 9717instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{ 9718 predicate (UseSSE<=1); 9719 match(Set dst (DivD dst src)); 9720 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); 9721 ins_cost(01); 9722 9723 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" 9724 "DMULp $dst,ST\n\t" 9725 "FLD $src\n\t" 9726 "FDIVp $dst,ST\n\t" 9727 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" 9728 "DMULp $dst,ST\n\t" %} 9729 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 9730 ins_encode( strictfp_bias1(dst), 9731 Push_Reg_D(src), 9732 OpcP, RegOpc(dst), 9733 strictfp_bias2(dst) ); 9734 ins_pipe( fpu_reg_reg ); 9735%} 9736 9737instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{ 9738 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); 9739 match(Set dst (RoundDouble (DivD src1 src2))); 9740 9741 format %{ "FLD $src1\n\t" 9742 "FDIV ST,$src2\n\t" 9743 "FSTP_D $dst\t# D-round" %} 9744 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ 9745 ins_encode( Push_Reg_D(src1), 9746 OpcP, RegOpc(src2), Pop_Mem_D(dst) ); 9747 ins_pipe( fpu_mem_reg_reg ); 9748%} 9749 9750 9751instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{ 9752 predicate(UseSSE<=1); 9753 match(Set dst (ModD dst src)); 9754 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS 9755 9756 format %{ "DMOD $dst,$src" %} 9757 ins_cost(250); 9758 ins_encode(Push_Reg_Mod_D(dst, src), 9759 emitModD(), 9760 Push_Result_Mod_D(src), 9761 Pop_Reg_D(dst)); 9762 ins_pipe( pipe_slow ); 9763%} 9764 9765instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{ 9766 predicate(UseSSE>=2); 9767 match(Set dst (ModD src0 src1)); 9768 effect(KILL rax, KILL cr); 9769 9770 format %{ "SUB ESP,8\t # DMOD\n" 9771 "\tMOVSD [ESP+0],$src1\n" 9772 "\tFLD_D [ESP+0]\n" 9773 "\tMOVSD [ESP+0],$src0\n" 9774 "\tFLD_D [ESP+0]\n" 9775 "loop:\tFPREM\n" 9776 "\tFWAIT\n" 9777 "\tFNSTSW AX\n" 9778 "\tSAHF\n" 9779 "\tJP loop\n" 9780 "\tFSTP_D [ESP+0]\n" 9781 "\tMOVSD $dst,[ESP+0]\n" 9782 "\tADD ESP,8\n" 9783 "\tFSTP ST0\t # Restore FPU Stack" 9784 %} 9785 ins_cost(250); 9786 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU); 9787 ins_pipe( pipe_slow ); 9788%} 9789 9790instruct sinD_reg(regDPR1 dst, regDPR1 src) %{ 9791 predicate (UseSSE<=1); 9792 match(Set dst (SinD src)); 9793 ins_cost(1800); 9794 format %{ "DSIN $dst" %} 9795 opcode(0xD9, 0xFE); 9796 ins_encode( OpcP, OpcS ); 9797 ins_pipe( pipe_slow ); 9798%} 9799 9800instruct sinXD_reg(regXD dst, eFlagsReg cr) %{ 9801 predicate (UseSSE>=2); 9802 match(Set dst (SinD dst)); 9803 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" 9804 ins_cost(1800); 9805 format %{ "DSIN $dst" %} 9806 opcode(0xD9, 0xFE); 9807 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); 9808 ins_pipe( pipe_slow ); 9809%} 9810 9811instruct cosD_reg(regDPR1 dst, regDPR1 src) %{ 9812 predicate (UseSSE<=1); 9813 match(Set dst (CosD src)); 9814 ins_cost(1800); 9815 format %{ "DCOS $dst" %} 9816 opcode(0xD9, 0xFF); 9817 ins_encode( OpcP, OpcS ); 9818 ins_pipe( pipe_slow ); 9819%} 9820 9821instruct cosXD_reg(regXD dst, eFlagsReg cr) %{ 9822 predicate (UseSSE>=2); 9823 match(Set dst (CosD dst)); 9824 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" 9825 ins_cost(1800); 9826 format %{ "DCOS $dst" %} 9827 opcode(0xD9, 0xFF); 9828 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); 9829 ins_pipe( pipe_slow ); 9830%} 9831 9832instruct tanD_reg(regDPR1 dst, regDPR1 src) %{ 9833 predicate (UseSSE<=1); 9834 match(Set dst(TanD src)); 9835 format %{ "DTAN $dst" %} 9836 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan 9837 Opcode(0xDD), Opcode(0xD8)); // fstp st 9838 ins_pipe( pipe_slow ); 9839%} 9840 9841instruct tanXD_reg(regXD dst, eFlagsReg cr) %{ 9842 predicate (UseSSE>=2); 9843 match(Set dst(TanD dst)); 9844 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" 9845 format %{ "DTAN $dst" %} 9846 ins_encode( Push_SrcXD(dst), 9847 Opcode(0xD9), Opcode(0xF2), // fptan 9848 Opcode(0xDD), Opcode(0xD8), // fstp st 9849 Push_ResultXD(dst) ); 9850 ins_pipe( pipe_slow ); 9851%} 9852 9853instruct atanD_reg(regD dst, regD src) %{ 9854 predicate (UseSSE<=1); 9855 match(Set dst(AtanD dst src)); 9856 format %{ "DATA $dst,$src" %} 9857 opcode(0xD9, 0xF3); 9858 ins_encode( Push_Reg_D(src), 9859 OpcP, OpcS, RegOpc(dst) ); 9860 ins_pipe( pipe_slow ); 9861%} 9862 9863instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{ 9864 predicate (UseSSE>=2); 9865 match(Set dst(AtanD dst src)); 9866 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" 9867 format %{ "DATA $dst,$src" %} 9868 opcode(0xD9, 0xF3); 9869 ins_encode( Push_SrcXD(src), 9870 OpcP, OpcS, Push_ResultXD(dst) ); 9871 ins_pipe( pipe_slow ); 9872%} 9873 9874instruct sqrtD_reg(regD dst, regD src) %{ 9875 predicate (UseSSE<=1); 9876 match(Set dst (SqrtD src)); 9877 format %{ "DSQRT $dst,$src" %} 9878 opcode(0xFA, 0xD9); 9879 ins_encode( Push_Reg_D(src), 9880 OpcS, OpcP, Pop_Reg_D(dst) ); 9881 ins_pipe( pipe_slow ); 9882%} 9883 9884instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ 9885 predicate (UseSSE<=1); 9886 match(Set Y (PowD X Y)); // Raise X to the Yth power 9887 effect(KILL rax, KILL rbx, KILL rcx); 9888 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" 9889 "FLD_D $X\n\t" 9890 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" 9891 9892 "FDUP \t\t\t# Q Q\n\t" 9893 "FRNDINT\t\t\t# int(Q) Q\n\t" 9894 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 9895 "FISTP dword [ESP]\n\t" 9896 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 9897 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 9898 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 9899 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 9900 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 9901 "ADD EAX,1023\t\t# Double exponent bias\n\t" 9902 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 9903 "SHL EAX,20\t\t# Shift exponent into place\n\t" 9904 "TEST EBX,ECX\t\t# Check for overflow\n\t" 9905 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 9906 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 9907 "MOV [ESP+0],0\n\t" 9908 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 9909 9910 "ADD ESP,8" 9911 %} 9912 ins_encode( push_stack_temp_qword, 9913 Push_Reg_D(X), 9914 Opcode(0xD9), Opcode(0xF1), // fyl2x 9915 pow_exp_core_encoding, 9916 pop_stack_temp_qword); 9917 ins_pipe( pipe_slow ); 9918%} 9919 9920instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{ 9921 predicate (UseSSE>=2); 9922 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power 9923 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx ); 9924 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" 9925 "MOVSD [ESP],$src1\n\t" 9926 "FLD FPR1,$src1\n\t" 9927 "MOVSD [ESP],$src0\n\t" 9928 "FLD FPR1,$src0\n\t" 9929 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" 9930 9931 "FDUP \t\t\t# Q Q\n\t" 9932 "FRNDINT\t\t\t# int(Q) Q\n\t" 9933 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 9934 "FISTP dword [ESP]\n\t" 9935 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 9936 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 9937 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 9938 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 9939 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 9940 "ADD EAX,1023\t\t# Double exponent bias\n\t" 9941 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 9942 "SHL EAX,20\t\t# Shift exponent into place\n\t" 9943 "TEST EBX,ECX\t\t# Check for overflow\n\t" 9944 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 9945 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 9946 "MOV [ESP+0],0\n\t" 9947 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 9948 9949 "FST_D [ESP]\n\t" 9950 "MOVSD $dst,[ESP]\n\t" 9951 "ADD ESP,8" 9952 %} 9953 ins_encode( push_stack_temp_qword, 9954 push_xmm_to_fpr1(src1), 9955 push_xmm_to_fpr1(src0), 9956 Opcode(0xD9), Opcode(0xF1), // fyl2x 9957 pow_exp_core_encoding, 9958 Push_ResultXD(dst) ); 9959 ins_pipe( pipe_slow ); 9960%} 9961 9962 9963instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ 9964 predicate (UseSSE<=1); 9965 match(Set dpr1 (ExpD dpr1)); 9966 effect(KILL rax, KILL rbx, KILL rcx); 9967 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding" 9968 "FLDL2E \t\t\t# Ld log2(e) X\n\t" 9969 "FMULP \t\t\t# Q=X*log2(e)\n\t" 9970 9971 "FDUP \t\t\t# Q Q\n\t" 9972 "FRNDINT\t\t\t# int(Q) Q\n\t" 9973 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 9974 "FISTP dword [ESP]\n\t" 9975 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 9976 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 9977 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 9978 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 9979 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 9980 "ADD EAX,1023\t\t# Double exponent bias\n\t" 9981 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 9982 "SHL EAX,20\t\t# Shift exponent into place\n\t" 9983 "TEST EBX,ECX\t\t# Check for overflow\n\t" 9984 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 9985 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 9986 "MOV [ESP+0],0\n\t" 9987 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 9988 9989 "ADD ESP,8" 9990 %} 9991 ins_encode( push_stack_temp_qword, 9992 Opcode(0xD9), Opcode(0xEA), // fldl2e 9993 Opcode(0xDE), Opcode(0xC9), // fmulp 9994 pow_exp_core_encoding, 9995 pop_stack_temp_qword); 9996 ins_pipe( pipe_slow ); 9997%} 9998 9999instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ 10000 predicate (UseSSE>=2); 10001 match(Set dst (ExpD src)); 10002 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx); 10003 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t" 10004 "MOVSD [ESP],$src\n\t" 10005 "FLDL2E \t\t\t# Ld log2(e) X\n\t" 10006 "FMULP \t\t\t# Q=X*log2(e) X\n\t" 10007 10008 "FDUP \t\t\t# Q Q\n\t" 10009 "FRNDINT\t\t\t# int(Q) Q\n\t" 10010 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 10011 "FISTP dword [ESP]\n\t" 10012 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 10013 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 10014 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 10015 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 10016 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 10017 "ADD EAX,1023\t\t# Double exponent bias\n\t" 10018 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 10019 "SHL EAX,20\t\t# Shift exponent into place\n\t" 10020 "TEST EBX,ECX\t\t# Check for overflow\n\t" 10021 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 10022 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 10023 "MOV [ESP+0],0\n\t" 10024 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 10025 10026 "FST_D [ESP]\n\t" 10027 "MOVSD $dst,[ESP]\n\t" 10028 "ADD ESP,8" 10029 %} 10030 ins_encode( Push_SrcXD(src), 10031 Opcode(0xD9), Opcode(0xEA), // fldl2e 10032 Opcode(0xDE), Opcode(0xC9), // fmulp 10033 pow_exp_core_encoding, 10034 Push_ResultXD(dst) ); 10035 ins_pipe( pipe_slow ); 10036%} 10037 10038 10039 10040instruct log10D_reg(regDPR1 dst, regDPR1 src) %{ 10041 predicate (UseSSE<=1); 10042 // The source Double operand on FPU stack 10043 match(Set dst (Log10D src)); 10044 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number 10045 // fxch ; swap ST(0) with ST(1) 10046 // fyl2x ; compute log_10(2) * log_2(x) 10047 format %{ "FLDLG2 \t\t\t#Log10\n\t" 10048 "FXCH \n\t" 10049 "FYL2X \t\t\t# Q=Log10*Log_2(x)" 10050 %} 10051 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 10052 Opcode(0xD9), Opcode(0xC9), // fxch 10053 Opcode(0xD9), Opcode(0xF1)); // fyl2x 10054 10055 ins_pipe( pipe_slow ); 10056%} 10057 10058instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{ 10059 predicate (UseSSE>=2); 10060 effect(KILL cr); 10061 match(Set dst (Log10D src)); 10062 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number 10063 // fyl2x ; compute log_10(2) * log_2(x) 10064 format %{ "FLDLG2 \t\t\t#Log10\n\t" 10065 "FYL2X \t\t\t# Q=Log10*Log_2(x)" 10066 %} 10067 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 10068 Push_SrcXD(src), 10069 Opcode(0xD9), Opcode(0xF1), // fyl2x 10070 Push_ResultXD(dst)); 10071 10072 ins_pipe( pipe_slow ); 10073%} 10074 10075instruct logD_reg(regDPR1 dst, regDPR1 src) %{ 10076 predicate (UseSSE<=1); 10077 // The source Double operand on FPU stack 10078 match(Set dst (LogD src)); 10079 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number 10080 // fxch ; swap ST(0) with ST(1) 10081 // fyl2x ; compute log_e(2) * log_2(x) 10082 format %{ "FLDLN2 \t\t\t#Log_e\n\t" 10083 "FXCH \n\t" 10084 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" 10085 %} 10086 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 10087 Opcode(0xD9), Opcode(0xC9), // fxch 10088 Opcode(0xD9), Opcode(0xF1)); // fyl2x 10089 10090 ins_pipe( pipe_slow ); 10091%} 10092 10093instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{ 10094 predicate (UseSSE>=2); 10095 effect(KILL cr); 10096 // The source and result Double operands in XMM registers 10097 match(Set dst (LogD src)); 10098 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number 10099 // fyl2x ; compute log_e(2) * log_2(x) 10100 format %{ "FLDLN2 \t\t\t#Log_e\n\t" 10101 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" 10102 %} 10103 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 10104 Push_SrcXD(src), 10105 Opcode(0xD9), Opcode(0xF1), // fyl2x 10106 Push_ResultXD(dst)); 10107 ins_pipe( pipe_slow ); 10108%} 10109 10110//-------------Float Instructions------------------------------- 10111// Float Math 10112 10113// Code for float compare: 10114// fcompp(); 10115// fwait(); fnstsw_ax(); 10116// sahf(); 10117// movl(dst, unordered_result); 10118// jcc(Assembler::parity, exit); 10119// movl(dst, less_result); 10120// jcc(Assembler::below, exit); 10121// movl(dst, equal_result); 10122// jcc(Assembler::equal, exit); 10123// movl(dst, greater_result); 10124// exit: 10125 10126// P6 version of float compare, sets condition codes in EFLAGS 10127instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{ 10128 predicate(VM_Version::supports_cmov() && UseSSE == 0); 10129 match(Set cr (CmpF src1 src2)); 10130 effect(KILL rax); 10131 ins_cost(150); 10132 format %{ "FLD $src1\n\t" 10133 "FUCOMIP ST,$src2 // P6 instruction\n\t" 10134 "JNP exit\n\t" 10135 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" 10136 "SAHF\n" 10137 "exit:\tNOP // avoid branch to branch" %} 10138 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 10139 ins_encode( Push_Reg_D(src1), 10140 OpcP, RegOpc(src2), 10141 cmpF_P6_fixup ); 10142 ins_pipe( pipe_slow ); 10143%} 10144 10145 10146// Compare & branch 10147instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{ 10148 predicate(UseSSE == 0); 10149 match(Set cr (CmpF src1 src2)); 10150 effect(KILL rax); 10151 ins_cost(200); 10152 format %{ "FLD $src1\n\t" 10153 "FCOMp $src2\n\t" 10154 "FNSTSW AX\n\t" 10155 "TEST AX,0x400\n\t" 10156 "JZ,s flags\n\t" 10157 "MOV AH,1\t# unordered treat as LT\n" 10158 "flags:\tSAHF" %} 10159 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 10160 ins_encode( Push_Reg_D(src1), 10161 OpcP, RegOpc(src2), 10162 fpu_flags); 10163 ins_pipe( pipe_slow ); 10164%} 10165 10166// Compare vs zero into -1,0,1 10167instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{ 10168 predicate(UseSSE == 0); 10169 match(Set dst (CmpF3 src1 zero)); 10170 effect(KILL cr, KILL rax); 10171 ins_cost(280); 10172 format %{ "FTSTF $dst,$src1" %} 10173 opcode(0xE4, 0xD9); 10174 ins_encode( Push_Reg_D(src1), 10175 OpcS, OpcP, PopFPU, 10176 CmpF_Result(dst)); 10177 ins_pipe( pipe_slow ); 10178%} 10179 10180// Compare into -1,0,1 10181instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{ 10182 predicate(UseSSE == 0); 10183 match(Set dst (CmpF3 src1 src2)); 10184 effect(KILL cr, KILL rax); 10185 ins_cost(300); 10186 format %{ "FCMPF $dst,$src1,$src2" %} 10187 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 10188 ins_encode( Push_Reg_D(src1), 10189 OpcP, RegOpc(src2), 10190 CmpF_Result(dst)); 10191 ins_pipe( pipe_slow ); 10192%} 10193 10194// float compare and set condition codes in EFLAGS by XMM regs 10195instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{ 10196 predicate(UseSSE>=1); 10197 match(Set cr (CmpF dst src)); 10198 effect(KILL rax); 10199 ins_cost(145); 10200 format %{ "COMISS $dst,$src\n" 10201 "\tJNP exit\n" 10202 "\tMOV ah,1 // saw a NaN, set CF\n" 10203 "\tSAHF\n" 10204 "exit:\tNOP // avoid branch to branch" %} 10205 opcode(0x0F, 0x2F); 10206 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup); 10207 ins_pipe( pipe_slow ); 10208%} 10209 10210// float compare and set condition codes in EFLAGS by XMM regs 10211instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{ 10212 predicate(UseSSE>=1); 10213 match(Set cr (CmpF dst (LoadF src))); 10214 effect(KILL rax); 10215 ins_cost(165); 10216 format %{ "COMISS $dst,$src\n" 10217 "\tJNP exit\n" 10218 "\tMOV ah,1 // saw a NaN, set CF\n" 10219 "\tSAHF\n" 10220 "exit:\tNOP // avoid branch to branch" %} 10221 opcode(0x0F, 0x2F); 10222 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup); 10223 ins_pipe( pipe_slow ); 10224%} 10225 10226// Compare into -1,0,1 in XMM 10227instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{ 10228 predicate(UseSSE>=1); 10229 match(Set dst (CmpF3 src1 src2)); 10230 effect(KILL cr); 10231 ins_cost(255); 10232 format %{ "XOR $dst,$dst\n" 10233 "\tCOMISS $src1,$src2\n" 10234 "\tJP,s nan\n" 10235 "\tJEQ,s exit\n" 10236 "\tJA,s inc\n" 10237 "nan:\tDEC $dst\n" 10238 "\tJMP,s exit\n" 10239 "inc:\tINC $dst\n" 10240 "exit:" 10241 %} 10242 opcode(0x0F, 0x2F); 10243 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst)); 10244 ins_pipe( pipe_slow ); 10245%} 10246 10247// Compare into -1,0,1 in XMM and memory 10248instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{ 10249 predicate(UseSSE>=1); 10250 match(Set dst (CmpF3 src1 (LoadF mem))); 10251 effect(KILL cr); 10252 ins_cost(275); 10253 format %{ "COMISS $src1,$mem\n" 10254 "\tMOV $dst,0\t\t# do not blow flags\n" 10255 "\tJP,s nan\n" 10256 "\tJEQ,s exit\n" 10257 "\tJA,s inc\n" 10258 "nan:\tDEC $dst\n" 10259 "\tJMP,s exit\n" 10260 "inc:\tINC $dst\n" 10261 "exit:" 10262 %} 10263 opcode(0x0F, 0x2F); 10264 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst)); 10265 ins_pipe( pipe_slow ); 10266%} 10267 10268// Spill to obtain 24-bit precision 10269instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{ 10270 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10271 match(Set dst (SubF src1 src2)); 10272 10273 format %{ "FSUB $dst,$src1 - $src2" %} 10274 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ 10275 ins_encode( Push_Reg_F(src1), 10276 OpcReg_F(src2), 10277 Pop_Mem_F(dst) ); 10278 ins_pipe( fpu_mem_reg_reg ); 10279%} 10280// 10281// This instruction does not round to 24-bits 10282instruct subF_reg(regF dst, regF src) %{ 10283 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10284 match(Set dst (SubF dst src)); 10285 10286 format %{ "FSUB $dst,$src" %} 10287 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ 10288 ins_encode( Push_Reg_F(src), 10289 OpcP, RegOpc(dst) ); 10290 ins_pipe( fpu_reg_reg ); 10291%} 10292 10293// Spill to obtain 24-bit precision 10294instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{ 10295 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10296 match(Set dst (AddF src1 src2)); 10297 10298 format %{ "FADD $dst,$src1,$src2" %} 10299 opcode(0xD8, 0x0); /* D8 C0+i */ 10300 ins_encode( Push_Reg_F(src2), 10301 OpcReg_F(src1), 10302 Pop_Mem_F(dst) ); 10303 ins_pipe( fpu_mem_reg_reg ); 10304%} 10305// 10306// This instruction does not round to 24-bits 10307instruct addF_reg(regF dst, regF src) %{ 10308 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10309 match(Set dst (AddF dst src)); 10310 10311 format %{ "FLD $src\n\t" 10312 "FADDp $dst,ST" %} 10313 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ 10314 ins_encode( Push_Reg_F(src), 10315 OpcP, RegOpc(dst) ); 10316 ins_pipe( fpu_reg_reg ); 10317%} 10318 10319// Add two single precision floating point values in xmm 10320instruct addX_reg(regX dst, regX src) %{ 10321 predicate(UseSSE>=1); 10322 match(Set dst (AddF dst src)); 10323 format %{ "ADDSS $dst,$src" %} 10324 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src)); 10325 ins_pipe( pipe_slow ); 10326%} 10327 10328instruct addX_imm(regX dst, immXF con) %{ 10329 predicate(UseSSE>=1); 10330 match(Set dst (AddF dst con)); 10331 format %{ "ADDSS $dst,[$con]" %} 10332 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) ); 10333 ins_pipe( pipe_slow ); 10334%} 10335 10336instruct addX_mem(regX dst, memory mem) %{ 10337 predicate(UseSSE>=1); 10338 match(Set dst (AddF dst (LoadF mem))); 10339 format %{ "ADDSS $dst,$mem" %} 10340 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem)); 10341 ins_pipe( pipe_slow ); 10342%} 10343 10344// Subtract two single precision floating point values in xmm 10345instruct subX_reg(regX dst, regX src) %{ 10346 predicate(UseSSE>=1); 10347 match(Set dst (SubF dst src)); 10348 format %{ "SUBSS $dst,$src" %} 10349 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src)); 10350 ins_pipe( pipe_slow ); 10351%} 10352 10353instruct subX_imm(regX dst, immXF con) %{ 10354 predicate(UseSSE>=1); 10355 match(Set dst (SubF dst con)); 10356 format %{ "SUBSS $dst,[$con]" %} 10357 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) ); 10358 ins_pipe( pipe_slow ); 10359%} 10360 10361instruct subX_mem(regX dst, memory mem) %{ 10362 predicate(UseSSE>=1); 10363 match(Set dst (SubF dst (LoadF mem))); 10364 format %{ "SUBSS $dst,$mem" %} 10365 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem)); 10366 ins_pipe( pipe_slow ); 10367%} 10368 10369// Multiply two single precision floating point values in xmm 10370instruct mulX_reg(regX dst, regX src) %{ 10371 predicate(UseSSE>=1); 10372 match(Set dst (MulF dst src)); 10373 format %{ "MULSS $dst,$src" %} 10374 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src)); 10375 ins_pipe( pipe_slow ); 10376%} 10377 10378instruct mulX_imm(regX dst, immXF con) %{ 10379 predicate(UseSSE>=1); 10380 match(Set dst (MulF dst con)); 10381 format %{ "MULSS $dst,[$con]" %} 10382 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) ); 10383 ins_pipe( pipe_slow ); 10384%} 10385 10386instruct mulX_mem(regX dst, memory mem) %{ 10387 predicate(UseSSE>=1); 10388 match(Set dst (MulF dst (LoadF mem))); 10389 format %{ "MULSS $dst,$mem" %} 10390 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem)); 10391 ins_pipe( pipe_slow ); 10392%} 10393 10394// Divide two single precision floating point values in xmm 10395instruct divX_reg(regX dst, regX src) %{ 10396 predicate(UseSSE>=1); 10397 match(Set dst (DivF dst src)); 10398 format %{ "DIVSS $dst,$src" %} 10399 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src)); 10400 ins_pipe( pipe_slow ); 10401%} 10402 10403instruct divX_imm(regX dst, immXF con) %{ 10404 predicate(UseSSE>=1); 10405 match(Set dst (DivF dst con)); 10406 format %{ "DIVSS $dst,[$con]" %} 10407 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) ); 10408 ins_pipe( pipe_slow ); 10409%} 10410 10411instruct divX_mem(regX dst, memory mem) %{ 10412 predicate(UseSSE>=1); 10413 match(Set dst (DivF dst (LoadF mem))); 10414 format %{ "DIVSS $dst,$mem" %} 10415 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem)); 10416 ins_pipe( pipe_slow ); 10417%} 10418 10419// Get the square root of a single precision floating point values in xmm 10420instruct sqrtX_reg(regX dst, regX src) %{ 10421 predicate(UseSSE>=1); 10422 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 10423 format %{ "SQRTSS $dst,$src" %} 10424 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src)); 10425 ins_pipe( pipe_slow ); 10426%} 10427 10428instruct sqrtX_mem(regX dst, memory mem) %{ 10429 predicate(UseSSE>=1); 10430 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem))))); 10431 format %{ "SQRTSS $dst,$mem" %} 10432 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem)); 10433 ins_pipe( pipe_slow ); 10434%} 10435 10436// Get the square root of a double precision floating point values in xmm 10437instruct sqrtXD_reg(regXD dst, regXD src) %{ 10438 predicate(UseSSE>=2); 10439 match(Set dst (SqrtD src)); 10440 format %{ "SQRTSD $dst,$src" %} 10441 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src)); 10442 ins_pipe( pipe_slow ); 10443%} 10444 10445instruct sqrtXD_mem(regXD dst, memory mem) %{ 10446 predicate(UseSSE>=2); 10447 match(Set dst (SqrtD (LoadD mem))); 10448 format %{ "SQRTSD $dst,$mem" %} 10449 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem)); 10450 ins_pipe( pipe_slow ); 10451%} 10452 10453instruct absF_reg(regFPR1 dst, regFPR1 src) %{ 10454 predicate(UseSSE==0); 10455 match(Set dst (AbsF src)); 10456 ins_cost(100); 10457 format %{ "FABS" %} 10458 opcode(0xE1, 0xD9); 10459 ins_encode( OpcS, OpcP ); 10460 ins_pipe( fpu_reg_reg ); 10461%} 10462 10463instruct absX_reg(regX dst ) %{ 10464 predicate(UseSSE>=1); 10465 match(Set dst (AbsF dst)); 10466 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %} 10467 ins_encode( AbsXF_encoding(dst)); 10468 ins_pipe( pipe_slow ); 10469%} 10470 10471instruct negF_reg(regFPR1 dst, regFPR1 src) %{ 10472 predicate(UseSSE==0); 10473 match(Set dst (NegF src)); 10474 ins_cost(100); 10475 format %{ "FCHS" %} 10476 opcode(0xE0, 0xD9); 10477 ins_encode( OpcS, OpcP ); 10478 ins_pipe( fpu_reg_reg ); 10479%} 10480 10481instruct negX_reg( regX dst ) %{ 10482 predicate(UseSSE>=1); 10483 match(Set dst (NegF dst)); 10484 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %} 10485 ins_encode( NegXF_encoding(dst)); 10486 ins_pipe( pipe_slow ); 10487%} 10488 10489// Cisc-alternate to addF_reg 10490// Spill to obtain 24-bit precision 10491instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{ 10492 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10493 match(Set dst (AddF src1 (LoadF src2))); 10494 10495 format %{ "FLD $src2\n\t" 10496 "FADD ST,$src1\n\t" 10497 "FSTP_S $dst" %} 10498 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 10499 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10500 OpcReg_F(src1), 10501 Pop_Mem_F(dst) ); 10502 ins_pipe( fpu_mem_reg_mem ); 10503%} 10504// 10505// Cisc-alternate to addF_reg 10506// This instruction does not round to 24-bits 10507instruct addF_reg_mem(regF dst, memory src) %{ 10508 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10509 match(Set dst (AddF dst (LoadF src))); 10510 10511 format %{ "FADD $dst,$src" %} 10512 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ 10513 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 10514 OpcP, RegOpc(dst) ); 10515 ins_pipe( fpu_reg_mem ); 10516%} 10517 10518// // Following two instructions for _222_mpegaudio 10519// Spill to obtain 24-bit precision 10520instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{ 10521 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10522 match(Set dst (AddF src1 src2)); 10523 10524 format %{ "FADD $dst,$src1,$src2" %} 10525 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 10526 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), 10527 OpcReg_F(src2), 10528 Pop_Mem_F(dst) ); 10529 ins_pipe( fpu_mem_reg_mem ); 10530%} 10531 10532// Cisc-spill variant 10533// Spill to obtain 24-bit precision 10534instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ 10535 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10536 match(Set dst (AddF src1 (LoadF src2))); 10537 10538 format %{ "FADD $dst,$src1,$src2 cisc" %} 10539 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 10540 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10541 set_instruction_start, 10542 OpcP, RMopc_Mem(secondary,src1), 10543 Pop_Mem_F(dst) ); 10544 ins_pipe( fpu_mem_mem_mem ); 10545%} 10546 10547// Spill to obtain 24-bit precision 10548instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ 10549 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10550 match(Set dst (AddF src1 src2)); 10551 10552 format %{ "FADD $dst,$src1,$src2" %} 10553 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ 10554 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10555 set_instruction_start, 10556 OpcP, RMopc_Mem(secondary,src1), 10557 Pop_Mem_F(dst) ); 10558 ins_pipe( fpu_mem_mem_mem ); 10559%} 10560 10561 10562// Spill to obtain 24-bit precision 10563instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{ 10564 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10565 match(Set dst (AddF src1 src2)); 10566 format %{ "FLD $src1\n\t" 10567 "FADD $src2\n\t" 10568 "FSTP_S $dst" %} 10569 opcode(0xD8, 0x00); /* D8 /0 */ 10570 ins_encode( Push_Reg_F(src1), 10571 Opc_MemImm_F(src2), 10572 Pop_Mem_F(dst)); 10573 ins_pipe( fpu_mem_reg_con ); 10574%} 10575// 10576// This instruction does not round to 24-bits 10577instruct addF_reg_imm(regF dst, regF src1, immF src2) %{ 10578 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10579 match(Set dst (AddF src1 src2)); 10580 format %{ "FLD $src1\n\t" 10581 "FADD $src2\n\t" 10582 "FSTP_S $dst" %} 10583 opcode(0xD8, 0x00); /* D8 /0 */ 10584 ins_encode( Push_Reg_F(src1), 10585 Opc_MemImm_F(src2), 10586 Pop_Reg_F(dst)); 10587 ins_pipe( fpu_reg_reg_con ); 10588%} 10589 10590// Spill to obtain 24-bit precision 10591instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{ 10592 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10593 match(Set dst (MulF src1 src2)); 10594 10595 format %{ "FLD $src1\n\t" 10596 "FMUL $src2\n\t" 10597 "FSTP_S $dst" %} 10598 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ 10599 ins_encode( Push_Reg_F(src1), 10600 OpcReg_F(src2), 10601 Pop_Mem_F(dst) ); 10602 ins_pipe( fpu_mem_reg_reg ); 10603%} 10604// 10605// This instruction does not round to 24-bits 10606instruct mulF_reg(regF dst, regF src1, regF src2) %{ 10607 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10608 match(Set dst (MulF src1 src2)); 10609 10610 format %{ "FLD $src1\n\t" 10611 "FMUL $src2\n\t" 10612 "FSTP_S $dst" %} 10613 opcode(0xD8, 0x1); /* D8 C8+i */ 10614 ins_encode( Push_Reg_F(src2), 10615 OpcReg_F(src1), 10616 Pop_Reg_F(dst) ); 10617 ins_pipe( fpu_reg_reg_reg ); 10618%} 10619 10620 10621// Spill to obtain 24-bit precision 10622// Cisc-alternate to reg-reg multiply 10623instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{ 10624 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10625 match(Set dst (MulF src1 (LoadF src2))); 10626 10627 format %{ "FLD_S $src2\n\t" 10628 "FMUL $src1\n\t" 10629 "FSTP_S $dst" %} 10630 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ 10631 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10632 OpcReg_F(src1), 10633 Pop_Mem_F(dst) ); 10634 ins_pipe( fpu_mem_reg_mem ); 10635%} 10636// 10637// This instruction does not round to 24-bits 10638// Cisc-alternate to reg-reg multiply 10639instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{ 10640 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10641 match(Set dst (MulF src1 (LoadF src2))); 10642 10643 format %{ "FMUL $dst,$src1,$src2" %} 10644 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ 10645 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10646 OpcReg_F(src1), 10647 Pop_Reg_F(dst) ); 10648 ins_pipe( fpu_reg_reg_mem ); 10649%} 10650 10651// Spill to obtain 24-bit precision 10652instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ 10653 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10654 match(Set dst (MulF src1 src2)); 10655 10656 format %{ "FMUL $dst,$src1,$src2" %} 10657 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ 10658 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10659 set_instruction_start, 10660 OpcP, RMopc_Mem(secondary,src1), 10661 Pop_Mem_F(dst) ); 10662 ins_pipe( fpu_mem_mem_mem ); 10663%} 10664 10665// Spill to obtain 24-bit precision 10666instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{ 10667 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10668 match(Set dst (MulF src1 src2)); 10669 10670 format %{ "FMULc $dst,$src1,$src2" %} 10671 opcode(0xD8, 0x1); /* D8 /1*/ 10672 ins_encode( Push_Reg_F(src1), 10673 Opc_MemImm_F(src2), 10674 Pop_Mem_F(dst)); 10675 ins_pipe( fpu_mem_reg_con ); 10676%} 10677// 10678// This instruction does not round to 24-bits 10679instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{ 10680 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10681 match(Set dst (MulF src1 src2)); 10682 10683 format %{ "FMULc $dst. $src1, $src2" %} 10684 opcode(0xD8, 0x1); /* D8 /1*/ 10685 ins_encode( Push_Reg_F(src1), 10686 Opc_MemImm_F(src2), 10687 Pop_Reg_F(dst)); 10688 ins_pipe( fpu_reg_reg_con ); 10689%} 10690 10691 10692// 10693// MACRO1 -- subsume unshared load into mulF 10694// This instruction does not round to 24-bits 10695instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{ 10696 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10697 match(Set dst (MulF (LoadF mem1) src)); 10698 10699 format %{ "FLD $mem1 ===MACRO1===\n\t" 10700 "FMUL ST,$src\n\t" 10701 "FSTP $dst" %} 10702 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ 10703 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), 10704 OpcReg_F(src), 10705 Pop_Reg_F(dst) ); 10706 ins_pipe( fpu_reg_reg_mem ); 10707%} 10708// 10709// MACRO2 -- addF a mulF which subsumed an unshared load 10710// This instruction does not round to 24-bits 10711instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{ 10712 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10713 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); 10714 ins_cost(95); 10715 10716 format %{ "FLD $mem1 ===MACRO2===\n\t" 10717 "FMUL ST,$src1 subsume mulF left load\n\t" 10718 "FADD ST,$src2\n\t" 10719 "FSTP $dst" %} 10720 opcode(0xD9); /* LoadF D9 /0 */ 10721 ins_encode( OpcP, RMopc_Mem(0x00,mem1), 10722 FMul_ST_reg(src1), 10723 FAdd_ST_reg(src2), 10724 Pop_Reg_F(dst) ); 10725 ins_pipe( fpu_reg_mem_reg_reg ); 10726%} 10727 10728// MACRO3 -- addF a mulF 10729// This instruction does not round to 24-bits. It is a '2-address' 10730// instruction in that the result goes back to src2. This eliminates 10731// a move from the macro; possibly the register allocator will have 10732// to add it back (and maybe not). 10733instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{ 10734 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10735 match(Set src2 (AddF (MulF src0 src1) src2)); 10736 10737 format %{ "FLD $src0 ===MACRO3===\n\t" 10738 "FMUL ST,$src1\n\t" 10739 "FADDP $src2,ST" %} 10740 opcode(0xD9); /* LoadF D9 /0 */ 10741 ins_encode( Push_Reg_F(src0), 10742 FMul_ST_reg(src1), 10743 FAddP_reg_ST(src2) ); 10744 ins_pipe( fpu_reg_reg_reg ); 10745%} 10746 10747// MACRO4 -- divF subF 10748// This instruction does not round to 24-bits 10749instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{ 10750 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10751 match(Set dst (DivF (SubF src2 src1) src3)); 10752 10753 format %{ "FLD $src2 ===MACRO4===\n\t" 10754 "FSUB ST,$src1\n\t" 10755 "FDIV ST,$src3\n\t" 10756 "FSTP $dst" %} 10757 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 10758 ins_encode( Push_Reg_F(src2), 10759 subF_divF_encode(src1,src3), 10760 Pop_Reg_F(dst) ); 10761 ins_pipe( fpu_reg_reg_reg_reg ); 10762%} 10763 10764// Spill to obtain 24-bit precision 10765instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{ 10766 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10767 match(Set dst (DivF src1 src2)); 10768 10769 format %{ "FDIV $dst,$src1,$src2" %} 10770 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ 10771 ins_encode( Push_Reg_F(src1), 10772 OpcReg_F(src2), 10773 Pop_Mem_F(dst) ); 10774 ins_pipe( fpu_mem_reg_reg ); 10775%} 10776// 10777// This instruction does not round to 24-bits 10778instruct divF_reg(regF dst, regF src) %{ 10779 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10780 match(Set dst (DivF dst src)); 10781 10782 format %{ "FDIV $dst,$src" %} 10783 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 10784 ins_encode( Push_Reg_F(src), 10785 OpcP, RegOpc(dst) ); 10786 ins_pipe( fpu_reg_reg ); 10787%} 10788 10789 10790// Spill to obtain 24-bit precision 10791instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{ 10792 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 10793 match(Set dst (ModF src1 src2)); 10794 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS 10795 10796 format %{ "FMOD $dst,$src1,$src2" %} 10797 ins_encode( Push_Reg_Mod_D(src1, src2), 10798 emitModD(), 10799 Push_Result_Mod_D(src2), 10800 Pop_Mem_F(dst)); 10801 ins_pipe( pipe_slow ); 10802%} 10803// 10804// This instruction does not round to 24-bits 10805instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{ 10806 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10807 match(Set dst (ModF dst src)); 10808 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS 10809 10810 format %{ "FMOD $dst,$src" %} 10811 ins_encode(Push_Reg_Mod_D(dst, src), 10812 emitModD(), 10813 Push_Result_Mod_D(src), 10814 Pop_Reg_F(dst)); 10815 ins_pipe( pipe_slow ); 10816%} 10817 10818instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{ 10819 predicate(UseSSE>=1); 10820 match(Set dst (ModF src0 src1)); 10821 effect(KILL rax, KILL cr); 10822 format %{ "SUB ESP,4\t # FMOD\n" 10823 "\tMOVSS [ESP+0],$src1\n" 10824 "\tFLD_S [ESP+0]\n" 10825 "\tMOVSS [ESP+0],$src0\n" 10826 "\tFLD_S [ESP+0]\n" 10827 "loop:\tFPREM\n" 10828 "\tFWAIT\n" 10829 "\tFNSTSW AX\n" 10830 "\tSAHF\n" 10831 "\tJP loop\n" 10832 "\tFSTP_S [ESP+0]\n" 10833 "\tMOVSS $dst,[ESP+0]\n" 10834 "\tADD ESP,4\n" 10835 "\tFSTP ST0\t # Restore FPU Stack" 10836 %} 10837 ins_cost(250); 10838 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU); 10839 ins_pipe( pipe_slow ); 10840%} 10841 10842 10843//----------Arithmetic Conversion Instructions--------------------------------- 10844// The conversions operations are all Alpha sorted. Please keep it that way! 10845 10846instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{ 10847 predicate(UseSSE==0); 10848 match(Set dst (RoundFloat src)); 10849 ins_cost(125); 10850 format %{ "FST_S $dst,$src\t# F-round" %} 10851 ins_encode( Pop_Mem_Reg_F(dst, src) ); 10852 ins_pipe( fpu_mem_reg ); 10853%} 10854 10855instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{ 10856 predicate(UseSSE<=1); 10857 match(Set dst (RoundDouble src)); 10858 ins_cost(125); 10859 format %{ "FST_D $dst,$src\t# D-round" %} 10860 ins_encode( Pop_Mem_Reg_D(dst, src) ); 10861 ins_pipe( fpu_mem_reg ); 10862%} 10863 10864// Force rounding to 24-bit precision and 6-bit exponent 10865instruct convD2F_reg(stackSlotF dst, regD src) %{ 10866 predicate(UseSSE==0); 10867 match(Set dst (ConvD2F src)); 10868 format %{ "FST_S $dst,$src\t# F-round" %} 10869 expand %{ 10870 roundFloat_mem_reg(dst,src); 10871 %} 10872%} 10873 10874// Force rounding to 24-bit precision and 6-bit exponent 10875instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{ 10876 predicate(UseSSE==1); 10877 match(Set dst (ConvD2F src)); 10878 effect( KILL cr ); 10879 format %{ "SUB ESP,4\n\t" 10880 "FST_S [ESP],$src\t# F-round\n\t" 10881 "MOVSS $dst,[ESP]\n\t" 10882 "ADD ESP,4" %} 10883 ins_encode( D2X_encoding(dst, src) ); 10884 ins_pipe( pipe_slow ); 10885%} 10886 10887// Force rounding double precision to single precision 10888instruct convXD2X_reg(regX dst, regXD src) %{ 10889 predicate(UseSSE>=2); 10890 match(Set dst (ConvD2F src)); 10891 format %{ "CVTSD2SS $dst,$src\t# F-round" %} 10892 opcode(0xF2, 0x0F, 0x5A); 10893 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 10894 ins_pipe( pipe_slow ); 10895%} 10896 10897instruct convF2D_reg_reg(regD dst, regF src) %{ 10898 predicate(UseSSE==0); 10899 match(Set dst (ConvF2D src)); 10900 format %{ "FST_S $dst,$src\t# D-round" %} 10901 ins_encode( Pop_Reg_Reg_D(dst, src)); 10902 ins_pipe( fpu_reg_reg ); 10903%} 10904 10905instruct convF2D_reg(stackSlotD dst, regF src) %{ 10906 predicate(UseSSE==1); 10907 match(Set dst (ConvF2D src)); 10908 format %{ "FST_D $dst,$src\t# D-round" %} 10909 expand %{ 10910 roundDouble_mem_reg(dst,src); 10911 %} 10912%} 10913 10914instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{ 10915 predicate(UseSSE==1); 10916 match(Set dst (ConvF2D src)); 10917 effect( KILL cr ); 10918 format %{ "SUB ESP,4\n\t" 10919 "MOVSS [ESP] $src\n\t" 10920 "FLD_S [ESP]\n\t" 10921 "ADD ESP,4\n\t" 10922 "FSTP $dst\t# D-round" %} 10923 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst)); 10924 ins_pipe( pipe_slow ); 10925%} 10926 10927instruct convX2XD_reg(regXD dst, regX src) %{ 10928 predicate(UseSSE>=2); 10929 match(Set dst (ConvF2D src)); 10930 format %{ "CVTSS2SD $dst,$src\t# D-round" %} 10931 opcode(0xF3, 0x0F, 0x5A); 10932 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 10933 ins_pipe( pipe_slow ); 10934%} 10935 10936// Convert a double to an int. If the double is a NAN, stuff a zero in instead. 10937instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ 10938 predicate(UseSSE<=1); 10939 match(Set dst (ConvD2I src)); 10940 effect( KILL tmp, KILL cr ); 10941 format %{ "FLD $src\t# Convert double to int \n\t" 10942 "FLDCW trunc mode\n\t" 10943 "SUB ESP,4\n\t" 10944 "FISTp [ESP + #0]\n\t" 10945 "FLDCW std/24-bit mode\n\t" 10946 "POP EAX\n\t" 10947 "CMP EAX,0x80000000\n\t" 10948 "JNE,s fast\n\t" 10949 "FLD_D $src\n\t" 10950 "CALL d2i_wrapper\n" 10951 "fast:" %} 10952 ins_encode( Push_Reg_D(src), D2I_encoding(src) ); 10953 ins_pipe( pipe_slow ); 10954%} 10955 10956// Convert a double to an int. If the double is a NAN, stuff a zero in instead. 10957instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{ 10958 predicate(UseSSE>=2); 10959 match(Set dst (ConvD2I src)); 10960 effect( KILL tmp, KILL cr ); 10961 format %{ "CVTTSD2SI $dst, $src\n\t" 10962 "CMP $dst,0x80000000\n\t" 10963 "JNE,s fast\n\t" 10964 "SUB ESP, 8\n\t" 10965 "MOVSD [ESP], $src\n\t" 10966 "FLD_D [ESP]\n\t" 10967 "ADD ESP, 8\n\t" 10968 "CALL d2i_wrapper\n" 10969 "fast:" %} 10970 opcode(0x1); // double-precision conversion 10971 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst)); 10972 ins_pipe( pipe_slow ); 10973%} 10974 10975instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ 10976 predicate(UseSSE<=1); 10977 match(Set dst (ConvD2L src)); 10978 effect( KILL cr ); 10979 format %{ "FLD $src\t# Convert double to long\n\t" 10980 "FLDCW trunc mode\n\t" 10981 "SUB ESP,8\n\t" 10982 "FISTp [ESP + #0]\n\t" 10983 "FLDCW std/24-bit mode\n\t" 10984 "POP EAX\n\t" 10985 "POP EDX\n\t" 10986 "CMP EDX,0x80000000\n\t" 10987 "JNE,s fast\n\t" 10988 "TEST EAX,EAX\n\t" 10989 "JNE,s fast\n\t" 10990 "FLD $src\n\t" 10991 "CALL d2l_wrapper\n" 10992 "fast:" %} 10993 ins_encode( Push_Reg_D(src), D2L_encoding(src) ); 10994 ins_pipe( pipe_slow ); 10995%} 10996 10997// XMM lacks a float/double->long conversion, so use the old FPU stack. 10998instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{ 10999 predicate (UseSSE>=2); 11000 match(Set dst (ConvD2L src)); 11001 effect( KILL cr ); 11002 format %{ "SUB ESP,8\t# Convert double to long\n\t" 11003 "MOVSD [ESP],$src\n\t" 11004 "FLD_D [ESP]\n\t" 11005 "FLDCW trunc mode\n\t" 11006 "FISTp [ESP + #0]\n\t" 11007 "FLDCW std/24-bit mode\n\t" 11008 "POP EAX\n\t" 11009 "POP EDX\n\t" 11010 "CMP EDX,0x80000000\n\t" 11011 "JNE,s fast\n\t" 11012 "TEST EAX,EAX\n\t" 11013 "JNE,s fast\n\t" 11014 "SUB ESP,8\n\t" 11015 "MOVSD [ESP],$src\n\t" 11016 "FLD_D [ESP]\n\t" 11017 "CALL d2l_wrapper\n" 11018 "fast:" %} 11019 ins_encode( XD2L_encoding(src) ); 11020 ins_pipe( pipe_slow ); 11021%} 11022 11023// Convert a double to an int. Java semantics require we do complex 11024// manglations in the corner cases. So we set the rounding mode to 11025// 'zero', store the darned double down as an int, and reset the 11026// rounding mode to 'nearest'. The hardware stores a flag value down 11027// if we would overflow or converted a NAN; we check for this and 11028// and go the slow path if needed. 11029instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ 11030 predicate(UseSSE==0); 11031 match(Set dst (ConvF2I src)); 11032 effect( KILL tmp, KILL cr ); 11033 format %{ "FLD $src\t# Convert float to int \n\t" 11034 "FLDCW trunc mode\n\t" 11035 "SUB ESP,4\n\t" 11036 "FISTp [ESP + #0]\n\t" 11037 "FLDCW std/24-bit mode\n\t" 11038 "POP EAX\n\t" 11039 "CMP EAX,0x80000000\n\t" 11040 "JNE,s fast\n\t" 11041 "FLD $src\n\t" 11042 "CALL d2i_wrapper\n" 11043 "fast:" %} 11044 // D2I_encoding works for F2I 11045 ins_encode( Push_Reg_F(src), D2I_encoding(src) ); 11046 ins_pipe( pipe_slow ); 11047%} 11048 11049// Convert a float in xmm to an int reg. 11050instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{ 11051 predicate(UseSSE>=1); 11052 match(Set dst (ConvF2I src)); 11053 effect( KILL tmp, KILL cr ); 11054 format %{ "CVTTSS2SI $dst, $src\n\t" 11055 "CMP $dst,0x80000000\n\t" 11056 "JNE,s fast\n\t" 11057 "SUB ESP, 4\n\t" 11058 "MOVSS [ESP], $src\n\t" 11059 "FLD [ESP]\n\t" 11060 "ADD ESP, 4\n\t" 11061 "CALL d2i_wrapper\n" 11062 "fast:" %} 11063 opcode(0x0); // single-precision conversion 11064 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst)); 11065 ins_pipe( pipe_slow ); 11066%} 11067 11068instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ 11069 predicate(UseSSE==0); 11070 match(Set dst (ConvF2L src)); 11071 effect( KILL cr ); 11072 format %{ "FLD $src\t# Convert float to long\n\t" 11073 "FLDCW trunc mode\n\t" 11074 "SUB ESP,8\n\t" 11075 "FISTp [ESP + #0]\n\t" 11076 "FLDCW std/24-bit mode\n\t" 11077 "POP EAX\n\t" 11078 "POP EDX\n\t" 11079 "CMP EDX,0x80000000\n\t" 11080 "JNE,s fast\n\t" 11081 "TEST EAX,EAX\n\t" 11082 "JNE,s fast\n\t" 11083 "FLD $src\n\t" 11084 "CALL d2l_wrapper\n" 11085 "fast:" %} 11086 // D2L_encoding works for F2L 11087 ins_encode( Push_Reg_F(src), D2L_encoding(src) ); 11088 ins_pipe( pipe_slow ); 11089%} 11090 11091// XMM lacks a float/double->long conversion, so use the old FPU stack. 11092instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{ 11093 predicate (UseSSE>=1); 11094 match(Set dst (ConvF2L src)); 11095 effect( KILL cr ); 11096 format %{ "SUB ESP,8\t# Convert float to long\n\t" 11097 "MOVSS [ESP],$src\n\t" 11098 "FLD_S [ESP]\n\t" 11099 "FLDCW trunc mode\n\t" 11100 "FISTp [ESP + #0]\n\t" 11101 "FLDCW std/24-bit mode\n\t" 11102 "POP EAX\n\t" 11103 "POP EDX\n\t" 11104 "CMP EDX,0x80000000\n\t" 11105 "JNE,s fast\n\t" 11106 "TEST EAX,EAX\n\t" 11107 "JNE,s fast\n\t" 11108 "SUB ESP,4\t# Convert float to long\n\t" 11109 "MOVSS [ESP],$src\n\t" 11110 "FLD_S [ESP]\n\t" 11111 "ADD ESP,4\n\t" 11112 "CALL d2l_wrapper\n" 11113 "fast:" %} 11114 ins_encode( X2L_encoding(src) ); 11115 ins_pipe( pipe_slow ); 11116%} 11117 11118instruct convI2D_reg(regD dst, stackSlotI src) %{ 11119 predicate( UseSSE<=1 ); 11120 match(Set dst (ConvI2D src)); 11121 format %{ "FILD $src\n\t" 11122 "FSTP $dst" %} 11123 opcode(0xDB, 0x0); /* DB /0 */ 11124 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst)); 11125 ins_pipe( fpu_reg_mem ); 11126%} 11127 11128instruct convI2XD_reg(regXD dst, eRegI src) %{ 11129 predicate( UseSSE>=2 && !UseXmmI2D ); 11130 match(Set dst (ConvI2D src)); 11131 format %{ "CVTSI2SD $dst,$src" %} 11132 opcode(0xF2, 0x0F, 0x2A); 11133 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 11134 ins_pipe( pipe_slow ); 11135%} 11136 11137instruct convI2XD_mem(regXD dst, memory mem) %{ 11138 predicate( UseSSE>=2 ); 11139 match(Set dst (ConvI2D (LoadI mem))); 11140 format %{ "CVTSI2SD $dst,$mem" %} 11141 opcode(0xF2, 0x0F, 0x2A); 11142 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem)); 11143 ins_pipe( pipe_slow ); 11144%} 11145 11146instruct convXI2XD_reg(regXD dst, eRegI src) 11147%{ 11148 predicate( UseSSE>=2 && UseXmmI2D ); 11149 match(Set dst (ConvI2D src)); 11150 11151 format %{ "MOVD $dst,$src\n\t" 11152 "CVTDQ2PD $dst,$dst\t# i2d" %} 11153 ins_encode %{ 11154 __ movd($dst$$XMMRegister, $src$$Register); 11155 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); 11156 %} 11157 ins_pipe(pipe_slow); // XXX 11158%} 11159 11160instruct convI2D_mem(regD dst, memory mem) %{ 11161 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); 11162 match(Set dst (ConvI2D (LoadI mem))); 11163 format %{ "FILD $mem\n\t" 11164 "FSTP $dst" %} 11165 opcode(0xDB); /* DB /0 */ 11166 ins_encode( OpcP, RMopc_Mem(0x00,mem), 11167 Pop_Reg_D(dst)); 11168 ins_pipe( fpu_reg_mem ); 11169%} 11170 11171// Convert a byte to a float; no rounding step needed. 11172instruct conv24I2F_reg(regF dst, stackSlotI src) %{ 11173 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); 11174 match(Set dst (ConvI2F src)); 11175 format %{ "FILD $src\n\t" 11176 "FSTP $dst" %} 11177 11178 opcode(0xDB, 0x0); /* DB /0 */ 11179 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst)); 11180 ins_pipe( fpu_reg_mem ); 11181%} 11182 11183// In 24-bit mode, force exponent rounding by storing back out 11184instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{ 11185 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 11186 match(Set dst (ConvI2F src)); 11187 ins_cost(200); 11188 format %{ "FILD $src\n\t" 11189 "FSTP_S $dst" %} 11190 opcode(0xDB, 0x0); /* DB /0 */ 11191 ins_encode( Push_Mem_I(src), 11192 Pop_Mem_F(dst)); 11193 ins_pipe( fpu_mem_mem ); 11194%} 11195 11196// In 24-bit mode, force exponent rounding by storing back out 11197instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{ 11198 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 11199 match(Set dst (ConvI2F (LoadI mem))); 11200 ins_cost(200); 11201 format %{ "FILD $mem\n\t" 11202 "FSTP_S $dst" %} 11203 opcode(0xDB); /* DB /0 */ 11204 ins_encode( OpcP, RMopc_Mem(0x00,mem), 11205 Pop_Mem_F(dst)); 11206 ins_pipe( fpu_mem_mem ); 11207%} 11208 11209// This instruction does not round to 24-bits 11210instruct convI2F_reg(regF dst, stackSlotI src) %{ 11211 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11212 match(Set dst (ConvI2F src)); 11213 format %{ "FILD $src\n\t" 11214 "FSTP $dst" %} 11215 opcode(0xDB, 0x0); /* DB /0 */ 11216 ins_encode( Push_Mem_I(src), 11217 Pop_Reg_F(dst)); 11218 ins_pipe( fpu_reg_mem ); 11219%} 11220 11221// This instruction does not round to 24-bits 11222instruct convI2F_mem(regF dst, memory mem) %{ 11223 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11224 match(Set dst (ConvI2F (LoadI mem))); 11225 format %{ "FILD $mem\n\t" 11226 "FSTP $dst" %} 11227 opcode(0xDB); /* DB /0 */ 11228 ins_encode( OpcP, RMopc_Mem(0x00,mem), 11229 Pop_Reg_F(dst)); 11230 ins_pipe( fpu_reg_mem ); 11231%} 11232 11233// Convert an int to a float in xmm; no rounding step needed. 11234instruct convI2X_reg(regX dst, eRegI src) %{ 11235 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); 11236 match(Set dst (ConvI2F src)); 11237 format %{ "CVTSI2SS $dst, $src" %} 11238 11239 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */ 11240 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 11241 ins_pipe( pipe_slow ); 11242%} 11243 11244 instruct convXI2X_reg(regX dst, eRegI src) 11245%{ 11246 predicate( UseSSE>=2 && UseXmmI2F ); 11247 match(Set dst (ConvI2F src)); 11248 11249 format %{ "MOVD $dst,$src\n\t" 11250 "CVTDQ2PS $dst,$dst\t# i2f" %} 11251 ins_encode %{ 11252 __ movd($dst$$XMMRegister, $src$$Register); 11253 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); 11254 %} 11255 ins_pipe(pipe_slow); // XXX 11256%} 11257 11258instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{ 11259 match(Set dst (ConvI2L src)); 11260 effect(KILL cr); 11261 format %{ "MOV $dst.lo,$src\n\t" 11262 "MOV $dst.hi,$src\n\t" 11263 "SAR $dst.hi,31" %} 11264 ins_encode(convert_int_long(dst,src)); 11265 ins_pipe( ialu_reg_reg_long ); 11266%} 11267 11268// Zero-extend convert int to long 11269instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{ 11270 match(Set dst (AndL (ConvI2L src) mask) ); 11271 effect( KILL flags ); 11272 format %{ "MOV $dst.lo,$src\n\t" 11273 "XOR $dst.hi,$dst.hi" %} 11274 opcode(0x33); // XOR 11275 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); 11276 ins_pipe( ialu_reg_reg_long ); 11277%} 11278 11279// Zero-extend long 11280instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ 11281 match(Set dst (AndL src mask) ); 11282 effect( KILL flags ); 11283 format %{ "MOV $dst.lo,$src.lo\n\t" 11284 "XOR $dst.hi,$dst.hi\n\t" %} 11285 opcode(0x33); // XOR 11286 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); 11287 ins_pipe( ialu_reg_reg_long ); 11288%} 11289 11290instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ 11291 predicate (UseSSE<=1); 11292 match(Set dst (ConvL2D src)); 11293 effect( KILL cr ); 11294 format %{ "PUSH $src.hi\t# Convert long to double\n\t" 11295 "PUSH $src.lo\n\t" 11296 "FILD ST,[ESP + #0]\n\t" 11297 "ADD ESP,8\n\t" 11298 "FSTP_D $dst\t# D-round" %} 11299 opcode(0xDF, 0x5); /* DF /5 */ 11300 ins_encode(convert_long_double(src), Pop_Mem_D(dst)); 11301 ins_pipe( pipe_slow ); 11302%} 11303 11304instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{ 11305 predicate (UseSSE>=2); 11306 match(Set dst (ConvL2D src)); 11307 effect( KILL cr ); 11308 format %{ "PUSH $src.hi\t# Convert long to double\n\t" 11309 "PUSH $src.lo\n\t" 11310 "FILD_D [ESP]\n\t" 11311 "FSTP_D [ESP]\n\t" 11312 "MOVSD $dst,[ESP]\n\t" 11313 "ADD ESP,8" %} 11314 opcode(0xDF, 0x5); /* DF /5 */ 11315 ins_encode(convert_long_double2(src), Push_ResultXD(dst)); 11316 ins_pipe( pipe_slow ); 11317%} 11318 11319instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{ 11320 predicate (UseSSE>=1); 11321 match(Set dst (ConvL2F src)); 11322 effect( KILL cr ); 11323 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" 11324 "PUSH $src.lo\n\t" 11325 "FILD_D [ESP]\n\t" 11326 "FSTP_S [ESP]\n\t" 11327 "MOVSS $dst,[ESP]\n\t" 11328 "ADD ESP,8" %} 11329 opcode(0xDF, 0x5); /* DF /5 */ 11330 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8)); 11331 ins_pipe( pipe_slow ); 11332%} 11333 11334instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ 11335 match(Set dst (ConvL2F src)); 11336 effect( KILL cr ); 11337 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" 11338 "PUSH $src.lo\n\t" 11339 "FILD ST,[ESP + #0]\n\t" 11340 "ADD ESP,8\n\t" 11341 "FSTP_S $dst\t# F-round" %} 11342 opcode(0xDF, 0x5); /* DF /5 */ 11343 ins_encode(convert_long_double(src), Pop_Mem_F(dst)); 11344 ins_pipe( pipe_slow ); 11345%} 11346 11347instruct convL2I_reg( eRegI dst, eRegL src ) %{ 11348 match(Set dst (ConvL2I src)); 11349 effect( DEF dst, USE src ); 11350 format %{ "MOV $dst,$src.lo" %} 11351 ins_encode(enc_CopyL_Lo(dst,src)); 11352 ins_pipe( ialu_reg_reg ); 11353%} 11354 11355 11356instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{ 11357 match(Set dst (MoveF2I src)); 11358 effect( DEF dst, USE src ); 11359 ins_cost(100); 11360 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} 11361 opcode(0x8B); 11362 ins_encode( OpcP, RegMem(dst,src)); 11363 ins_pipe( ialu_reg_mem ); 11364%} 11365 11366instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 11367 predicate(UseSSE==0); 11368 match(Set dst (MoveF2I src)); 11369 effect( DEF dst, USE src ); 11370 11371 ins_cost(125); 11372 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} 11373 ins_encode( Pop_Mem_Reg_F(dst, src) ); 11374 ins_pipe( fpu_mem_reg ); 11375%} 11376 11377instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{ 11378 predicate(UseSSE>=1); 11379 match(Set dst (MoveF2I src)); 11380 effect( DEF dst, USE src ); 11381 11382 ins_cost(95); 11383 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} 11384 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst)); 11385 ins_pipe( pipe_slow ); 11386%} 11387 11388instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{ 11389 predicate(UseSSE>=2); 11390 match(Set dst (MoveF2I src)); 11391 effect( DEF dst, USE src ); 11392 ins_cost(85); 11393 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} 11394 ins_encode( MovX2I_reg(dst, src)); 11395 ins_pipe( pipe_slow ); 11396%} 11397 11398instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{ 11399 match(Set dst (MoveI2F src)); 11400 effect( DEF dst, USE src ); 11401 11402 ins_cost(100); 11403 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} 11404 opcode(0x89); 11405 ins_encode( OpcPRegSS( dst, src ) ); 11406 ins_pipe( ialu_mem_reg ); 11407%} 11408 11409 11410instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 11411 predicate(UseSSE==0); 11412 match(Set dst (MoveI2F src)); 11413 effect(DEF dst, USE src); 11414 11415 ins_cost(125); 11416 format %{ "FLD_S $src\n\t" 11417 "FSTP $dst\t# MoveI2F_stack_reg" %} 11418 opcode(0xD9); /* D9 /0, FLD m32real */ 11419 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 11420 Pop_Reg_F(dst) ); 11421 ins_pipe( fpu_reg_mem ); 11422%} 11423 11424instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{ 11425 predicate(UseSSE>=1); 11426 match(Set dst (MoveI2F src)); 11427 effect( DEF dst, USE src ); 11428 11429 ins_cost(95); 11430 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} 11431 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src)); 11432 ins_pipe( pipe_slow ); 11433%} 11434 11435instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{ 11436 predicate(UseSSE>=2); 11437 match(Set dst (MoveI2F src)); 11438 effect( DEF dst, USE src ); 11439 11440 ins_cost(85); 11441 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} 11442 ins_encode( MovI2X_reg(dst, src) ); 11443 ins_pipe( pipe_slow ); 11444%} 11445 11446instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ 11447 match(Set dst (MoveD2L src)); 11448 effect(DEF dst, USE src); 11449 11450 ins_cost(250); 11451 format %{ "MOV $dst.lo,$src\n\t" 11452 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} 11453 opcode(0x8B, 0x8B); 11454 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); 11455 ins_pipe( ialu_mem_long_reg ); 11456%} 11457 11458instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 11459 predicate(UseSSE<=1); 11460 match(Set dst (MoveD2L src)); 11461 effect(DEF dst, USE src); 11462 11463 ins_cost(125); 11464 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} 11465 ins_encode( Pop_Mem_Reg_D(dst, src) ); 11466 ins_pipe( fpu_mem_reg ); 11467%} 11468 11469instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{ 11470 predicate(UseSSE>=2); 11471 match(Set dst (MoveD2L src)); 11472 effect(DEF dst, USE src); 11473 ins_cost(95); 11474 11475 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} 11476 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst)); 11477 ins_pipe( pipe_slow ); 11478%} 11479 11480instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{ 11481 predicate(UseSSE>=2); 11482 match(Set dst (MoveD2L src)); 11483 effect(DEF dst, USE src, TEMP tmp); 11484 ins_cost(85); 11485 format %{ "MOVD $dst.lo,$src\n\t" 11486 "PSHUFLW $tmp,$src,0x4E\n\t" 11487 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} 11488 ins_encode( MovXD2L_reg(dst, src, tmp) ); 11489 ins_pipe( pipe_slow ); 11490%} 11491 11492instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ 11493 match(Set dst (MoveL2D src)); 11494 effect(DEF dst, USE src); 11495 11496 ins_cost(200); 11497 format %{ "MOV $dst,$src.lo\n\t" 11498 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} 11499 opcode(0x89, 0x89); 11500 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); 11501 ins_pipe( ialu_mem_long_reg ); 11502%} 11503 11504 11505instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 11506 predicate(UseSSE<=1); 11507 match(Set dst (MoveL2D src)); 11508 effect(DEF dst, USE src); 11509 ins_cost(125); 11510 11511 format %{ "FLD_D $src\n\t" 11512 "FSTP $dst\t# MoveL2D_stack_reg" %} 11513 opcode(0xDD); /* DD /0, FLD m64real */ 11514 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 11515 Pop_Reg_D(dst) ); 11516 ins_pipe( fpu_reg_mem ); 11517%} 11518 11519 11520instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{ 11521 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); 11522 match(Set dst (MoveL2D src)); 11523 effect(DEF dst, USE src); 11524 11525 ins_cost(95); 11526 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} 11527 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src)); 11528 ins_pipe( pipe_slow ); 11529%} 11530 11531instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{ 11532 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); 11533 match(Set dst (MoveL2D src)); 11534 effect(DEF dst, USE src); 11535 11536 ins_cost(95); 11537 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} 11538 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src)); 11539 ins_pipe( pipe_slow ); 11540%} 11541 11542instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{ 11543 predicate(UseSSE>=2); 11544 match(Set dst (MoveL2D src)); 11545 effect(TEMP dst, USE src, TEMP tmp); 11546 ins_cost(85); 11547 format %{ "MOVD $dst,$src.lo\n\t" 11548 "MOVD $tmp,$src.hi\n\t" 11549 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} 11550 ins_encode( MovL2XD_reg(dst, src, tmp) ); 11551 ins_pipe( pipe_slow ); 11552%} 11553 11554// Replicate scalar to packed byte (1 byte) values in xmm 11555instruct Repl8B_reg(regXD dst, regXD src) %{ 11556 predicate(UseSSE>=2); 11557 match(Set dst (Replicate8B src)); 11558 format %{ "MOVDQA $dst,$src\n\t" 11559 "PUNPCKLBW $dst,$dst\n\t" 11560 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} 11561 ins_encode( pshufd_8x8(dst, src)); 11562 ins_pipe( pipe_slow ); 11563%} 11564 11565// Replicate scalar to packed byte (1 byte) values in xmm 11566instruct Repl8B_eRegI(regXD dst, eRegI src) %{ 11567 predicate(UseSSE>=2); 11568 match(Set dst (Replicate8B src)); 11569 format %{ "MOVD $dst,$src\n\t" 11570 "PUNPCKLBW $dst,$dst\n\t" 11571 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} 11572 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst)); 11573 ins_pipe( pipe_slow ); 11574%} 11575 11576// Replicate scalar zero to packed byte (1 byte) values in xmm 11577instruct Repl8B_immI0(regXD dst, immI0 zero) %{ 11578 predicate(UseSSE>=2); 11579 match(Set dst (Replicate8B zero)); 11580 format %{ "PXOR $dst,$dst\t! replicate8B" %} 11581 ins_encode( pxor(dst, dst)); 11582 ins_pipe( fpu_reg_reg ); 11583%} 11584 11585// Replicate scalar to packed shore (2 byte) values in xmm 11586instruct Repl4S_reg(regXD dst, regXD src) %{ 11587 predicate(UseSSE>=2); 11588 match(Set dst (Replicate4S src)); 11589 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} 11590 ins_encode( pshufd_4x16(dst, src)); 11591 ins_pipe( fpu_reg_reg ); 11592%} 11593 11594// Replicate scalar to packed shore (2 byte) values in xmm 11595instruct Repl4S_eRegI(regXD dst, eRegI src) %{ 11596 predicate(UseSSE>=2); 11597 match(Set dst (Replicate4S src)); 11598 format %{ "MOVD $dst,$src\n\t" 11599 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} 11600 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); 11601 ins_pipe( fpu_reg_reg ); 11602%} 11603 11604// Replicate scalar zero to packed short (2 byte) values in xmm 11605instruct Repl4S_immI0(regXD dst, immI0 zero) %{ 11606 predicate(UseSSE>=2); 11607 match(Set dst (Replicate4S zero)); 11608 format %{ "PXOR $dst,$dst\t! replicate4S" %} 11609 ins_encode( pxor(dst, dst)); 11610 ins_pipe( fpu_reg_reg ); 11611%} 11612 11613// Replicate scalar to packed char (2 byte) values in xmm 11614instruct Repl4C_reg(regXD dst, regXD src) %{ 11615 predicate(UseSSE>=2); 11616 match(Set dst (Replicate4C src)); 11617 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} 11618 ins_encode( pshufd_4x16(dst, src)); 11619 ins_pipe( fpu_reg_reg ); 11620%} 11621 11622// Replicate scalar to packed char (2 byte) values in xmm 11623instruct Repl4C_eRegI(regXD dst, eRegI src) %{ 11624 predicate(UseSSE>=2); 11625 match(Set dst (Replicate4C src)); 11626 format %{ "MOVD $dst,$src\n\t" 11627 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} 11628 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); 11629 ins_pipe( fpu_reg_reg ); 11630%} 11631 11632// Replicate scalar zero to packed char (2 byte) values in xmm 11633instruct Repl4C_immI0(regXD dst, immI0 zero) %{ 11634 predicate(UseSSE>=2); 11635 match(Set dst (Replicate4C zero)); 11636 format %{ "PXOR $dst,$dst\t! replicate4C" %} 11637 ins_encode( pxor(dst, dst)); 11638 ins_pipe( fpu_reg_reg ); 11639%} 11640 11641// Replicate scalar to packed integer (4 byte) values in xmm 11642instruct Repl2I_reg(regXD dst, regXD src) %{ 11643 predicate(UseSSE>=2); 11644 match(Set dst (Replicate2I src)); 11645 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} 11646 ins_encode( pshufd(dst, src, 0x00)); 11647 ins_pipe( fpu_reg_reg ); 11648%} 11649 11650// Replicate scalar to packed integer (4 byte) values in xmm 11651instruct Repl2I_eRegI(regXD dst, eRegI src) %{ 11652 predicate(UseSSE>=2); 11653 match(Set dst (Replicate2I src)); 11654 format %{ "MOVD $dst,$src\n\t" 11655 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} 11656 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00)); 11657 ins_pipe( fpu_reg_reg ); 11658%} 11659 11660// Replicate scalar zero to packed integer (2 byte) values in xmm 11661instruct Repl2I_immI0(regXD dst, immI0 zero) %{ 11662 predicate(UseSSE>=2); 11663 match(Set dst (Replicate2I zero)); 11664 format %{ "PXOR $dst,$dst\t! replicate2I" %} 11665 ins_encode( pxor(dst, dst)); 11666 ins_pipe( fpu_reg_reg ); 11667%} 11668 11669// Replicate scalar to packed single precision floating point values in xmm 11670instruct Repl2F_reg(regXD dst, regXD src) %{ 11671 predicate(UseSSE>=2); 11672 match(Set dst (Replicate2F src)); 11673 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} 11674 ins_encode( pshufd(dst, src, 0xe0)); 11675 ins_pipe( fpu_reg_reg ); 11676%} 11677 11678// Replicate scalar to packed single precision floating point values in xmm 11679instruct Repl2F_regX(regXD dst, regX src) %{ 11680 predicate(UseSSE>=2); 11681 match(Set dst (Replicate2F src)); 11682 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} 11683 ins_encode( pshufd(dst, src, 0xe0)); 11684 ins_pipe( fpu_reg_reg ); 11685%} 11686 11687// Replicate scalar to packed single precision floating point values in xmm 11688instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{ 11689 predicate(UseSSE>=2); 11690 match(Set dst (Replicate2F zero)); 11691 format %{ "PXOR $dst,$dst\t! replicate2F" %} 11692 ins_encode( pxor(dst, dst)); 11693 ins_pipe( fpu_reg_reg ); 11694%} 11695 11696 11697 11698// ======================================================================= 11699// fast clearing of an array 11700 11701instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ 11702 match(Set dummy (ClearArray cnt base)); 11703 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); 11704 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t" 11705 "XOR EAX,EAX\n\t" 11706 "REP STOS\t# store EAX into [EDI++] while ECX--" %} 11707 opcode(0,0x4); 11708 ins_encode( Opcode(0xD1), RegOpc(ECX), 11709 OpcRegReg(0x33,EAX,EAX), 11710 Opcode(0xF3), Opcode(0xAB) ); 11711 ins_pipe( pipe_slow ); 11712%} 11713 11714instruct string_compare(eDIRegP str1, eSIRegP str2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{ 11715 match(Set result (StrComp str1 str2)); 11716 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL cr); 11717 //ins_cost(300); 11718 11719 format %{ "String Compare $str1,$str2 -> $result // KILL EAX, EBX" %} 11720 ins_encode( enc_String_Compare() ); 11721 ins_pipe( pipe_slow ); 11722%} 11723 11724// fast array equals 11725instruct array_equals(eDIRegP ary1, eSIRegP ary2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{ 11726 match(Set result (AryEq ary1 ary2)); 11727 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL cr); 11728 //ins_cost(300); 11729 11730 format %{ "Array Equals $ary1,$ary2 -> $result // KILL EAX, EBX" %} 11731 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result) ); 11732 ins_pipe( pipe_slow ); 11733%} 11734 11735//----------Control Flow Instructions------------------------------------------ 11736// Signed compare Instructions 11737instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{ 11738 match(Set cr (CmpI op1 op2)); 11739 effect( DEF cr, USE op1, USE op2 ); 11740 format %{ "CMP $op1,$op2" %} 11741 opcode(0x3B); /* Opcode 3B /r */ 11742 ins_encode( OpcP, RegReg( op1, op2) ); 11743 ins_pipe( ialu_cr_reg_reg ); 11744%} 11745 11746instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{ 11747 match(Set cr (CmpI op1 op2)); 11748 effect( DEF cr, USE op1 ); 11749 format %{ "CMP $op1,$op2" %} 11750 opcode(0x81,0x07); /* Opcode 81 /7 */ 11751 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ 11752 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 11753 ins_pipe( ialu_cr_reg_imm ); 11754%} 11755 11756// Cisc-spilled version of cmpI_eReg 11757instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{ 11758 match(Set cr (CmpI op1 (LoadI op2))); 11759 11760 format %{ "CMP $op1,$op2" %} 11761 ins_cost(500); 11762 opcode(0x3B); /* Opcode 3B /r */ 11763 ins_encode( OpcP, RegMem( op1, op2) ); 11764 ins_pipe( ialu_cr_reg_mem ); 11765%} 11766 11767instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{ 11768 match(Set cr (CmpI src zero)); 11769 effect( DEF cr, USE src ); 11770 11771 format %{ "TEST $src,$src" %} 11772 opcode(0x85); 11773 ins_encode( OpcP, RegReg( src, src ) ); 11774 ins_pipe( ialu_cr_reg_imm ); 11775%} 11776 11777instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{ 11778 match(Set cr (CmpI (AndI src con) zero)); 11779 11780 format %{ "TEST $src,$con" %} 11781 opcode(0xF7,0x00); 11782 ins_encode( OpcP, RegOpc(src), Con32(con) ); 11783 ins_pipe( ialu_cr_reg_imm ); 11784%} 11785 11786instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{ 11787 match(Set cr (CmpI (AndI src mem) zero)); 11788 11789 format %{ "TEST $src,$mem" %} 11790 opcode(0x85); 11791 ins_encode( OpcP, RegMem( src, mem ) ); 11792 ins_pipe( ialu_cr_reg_mem ); 11793%} 11794 11795// Unsigned compare Instructions; really, same as signed except they 11796// produce an eFlagsRegU instead of eFlagsReg. 11797instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{ 11798 match(Set cr (CmpU op1 op2)); 11799 11800 format %{ "CMPu $op1,$op2" %} 11801 opcode(0x3B); /* Opcode 3B /r */ 11802 ins_encode( OpcP, RegReg( op1, op2) ); 11803 ins_pipe( ialu_cr_reg_reg ); 11804%} 11805 11806instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{ 11807 match(Set cr (CmpU op1 op2)); 11808 11809 format %{ "CMPu $op1,$op2" %} 11810 opcode(0x81,0x07); /* Opcode 81 /7 */ 11811 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 11812 ins_pipe( ialu_cr_reg_imm ); 11813%} 11814 11815// // Cisc-spilled version of cmpU_eReg 11816instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{ 11817 match(Set cr (CmpU op1 (LoadI op2))); 11818 11819 format %{ "CMPu $op1,$op2" %} 11820 ins_cost(500); 11821 opcode(0x3B); /* Opcode 3B /r */ 11822 ins_encode( OpcP, RegMem( op1, op2) ); 11823 ins_pipe( ialu_cr_reg_mem ); 11824%} 11825 11826// // Cisc-spilled version of cmpU_eReg 11827//instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{ 11828// match(Set cr (CmpU (LoadI op1) op2)); 11829// 11830// format %{ "CMPu $op1,$op2" %} 11831// ins_cost(500); 11832// opcode(0x39); /* Opcode 39 /r */ 11833// ins_encode( OpcP, RegMem( op1, op2) ); 11834//%} 11835 11836instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{ 11837 match(Set cr (CmpU src zero)); 11838 11839 format %{ "TESTu $src,$src" %} 11840 opcode(0x85); 11841 ins_encode( OpcP, RegReg( src, src ) ); 11842 ins_pipe( ialu_cr_reg_imm ); 11843%} 11844 11845// Unsigned pointer compare Instructions 11846instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ 11847 match(Set cr (CmpP op1 op2)); 11848 11849 format %{ "CMPu $op1,$op2" %} 11850 opcode(0x3B); /* Opcode 3B /r */ 11851 ins_encode( OpcP, RegReg( op1, op2) ); 11852 ins_pipe( ialu_cr_reg_reg ); 11853%} 11854 11855instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ 11856 match(Set cr (CmpP op1 op2)); 11857 11858 format %{ "CMPu $op1,$op2" %} 11859 opcode(0x81,0x07); /* Opcode 81 /7 */ 11860 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 11861 ins_pipe( ialu_cr_reg_imm ); 11862%} 11863 11864// // Cisc-spilled version of cmpP_eReg 11865instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ 11866 match(Set cr (CmpP op1 (LoadP op2))); 11867 11868 format %{ "CMPu $op1,$op2" %} 11869 ins_cost(500); 11870 opcode(0x3B); /* Opcode 3B /r */ 11871 ins_encode( OpcP, RegMem( op1, op2) ); 11872 ins_pipe( ialu_cr_reg_mem ); 11873%} 11874 11875// // Cisc-spilled version of cmpP_eReg 11876//instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ 11877// match(Set cr (CmpP (LoadP op1) op2)); 11878// 11879// format %{ "CMPu $op1,$op2" %} 11880// ins_cost(500); 11881// opcode(0x39); /* Opcode 39 /r */ 11882// ins_encode( OpcP, RegMem( op1, op2) ); 11883//%} 11884 11885// Compare raw pointer (used in out-of-heap check). 11886// Only works because non-oop pointers must be raw pointers 11887// and raw pointers have no anti-dependencies. 11888instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ 11889 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() ); 11890 match(Set cr (CmpP op1 (LoadP op2))); 11891 11892 format %{ "CMPu $op1,$op2" %} 11893 opcode(0x3B); /* Opcode 3B /r */ 11894 ins_encode( OpcP, RegMem( op1, op2) ); 11895 ins_pipe( ialu_cr_reg_mem ); 11896%} 11897 11898// 11899// This will generate a signed flags result. This should be ok 11900// since any compare to a zero should be eq/neq. 11901instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ 11902 match(Set cr (CmpP src zero)); 11903 11904 format %{ "TEST $src,$src" %} 11905 opcode(0x85); 11906 ins_encode( OpcP, RegReg( src, src ) ); 11907 ins_pipe( ialu_cr_reg_imm ); 11908%} 11909 11910// Cisc-spilled version of testP_reg 11911// This will generate a signed flags result. This should be ok 11912// since any compare to a zero should be eq/neq. 11913instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ 11914 match(Set cr (CmpP (LoadP op) zero)); 11915 11916 format %{ "TEST $op,0xFFFFFFFF" %} 11917 ins_cost(500); 11918 opcode(0xF7); /* Opcode F7 /0 */ 11919 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); 11920 ins_pipe( ialu_cr_reg_imm ); 11921%} 11922 11923// Yanked all unsigned pointer compare operations. 11924// Pointer compares are done with CmpP which is already unsigned. 11925 11926//----------Max and Min-------------------------------------------------------- 11927// Min Instructions 11928//// 11929// *** Min and Max using the conditional move are slower than the 11930// *** branch version on a Pentium III. 11931// // Conditional move for min 11932//instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ 11933// effect( USE_DEF op2, USE op1, USE cr ); 11934// format %{ "CMOVlt $op2,$op1\t! min" %} 11935// opcode(0x4C,0x0F); 11936// ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); 11937// ins_pipe( pipe_cmov_reg ); 11938//%} 11939// 11940//// Min Register with Register (P6 version) 11941//instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{ 11942// predicate(VM_Version::supports_cmov() ); 11943// match(Set op2 (MinI op1 op2)); 11944// ins_cost(200); 11945// expand %{ 11946// eFlagsReg cr; 11947// compI_eReg(cr,op1,op2); 11948// cmovI_reg_lt(op2,op1,cr); 11949// %} 11950//%} 11951 11952// Min Register with Register (generic version) 11953instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ 11954 match(Set dst (MinI dst src)); 11955 effect(KILL flags); 11956 ins_cost(300); 11957 11958 format %{ "MIN $dst,$src" %} 11959 opcode(0xCC); 11960 ins_encode( min_enc(dst,src) ); 11961 ins_pipe( pipe_slow ); 11962%} 11963 11964// Max Register with Register 11965// *** Min and Max using the conditional move are slower than the 11966// *** branch version on a Pentium III. 11967// // Conditional move for max 11968//instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ 11969// effect( USE_DEF op2, USE op1, USE cr ); 11970// format %{ "CMOVgt $op2,$op1\t! max" %} 11971// opcode(0x4F,0x0F); 11972// ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); 11973// ins_pipe( pipe_cmov_reg ); 11974//%} 11975// 11976// // Max Register with Register (P6 version) 11977//instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{ 11978// predicate(VM_Version::supports_cmov() ); 11979// match(Set op2 (MaxI op1 op2)); 11980// ins_cost(200); 11981// expand %{ 11982// eFlagsReg cr; 11983// compI_eReg(cr,op1,op2); 11984// cmovI_reg_gt(op2,op1,cr); 11985// %} 11986//%} 11987 11988// Max Register with Register (generic version) 11989instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ 11990 match(Set dst (MaxI dst src)); 11991 effect(KILL flags); 11992 ins_cost(300); 11993 11994 format %{ "MAX $dst,$src" %} 11995 opcode(0xCC); 11996 ins_encode( max_enc(dst,src) ); 11997 ins_pipe( pipe_slow ); 11998%} 11999 12000// ============================================================================ 12001// Branch Instructions 12002// Jump Table 12003instruct jumpXtnd(eRegI switch_val) %{ 12004 match(Jump switch_val); 12005 ins_cost(350); 12006 12007 format %{ "JMP [table_base](,$switch_val,1)\n\t" %} 12008 12009 ins_encode %{ 12010 address table_base = __ address_table_constant(_index2label); 12011 12012 // Jump to Address(table_base + switch_reg) 12013 InternalAddress table(table_base); 12014 Address index(noreg, $switch_val$$Register, Address::times_1); 12015 __ jump(ArrayAddress(table, index)); 12016 %} 12017 ins_pc_relative(1); 12018 ins_pipe(pipe_jmp); 12019%} 12020 12021// Jump Direct - Label defines a relative address from JMP+1 12022instruct jmpDir(label labl) %{ 12023 match(Goto); 12024 effect(USE labl); 12025 12026 ins_cost(300); 12027 format %{ "JMP $labl" %} 12028 size(5); 12029 opcode(0xE9); 12030 ins_encode( OpcP, Lbl( labl ) ); 12031 ins_pipe( pipe_jmp ); 12032 ins_pc_relative(1); 12033%} 12034 12035// Jump Direct Conditional - Label defines a relative address from Jcc+1 12036instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ 12037 match(If cop cr); 12038 effect(USE labl); 12039 12040 ins_cost(300); 12041 format %{ "J$cop $labl" %} 12042 size(6); 12043 opcode(0x0F, 0x80); 12044 ins_encode( Jcc( cop, labl) ); 12045 ins_pipe( pipe_jcc ); 12046 ins_pc_relative(1); 12047%} 12048 12049// Jump Direct Conditional - Label defines a relative address from Jcc+1 12050instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ 12051 match(CountedLoopEnd cop cr); 12052 effect(USE labl); 12053 12054 ins_cost(300); 12055 format %{ "J$cop $labl\t# Loop end" %} 12056 size(6); 12057 opcode(0x0F, 0x80); 12058 ins_encode( Jcc( cop, labl) ); 12059 ins_pipe( pipe_jcc ); 12060 ins_pc_relative(1); 12061%} 12062 12063// Jump Direct Conditional - Label defines a relative address from Jcc+1 12064instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12065 match(CountedLoopEnd cop cmp); 12066 effect(USE labl); 12067 12068 ins_cost(300); 12069 format %{ "J$cop,u $labl\t# Loop end" %} 12070 size(6); 12071 opcode(0x0F, 0x80); 12072 ins_encode( Jcc( cop, labl) ); 12073 ins_pipe( pipe_jcc ); 12074 ins_pc_relative(1); 12075%} 12076 12077// Jump Direct Conditional - using unsigned comparison 12078instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12079 match(If cop cmp); 12080 effect(USE labl); 12081 12082 ins_cost(300); 12083 format %{ "J$cop,u $labl" %} 12084 size(6); 12085 opcode(0x0F, 0x80); 12086 ins_encode( Jcc( cop, labl) ); 12087 ins_pipe( pipe_jcc ); 12088 ins_pc_relative(1); 12089%} 12090 12091// ============================================================================ 12092// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 12093// array for an instance of the superklass. Set a hidden internal cache on a 12094// hit (cache is checked with exposed code in gen_subtype_check()). Return 12095// NZ for a miss or zero for a hit. The encoding ALSO sets flags. 12096instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ 12097 match(Set result (PartialSubtypeCheck sub super)); 12098 effect( KILL rcx, KILL cr ); 12099 12100 ins_cost(1100); // slightly larger than the next version 12101 format %{ "CMPL EAX,ESI\n\t" 12102 "JEQ,s hit\n\t" 12103 "MOV EDI,[$sub+Klass::secondary_supers]\n\t" 12104 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" 12105 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" 12106 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" 12107 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" 12108 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" 12109 "hit:\n\t" 12110 "XOR $result,$result\t\t Hit: EDI zero\n\t" 12111 "miss:\t" %} 12112 12113 opcode(0x1); // Force a XOR of EDI 12114 ins_encode( enc_PartialSubtypeCheck() ); 12115 ins_pipe( pipe_slow ); 12116%} 12117 12118instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ 12119 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); 12120 effect( KILL rcx, KILL result ); 12121 12122 ins_cost(1000); 12123 format %{ "CMPL EAX,ESI\n\t" 12124 "JEQ,s miss\t# Actually a hit; we are done.\n\t" 12125 "MOV EDI,[$sub+Klass::secondary_supers]\n\t" 12126 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" 12127 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" 12128 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" 12129 "JNE,s miss\t\t# Missed: flags NZ\n\t" 12130 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" 12131 "miss:\t" %} 12132 12133 opcode(0x0); // No need to XOR EDI 12134 ins_encode( enc_PartialSubtypeCheck() ); 12135 ins_pipe( pipe_slow ); 12136%} 12137 12138// ============================================================================ 12139// Branch Instructions -- short offset versions 12140// 12141// These instructions are used to replace jumps of a long offset (the default 12142// match) with jumps of a shorter offset. These instructions are all tagged 12143// with the ins_short_branch attribute, which causes the ADLC to suppress the 12144// match rules in general matching. Instead, the ADLC generates a conversion 12145// method in the MachNode which can be used to do in-place replacement of the 12146// long variant with the shorter variant. The compiler will determine if a 12147// branch can be taken by the is_short_branch_offset() predicate in the machine 12148// specific code section of the file. 12149 12150// Jump Direct - Label defines a relative address from JMP+1 12151instruct jmpDir_short(label labl) %{ 12152 match(Goto); 12153 effect(USE labl); 12154 12155 ins_cost(300); 12156 format %{ "JMP,s $labl" %} 12157 size(2); 12158 opcode(0xEB); 12159 ins_encode( OpcP, LblShort( labl ) ); 12160 ins_pipe( pipe_jmp ); 12161 ins_pc_relative(1); 12162 ins_short_branch(1); 12163%} 12164 12165// Jump Direct Conditional - Label defines a relative address from Jcc+1 12166instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ 12167 match(If cop cr); 12168 effect(USE labl); 12169 12170 ins_cost(300); 12171 format %{ "J$cop,s $labl" %} 12172 size(2); 12173 opcode(0x70); 12174 ins_encode( JccShort( cop, labl) ); 12175 ins_pipe( pipe_jcc ); 12176 ins_pc_relative(1); 12177 ins_short_branch(1); 12178%} 12179 12180// Jump Direct Conditional - Label defines a relative address from Jcc+1 12181instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ 12182 match(CountedLoopEnd cop cr); 12183 effect(USE labl); 12184 12185 ins_cost(300); 12186 format %{ "J$cop,s $labl" %} 12187 size(2); 12188 opcode(0x70); 12189 ins_encode( JccShort( cop, labl) ); 12190 ins_pipe( pipe_jcc ); 12191 ins_pc_relative(1); 12192 ins_short_branch(1); 12193%} 12194 12195// Jump Direct Conditional - Label defines a relative address from Jcc+1 12196instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12197 match(CountedLoopEnd cop cmp); 12198 effect(USE labl); 12199 12200 ins_cost(300); 12201 format %{ "J$cop,us $labl" %} 12202 size(2); 12203 opcode(0x70); 12204 ins_encode( JccShort( cop, labl) ); 12205 ins_pipe( pipe_jcc ); 12206 ins_pc_relative(1); 12207 ins_short_branch(1); 12208%} 12209 12210// Jump Direct Conditional - using unsigned comparison 12211instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12212 match(If cop cmp); 12213 effect(USE labl); 12214 12215 ins_cost(300); 12216 format %{ "J$cop,us $labl" %} 12217 size(2); 12218 opcode(0x70); 12219 ins_encode( JccShort( cop, labl) ); 12220 ins_pipe( pipe_jcc ); 12221 ins_pc_relative(1); 12222 ins_short_branch(1); 12223%} 12224 12225// ============================================================================ 12226// Long Compare 12227// 12228// Currently we hold longs in 2 registers. Comparing such values efficiently 12229// is tricky. The flavor of compare used depends on whether we are testing 12230// for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 12231// The GE test is the negated LT test. The LE test can be had by commuting 12232// the operands (yielding a GE test) and then negating; negate again for the 12233// GT test. The EQ test is done by ORcc'ing the high and low halves, and the 12234// NE test is negated from that. 12235 12236// Due to a shortcoming in the ADLC, it mixes up expressions like: 12237// (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 12238// difference between 'Y' and '0L'. The tree-matches for the CmpI sections 12239// are collapsed internally in the ADLC's dfa-gen code. The match for 12240// (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 12241// foo match ends up with the wrong leaf. One fix is to not match both 12242// reg-reg and reg-zero forms of long-compare. This is unfortunate because 12243// both forms beat the trinary form of long-compare and both are very useful 12244// on Intel which has so few registers. 12245 12246// Manifest a CmpL result in an integer register. Very painful. 12247// This is the test to avoid. 12248instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ 12249 match(Set dst (CmpL3 src1 src2)); 12250 effect( KILL flags ); 12251 ins_cost(1000); 12252 format %{ "XOR $dst,$dst\n\t" 12253 "CMP $src1.hi,$src2.hi\n\t" 12254 "JLT,s m_one\n\t" 12255 "JGT,s p_one\n\t" 12256 "CMP $src1.lo,$src2.lo\n\t" 12257 "JB,s m_one\n\t" 12258 "JEQ,s done\n" 12259 "p_one:\tINC $dst\n\t" 12260 "JMP,s done\n" 12261 "m_one:\tDEC $dst\n" 12262 "done:" %} 12263 ins_encode %{ 12264 Label p_one, m_one, done; 12265 __ xorl($dst$$Register, $dst$$Register); 12266 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); 12267 __ jccb(Assembler::less, m_one); 12268 __ jccb(Assembler::greater, p_one); 12269 __ cmpl($src1$$Register, $src2$$Register); 12270 __ jccb(Assembler::below, m_one); 12271 __ jccb(Assembler::equal, done); 12272 __ bind(p_one); 12273 __ increment($dst$$Register); 12274 __ jmpb(done); 12275 __ bind(m_one); 12276 __ decrement($dst$$Register); 12277 __ bind(done); 12278 %} 12279 ins_pipe( pipe_slow ); 12280%} 12281 12282//====== 12283// Manifest a CmpL result in the normal flags. Only good for LT or GE 12284// compares. Can be used for LE or GT compares by reversing arguments. 12285// NOT GOOD FOR EQ/NE tests. 12286instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ 12287 match( Set flags (CmpL src zero )); 12288 ins_cost(100); 12289 format %{ "TEST $src.hi,$src.hi" %} 12290 opcode(0x85); 12291 ins_encode( OpcP, RegReg_Hi2( src, src ) ); 12292 ins_pipe( ialu_cr_reg_reg ); 12293%} 12294 12295// Manifest a CmpL result in the normal flags. Only good for LT or GE 12296// compares. Can be used for LE or GT compares by reversing arguments. 12297// NOT GOOD FOR EQ/NE tests. 12298instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{ 12299 match( Set flags (CmpL src1 src2 )); 12300 effect( TEMP tmp ); 12301 ins_cost(300); 12302 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" 12303 "MOV $tmp,$src1.hi\n\t" 12304 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} 12305 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); 12306 ins_pipe( ialu_cr_reg_reg ); 12307%} 12308 12309// Long compares reg < zero/req OR reg >= zero/req. 12310// Just a wrapper for a normal branch, plus the predicate test. 12311instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ 12312 match(If cmp flags); 12313 effect(USE labl); 12314 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12315 expand %{ 12316 jmpCon(cmp,flags,labl); // JLT or JGE... 12317 %} 12318%} 12319 12320// Compare 2 longs and CMOVE longs. 12321instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ 12322 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 12323 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12324 ins_cost(400); 12325 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12326 "CMOV$cmp $dst.hi,$src.hi" %} 12327 opcode(0x0F,0x40); 12328 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 12329 ins_pipe( pipe_cmov_reg_long ); 12330%} 12331 12332instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ 12333 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 12334 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12335 ins_cost(500); 12336 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12337 "CMOV$cmp $dst.hi,$src.hi" %} 12338 opcode(0x0F,0x40); 12339 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 12340 ins_pipe( pipe_cmov_reg_long ); 12341%} 12342 12343// Compare 2 longs and CMOVE ints. 12344instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{ 12345 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12346 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 12347 ins_cost(200); 12348 format %{ "CMOV$cmp $dst,$src" %} 12349 opcode(0x0F,0x40); 12350 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12351 ins_pipe( pipe_cmov_reg ); 12352%} 12353 12354instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{ 12355 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12356 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 12357 ins_cost(250); 12358 format %{ "CMOV$cmp $dst,$src" %} 12359 opcode(0x0F,0x40); 12360 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 12361 ins_pipe( pipe_cmov_mem ); 12362%} 12363 12364// Compare 2 longs and CMOVE ints. 12365instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ 12366 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12367 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 12368 ins_cost(200); 12369 format %{ "CMOV$cmp $dst,$src" %} 12370 opcode(0x0F,0x40); 12371 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12372 ins_pipe( pipe_cmov_reg ); 12373%} 12374 12375// Compare 2 longs and CMOVE doubles 12376instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ 12377 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12378 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12379 ins_cost(200); 12380 expand %{ 12381 fcmovD_regS(cmp,flags,dst,src); 12382 %} 12383%} 12384 12385// Compare 2 longs and CMOVE doubles 12386instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{ 12387 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12388 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12389 ins_cost(200); 12390 expand %{ 12391 fcmovXD_regS(cmp,flags,dst,src); 12392 %} 12393%} 12394 12395instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ 12396 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12397 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12398 ins_cost(200); 12399 expand %{ 12400 fcmovF_regS(cmp,flags,dst,src); 12401 %} 12402%} 12403 12404instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{ 12405 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12406 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12407 ins_cost(200); 12408 expand %{ 12409 fcmovX_regS(cmp,flags,dst,src); 12410 %} 12411%} 12412 12413//====== 12414// Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. 12415instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{ 12416 match( Set flags (CmpL src zero )); 12417 effect(TEMP tmp); 12418 ins_cost(200); 12419 format %{ "MOV $tmp,$src.lo\n\t" 12420 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} 12421 ins_encode( long_cmp_flags0( src, tmp ) ); 12422 ins_pipe( ialu_reg_reg_long ); 12423%} 12424 12425// Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. 12426instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ 12427 match( Set flags (CmpL src1 src2 )); 12428 ins_cost(200+300); 12429 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" 12430 "JNE,s skip\n\t" 12431 "CMP $src1.hi,$src2.hi\n\t" 12432 "skip:\t" %} 12433 ins_encode( long_cmp_flags1( src1, src2 ) ); 12434 ins_pipe( ialu_cr_reg_reg ); 12435%} 12436 12437// Long compare reg == zero/reg OR reg != zero/reg 12438// Just a wrapper for a normal branch, plus the predicate test. 12439instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ 12440 match(If cmp flags); 12441 effect(USE labl); 12442 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12443 expand %{ 12444 jmpCon(cmp,flags,labl); // JEQ or JNE... 12445 %} 12446%} 12447 12448// Compare 2 longs and CMOVE longs. 12449instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ 12450 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 12451 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12452 ins_cost(400); 12453 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12454 "CMOV$cmp $dst.hi,$src.hi" %} 12455 opcode(0x0F,0x40); 12456 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 12457 ins_pipe( pipe_cmov_reg_long ); 12458%} 12459 12460instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ 12461 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 12462 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12463 ins_cost(500); 12464 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12465 "CMOV$cmp $dst.hi,$src.hi" %} 12466 opcode(0x0F,0x40); 12467 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 12468 ins_pipe( pipe_cmov_reg_long ); 12469%} 12470 12471// Compare 2 longs and CMOVE ints. 12472instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{ 12473 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12474 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 12475 ins_cost(200); 12476 format %{ "CMOV$cmp $dst,$src" %} 12477 opcode(0x0F,0x40); 12478 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12479 ins_pipe( pipe_cmov_reg ); 12480%} 12481 12482instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{ 12483 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12484 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 12485 ins_cost(250); 12486 format %{ "CMOV$cmp $dst,$src" %} 12487 opcode(0x0F,0x40); 12488 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 12489 ins_pipe( pipe_cmov_mem ); 12490%} 12491 12492// Compare 2 longs and CMOVE ints. 12493instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ 12494 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12495 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 12496 ins_cost(200); 12497 format %{ "CMOV$cmp $dst,$src" %} 12498 opcode(0x0F,0x40); 12499 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12500 ins_pipe( pipe_cmov_reg ); 12501%} 12502 12503// Compare 2 longs and CMOVE doubles 12504instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ 12505 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12506 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12507 ins_cost(200); 12508 expand %{ 12509 fcmovD_regS(cmp,flags,dst,src); 12510 %} 12511%} 12512 12513// Compare 2 longs and CMOVE doubles 12514instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{ 12515 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12516 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12517 ins_cost(200); 12518 expand %{ 12519 fcmovXD_regS(cmp,flags,dst,src); 12520 %} 12521%} 12522 12523instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ 12524 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12525 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12526 ins_cost(200); 12527 expand %{ 12528 fcmovF_regS(cmp,flags,dst,src); 12529 %} 12530%} 12531 12532instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{ 12533 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12534 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12535 ins_cost(200); 12536 expand %{ 12537 fcmovX_regS(cmp,flags,dst,src); 12538 %} 12539%} 12540 12541//====== 12542// Manifest a CmpL result in the normal flags. Only good for LE or GT compares. 12543// Same as cmpL_reg_flags_LEGT except must negate src 12544instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{ 12545 match( Set flags (CmpL src zero )); 12546 effect( TEMP tmp ); 12547 ins_cost(300); 12548 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" 12549 "CMP $tmp,$src.lo\n\t" 12550 "SBB $tmp,$src.hi\n\t" %} 12551 ins_encode( long_cmp_flags3(src, tmp) ); 12552 ins_pipe( ialu_reg_reg_long ); 12553%} 12554 12555// Manifest a CmpL result in the normal flags. Only good for LE or GT compares. 12556// Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands 12557// requires a commuted test to get the same result. 12558instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{ 12559 match( Set flags (CmpL src1 src2 )); 12560 effect( TEMP tmp ); 12561 ins_cost(300); 12562 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" 12563 "MOV $tmp,$src2.hi\n\t" 12564 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} 12565 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); 12566 ins_pipe( ialu_cr_reg_reg ); 12567%} 12568 12569// Long compares reg < zero/req OR reg >= zero/req. 12570// Just a wrapper for a normal branch, plus the predicate test 12571instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ 12572 match(If cmp flags); 12573 effect(USE labl); 12574 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); 12575 ins_cost(300); 12576 expand %{ 12577 jmpCon(cmp,flags,labl); // JGT or JLE... 12578 %} 12579%} 12580 12581// Compare 2 longs and CMOVE longs. 12582instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ 12583 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 12584 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12585 ins_cost(400); 12586 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12587 "CMOV$cmp $dst.hi,$src.hi" %} 12588 opcode(0x0F,0x40); 12589 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 12590 ins_pipe( pipe_cmov_reg_long ); 12591%} 12592 12593instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ 12594 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 12595 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12596 ins_cost(500); 12597 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12598 "CMOV$cmp $dst.hi,$src.hi+4" %} 12599 opcode(0x0F,0x40); 12600 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 12601 ins_pipe( pipe_cmov_reg_long ); 12602%} 12603 12604// Compare 2 longs and CMOVE ints. 12605instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{ 12606 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12607 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 12608 ins_cost(200); 12609 format %{ "CMOV$cmp $dst,$src" %} 12610 opcode(0x0F,0x40); 12611 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12612 ins_pipe( pipe_cmov_reg ); 12613%} 12614 12615instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{ 12616 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12617 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 12618 ins_cost(250); 12619 format %{ "CMOV$cmp $dst,$src" %} 12620 opcode(0x0F,0x40); 12621 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 12622 ins_pipe( pipe_cmov_mem ); 12623%} 12624 12625// Compare 2 longs and CMOVE ptrs. 12626instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ 12627 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12628 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 12629 ins_cost(200); 12630 format %{ "CMOV$cmp $dst,$src" %} 12631 opcode(0x0F,0x40); 12632 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12633 ins_pipe( pipe_cmov_reg ); 12634%} 12635 12636// Compare 2 longs and CMOVE doubles 12637instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ 12638 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 12639 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12640 ins_cost(200); 12641 expand %{ 12642 fcmovD_regS(cmp,flags,dst,src); 12643 %} 12644%} 12645 12646// Compare 2 longs and CMOVE doubles 12647instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{ 12648 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 12649 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12650 ins_cost(200); 12651 expand %{ 12652 fcmovXD_regS(cmp,flags,dst,src); 12653 %} 12654%} 12655 12656instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ 12657 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 12658 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12659 ins_cost(200); 12660 expand %{ 12661 fcmovF_regS(cmp,flags,dst,src); 12662 %} 12663%} 12664 12665 12666instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{ 12667 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 12668 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12669 ins_cost(200); 12670 expand %{ 12671 fcmovX_regS(cmp,flags,dst,src); 12672 %} 12673%} 12674 12675 12676// ============================================================================ 12677// Procedure Call/Return Instructions 12678// Call Java Static Instruction 12679// Note: If this code changes, the corresponding ret_addr_offset() and 12680// compute_padding() functions will have to be adjusted. 12681instruct CallStaticJavaDirect(method meth) %{ 12682 match(CallStaticJava); 12683 effect(USE meth); 12684 12685 ins_cost(300); 12686 format %{ "CALL,static " %} 12687 opcode(0xE8); /* E8 cd */ 12688 ins_encode( pre_call_FPU, 12689 Java_Static_Call( meth ), 12690 call_epilog, 12691 post_call_FPU ); 12692 ins_pipe( pipe_slow ); 12693 ins_pc_relative(1); 12694 ins_alignment(4); 12695%} 12696 12697// Call Java Dynamic Instruction 12698// Note: If this code changes, the corresponding ret_addr_offset() and 12699// compute_padding() functions will have to be adjusted. 12700instruct CallDynamicJavaDirect(method meth) %{ 12701 match(CallDynamicJava); 12702 effect(USE meth); 12703 12704 ins_cost(300); 12705 format %{ "MOV EAX,(oop)-1\n\t" 12706 "CALL,dynamic" %} 12707 opcode(0xE8); /* E8 cd */ 12708 ins_encode( pre_call_FPU, 12709 Java_Dynamic_Call( meth ), 12710 call_epilog, 12711 post_call_FPU ); 12712 ins_pipe( pipe_slow ); 12713 ins_pc_relative(1); 12714 ins_alignment(4); 12715%} 12716 12717// Call Runtime Instruction 12718instruct CallRuntimeDirect(method meth) %{ 12719 match(CallRuntime ); 12720 effect(USE meth); 12721 12722 ins_cost(300); 12723 format %{ "CALL,runtime " %} 12724 opcode(0xE8); /* E8 cd */ 12725 // Use FFREEs to clear entries in float stack 12726 ins_encode( pre_call_FPU, 12727 FFree_Float_Stack_All, 12728 Java_To_Runtime( meth ), 12729 post_call_FPU ); 12730 ins_pipe( pipe_slow ); 12731 ins_pc_relative(1); 12732%} 12733 12734// Call runtime without safepoint 12735instruct CallLeafDirect(method meth) %{ 12736 match(CallLeaf); 12737 effect(USE meth); 12738 12739 ins_cost(300); 12740 format %{ "CALL_LEAF,runtime " %} 12741 opcode(0xE8); /* E8 cd */ 12742 ins_encode( pre_call_FPU, 12743 FFree_Float_Stack_All, 12744 Java_To_Runtime( meth ), 12745 Verify_FPU_For_Leaf, post_call_FPU ); 12746 ins_pipe( pipe_slow ); 12747 ins_pc_relative(1); 12748%} 12749 12750instruct CallLeafNoFPDirect(method meth) %{ 12751 match(CallLeafNoFP); 12752 effect(USE meth); 12753 12754 ins_cost(300); 12755 format %{ "CALL_LEAF_NOFP,runtime " %} 12756 opcode(0xE8); /* E8 cd */ 12757 ins_encode(Java_To_Runtime(meth)); 12758 ins_pipe( pipe_slow ); 12759 ins_pc_relative(1); 12760%} 12761 12762 12763// Return Instruction 12764// Remove the return address & jump to it. 12765instruct Ret() %{ 12766 match(Return); 12767 format %{ "RET" %} 12768 opcode(0xC3); 12769 ins_encode(OpcP); 12770 ins_pipe( pipe_jmp ); 12771%} 12772 12773// Tail Call; Jump from runtime stub to Java code. 12774// Also known as an 'interprocedural jump'. 12775// Target of jump will eventually return to caller. 12776// TailJump below removes the return address. 12777instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ 12778 match(TailCall jump_target method_oop ); 12779 ins_cost(300); 12780 format %{ "JMP $jump_target \t# EBX holds method oop" %} 12781 opcode(0xFF, 0x4); /* Opcode FF /4 */ 12782 ins_encode( OpcP, RegOpc(jump_target) ); 12783 ins_pipe( pipe_jmp ); 12784%} 12785 12786 12787// Tail Jump; remove the return address; jump to target. 12788// TailCall above leaves the return address around. 12789instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ 12790 match( TailJump jump_target ex_oop ); 12791 ins_cost(300); 12792 format %{ "POP EDX\t# pop return address into dummy\n\t" 12793 "JMP $jump_target " %} 12794 opcode(0xFF, 0x4); /* Opcode FF /4 */ 12795 ins_encode( enc_pop_rdx, 12796 OpcP, RegOpc(jump_target) ); 12797 ins_pipe( pipe_jmp ); 12798%} 12799 12800// Create exception oop: created by stack-crawling runtime code. 12801// Created exception is now available to this handler, and is setup 12802// just prior to jumping to this handler. No code emitted. 12803instruct CreateException( eAXRegP ex_oop ) 12804%{ 12805 match(Set ex_oop (CreateEx)); 12806 12807 size(0); 12808 // use the following format syntax 12809 format %{ "# exception oop is in EAX; no code emitted" %} 12810 ins_encode(); 12811 ins_pipe( empty ); 12812%} 12813 12814 12815// Rethrow exception: 12816// The exception oop will come in the first argument position. 12817// Then JUMP (not call) to the rethrow stub code. 12818instruct RethrowException() 12819%{ 12820 match(Rethrow); 12821 12822 // use the following format syntax 12823 format %{ "JMP rethrow_stub" %} 12824 ins_encode(enc_rethrow); 12825 ins_pipe( pipe_jmp ); 12826%} 12827 12828// inlined locking and unlocking 12829 12830 12831instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{ 12832 match( Set cr (FastLock object box) ); 12833 effect( TEMP tmp, TEMP scr ); 12834 ins_cost(300); 12835 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %} 12836 ins_encode( Fast_Lock(object,box,tmp,scr) ); 12837 ins_pipe( pipe_slow ); 12838 ins_pc_relative(1); 12839%} 12840 12841instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ 12842 match( Set cr (FastUnlock object box) ); 12843 effect( TEMP tmp ); 12844 ins_cost(300); 12845 format %{ "FASTUNLOCK $object, $box, $tmp" %} 12846 ins_encode( Fast_Unlock(object,box,tmp) ); 12847 ins_pipe( pipe_slow ); 12848 ins_pc_relative(1); 12849%} 12850 12851 12852 12853// ============================================================================ 12854// Safepoint Instruction 12855instruct safePoint_poll(eFlagsReg cr) %{ 12856 match(SafePoint); 12857 effect(KILL cr); 12858 12859 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. 12860 // On SPARC that might be acceptable as we can generate the address with 12861 // just a sethi, saving an or. By polling at offset 0 we can end up 12862 // putting additional pressure on the index-0 in the D$. Because of 12863 // alignment (just like the situation at hand) the lower indices tend 12864 // to see more traffic. It'd be better to change the polling address 12865 // to offset 0 of the last $line in the polling page. 12866 12867 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} 12868 ins_cost(125); 12869 size(6) ; 12870 ins_encode( Safepoint_Poll() ); 12871 ins_pipe( ialu_reg_mem ); 12872%} 12873 12874//----------PEEPHOLE RULES----------------------------------------------------- 12875// These must follow all instruction definitions as they use the names 12876// defined in the instructions definitions. 12877// 12878// peepmatch ( root_instr_name [preceeding_instruction]* ); 12879// 12880// peepconstraint %{ 12881// (instruction_number.operand_name relational_op instruction_number.operand_name 12882// [, ...] ); 12883// // instruction numbers are zero-based using left to right order in peepmatch 12884// 12885// peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 12886// // provide an instruction_number.operand_name for each operand that appears 12887// // in the replacement instruction's match rule 12888// 12889// ---------VM FLAGS--------------------------------------------------------- 12890// 12891// All peephole optimizations can be turned off using -XX:-OptoPeephole 12892// 12893// Each peephole rule is given an identifying number starting with zero and 12894// increasing by one in the order seen by the parser. An individual peephole 12895// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 12896// on the command-line. 12897// 12898// ---------CURRENT LIMITATIONS---------------------------------------------- 12899// 12900// Only match adjacent instructions in same basic block 12901// Only equality constraints 12902// Only constraints between operands, not (0.dest_reg == EAX_enc) 12903// Only one replacement instruction 12904// 12905// ---------EXAMPLE---------------------------------------------------------- 12906// 12907// // pertinent parts of existing instructions in architecture description 12908// instruct movI(eRegI dst, eRegI src) %{ 12909// match(Set dst (CopyI src)); 12910// %} 12911// 12912// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 12913// match(Set dst (AddI dst src)); 12914// effect(KILL cr); 12915// %} 12916// 12917// // Change (inc mov) to lea 12918// peephole %{ 12919// // increment preceeded by register-register move 12920// peepmatch ( incI_eReg movI ); 12921// // require that the destination register of the increment 12922// // match the destination register of the move 12923// peepconstraint ( 0.dst == 1.dst ); 12924// // construct a replacement instruction that sets 12925// // the destination to ( move's source register + one ) 12926// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12927// %} 12928// 12929// Implementation no longer uses movX instructions since 12930// machine-independent system no longer uses CopyX nodes. 12931// 12932// peephole %{ 12933// peepmatch ( incI_eReg movI ); 12934// peepconstraint ( 0.dst == 1.dst ); 12935// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12936// %} 12937// 12938// peephole %{ 12939// peepmatch ( decI_eReg movI ); 12940// peepconstraint ( 0.dst == 1.dst ); 12941// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12942// %} 12943// 12944// peephole %{ 12945// peepmatch ( addI_eReg_imm movI ); 12946// peepconstraint ( 0.dst == 1.dst ); 12947// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12948// %} 12949// 12950// peephole %{ 12951// peepmatch ( addP_eReg_imm movP ); 12952// peepconstraint ( 0.dst == 1.dst ); 12953// peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); 12954// %} 12955 12956// // Change load of spilled value to only a spill 12957// instruct storeI(memory mem, eRegI src) %{ 12958// match(Set mem (StoreI mem src)); 12959// %} 12960// 12961// instruct loadI(eRegI dst, memory mem) %{ 12962// match(Set dst (LoadI mem)); 12963// %} 12964// 12965peephole %{ 12966 peepmatch ( loadI storeI ); 12967 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12968 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 12969%} 12970 12971//----------SMARTSPILL RULES--------------------------------------------------- 12972// These must follow all instruction definitions as they use the names 12973// defined in the instructions definitions. 12974