x86_32.ad revision 113:ba764ed4b6f2
1219019Sgabor// 2219019Sgabor// Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved. 3219019Sgabor// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4219019Sgabor// 5219019Sgabor// This code is free software; you can redistribute it and/or modify it 6219019Sgabor// under the terms of the GNU General Public License version 2 only, as 7219019Sgabor// published by the Free Software Foundation. 8219019Sgabor// 9219019Sgabor// This code is distributed in the hope that it will be useful, but WITHOUT 10219019Sgabor// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11219019Sgabor// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12219019Sgabor// version 2 for more details (a copy is included in the LICENSE file that 13219019Sgabor// accompanied this code). 14219019Sgabor// 15219019Sgabor// You should have received a copy of the GNU General Public License version 16219019Sgabor// 2 along with this work; if not, write to the Free Software Foundation, 17219019Sgabor// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18219019Sgabor// 19219019Sgabor// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20219019Sgabor// CA 95054 USA or visit www.sun.com if you need additional information or 21219019Sgabor// have any questions. 22219019Sgabor// 23219019Sgabor// 24219019Sgabor 25219019Sgabor// X86 Architecture Description File 26219019Sgabor 27219019Sgabor//----------REGISTER DEFINITION BLOCK------------------------------------------ 28219019Sgabor// This information is used by the matcher and the register allocator to 29219019Sgabor// describe individual registers and classes of registers within the target 30219019Sgabor// archtecture. 31219019Sgabor 32219019Sgaborregister %{ 33219019Sgabor//----------Architecture Description Register Definitions---------------------- 34219019Sgabor// General Registers 35219019Sgabor// "reg_def" name ( register save type, C convention save type, 36219019Sgabor// ideal register type, encoding ); 37219019Sgabor// Register Save Types: 38219019Sgabor// 39219019Sgabor// NS = No-Save: The register allocator assumes that these registers 40219019Sgabor// can be used without saving upon entry to the method, & 41219019Sgabor// that they do not need to be saved at call sites. 42219019Sgabor// 43219019Sgabor// SOC = Save-On-Call: The register allocator assumes that these registers 44219019Sgabor// can be used without saving upon entry to the method, 45219019Sgabor// but that they must be saved at call sites. 46219019Sgabor// 47219019Sgabor// SOE = Save-On-Entry: The register allocator assumes that these registers 48219019Sgabor// must be saved before using them upon entry to the 49219019Sgabor// method, but they do not need to be saved at call 50219019Sgabor// sites. 51219019Sgabor// 52219019Sgabor// AS = Always-Save: The register allocator assumes that these registers 53219019Sgabor// must be saved before using them upon entry to the 54219019Sgabor// method, & that they must be saved at call sites. 55219019Sgabor// 56219019Sgabor// Ideal Register Type is used to determine how to save & restore a 57219019Sgabor// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 58219019Sgabor// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 59219019Sgabor// 60219019Sgabor// The encoding number is the actual bit-pattern placed into the opcodes. 61219019Sgabor 62219019Sgabor// General Registers 63219019Sgabor// Previously set EBX, ESI, and EDI as save-on-entry for java code 64219019Sgabor// Turn off SOE in java-code due to frequent use of uncommon-traps. 65219019Sgabor// Now that allocator is better, turn on ESI and EDI as SOE registers. 66219019Sgabor 67219019Sgaborreg_def EBX(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()); 68219019Sgaborreg_def ECX(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()); 69219019Sgaborreg_def ESI(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()); 70219019Sgaborreg_def EDI(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()); 71219019Sgabor// now that adapter frames are gone EBP is always saved and restored by the prolog/epilog code 72219019Sgaborreg_def EBP(NS, SOE, Op_RegI, 5, rbp->as_VMReg()); 73219019Sgaborreg_def EDX(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()); 74219019Sgaborreg_def EAX(SOC, SOC, Op_RegI, 0, rax->as_VMReg()); 75219019Sgaborreg_def ESP( NS, NS, Op_RegI, 4, rsp->as_VMReg()); 76219019Sgabor 77219019Sgabor// Special Registers 78219019Sgaborreg_def EFLAGS(SOC, SOC, 0, 8, VMRegImpl::Bad()); 79219019Sgabor 80219019Sgabor// Float registers. We treat TOS/FPR0 special. It is invisible to the 81219019Sgabor// allocator, and only shows up in the encodings. 82219019Sgaborreg_def FPR0L( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); 83219019Sgaborreg_def FPR0H( SOC, SOC, Op_RegF, 0, VMRegImpl::Bad()); 84219019Sgabor// Ok so here's the trick FPR1 is really st(0) except in the midst 85219019Sgabor// of emission of assembly for a machnode. During the emission the fpu stack 86219019Sgabor// is pushed making FPR1 == st(1) temporarily. However at any safepoint 87219019Sgabor// the stack will not have this element so FPR1 == st(0) from the 88219019Sgabor// oopMap viewpoint. This same weirdness with numbering causes 89219019Sgabor// instruction encoding to have to play games with the register 90219019Sgabor// encode to correct for this 0/1 issue. See MachSpillCopyNode::implementation 91219019Sgabor// where it does flt->flt moves to see an example 92219019Sgabor// 93219019Sgaborreg_def FPR1L( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()); 94219019Sgaborreg_def FPR1H( SOC, SOC, Op_RegF, 1, as_FloatRegister(0)->as_VMReg()->next()); 95219019Sgaborreg_def FPR2L( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()); 96219019Sgaborreg_def FPR2H( SOC, SOC, Op_RegF, 2, as_FloatRegister(1)->as_VMReg()->next()); 97219019Sgaborreg_def FPR3L( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()); 98219019Sgaborreg_def FPR3H( SOC, SOC, Op_RegF, 3, as_FloatRegister(2)->as_VMReg()->next()); 99219019Sgaborreg_def FPR4L( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()); 100219019Sgaborreg_def FPR4H( SOC, SOC, Op_RegF, 4, as_FloatRegister(3)->as_VMReg()->next()); 101219019Sgaborreg_def FPR5L( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()); 102219019Sgaborreg_def FPR5H( SOC, SOC, Op_RegF, 5, as_FloatRegister(4)->as_VMReg()->next()); 103219019Sgaborreg_def FPR6L( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()); 104219019Sgaborreg_def FPR6H( SOC, SOC, Op_RegF, 6, as_FloatRegister(5)->as_VMReg()->next()); 105219019Sgaborreg_def FPR7L( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()); 106219019Sgaborreg_def FPR7H( SOC, SOC, Op_RegF, 7, as_FloatRegister(6)->as_VMReg()->next()); 107219019Sgabor 108219019Sgabor// XMM registers. 128-bit registers or 4 words each, labeled a-d. 109219019Sgabor// Word a in each register holds a Float, words ab hold a Double. 110219019Sgabor// We currently do not use the SIMD capabilities, so registers cd 111219019Sgabor// are unused at the moment. 112219019Sgaborreg_def XMM0a( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()); 113219019Sgaborreg_def XMM0b( SOC, SOC, Op_RegF, 0, xmm0->as_VMReg()->next()); 114219019Sgaborreg_def XMM1a( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()); 115219019Sgaborreg_def XMM1b( SOC, SOC, Op_RegF, 1, xmm1->as_VMReg()->next()); 116219019Sgaborreg_def XMM2a( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()); 117219019Sgaborreg_def XMM2b( SOC, SOC, Op_RegF, 2, xmm2->as_VMReg()->next()); 118219019Sgaborreg_def XMM3a( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()); 119219019Sgaborreg_def XMM3b( SOC, SOC, Op_RegF, 3, xmm3->as_VMReg()->next()); 120219019Sgaborreg_def XMM4a( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()); 121219019Sgaborreg_def XMM4b( SOC, SOC, Op_RegF, 4, xmm4->as_VMReg()->next()); 122219019Sgaborreg_def XMM5a( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()); 123219019Sgaborreg_def XMM5b( SOC, SOC, Op_RegF, 5, xmm5->as_VMReg()->next()); 124219019Sgaborreg_def XMM6a( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()); 125219019Sgaborreg_def XMM6b( SOC, SOC, Op_RegF, 6, xmm6->as_VMReg()->next()); 126219019Sgaborreg_def XMM7a( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()); 127219019Sgaborreg_def XMM7b( SOC, SOC, Op_RegF, 7, xmm7->as_VMReg()->next()); 128219019Sgabor 129219019Sgabor// Specify priority of register selection within phases of register 130219019Sgabor// allocation. Highest priority is first. A useful heuristic is to 131219019Sgabor// give registers a low priority when they are required by machine 132219019Sgabor// instructions, like EAX and EDX. Registers which are used as 133219019Sgabor// pairs must fall on an even boundry (witness the FPR#L's in this list). 134219019Sgabor// For the Intel integer registers, the equivalent Long pairs are 135219019Sgabor// EDX:EAX, EBX:ECX, and EDI:EBP. 136219019Sgaboralloc_class chunk0( ECX, EBX, EBP, EDI, EAX, EDX, ESI, ESP, 137219019Sgabor FPR0L, FPR0H, FPR1L, FPR1H, FPR2L, FPR2H, 138219019Sgabor FPR3L, FPR3H, FPR4L, FPR4H, FPR5L, FPR5H, 139219019Sgabor FPR6L, FPR6H, FPR7L, FPR7H ); 140219019Sgabor 141219019Sgaboralloc_class chunk1( XMM0a, XMM0b, 142219019Sgabor XMM1a, XMM1b, 143219019Sgabor XMM2a, XMM2b, 144219019Sgabor XMM3a, XMM3b, 145219019Sgabor XMM4a, XMM4b, 146219019Sgabor XMM5a, XMM5b, 147219019Sgabor XMM6a, XMM6b, 148219019Sgabor XMM7a, XMM7b, EFLAGS); 149219019Sgabor 150219019Sgabor 151219019Sgabor//----------Architecture Description Register Classes-------------------------- 152219019Sgabor// Several register classes are automatically defined based upon information in 153219019Sgabor// this architecture description. 154219019Sgabor// 1) reg_class inline_cache_reg ( /* as def'd in frame section */ ) 155219019Sgabor// 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ ) 156219019Sgabor// 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ ) 157219019Sgabor// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 158219019Sgabor// 159219019Sgabor// Class for all registers 160219019Sgaborreg_class any_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX, ESP); 161219019Sgabor// Class for general registers 162219019Sgaborreg_class e_reg(EAX, EDX, EBP, EDI, ESI, ECX, EBX); 163219019Sgabor// Class for general registers which may be used for implicit null checks on win95 164219019Sgabor// Also safe for use by tailjump. We don't want to allocate in rbp, 165219019Sgaborreg_class e_reg_no_rbp(EAX, EDX, EDI, ESI, ECX, EBX); 166219019Sgabor// Class of "X" registers 167219019Sgaborreg_class x_reg(EBX, ECX, EDX, EAX); 168219019Sgabor// Class of registers that can appear in an address with no offset. 169219019Sgabor// EBP and ESP require an extra instruction byte for zero offset. 170219019Sgabor// Used in fast-unlock 171219019Sgaborreg_class p_reg(EDX, EDI, ESI, EBX); 172219019Sgabor// Class for general registers not including ECX 173219019Sgaborreg_class ncx_reg(EAX, EDX, EBP, EDI, ESI, EBX); 174219019Sgabor// Class for general registers not including EAX 175219019Sgaborreg_class nax_reg(EDX, EDI, ESI, ECX, EBX); 176219019Sgabor// Class for general registers not including EAX or EBX. 177219019Sgaborreg_class nabx_reg(EDX, EDI, ESI, ECX, EBP); 178219019Sgabor// Class of EAX (for multiply and divide operations) 179219019Sgaborreg_class eax_reg(EAX); 180219019Sgabor// Class of EBX (for atomic add) 181219019Sgaborreg_class ebx_reg(EBX); 182219019Sgabor// Class of ECX (for shift and JCXZ operations and cmpLTMask) 183219019Sgaborreg_class ecx_reg(ECX); 184219019Sgabor// Class of EDX (for multiply and divide operations) 185219019Sgaborreg_class edx_reg(EDX); 186219019Sgabor// Class of EDI (for synchronization) 187219019Sgaborreg_class edi_reg(EDI); 188219019Sgabor// Class of ESI (for synchronization) 189219019Sgaborreg_class esi_reg(ESI); 190219019Sgabor// Singleton class for interpreter's stack pointer 191219019Sgaborreg_class ebp_reg(EBP); 192219019Sgabor// Singleton class for stack pointer 193219019Sgaborreg_class sp_reg(ESP); 194219019Sgabor// Singleton class for instruction pointer 195219019Sgabor// reg_class ip_reg(EIP); 196219019Sgabor// Singleton class for condition codes 197219019Sgaborreg_class int_flags(EFLAGS); 198219019Sgabor// Class of integer register pairs 199219019Sgaborreg_class long_reg( EAX,EDX, ECX,EBX, EBP,EDI ); 200219019Sgabor// Class of integer register pairs that aligns with calling convention 201219019Sgaborreg_class eadx_reg( EAX,EDX ); 202219019Sgaborreg_class ebcx_reg( ECX,EBX ); 203219019Sgabor// Not AX or DX, used in divides 204219019Sgaborreg_class nadx_reg( EBX,ECX,ESI,EDI,EBP ); 205219019Sgabor 206219019Sgabor// Floating point registers. Notice FPR0 is not a choice. 207219019Sgabor// FPR0 is not ever allocated; we use clever encodings to fake 208219019Sgabor// a 2-address instructions out of Intels FP stack. 209219019Sgaborreg_class flt_reg( FPR1L,FPR2L,FPR3L,FPR4L,FPR5L,FPR6L,FPR7L ); 210219019Sgabor 211219019Sgabor// make a register class for SSE registers 212219019Sgaborreg_class xmm_reg(XMM0a, XMM1a, XMM2a, XMM3a, XMM4a, XMM5a, XMM6a, XMM7a); 213219019Sgabor 214219019Sgabor// make a double register class for SSE2 registers 215219019Sgaborreg_class xdb_reg(XMM0a,XMM0b, XMM1a,XMM1b, XMM2a,XMM2b, XMM3a,XMM3b, 216219019Sgabor XMM4a,XMM4b, XMM5a,XMM5b, XMM6a,XMM6b, XMM7a,XMM7b ); 217219019Sgabor 218219019Sgaborreg_class dbl_reg( FPR1L,FPR1H, FPR2L,FPR2H, FPR3L,FPR3H, 219219019Sgabor FPR4L,FPR4H, FPR5L,FPR5H, FPR6L,FPR6H, 220219019Sgabor FPR7L,FPR7H ); 221219019Sgabor 222219019Sgaborreg_class flt_reg0( FPR1L ); 223219019Sgaborreg_class dbl_reg0( FPR1L,FPR1H ); 224219019Sgaborreg_class dbl_reg1( FPR2L,FPR2H ); 225219019Sgaborreg_class dbl_notreg0( FPR2L,FPR2H, FPR3L,FPR3H, FPR4L,FPR4H, 226219019Sgabor FPR5L,FPR5H, FPR6L,FPR6H, FPR7L,FPR7H ); 227219019Sgabor 228219019Sgabor// XMM6 and XMM7 could be used as temporary registers for long, float and 229219019Sgabor// double values for SSE2. 230219019Sgaborreg_class xdb_reg6( XMM6a,XMM6b ); 231219019Sgaborreg_class xdb_reg7( XMM7a,XMM7b ); 232219019Sgabor%} 233219019Sgabor 234219019Sgabor 235219019Sgabor//----------SOURCE BLOCK------------------------------------------------------- 236219019Sgabor// This is a block of C++ code which provides values, functions, and 237219019Sgabor// definitions necessary in the rest of the architecture description 238219019Sgaborsource %{ 239219019Sgabor#define RELOC_IMM32 Assembler::imm32_operand 240219019Sgabor#define RELOC_DISP32 Assembler::disp32_operand 241219019Sgabor 242219019Sgabor#define __ _masm. 243219019Sgabor 244219019Sgabor// How to find the high register of a Long pair, given the low register 245219019Sgabor#define HIGH_FROM_LOW(x) ((x)+2) 246219019Sgabor 247219019Sgabor// These masks are used to provide 128-bit aligned bitmasks to the XMM 248219019Sgabor// instructions, to allow sign-masking or sign-bit flipping. They allow 249219019Sgabor// fast versions of NegF/NegD and AbsF/AbsD. 250219019Sgabor 251219019Sgabor// Note: 'double' and 'long long' have 32-bits alignment on x86. 252219019Sgaborstatic jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 253219019Sgabor // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 254219019Sgabor // of 128-bits operands for SSE instructions. 255219019Sgabor jlong *operand = (jlong*)(((uintptr_t)adr)&((uintptr_t)(~0xF))); 256219019Sgabor // Store the value to a 128-bits operand. 257219019Sgabor operand[0] = lo; 258219019Sgabor operand[1] = hi; 259219019Sgabor return operand; 260219019Sgabor} 261219019Sgabor 262219019Sgabor// Buffer for 128-bits masks used by SSE instructions. 263219019Sgaborstatic jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 264219019Sgabor 265219019Sgabor// Static initialization during VM startup. 266219019Sgaborstatic jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 267219019Sgaborstatic jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 268219019Sgaborstatic jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); 269219019Sgaborstatic jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); 270219019Sgabor 271219019Sgabor// !!!!! Special hack to get all type of calls to specify the byte offset 272219019Sgabor// from the start of the call to the point where the return address 273219019Sgabor// will point. 274219019Sgaborint MachCallStaticJavaNode::ret_addr_offset() { 275219019Sgabor return 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 5 bytes from start of call to where return address points 276219019Sgabor} 277219019Sgabor 278219019Sgaborint MachCallDynamicJavaNode::ret_addr_offset() { 279219019Sgabor return 10 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); // 10 bytes from start of call to where return address points 280219019Sgabor} 281219019Sgabor 282219019Sgaborstatic int sizeof_FFree_Float_Stack_All = -1; 283219019Sgabor 284219019Sgaborint MachCallRuntimeNode::ret_addr_offset() { 285219019Sgabor assert(sizeof_FFree_Float_Stack_All != -1, "must have been emitted already"); 286219019Sgabor return sizeof_FFree_Float_Stack_All + 5 + (Compile::current()->in_24_bit_fp_mode() ? 6 : 0); 287219019Sgabor} 288219019Sgabor 289219019Sgabor// Indicate if the safepoint node needs the polling page as an input. 290219019Sgabor// Since x86 does have absolute addressing, it doesn't. 291219019Sgaborbool SafePointNode::needs_polling_address_input() { 292219019Sgabor return false; 293219019Sgabor} 294219019Sgabor 295219019Sgabor// 296219019Sgabor// Compute padding required for nodes which need alignment 297219019Sgabor// 298219019Sgabor 299219019Sgabor// The address of the call instruction needs to be 4-byte aligned to 300219019Sgabor// ensure that it does not span a cache line so that it can be patched. 301219019Sgaborint CallStaticJavaDirectNode::compute_padding(int current_offset) const { 302219019Sgabor if (Compile::current()->in_24_bit_fp_mode()) 303219019Sgabor current_offset += 6; // skip fldcw in pre_call_FPU, if any 304219019Sgabor current_offset += 1; // skip call opcode byte 305219019Sgabor return round_to(current_offset, alignment_required()) - current_offset; 306219019Sgabor} 307219019Sgabor 308219019Sgabor// The address of the call instruction needs to be 4-byte aligned to 309219019Sgabor// ensure that it does not span a cache line so that it can be patched. 310219019Sgaborint CallDynamicJavaDirectNode::compute_padding(int current_offset) const { 311219019Sgabor if (Compile::current()->in_24_bit_fp_mode()) 312219019Sgabor current_offset += 6; // skip fldcw in pre_call_FPU, if any 313219019Sgabor current_offset += 5; // skip MOV instruction 314219019Sgabor current_offset += 1; // skip call opcode byte 315219019Sgabor return round_to(current_offset, alignment_required()) - current_offset; 316219019Sgabor} 317219019Sgabor 318219019Sgabor#ifndef PRODUCT 319219019Sgaborvoid MachBreakpointNode::format( PhaseRegAlloc *, outputStream* st ) const { 320219019Sgabor st->print("INT3"); 321219019Sgabor} 322219019Sgabor#endif 323219019Sgabor 324219019Sgabor// EMIT_RM() 325219019Sgaborvoid emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) { 326219019Sgabor unsigned char c = (unsigned char)((f1 << 6) | (f2 << 3) | f3); 327219019Sgabor *(cbuf.code_end()) = c; 328219019Sgabor cbuf.set_code_end(cbuf.code_end() + 1); 329219019Sgabor} 330219019Sgabor 331219019Sgabor// EMIT_CC() 332219019Sgaborvoid emit_cc(CodeBuffer &cbuf, int f1, int f2) { 333219019Sgabor unsigned char c = (unsigned char)( f1 | f2 ); 334219019Sgabor *(cbuf.code_end()) = c; 335219019Sgabor cbuf.set_code_end(cbuf.code_end() + 1); 336219019Sgabor} 337219019Sgabor 338219019Sgabor// EMIT_OPCODE() 339219019Sgaborvoid emit_opcode(CodeBuffer &cbuf, int code) { 340219019Sgabor *(cbuf.code_end()) = (unsigned char)code; 341219019Sgabor cbuf.set_code_end(cbuf.code_end() + 1); 342219019Sgabor} 343219019Sgabor 344219019Sgabor// EMIT_OPCODE() w/ relocation information 345219019Sgaborvoid emit_opcode(CodeBuffer &cbuf, int code, relocInfo::relocType reloc, int offset = 0) { 346219019Sgabor cbuf.relocate(cbuf.inst_mark() + offset, reloc); 347219019Sgabor emit_opcode(cbuf, code); 348219019Sgabor} 349219019Sgabor 350219019Sgabor// EMIT_D8() 351219019Sgaborvoid emit_d8(CodeBuffer &cbuf, int d8) { 352219019Sgabor *(cbuf.code_end()) = (unsigned char)d8; 353219019Sgabor cbuf.set_code_end(cbuf.code_end() + 1); 354219019Sgabor} 355219019Sgabor 356219019Sgabor// EMIT_D16() 357219019Sgaborvoid emit_d16(CodeBuffer &cbuf, int d16) { 358219019Sgabor *((short *)(cbuf.code_end())) = d16; 359219019Sgabor cbuf.set_code_end(cbuf.code_end() + 2); 360219019Sgabor} 361219019Sgabor 362219019Sgabor// EMIT_D32() 363219019Sgaborvoid emit_d32(CodeBuffer &cbuf, int d32) { 364219019Sgabor *((int *)(cbuf.code_end())) = d32; 365219019Sgabor cbuf.set_code_end(cbuf.code_end() + 4); 366219019Sgabor} 367219019Sgabor 368219019Sgabor// emit 32 bit value and construct relocation entry from relocInfo::relocType 369219019Sgaborvoid emit_d32_reloc(CodeBuffer &cbuf, int d32, relocInfo::relocType reloc, 370219019Sgabor int format) { 371219019Sgabor cbuf.relocate(cbuf.inst_mark(), reloc, format); 372219019Sgabor 373219019Sgabor *((int *)(cbuf.code_end())) = d32; 374219019Sgabor cbuf.set_code_end(cbuf.code_end() + 4); 375219019Sgabor} 376219019Sgabor 377219019Sgabor// emit 32 bit value and construct relocation entry from RelocationHolder 378219019Sgaborvoid emit_d32_reloc(CodeBuffer &cbuf, int d32, RelocationHolder const& rspec, 379219019Sgabor int format) { 380219019Sgabor#ifdef ASSERT 381219019Sgabor if (rspec.reloc()->type() == relocInfo::oop_type && d32 != 0 && d32 != (int)Universe::non_oop_word()) { 382219019Sgabor assert(oop(d32)->is_oop() && oop(d32)->is_perm(), "cannot embed non-perm oops in code"); 383219019Sgabor } 384219019Sgabor#endif 385219019Sgabor cbuf.relocate(cbuf.inst_mark(), rspec, format); 386219019Sgabor 387219019Sgabor *((int *)(cbuf.code_end())) = d32; 388219019Sgabor cbuf.set_code_end(cbuf.code_end() + 4); 389219019Sgabor} 390219019Sgabor 391219019Sgabor// Access stack slot for load or store 392219019Sgaborvoid store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp) { 393219019Sgabor emit_opcode( cbuf, opcode ); // (e.g., FILD [ESP+src]) 394219019Sgabor if( -128 <= disp && disp <= 127 ) { 395219019Sgabor emit_rm( cbuf, 0x01, rm_field, ESP_enc ); // R/M byte 396219019Sgabor emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 397219019Sgabor emit_d8 (cbuf, disp); // Displacement // R/M byte 398219019Sgabor } else { 399219019Sgabor emit_rm( cbuf, 0x02, rm_field, ESP_enc ); // R/M byte 400219019Sgabor emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 401219019Sgabor emit_d32(cbuf, disp); // Displacement // R/M byte 402219019Sgabor } 403219019Sgabor} 404219019Sgabor 405219019Sgabor // eRegI ereg, memory mem) %{ // emit_reg_mem 406219019Sgaborvoid encode_RegMem( CodeBuffer &cbuf, int reg_encoding, int base, int index, int scale, int displace, bool displace_is_oop ) { 407219019Sgabor // There is no index & no scale, use form without SIB byte 408219019Sgabor if ((index == 0x4) && 409219019Sgabor (scale == 0) && (base != ESP_enc)) { 410219019Sgabor // If no displacement, mode is 0x0; unless base is [EBP] 411219019Sgabor if ( (displace == 0) && (base != EBP_enc) ) { 412219019Sgabor emit_rm(cbuf, 0x0, reg_encoding, base); 413219019Sgabor } 414219019Sgabor else { // If 8-bit displacement, mode 0x1 415219019Sgabor if ((displace >= -128) && (displace <= 127) 416219019Sgabor && !(displace_is_oop) ) { 417219019Sgabor emit_rm(cbuf, 0x1, reg_encoding, base); 418219019Sgabor emit_d8(cbuf, displace); 419219019Sgabor } 420219019Sgabor else { // If 32-bit displacement 421219019Sgabor if (base == -1) { // Special flag for absolute address 422219019Sgabor emit_rm(cbuf, 0x0, reg_encoding, 0x5); 423219019Sgabor // (manual lies; no SIB needed here) 424219019Sgabor if ( displace_is_oop ) { 425219019Sgabor emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 426219019Sgabor } else { 427219019Sgabor emit_d32 (cbuf, displace); 428219019Sgabor } 429219019Sgabor } 430219019Sgabor else { // Normal base + offset 431219019Sgabor emit_rm(cbuf, 0x2, reg_encoding, base); 432219019Sgabor if ( displace_is_oop ) { 433219019Sgabor emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 434219019Sgabor } else { 435219019Sgabor emit_d32 (cbuf, displace); 436219019Sgabor } 437219019Sgabor } 438219019Sgabor } 439219019Sgabor } 440219019Sgabor } 441219019Sgabor else { // Else, encode with the SIB byte 442219019Sgabor // If no displacement, mode is 0x0; unless base is [EBP] 443219019Sgabor if (displace == 0 && (base != EBP_enc)) { // If no displacement 444219019Sgabor emit_rm(cbuf, 0x0, reg_encoding, 0x4); 445219019Sgabor emit_rm(cbuf, scale, index, base); 446219019Sgabor } 447219019Sgabor else { // If 8-bit displacement, mode 0x1 448219019Sgabor if ((displace >= -128) && (displace <= 127) 449219019Sgabor && !(displace_is_oop) ) { 450219019Sgabor emit_rm(cbuf, 0x1, reg_encoding, 0x4); 451219019Sgabor emit_rm(cbuf, scale, index, base); 452219019Sgabor emit_d8(cbuf, displace); 453219019Sgabor } 454219019Sgabor else { // If 32-bit displacement 455219019Sgabor if (base == 0x04 ) { 456219019Sgabor emit_rm(cbuf, 0x2, reg_encoding, 0x4); 457219019Sgabor emit_rm(cbuf, scale, index, 0x04); 458219019Sgabor } else { 459219019Sgabor emit_rm(cbuf, 0x2, reg_encoding, 0x4); 460219019Sgabor emit_rm(cbuf, scale, index, base); 461219019Sgabor } 462219019Sgabor if ( displace_is_oop ) { 463219019Sgabor emit_d32_reloc(cbuf, displace, relocInfo::oop_type, 1); 464219019Sgabor } else { 465219019Sgabor emit_d32 (cbuf, displace); 466219019Sgabor } 467219019Sgabor } 468219019Sgabor } 469219019Sgabor } 470219019Sgabor} 471219019Sgabor 472219019Sgabor 473219019Sgaborvoid encode_Copy( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { 474219019Sgabor if( dst_encoding == src_encoding ) { 475219019Sgabor // reg-reg copy, use an empty encoding 476219019Sgabor } else { 477219019Sgabor emit_opcode( cbuf, 0x8B ); 478219019Sgabor emit_rm(cbuf, 0x3, dst_encoding, src_encoding ); 479219019Sgabor } 480219019Sgabor} 481219019Sgabor 482219019Sgaborvoid encode_CopyXD( CodeBuffer &cbuf, int dst_encoding, int src_encoding ) { 483219019Sgabor if( dst_encoding == src_encoding ) { 484219019Sgabor // reg-reg copy, use an empty encoding 485219019Sgabor } else { 486219019Sgabor MacroAssembler _masm(&cbuf); 487219019Sgabor 488219019Sgabor __ movdqa(as_XMMRegister(dst_encoding), as_XMMRegister(src_encoding)); 489219019Sgabor } 490219019Sgabor} 491219019Sgabor 492219019Sgabor 493219019Sgabor//============================================================================= 494219019Sgabor#ifndef PRODUCT 495219019Sgaborvoid MachPrologNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 496219019Sgabor Compile* C = ra_->C; 497219019Sgabor if( C->in_24_bit_fp_mode() ) { 498219019Sgabor tty->print("FLDCW 24 bit fpu control word"); 499219019Sgabor tty->print_cr(""); tty->print("\t"); 500219019Sgabor } 501219019Sgabor 502219019Sgabor int framesize = C->frame_slots() << LogBytesPerInt; 503219019Sgabor assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 504219019Sgabor // Remove two words for return addr and rbp, 505219019Sgabor framesize -= 2*wordSize; 506219019Sgabor 507219019Sgabor // Calls to C2R adapters often do not accept exceptional returns. 508219019Sgabor // We require that their callers must bang for them. But be careful, because 509219019Sgabor // some VM calls (such as call site linkage) can use several kilobytes of 510219019Sgabor // stack. But the stack safety zone should account for that. 511219019Sgabor // See bugs 4446381, 4468289, 4497237. 512219019Sgabor if (C->need_stack_bang(framesize)) { 513219019Sgabor tty->print_cr("# stack bang"); tty->print("\t"); 514219019Sgabor } 515219019Sgabor tty->print_cr("PUSHL EBP"); tty->print("\t"); 516219019Sgabor 517219019Sgabor if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth 518219019Sgabor tty->print("PUSH 0xBADB100D\t# Majik cookie for stack depth check"); 519219019Sgabor tty->print_cr(""); tty->print("\t"); 520219019Sgabor framesize -= wordSize; 521219019Sgabor } 522219019Sgabor 523219019Sgabor if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { 524219019Sgabor if (framesize) { 525219019Sgabor tty->print("SUB ESP,%d\t# Create frame",framesize); 526219019Sgabor } 527219019Sgabor } else { 528219019Sgabor tty->print("SUB ESP,%d\t# Create frame",framesize); 529219019Sgabor } 530219019Sgabor} 531219019Sgabor#endif 532219019Sgabor 533219019Sgabor 534219019Sgaborvoid MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 535219019Sgabor Compile* C = ra_->C; 536219019Sgabor 537219019Sgabor if (UseSSE >= 2 && VerifyFPU) { 538219019Sgabor MacroAssembler masm(&cbuf); 539219019Sgabor masm.verify_FPU(0, "FPU stack must be clean on entry"); 540219019Sgabor } 541219019Sgabor 542219019Sgabor // WARNING: Initial instruction MUST be 5 bytes or longer so that 543219019Sgabor // NativeJump::patch_verified_entry will be able to patch out the entry 544219019Sgabor // code safely. The fldcw is ok at 6 bytes, the push to verify stack 545219019Sgabor // depth is ok at 5 bytes, the frame allocation can be either 3 or 546219019Sgabor // 6 bytes. So if we don't do the fldcw or the push then we must 547219019Sgabor // use the 6 byte frame allocation even if we have no frame. :-( 548219019Sgabor // If method sets FPU control word do it now 549219019Sgabor if( C->in_24_bit_fp_mode() ) { 550219019Sgabor MacroAssembler masm(&cbuf); 551219019Sgabor masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 552219019Sgabor } 553219019Sgabor 554219019Sgabor int framesize = C->frame_slots() << LogBytesPerInt; 555219019Sgabor assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 556219019Sgabor // Remove two words for return addr and rbp, 557219019Sgabor framesize -= 2*wordSize; 558219019Sgabor 559219019Sgabor // Calls to C2R adapters often do not accept exceptional returns. 560219019Sgabor // We require that their callers must bang for them. But be careful, because 561219019Sgabor // some VM calls (such as call site linkage) can use several kilobytes of 562219019Sgabor // stack. But the stack safety zone should account for that. 563219019Sgabor // See bugs 4446381, 4468289, 4497237. 564219019Sgabor if (C->need_stack_bang(framesize)) { 565219019Sgabor MacroAssembler masm(&cbuf); 566219019Sgabor masm.generate_stack_overflow_check(framesize); 567219019Sgabor } 568219019Sgabor 569219019Sgabor // We always push rbp, so that on return to interpreter rbp, will be 570219019Sgabor // restored correctly and we can correct the stack. 571219019Sgabor emit_opcode(cbuf, 0x50 | EBP_enc); 572219019Sgabor 573219019Sgabor if( VerifyStackAtCalls ) { // Majik cookie to verify stack depth 574219019Sgabor emit_opcode(cbuf, 0x68); // push 0xbadb100d 575219019Sgabor emit_d32(cbuf, 0xbadb100d); 576219019Sgabor framesize -= wordSize; 577219019Sgabor } 578219019Sgabor 579219019Sgabor if ((C->in_24_bit_fp_mode() || VerifyStackAtCalls ) && framesize < 128 ) { 580219019Sgabor if (framesize) { 581219019Sgabor emit_opcode(cbuf, 0x83); // sub SP,#framesize 582219019Sgabor emit_rm(cbuf, 0x3, 0x05, ESP_enc); 583219019Sgabor emit_d8(cbuf, framesize); 584219019Sgabor } 585219019Sgabor } else { 586219019Sgabor emit_opcode(cbuf, 0x81); // sub SP,#framesize 587219019Sgabor emit_rm(cbuf, 0x3, 0x05, ESP_enc); 588219019Sgabor emit_d32(cbuf, framesize); 589219019Sgabor } 590219019Sgabor C->set_frame_complete(cbuf.code_end() - cbuf.code_begin()); 591219019Sgabor 592219019Sgabor#ifdef ASSERT 593219019Sgabor if (VerifyStackAtCalls) { 594219019Sgabor Label L; 595219019Sgabor MacroAssembler masm(&cbuf); 596219019Sgabor masm.pushl(rax); 597219019Sgabor masm.movl(rax, rsp); 598219019Sgabor masm.andl(rax, StackAlignmentInBytes-1); 599219019Sgabor masm.cmpl(rax, StackAlignmentInBytes-wordSize); 600219019Sgabor masm.popl(rax); 601219019Sgabor masm.jcc(Assembler::equal, L); 602219019Sgabor masm.stop("Stack is not properly aligned!"); 603219019Sgabor masm.bind(L); 604219019Sgabor } 605219019Sgabor#endif 606219019Sgabor 607219019Sgabor} 608219019Sgabor 609219019Sgaboruint MachPrologNode::size(PhaseRegAlloc *ra_) const { 610219019Sgabor return MachNode::size(ra_); // too many variables; just compute it the hard way 611219019Sgabor} 612219019Sgabor 613219019Sgaborint MachPrologNode::reloc() const { 614219019Sgabor return 0; // a large enough number 615219019Sgabor} 616219019Sgabor 617219019Sgabor//============================================================================= 618219019Sgabor#ifndef PRODUCT 619219019Sgaborvoid MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 620219019Sgabor Compile *C = ra_->C; 621219019Sgabor int framesize = C->frame_slots() << LogBytesPerInt; 622219019Sgabor assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 623219019Sgabor // Remove two words for return addr and rbp, 624219019Sgabor framesize -= 2*wordSize; 625219019Sgabor 626219019Sgabor if( C->in_24_bit_fp_mode() ) { 627219019Sgabor st->print("FLDCW standard control word"); 628219019Sgabor st->cr(); st->print("\t"); 629219019Sgabor } 630219019Sgabor if( framesize ) { 631219019Sgabor st->print("ADD ESP,%d\t# Destroy frame",framesize); 632219019Sgabor st->cr(); st->print("\t"); 633219019Sgabor } 634219019Sgabor st->print_cr("POPL EBP"); st->print("\t"); 635219019Sgabor if( do_polling() && C->is_method_compilation() ) { 636219019Sgabor st->print("TEST PollPage,EAX\t! Poll Safepoint"); 637219019Sgabor st->cr(); st->print("\t"); 638219019Sgabor } 639219019Sgabor} 640219019Sgabor#endif 641219019Sgabor 642219019Sgaborvoid MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 643219019Sgabor Compile *C = ra_->C; 644219019Sgabor 645219019Sgabor // If method set FPU control word, restore to standard control word 646219019Sgabor if( C->in_24_bit_fp_mode() ) { 647219019Sgabor MacroAssembler masm(&cbuf); 648219019Sgabor masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 649219019Sgabor } 650219019Sgabor 651219019Sgabor int framesize = C->frame_slots() << LogBytesPerInt; 652219019Sgabor assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 653219019Sgabor // Remove two words for return addr and rbp, 654219019Sgabor framesize -= 2*wordSize; 655219019Sgabor 656219019Sgabor // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here 657219019Sgabor 658219019Sgabor if( framesize >= 128 ) { 659219019Sgabor emit_opcode(cbuf, 0x81); // add SP, #framesize 660219019Sgabor emit_rm(cbuf, 0x3, 0x00, ESP_enc); 661219019Sgabor emit_d32(cbuf, framesize); 662219019Sgabor } 663219019Sgabor else if( framesize ) { 664219019Sgabor emit_opcode(cbuf, 0x83); // add SP, #framesize 665219019Sgabor emit_rm(cbuf, 0x3, 0x00, ESP_enc); 666219019Sgabor emit_d8(cbuf, framesize); 667219019Sgabor } 668219019Sgabor 669219019Sgabor emit_opcode(cbuf, 0x58 | EBP_enc); 670219019Sgabor 671219019Sgabor if( do_polling() && C->is_method_compilation() ) { 672219019Sgabor cbuf.relocate(cbuf.code_end(), relocInfo::poll_return_type, 0); 673219019Sgabor emit_opcode(cbuf,0x85); 674219019Sgabor emit_rm(cbuf, 0x0, EAX_enc, 0x5); // EAX 675219019Sgabor emit_d32(cbuf, (intptr_t)os::get_polling_page()); 676219019Sgabor } 677219019Sgabor} 678219019Sgabor 679219019Sgaboruint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 680219019Sgabor Compile *C = ra_->C; 681219019Sgabor // If method set FPU control word, restore to standard control word 682219019Sgabor int size = C->in_24_bit_fp_mode() ? 6 : 0; 683219019Sgabor if( do_polling() && C->is_method_compilation() ) size += 6; 684219019Sgabor 685219019Sgabor int framesize = C->frame_slots() << LogBytesPerInt; 686219019Sgabor assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 687219019Sgabor // Remove two words for return addr and rbp, 688219019Sgabor framesize -= 2*wordSize; 689219019Sgabor 690219019Sgabor size++; // popl rbp, 691219019Sgabor 692219019Sgabor if( framesize >= 128 ) { 693219019Sgabor size += 6; 694219019Sgabor } else { 695219019Sgabor size += framesize ? 3 : 0; 696219019Sgabor } 697219019Sgabor return size; 698219019Sgabor} 699219019Sgabor 700219019Sgaborint MachEpilogNode::reloc() const { 701219019Sgabor return 0; // a large enough number 702219019Sgabor} 703219019Sgabor 704219019Sgaborconst Pipeline * MachEpilogNode::pipeline() const { 705219019Sgabor return MachNode::pipeline_class(); 706219019Sgabor} 707219019Sgabor 708219019Sgaborint MachEpilogNode::safepoint_offset() const { return 0; } 709219019Sgabor 710219019Sgabor//============================================================================= 711219019Sgabor 712219019Sgaborenum RC { rc_bad, rc_int, rc_float, rc_xmm, rc_stack }; 713219019Sgaborstatic enum RC rc_class( OptoReg::Name reg ) { 714219019Sgabor 715219019Sgabor if( !OptoReg::is_valid(reg) ) return rc_bad; 716219019Sgabor if (OptoReg::is_stack(reg)) return rc_stack; 717219019Sgabor 718219019Sgabor VMReg r = OptoReg::as_VMReg(reg); 719219019Sgabor if (r->is_Register()) return rc_int; 720219019Sgabor if (r->is_FloatRegister()) { 721219019Sgabor assert(UseSSE < 2, "shouldn't be used in SSE2+ mode"); 722219019Sgabor return rc_float; 723219019Sgabor } 724219019Sgabor assert(r->is_XMMRegister(), "must be"); 725219019Sgabor return rc_xmm; 726219019Sgabor} 727219019Sgabor 728219019Sgaborstatic int impl_helper( CodeBuffer *cbuf, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size ) { 729219019Sgabor if( cbuf ) { 730219019Sgabor emit_opcode (*cbuf, opcode ); 731219019Sgabor encode_RegMem(*cbuf, Matcher::_regEncode[reg], ESP_enc, 0x4, 0, offset, false); 732219019Sgabor#ifndef PRODUCT 733219019Sgabor } else if( !do_size ) { 734219019Sgabor if( size != 0 ) tty->print("\n\t"); 735219019Sgabor if( opcode == 0x8B || opcode == 0x89 ) { // MOV 736219019Sgabor if( is_load ) tty->print("%s %s,[ESP + #%d]",op_str,Matcher::regName[reg],offset); 737219019Sgabor else tty->print("%s [ESP + #%d],%s",op_str,offset,Matcher::regName[reg]); 738219019Sgabor } else { // FLD, FST, PUSH, POP 739219019Sgabor tty->print("%s [ESP + #%d]",op_str,offset); 740219019Sgabor } 741219019Sgabor#endif 742219019Sgabor } 743219019Sgabor int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 744219019Sgabor return size+3+offset_size; 745219019Sgabor} 746219019Sgabor 747219019Sgabor// Helper for XMM registers. Extra opcode bits, limited syntax. 748219019Sgaborstatic int impl_x_helper( CodeBuffer *cbuf, bool do_size, bool is_load, 749219019Sgabor int offset, int reg_lo, int reg_hi, int size ) { 750219019Sgabor if( cbuf ) { 751219019Sgabor if( reg_lo+1 == reg_hi ) { // double move? 752219019Sgabor if( is_load && !UseXmmLoadAndClearUpper ) 753219019Sgabor emit_opcode(*cbuf, 0x66 ); // use 'movlpd' for load 754219019Sgabor else 755219019Sgabor emit_opcode(*cbuf, 0xF2 ); // use 'movsd' otherwise 756219019Sgabor } else { 757219019Sgabor emit_opcode(*cbuf, 0xF3 ); 758219019Sgabor } 759219019Sgabor emit_opcode(*cbuf, 0x0F ); 760219019Sgabor if( reg_lo+1 == reg_hi && is_load && !UseXmmLoadAndClearUpper ) 761219019Sgabor emit_opcode(*cbuf, 0x12 ); // use 'movlpd' for load 762219019Sgabor else 763219019Sgabor emit_opcode(*cbuf, is_load ? 0x10 : 0x11 ); 764219019Sgabor encode_RegMem(*cbuf, Matcher::_regEncode[reg_lo], ESP_enc, 0x4, 0, offset, false); 765219019Sgabor#ifndef PRODUCT 766219019Sgabor } else if( !do_size ) { 767219019Sgabor if( size != 0 ) tty->print("\n\t"); 768219019Sgabor if( reg_lo+1 == reg_hi ) { // double move? 769219019Sgabor if( is_load ) tty->print("%s %s,[ESP + #%d]", 770219019Sgabor UseXmmLoadAndClearUpper ? "MOVSD " : "MOVLPD", 771219019Sgabor Matcher::regName[reg_lo], offset); 772219019Sgabor else tty->print("MOVSD [ESP + #%d],%s", 773219019Sgabor offset, Matcher::regName[reg_lo]); 774219019Sgabor } else { 775219019Sgabor if( is_load ) tty->print("MOVSS %s,[ESP + #%d]", 776219019Sgabor Matcher::regName[reg_lo], offset); 777219019Sgabor else tty->print("MOVSS [ESP + #%d],%s", 778219019Sgabor offset, Matcher::regName[reg_lo]); 779219019Sgabor } 780219019Sgabor#endif 781219019Sgabor } 782219019Sgabor int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 783219019Sgabor return size+5+offset_size; 784219019Sgabor} 785219019Sgabor 786219019Sgabor 787219019Sgaborstatic int impl_movx_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo, 788219019Sgabor int src_hi, int dst_hi, int size ) { 789219019Sgabor if( UseXmmRegToRegMoveAll ) {//Use movaps,movapd to move between xmm registers 790219019Sgabor if( cbuf ) { 791219019Sgabor if( (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ) { 792219019Sgabor emit_opcode(*cbuf, 0x66 ); 793219019Sgabor } 794219019Sgabor emit_opcode(*cbuf, 0x0F ); 795219019Sgabor emit_opcode(*cbuf, 0x28 ); 796219019Sgabor emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] ); 797219019Sgabor#ifndef PRODUCT 798219019Sgabor } else if( !do_size ) { 799219019Sgabor if( size != 0 ) tty->print("\n\t"); 800219019Sgabor if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? 801219019Sgabor tty->print("MOVAPD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 802219019Sgabor } else { 803219019Sgabor tty->print("MOVAPS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 804219019Sgabor } 805219019Sgabor#endif 806219019Sgabor } 807219019Sgabor return size + ((src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 4 : 3); 808219019Sgabor } else { 809219019Sgabor if( cbuf ) { 810219019Sgabor emit_opcode(*cbuf, (src_lo+1 == src_hi && dst_lo+1 == dst_hi) ? 0xF2 : 0xF3 ); 811219019Sgabor emit_opcode(*cbuf, 0x0F ); 812219019Sgabor emit_opcode(*cbuf, 0x10 ); 813219019Sgabor emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst_lo], Matcher::_regEncode[src_lo] ); 814219019Sgabor#ifndef PRODUCT 815219019Sgabor } else if( !do_size ) { 816219019Sgabor if( size != 0 ) tty->print("\n\t"); 817219019Sgabor if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double move? 818219019Sgabor tty->print("MOVSD %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 819219019Sgabor } else { 820219019Sgabor tty->print("MOVSS %s,%s",Matcher::regName[dst_lo],Matcher::regName[src_lo]); 821219019Sgabor } 822219019Sgabor#endif 823219019Sgabor } 824219019Sgabor return size+4; 825219019Sgabor } 826219019Sgabor} 827219019Sgabor 828219019Sgaborstatic int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int size ) { 829219019Sgabor if( cbuf ) { 830219019Sgabor emit_opcode(*cbuf, 0x8B ); 831219019Sgabor emit_rm (*cbuf, 0x3, Matcher::_regEncode[dst], Matcher::_regEncode[src] ); 832219019Sgabor#ifndef PRODUCT 833219019Sgabor } else if( !do_size ) { 834219019Sgabor if( size != 0 ) tty->print("\n\t"); 835219019Sgabor tty->print("MOV %s,%s",Matcher::regName[dst],Matcher::regName[src]); 836219019Sgabor#endif 837219019Sgabor } 838219019Sgabor return size+2; 839219019Sgabor} 840219019Sgabor 841219019Sgaborstatic int impl_fp_store_helper( CodeBuffer *cbuf, bool do_size, int src_lo, int src_hi, int dst_lo, int dst_hi, int offset, int size ) { 842219019Sgabor if( src_lo != FPR1L_num ) { // Move value to top of FP stack, if not already there 843219019Sgabor if( cbuf ) { 844219019Sgabor emit_opcode( *cbuf, 0xD9 ); // FLD (i.e., push it) 845219019Sgabor emit_d8( *cbuf, 0xC0-1+Matcher::_regEncode[src_lo] ); 846219019Sgabor#ifndef PRODUCT 847219019Sgabor } else if( !do_size ) { 848219019Sgabor if( size != 0 ) tty->print("\n\t"); 849219019Sgabor tty->print("FLD %s",Matcher::regName[src_lo]); 850219019Sgabor#endif 851219019Sgabor } 852219019Sgabor size += 2; 853219019Sgabor } 854219019Sgabor 855219019Sgabor int st_op = (src_lo != FPR1L_num) ? EBX_num /*store & pop*/ : EDX_num /*store no pop*/; 856219019Sgabor const char *op_str; 857219019Sgabor int op; 858219019Sgabor if( src_lo+1 == src_hi && dst_lo+1 == dst_hi ) { // double store? 859219019Sgabor op_str = (src_lo != FPR1L_num) ? "FSTP_D" : "FST_D "; 860219019Sgabor op = 0xDD; 861219019Sgabor } else { // 32-bit store 862219019Sgabor op_str = (src_lo != FPR1L_num) ? "FSTP_S" : "FST_S "; 863219019Sgabor op = 0xD9; 864219019Sgabor assert( !OptoReg::is_valid(src_hi) && !OptoReg::is_valid(dst_hi), "no non-adjacent float-stores" ); 865219019Sgabor } 866219019Sgabor 867219019Sgabor return impl_helper(cbuf,do_size,false,offset,st_op,op,op_str,size); 868219019Sgabor} 869219019Sgabor 870219019Sgaboruint MachSpillCopyNode::implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const { 871219019Sgabor // Get registers to move 872219019Sgabor OptoReg::Name src_second = ra_->get_reg_second(in(1)); 873219019Sgabor OptoReg::Name src_first = ra_->get_reg_first(in(1)); 874219019Sgabor OptoReg::Name dst_second = ra_->get_reg_second(this ); 875219019Sgabor OptoReg::Name dst_first = ra_->get_reg_first(this ); 876219019Sgabor 877219019Sgabor enum RC src_second_rc = rc_class(src_second); 878219019Sgabor enum RC src_first_rc = rc_class(src_first); 879219019Sgabor enum RC dst_second_rc = rc_class(dst_second); 880219019Sgabor enum RC dst_first_rc = rc_class(dst_first); 881219019Sgabor 882219019Sgabor assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 883219019Sgabor 884219019Sgabor // Generate spill code! 885219019Sgabor int size = 0; 886219019Sgabor 887219019Sgabor if( src_first == dst_first && src_second == dst_second ) 888219019Sgabor return size; // Self copy, no move 889219019Sgabor 890219019Sgabor // -------------------------------------- 891219019Sgabor // Check for mem-mem move. push/pop to move. 892219019Sgabor if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 893219019Sgabor if( src_second == dst_first ) { // overlapping stack copy ranges 894219019Sgabor assert( src_second_rc == rc_stack && dst_second_rc == rc_stack, "we only expect a stk-stk copy here" ); 895219019Sgabor size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size); 896219019Sgabor size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size); 897219019Sgabor src_second_rc = dst_second_rc = rc_bad; // flag as already moved the second bits 898219019Sgabor } 899219019Sgabor // move low bits 900219019Sgabor size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),ESI_num,0xFF,"PUSH ",size); 901219019Sgabor size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),EAX_num,0x8F,"POP ",size); 902219019Sgabor if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { // mov second bits 903219019Sgabor size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),ESI_num,0xFF,"PUSH ",size); 904219019Sgabor size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),EAX_num,0x8F,"POP ",size); 905219019Sgabor } 906219019Sgabor return size; 907219019Sgabor } 908219019Sgabor 909219019Sgabor // -------------------------------------- 910219019Sgabor // Check for integer reg-reg copy 911219019Sgabor if( src_first_rc == rc_int && dst_first_rc == rc_int ) 912219019Sgabor size = impl_mov_helper(cbuf,do_size,src_first,dst_first,size); 913219019Sgabor 914219019Sgabor // Check for integer store 915219019Sgabor if( src_first_rc == rc_int && dst_first_rc == rc_stack ) 916219019Sgabor size = impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first,0x89,"MOV ",size); 917219019Sgabor 918219019Sgabor // Check for integer load 919219019Sgabor if( dst_first_rc == rc_int && src_first_rc == rc_stack ) 920219019Sgabor size = impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first,0x8B,"MOV ",size); 921219019Sgabor 922219019Sgabor // -------------------------------------- 923219019Sgabor // Check for float reg-reg copy 924219019Sgabor if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 925219019Sgabor assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || 926219019Sgabor (src_first+1 == src_second && dst_first+1 == dst_second), "no non-adjacent float-moves" ); 927219019Sgabor if( cbuf ) { 928219019Sgabor 929219019Sgabor // Note the mucking with the register encode to compensate for the 0/1 930219019Sgabor // indexing issue mentioned in a comment in the reg_def sections 931219019Sgabor // for FPR registers many lines above here. 932219019Sgabor 933219019Sgabor if( src_first != FPR1L_num ) { 934219019Sgabor emit_opcode (*cbuf, 0xD9 ); // FLD ST(i) 935219019Sgabor emit_d8 (*cbuf, 0xC0+Matcher::_regEncode[src_first]-1 ); 936219019Sgabor emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) 937219019Sgabor emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); 938219019Sgabor } else { 939219019Sgabor emit_opcode (*cbuf, 0xDD ); // FST ST(i) 940219019Sgabor emit_d8 (*cbuf, 0xD0+Matcher::_regEncode[dst_first]-1 ); 941219019Sgabor } 942219019Sgabor#ifndef PRODUCT 943219019Sgabor } else if( !do_size ) { 944219019Sgabor if( size != 0 ) st->print("\n\t"); 945219019Sgabor if( src_first != FPR1L_num ) st->print("FLD %s\n\tFSTP %s",Matcher::regName[src_first],Matcher::regName[dst_first]); 946219019Sgabor else st->print( "FST %s", Matcher::regName[dst_first]); 947219019Sgabor#endif 948219019Sgabor } 949219019Sgabor return size + ((src_first != FPR1L_num) ? 2+2 : 2); 950219019Sgabor } 951219019Sgabor 952219019Sgabor // Check for float store 953219019Sgabor if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 954219019Sgabor return impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,ra_->reg2offset(dst_first),size); 955219019Sgabor } 956219019Sgabor 957219019Sgabor // Check for float load 958219019Sgabor if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 959219019Sgabor int offset = ra_->reg2offset(src_first); 960219019Sgabor const char *op_str; 961219019Sgabor int op; 962219019Sgabor if( src_first+1 == src_second && dst_first+1 == dst_second ) { // double load? 963219019Sgabor op_str = "FLD_D"; 964219019Sgabor op = 0xDD; 965219019Sgabor } else { // 32-bit load 966219019Sgabor op_str = "FLD_S"; 967219019Sgabor op = 0xD9; 968219019Sgabor assert( src_second_rc == rc_bad && dst_second_rc == rc_bad, "no non-adjacent float-loads" ); 969219019Sgabor } 970219019Sgabor if( cbuf ) { 971219019Sgabor emit_opcode (*cbuf, op ); 972219019Sgabor encode_RegMem(*cbuf, 0x0, ESP_enc, 0x4, 0, offset, false); 973219019Sgabor emit_opcode (*cbuf, 0xDD ); // FSTP ST(i) 974219019Sgabor emit_d8 (*cbuf, 0xD8+Matcher::_regEncode[dst_first] ); 975219019Sgabor#ifndef PRODUCT 976219019Sgabor } else if( !do_size ) { 977219019Sgabor if( size != 0 ) st->print("\n\t"); 978219019Sgabor st->print("%s ST,[ESP + #%d]\n\tFSTP %s",op_str, offset,Matcher::regName[dst_first]); 979219019Sgabor#endif 980219019Sgabor } 981219019Sgabor int offset_size = (offset == 0) ? 0 : ((offset <= 127) ? 1 : 4); 982219019Sgabor return size + 3+offset_size+2; 983219019Sgabor } 984219019Sgabor 985219019Sgabor // Check for xmm reg-reg copy 986219019Sgabor if( src_first_rc == rc_xmm && dst_first_rc == rc_xmm ) { 987219019Sgabor assert( (src_second_rc == rc_bad && dst_second_rc == rc_bad) || 988219019Sgabor (src_first+1 == src_second && dst_first+1 == dst_second), 989219019Sgabor "no non-adjacent float-moves" ); 990219019Sgabor return impl_movx_helper(cbuf,do_size,src_first,dst_first,src_second, dst_second, size); 991219019Sgabor } 992219019Sgabor 993219019Sgabor // Check for xmm store 994219019Sgabor if( src_first_rc == rc_xmm && dst_first_rc == rc_stack ) { 995219019Sgabor return impl_x_helper(cbuf,do_size,false,ra_->reg2offset(dst_first),src_first, src_second, size); 996219019Sgabor } 997219019Sgabor 998219019Sgabor // Check for float xmm load 999219019Sgabor if( dst_first_rc == rc_xmm && src_first_rc == rc_stack ) { 1000219019Sgabor return impl_x_helper(cbuf,do_size,true ,ra_->reg2offset(src_first),dst_first, dst_second, size); 1001219019Sgabor } 1002219019Sgabor 1003219019Sgabor // Copy from float reg to xmm reg 1004219019Sgabor if( dst_first_rc == rc_xmm && src_first_rc == rc_float ) { 1005219019Sgabor // copy to the top of stack from floating point reg 1006219019Sgabor // and use LEA to preserve flags 1007219019Sgabor if( cbuf ) { 1008219019Sgabor emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP-8] 1009219019Sgabor emit_rm(*cbuf, 0x1, ESP_enc, 0x04); 1010 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); 1011 emit_d8(*cbuf,0xF8); 1012#ifndef PRODUCT 1013 } else if( !do_size ) { 1014 if( size != 0 ) st->print("\n\t"); 1015 st->print("LEA ESP,[ESP-8]"); 1016#endif 1017 } 1018 size += 4; 1019 1020 size = impl_fp_store_helper(cbuf,do_size,src_first,src_second,dst_first,dst_second,0,size); 1021 1022 // Copy from the temp memory to the xmm reg. 1023 size = impl_x_helper(cbuf,do_size,true ,0,dst_first, dst_second, size); 1024 1025 if( cbuf ) { 1026 emit_opcode(*cbuf,0x8D); // LEA ESP,[ESP+8] 1027 emit_rm(*cbuf, 0x1, ESP_enc, 0x04); 1028 emit_rm(*cbuf, 0x0, 0x04, ESP_enc); 1029 emit_d8(*cbuf,0x08); 1030#ifndef PRODUCT 1031 } else if( !do_size ) { 1032 if( size != 0 ) st->print("\n\t"); 1033 st->print("LEA ESP,[ESP+8]"); 1034#endif 1035 } 1036 size += 4; 1037 return size; 1038 } 1039 1040 assert( size > 0, "missed a case" ); 1041 1042 // -------------------------------------------------------------------- 1043 // Check for second bits still needing moving. 1044 if( src_second == dst_second ) 1045 return size; // Self copy; no move 1046 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1047 1048 // Check for second word int-int move 1049 if( src_second_rc == rc_int && dst_second_rc == rc_int ) 1050 return impl_mov_helper(cbuf,do_size,src_second,dst_second,size); 1051 1052 // Check for second word integer store 1053 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1054 return impl_helper(cbuf,do_size,false,ra_->reg2offset(dst_second),src_second,0x89,"MOV ",size); 1055 1056 // Check for second word integer load 1057 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1058 return impl_helper(cbuf,do_size,true ,ra_->reg2offset(src_second),dst_second,0x8B,"MOV ",size); 1059 1060 1061 Unimplemented(); 1062} 1063 1064#ifndef PRODUCT 1065void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1066 implementation( NULL, ra_, false, st ); 1067} 1068#endif 1069 1070void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1071 implementation( &cbuf, ra_, false, NULL ); 1072} 1073 1074uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1075 return implementation( NULL, ra_, true, NULL ); 1076} 1077 1078//============================================================================= 1079#ifndef PRODUCT 1080void MachNopNode::format( PhaseRegAlloc *, outputStream* st ) const { 1081 st->print("NOP \t# %d bytes pad for loops and calls", _count); 1082} 1083#endif 1084 1085void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { 1086 MacroAssembler _masm(&cbuf); 1087 __ nop(_count); 1088} 1089 1090uint MachNopNode::size(PhaseRegAlloc *) const { 1091 return _count; 1092} 1093 1094 1095//============================================================================= 1096#ifndef PRODUCT 1097void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1098 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1099 int reg = ra_->get_reg_first(this); 1100 st->print("LEA %s,[ESP + #%d]",Matcher::regName[reg],offset); 1101} 1102#endif 1103 1104void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1105 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1106 int reg = ra_->get_encode(this); 1107 if( offset >= 128 ) { 1108 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] 1109 emit_rm(cbuf, 0x2, reg, 0x04); 1110 emit_rm(cbuf, 0x0, 0x04, ESP_enc); 1111 emit_d32(cbuf, offset); 1112 } 1113 else { 1114 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset] 1115 emit_rm(cbuf, 0x1, reg, 0x04); 1116 emit_rm(cbuf, 0x0, 0x04, ESP_enc); 1117 emit_d8(cbuf, offset); 1118 } 1119} 1120 1121uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1122 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1123 if( offset >= 128 ) { 1124 return 7; 1125 } 1126 else { 1127 return 4; 1128 } 1129} 1130 1131//============================================================================= 1132 1133// emit call stub, compiled java to interpreter 1134void emit_java_to_interp(CodeBuffer &cbuf ) { 1135 // Stub is fixed up when the corresponding call is converted from calling 1136 // compiled code to calling interpreted code. 1137 // mov rbx,0 1138 // jmp -1 1139 1140 address mark = cbuf.inst_mark(); // get mark within main instrs section 1141 1142 // Note that the code buffer's inst_mark is always relative to insts. 1143 // That's why we must use the macroassembler to generate a stub. 1144 MacroAssembler _masm(&cbuf); 1145 1146 address base = 1147 __ start_a_stub(Compile::MAX_stubs_size); 1148 if (base == NULL) return; // CodeBuffer::expand failed 1149 // static stub relocation stores the instruction address of the call 1150 __ relocate(static_stub_Relocation::spec(mark), RELOC_IMM32); 1151 // static stub relocation also tags the methodOop in the code-stream. 1152 __ movoop(rbx, (jobject)NULL); // method is zapped till fixup time 1153 __ jump(RuntimeAddress((address)-1)); 1154 1155 __ end_a_stub(); 1156 // Update current stubs pointer and restore code_end. 1157} 1158// size of call stub, compiled java to interpretor 1159uint size_java_to_interp() { 1160 return 10; // movl; jmp 1161} 1162// relocation entries for call stub, compiled java to interpretor 1163uint reloc_java_to_interp() { 1164 return 4; // 3 in emit_java_to_interp + 1 in Java_Static_Call 1165} 1166 1167//============================================================================= 1168#ifndef PRODUCT 1169void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream* st ) const { 1170 st->print_cr( "CMP EAX,[ECX+4]\t# Inline cache check"); 1171 st->print_cr("\tJNE SharedRuntime::handle_ic_miss_stub"); 1172 st->print_cr("\tNOP"); 1173 st->print_cr("\tNOP"); 1174 if( !OptoBreakpoint ) 1175 st->print_cr("\tNOP"); 1176} 1177#endif 1178 1179void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1180 MacroAssembler masm(&cbuf); 1181#ifdef ASSERT 1182 uint code_size = cbuf.code_size(); 1183#endif 1184 masm.cmpl(rax, Address(rcx, oopDesc::klass_offset_in_bytes())); 1185 masm.jump_cc(Assembler::notEqual, 1186 RuntimeAddress(SharedRuntime::get_ic_miss_stub())); 1187 /* WARNING these NOPs are critical so that verified entry point is properly 1188 aligned for patching by NativeJump::patch_verified_entry() */ 1189 int nops_cnt = 2; 1190 if( !OptoBreakpoint ) // Leave space for int3 1191 nops_cnt += 1; 1192 masm.nop(nops_cnt); 1193 1194 assert(cbuf.code_size() - code_size == size(ra_), "checking code size of inline cache node"); 1195} 1196 1197uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1198 return OptoBreakpoint ? 11 : 12; 1199} 1200 1201 1202//============================================================================= 1203uint size_exception_handler() { 1204 // NativeCall instruction size is the same as NativeJump. 1205 // exception handler starts out as jump and can be patched to 1206 // a call be deoptimization. (4932387) 1207 // Note that this value is also credited (in output.cpp) to 1208 // the size of the code section. 1209 return NativeJump::instruction_size; 1210} 1211 1212// Emit exception handler code. Stuff framesize into a register 1213// and call a VM stub routine. 1214int emit_exception_handler(CodeBuffer& cbuf) { 1215 1216 // Note that the code buffer's inst_mark is always relative to insts. 1217 // That's why we must use the macroassembler to generate a handler. 1218 MacroAssembler _masm(&cbuf); 1219 address base = 1220 __ start_a_stub(size_exception_handler()); 1221 if (base == NULL) return 0; // CodeBuffer::expand failed 1222 int offset = __ offset(); 1223 __ jump(RuntimeAddress(OptoRuntime::exception_blob()->instructions_begin())); 1224 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1225 __ end_a_stub(); 1226 return offset; 1227} 1228 1229uint size_deopt_handler() { 1230 // NativeCall instruction size is the same as NativeJump. 1231 // exception handler starts out as jump and can be patched to 1232 // a call be deoptimization. (4932387) 1233 // Note that this value is also credited (in output.cpp) to 1234 // the size of the code section. 1235 return 5 + NativeJump::instruction_size; // pushl(); jmp; 1236} 1237 1238// Emit deopt handler code. 1239int emit_deopt_handler(CodeBuffer& cbuf) { 1240 1241 // Note that the code buffer's inst_mark is always relative to insts. 1242 // That's why we must use the macroassembler to generate a handler. 1243 MacroAssembler _masm(&cbuf); 1244 address base = 1245 __ start_a_stub(size_exception_handler()); 1246 if (base == NULL) return 0; // CodeBuffer::expand failed 1247 int offset = __ offset(); 1248 InternalAddress here(__ pc()); 1249 __ pushptr(here.addr()); 1250 1251 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 1252 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1253 __ end_a_stub(); 1254 return offset; 1255} 1256 1257 1258static void emit_double_constant(CodeBuffer& cbuf, double x) { 1259 int mark = cbuf.insts()->mark_off(); 1260 MacroAssembler _masm(&cbuf); 1261 address double_address = __ double_constant(x); 1262 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift 1263 emit_d32_reloc(cbuf, 1264 (int)double_address, 1265 internal_word_Relocation::spec(double_address), 1266 RELOC_DISP32); 1267} 1268 1269static void emit_float_constant(CodeBuffer& cbuf, float x) { 1270 int mark = cbuf.insts()->mark_off(); 1271 MacroAssembler _masm(&cbuf); 1272 address float_address = __ float_constant(x); 1273 cbuf.insts()->set_mark_off(mark); // preserve mark across masm shift 1274 emit_d32_reloc(cbuf, 1275 (int)float_address, 1276 internal_word_Relocation::spec(float_address), 1277 RELOC_DISP32); 1278} 1279 1280 1281int Matcher::regnum_to_fpu_offset(int regnum) { 1282 return regnum - 32; // The FP registers are in the second chunk 1283} 1284 1285bool is_positive_zero_float(jfloat f) { 1286 return jint_cast(f) == jint_cast(0.0F); 1287} 1288 1289bool is_positive_one_float(jfloat f) { 1290 return jint_cast(f) == jint_cast(1.0F); 1291} 1292 1293bool is_positive_zero_double(jdouble d) { 1294 return jlong_cast(d) == jlong_cast(0.0); 1295} 1296 1297bool is_positive_one_double(jdouble d) { 1298 return jlong_cast(d) == jlong_cast(1.0); 1299} 1300 1301// This is UltraSparc specific, true just means we have fast l2f conversion 1302const bool Matcher::convL2FSupported(void) { 1303 return true; 1304} 1305 1306// Vector width in bytes 1307const uint Matcher::vector_width_in_bytes(void) { 1308 return UseSSE >= 2 ? 8 : 0; 1309} 1310 1311// Vector ideal reg 1312const uint Matcher::vector_ideal_reg(void) { 1313 return Op_RegD; 1314} 1315 1316// Is this branch offset short enough that a short branch can be used? 1317// 1318// NOTE: If the platform does not provide any short branch variants, then 1319// this method should return false for offset 0. 1320bool Matcher::is_short_branch_offset(int offset) { 1321 return (-128 <= offset && offset <= 127); 1322} 1323 1324const bool Matcher::isSimpleConstant64(jlong value) { 1325 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1326 return false; 1327} 1328 1329// The ecx parameter to rep stos for the ClearArray node is in dwords. 1330const bool Matcher::init_array_count_is_in_bytes = false; 1331 1332// Threshold size for cleararray. 1333const int Matcher::init_array_short_size = 8 * BytesPerLong; 1334 1335// Should the Matcher clone shifts on addressing modes, expecting them to 1336// be subsumed into complex addressing expressions or compute them into 1337// registers? True for Intel but false for most RISCs 1338const bool Matcher::clone_shift_expressions = true; 1339 1340// Is it better to copy float constants, or load them directly from memory? 1341// Intel can load a float constant from a direct address, requiring no 1342// extra registers. Most RISCs will have to materialize an address into a 1343// register first, so they would do better to copy the constant from stack. 1344const bool Matcher::rematerialize_float_constants = true; 1345 1346// If CPU can load and store mis-aligned doubles directly then no fixup is 1347// needed. Else we split the double into 2 integer pieces and move it 1348// piece-by-piece. Only happens when passing doubles into C code as the 1349// Java calling convention forces doubles to be aligned. 1350const bool Matcher::misaligned_doubles_ok = true; 1351 1352 1353void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1354 // Get the memory operand from the node 1355 uint numopnds = node->num_opnds(); // Virtual call for number of operands 1356 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far 1357 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" ); 1358 uint opcnt = 1; // First operand 1359 uint num_edges = node->_opnds[1]->num_edges(); // leaves for first operand 1360 while( idx >= skipped+num_edges ) { 1361 skipped += num_edges; 1362 opcnt++; // Bump operand count 1363 assert( opcnt < numopnds, "Accessing non-existent operand" ); 1364 num_edges = node->_opnds[opcnt]->num_edges(); // leaves for next operand 1365 } 1366 1367 MachOper *memory = node->_opnds[opcnt]; 1368 MachOper *new_memory = NULL; 1369 switch (memory->opcode()) { 1370 case DIRECT: 1371 case INDOFFSET32X: 1372 // No transformation necessary. 1373 return; 1374 case INDIRECT: 1375 new_memory = new (C) indirect_win95_safeOper( ); 1376 break; 1377 case INDOFFSET8: 1378 new_memory = new (C) indOffset8_win95_safeOper(memory->disp(NULL, NULL, 0)); 1379 break; 1380 case INDOFFSET32: 1381 new_memory = new (C) indOffset32_win95_safeOper(memory->disp(NULL, NULL, 0)); 1382 break; 1383 case INDINDEXOFFSET: 1384 new_memory = new (C) indIndexOffset_win95_safeOper(memory->disp(NULL, NULL, 0)); 1385 break; 1386 case INDINDEXSCALE: 1387 new_memory = new (C) indIndexScale_win95_safeOper(memory->scale()); 1388 break; 1389 case INDINDEXSCALEOFFSET: 1390 new_memory = new (C) indIndexScaleOffset_win95_safeOper(memory->scale(), memory->disp(NULL, NULL, 0)); 1391 break; 1392 case LOAD_LONG_INDIRECT: 1393 case LOAD_LONG_INDOFFSET32: 1394 // Does not use EBP as address register, use { EDX, EBX, EDI, ESI} 1395 return; 1396 default: 1397 assert(false, "unexpected memory operand in pd_implicit_null_fixup()"); 1398 return; 1399 } 1400 node->_opnds[opcnt] = new_memory; 1401} 1402 1403// Advertise here if the CPU requires explicit rounding operations 1404// to implement the UseStrictFP mode. 1405const bool Matcher::strict_fp_requires_explicit_rounding = true; 1406 1407// Do floats take an entire double register or just half? 1408const bool Matcher::float_in_double = true; 1409// Do ints take an entire long register or just half? 1410const bool Matcher::int_in_long = false; 1411 1412// Return whether or not this register is ever used as an argument. This 1413// function is used on startup to build the trampoline stubs in generateOptoStub. 1414// Registers not mentioned will be killed by the VM call in the trampoline, and 1415// arguments in those registers not be available to the callee. 1416bool Matcher::can_be_java_arg( int reg ) { 1417 if( reg == ECX_num || reg == EDX_num ) return true; 1418 if( (reg == XMM0a_num || reg == XMM1a_num) && UseSSE>=1 ) return true; 1419 if( (reg == XMM0b_num || reg == XMM1b_num) && UseSSE>=2 ) return true; 1420 return false; 1421} 1422 1423bool Matcher::is_spillable_arg( int reg ) { 1424 return can_be_java_arg(reg); 1425} 1426 1427// Register for DIVI projection of divmodI 1428RegMask Matcher::divI_proj_mask() { 1429 return EAX_REG_mask; 1430} 1431 1432// Register for MODI projection of divmodI 1433RegMask Matcher::modI_proj_mask() { 1434 return EDX_REG_mask; 1435} 1436 1437// Register for DIVL projection of divmodL 1438RegMask Matcher::divL_proj_mask() { 1439 ShouldNotReachHere(); 1440 return RegMask(); 1441} 1442 1443// Register for MODL projection of divmodL 1444RegMask Matcher::modL_proj_mask() { 1445 ShouldNotReachHere(); 1446 return RegMask(); 1447} 1448 1449%} 1450 1451//----------ENCODING BLOCK----------------------------------------------------- 1452// This block specifies the encoding classes used by the compiler to output 1453// byte streams. Encoding classes generate functions which are called by 1454// Machine Instruction Nodes in order to generate the bit encoding of the 1455// instruction. Operands specify their base encoding interface with the 1456// interface keyword. There are currently supported four interfaces, 1457// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1458// operand to generate a function which returns its register number when 1459// queried. CONST_INTER causes an operand to generate a function which 1460// returns the value of the constant when queried. MEMORY_INTER causes an 1461// operand to generate four functions which return the Base Register, the 1462// Index Register, the Scale Value, and the Offset Value of the operand when 1463// queried. COND_INTER causes an operand to generate six functions which 1464// return the encoding code (ie - encoding bits for the instruction) 1465// associated with each basic boolean condition for a conditional instruction. 1466// Instructions specify two basic values for encoding. They use the 1467// ins_encode keyword to specify their encoding class (which must be one of 1468// the class names specified in the encoding block), and they use the 1469// opcode keyword to specify, in order, their primary, secondary, and 1470// tertiary opcode. Only the opcode sections which a particular instruction 1471// needs for encoding need to be specified. 1472encode %{ 1473 // Build emit functions for each basic byte or larger field in the intel 1474 // encoding scheme (opcode, rm, sib, immediate), and call them from C++ 1475 // code in the enc_class source block. Emit functions will live in the 1476 // main source block for now. In future, we can generalize this by 1477 // adding a syntax that specifies the sizes of fields in an order, 1478 // so that the adlc can build the emit functions automagically 1479 enc_class OpcP %{ // Emit opcode 1480 emit_opcode(cbuf,$primary); 1481 %} 1482 1483 enc_class OpcS %{ // Emit opcode 1484 emit_opcode(cbuf,$secondary); 1485 %} 1486 1487 enc_class Opcode(immI d8 ) %{ // Emit opcode 1488 emit_opcode(cbuf,$d8$$constant); 1489 %} 1490 1491 enc_class SizePrefix %{ 1492 emit_opcode(cbuf,0x66); 1493 %} 1494 1495 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) 1496 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1497 %} 1498 1499 enc_class OpcRegReg (immI opcode, eRegI dst, eRegI src) %{ // OpcRegReg(Many) 1500 emit_opcode(cbuf,$opcode$$constant); 1501 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1502 %} 1503 1504 enc_class mov_r32_imm0( eRegI dst ) %{ 1505 emit_opcode( cbuf, 0xB8 + $dst$$reg ); // 0xB8+ rd -- MOV r32 ,imm32 1506 emit_d32 ( cbuf, 0x0 ); // imm32==0x0 1507 %} 1508 1509 enc_class cdq_enc %{ 1510 // Full implementation of Java idiv and irem; checks for 1511 // special case as described in JVM spec., p.243 & p.271. 1512 // 1513 // normal case special case 1514 // 1515 // input : rax,: dividend min_int 1516 // reg: divisor -1 1517 // 1518 // output: rax,: quotient (= rax, idiv reg) min_int 1519 // rdx: remainder (= rax, irem reg) 0 1520 // 1521 // Code sequnce: 1522 // 1523 // 81 F8 00 00 00 80 cmp rax,80000000h 1524 // 0F 85 0B 00 00 00 jne normal_case 1525 // 33 D2 xor rdx,edx 1526 // 83 F9 FF cmp rcx,0FFh 1527 // 0F 84 03 00 00 00 je done 1528 // normal_case: 1529 // 99 cdq 1530 // F7 F9 idiv rax,ecx 1531 // done: 1532 // 1533 emit_opcode(cbuf,0x81); emit_d8(cbuf,0xF8); 1534 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); 1535 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x80); // cmp rax,80000000h 1536 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x85); 1537 emit_opcode(cbuf,0x0B); emit_d8(cbuf,0x00); 1538 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // jne normal_case 1539 emit_opcode(cbuf,0x33); emit_d8(cbuf,0xD2); // xor rdx,edx 1540 emit_opcode(cbuf,0x83); emit_d8(cbuf,0xF9); emit_d8(cbuf,0xFF); // cmp rcx,0FFh 1541 emit_opcode(cbuf,0x0F); emit_d8(cbuf,0x84); 1542 emit_opcode(cbuf,0x03); emit_d8(cbuf,0x00); 1543 emit_opcode(cbuf,0x00); emit_d8(cbuf,0x00); // je done 1544 // normal_case: 1545 emit_opcode(cbuf,0x99); // cdq 1546 // idiv (note: must be emitted by the user of this rule) 1547 // normal: 1548 %} 1549 1550 // Dense encoding for older common ops 1551 enc_class Opc_plus(immI opcode, eRegI reg) %{ 1552 emit_opcode(cbuf, $opcode$$constant + $reg$$reg); 1553 %} 1554 1555 1556 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension 1557 enc_class OpcSE (immI imm) %{ // Emit primary opcode and set sign-extend bit 1558 // Check for 8-bit immediate, and set sign extend bit in opcode 1559 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1560 emit_opcode(cbuf, $primary | 0x02); 1561 } 1562 else { // If 32-bit immediate 1563 emit_opcode(cbuf, $primary); 1564 } 1565 %} 1566 1567 enc_class OpcSErm (eRegI dst, immI imm) %{ // OpcSEr/m 1568 // Emit primary opcode and set sign-extend bit 1569 // Check for 8-bit immediate, and set sign extend bit in opcode 1570 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1571 emit_opcode(cbuf, $primary | 0x02); } 1572 else { // If 32-bit immediate 1573 emit_opcode(cbuf, $primary); 1574 } 1575 // Emit r/m byte with secondary opcode, after primary opcode. 1576 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1577 %} 1578 1579 enc_class Con8or32 (immI imm) %{ // Con8or32(storeImmI), 8 or 32 bits 1580 // Check for 8-bit immediate, and set sign extend bit in opcode 1581 if (($imm$$constant >= -128) && ($imm$$constant <= 127)) { 1582 $$$emit8$imm$$constant; 1583 } 1584 else { // If 32-bit immediate 1585 // Output immediate 1586 $$$emit32$imm$$constant; 1587 } 1588 %} 1589 1590 enc_class Long_OpcSErm_Lo(eRegL dst, immL imm) %{ 1591 // Emit primary opcode and set sign-extend bit 1592 // Check for 8-bit immediate, and set sign extend bit in opcode 1593 int con = (int)$imm$$constant; // Throw away top bits 1594 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); 1595 // Emit r/m byte with secondary opcode, after primary opcode. 1596 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1597 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); 1598 else emit_d32(cbuf,con); 1599 %} 1600 1601 enc_class Long_OpcSErm_Hi(eRegL dst, immL imm) %{ 1602 // Emit primary opcode and set sign-extend bit 1603 // Check for 8-bit immediate, and set sign extend bit in opcode 1604 int con = (int)($imm$$constant >> 32); // Throw away bottom bits 1605 emit_opcode(cbuf, ((con >= -128) && (con <= 127)) ? ($primary | 0x02) : $primary); 1606 // Emit r/m byte with tertiary opcode, after primary opcode. 1607 emit_rm(cbuf, 0x3, $tertiary, HIGH_FROM_LOW($dst$$reg)); 1608 if ((con >= -128) && (con <= 127)) emit_d8 (cbuf,con); 1609 else emit_d32(cbuf,con); 1610 %} 1611 1612 enc_class Lbl (label labl) %{ // JMP, CALL 1613 Label *l = $labl$$label; 1614 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0); 1615 %} 1616 1617 enc_class LblShort (label labl) %{ // JMP, CALL 1618 Label *l = $labl$$label; 1619 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0; 1620 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); 1621 emit_d8(cbuf, disp); 1622 %} 1623 1624 enc_class OpcSReg (eRegI dst) %{ // BSWAP 1625 emit_cc(cbuf, $secondary, $dst$$reg ); 1626 %} 1627 1628 enc_class bswap_long_bytes(eRegL dst) %{ // BSWAP 1629 int destlo = $dst$$reg; 1630 int desthi = HIGH_FROM_LOW(destlo); 1631 // bswap lo 1632 emit_opcode(cbuf, 0x0F); 1633 emit_cc(cbuf, 0xC8, destlo); 1634 // bswap hi 1635 emit_opcode(cbuf, 0x0F); 1636 emit_cc(cbuf, 0xC8, desthi); 1637 // xchg lo and hi 1638 emit_opcode(cbuf, 0x87); 1639 emit_rm(cbuf, 0x3, destlo, desthi); 1640 %} 1641 1642 enc_class RegOpc (eRegI div) %{ // IDIV, IMOD, JMP indirect, ... 1643 emit_rm(cbuf, 0x3, $secondary, $div$$reg ); 1644 %} 1645 1646 enc_class Jcc (cmpOp cop, label labl) %{ // JCC 1647 Label *l = $labl$$label; 1648 $$$emit8$primary; 1649 emit_cc(cbuf, $secondary, $cop$$cmpcode); 1650 emit_d32(cbuf, l ? (l->loc_pos() - (cbuf.code_size()+4)) : 0); 1651 %} 1652 1653 enc_class JccShort (cmpOp cop, label labl) %{ // JCC 1654 Label *l = $labl$$label; 1655 emit_cc(cbuf, $primary, $cop$$cmpcode); 1656 int disp = l ? (l->loc_pos() - (cbuf.code_size()+1)) : 0; 1657 assert(-128 <= disp && disp <= 127, "Displacement too large for short jmp"); 1658 emit_d8(cbuf, disp); 1659 %} 1660 1661 enc_class enc_cmov(cmpOp cop ) %{ // CMOV 1662 $$$emit8$primary; 1663 emit_cc(cbuf, $secondary, $cop$$cmpcode); 1664 %} 1665 1666 enc_class enc_cmov_d(cmpOp cop, regD src ) %{ // CMOV 1667 int op = 0xDA00 + $cop$$cmpcode + ($src$$reg-1); 1668 emit_d8(cbuf, op >> 8 ); 1669 emit_d8(cbuf, op & 255); 1670 %} 1671 1672 // emulate a CMOV with a conditional branch around a MOV 1673 enc_class enc_cmov_branch( cmpOp cop, immI brOffs ) %{ // CMOV 1674 // Invert sense of branch from sense of CMOV 1675 emit_cc( cbuf, 0x70, ($cop$$cmpcode^1) ); 1676 emit_d8( cbuf, $brOffs$$constant ); 1677 %} 1678 1679 enc_class enc_PartialSubtypeCheck( ) %{ 1680 Register Redi = as_Register(EDI_enc); // result register 1681 Register Reax = as_Register(EAX_enc); // super class 1682 Register Recx = as_Register(ECX_enc); // killed 1683 Register Resi = as_Register(ESI_enc); // sub class 1684 Label hit, miss; 1685 1686 MacroAssembler _masm(&cbuf); 1687 // Compare super with sub directly, since super is not in its own SSA. 1688 // The compiler used to emit this test, but we fold it in here, 1689 // to allow platform-specific tweaking on sparc. 1690 __ cmpl(Reax, Resi); 1691 __ jcc(Assembler::equal, hit); 1692#ifndef PRODUCT 1693 __ increment(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr)); 1694#endif //PRODUCT 1695 __ movl(Redi,Address(Resi,sizeof(oopDesc) + Klass::secondary_supers_offset_in_bytes())); 1696 __ movl(Recx,Address(Redi,arrayOopDesc::length_offset_in_bytes())); 1697 __ addl(Redi,arrayOopDesc::base_offset_in_bytes(T_OBJECT)); 1698 __ repne_scan(); 1699 __ jcc(Assembler::notEqual, miss); 1700 __ movl(Address(Resi,sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()),Reax); 1701 __ bind(hit); 1702 if( $primary ) 1703 __ xorl(Redi,Redi); 1704 __ bind(miss); 1705 %} 1706 1707 enc_class FFree_Float_Stack_All %{ // Free_Float_Stack_All 1708 MacroAssembler masm(&cbuf); 1709 int start = masm.offset(); 1710 if (UseSSE >= 2) { 1711 if (VerifyFPU) { 1712 masm.verify_FPU(0, "must be empty in SSE2+ mode"); 1713 } 1714 } else { 1715 // External c_calling_convention expects the FPU stack to be 'clean'. 1716 // Compiled code leaves it dirty. Do cleanup now. 1717 masm.empty_FPU_stack(); 1718 } 1719 if (sizeof_FFree_Float_Stack_All == -1) { 1720 sizeof_FFree_Float_Stack_All = masm.offset() - start; 1721 } else { 1722 assert(masm.offset() - start == sizeof_FFree_Float_Stack_All, "wrong size"); 1723 } 1724 %} 1725 1726 enc_class Verify_FPU_For_Leaf %{ 1727 if( VerifyFPU ) { 1728 MacroAssembler masm(&cbuf); 1729 masm.verify_FPU( -3, "Returning from Runtime Leaf call"); 1730 } 1731 %} 1732 1733 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime, Java_To_Runtime_Leaf 1734 // This is the instruction starting address for relocation info. 1735 cbuf.set_inst_mark(); 1736 $$$emit8$primary; 1737 // CALL directly to the runtime 1738 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1739 runtime_call_Relocation::spec(), RELOC_IMM32 ); 1740 1741 if (UseSSE >= 2) { 1742 MacroAssembler _masm(&cbuf); 1743 BasicType rt = tf()->return_type(); 1744 1745 if ((rt == T_FLOAT || rt == T_DOUBLE) && !return_value_is_used()) { 1746 // A C runtime call where the return value is unused. In SSE2+ 1747 // mode the result needs to be removed from the FPU stack. It's 1748 // likely that this function call could be removed by the 1749 // optimizer if the C function is a pure function. 1750 __ ffree(0); 1751 } else if (rt == T_FLOAT) { 1752 __ leal(rsp, Address(rsp, -4)); 1753 __ fstp_s(Address(rsp, 0)); 1754 __ movflt(xmm0, Address(rsp, 0)); 1755 __ leal(rsp, Address(rsp, 4)); 1756 } else if (rt == T_DOUBLE) { 1757 __ leal(rsp, Address(rsp, -8)); 1758 __ fstp_d(Address(rsp, 0)); 1759 __ movdbl(xmm0, Address(rsp, 0)); 1760 __ leal(rsp, Address(rsp, 8)); 1761 } 1762 } 1763 %} 1764 1765 1766 enc_class pre_call_FPU %{ 1767 // If method sets FPU control word restore it here 1768 if( Compile::current()->in_24_bit_fp_mode() ) { 1769 MacroAssembler masm(&cbuf); 1770 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1771 } 1772 %} 1773 1774 enc_class post_call_FPU %{ 1775 // If method sets FPU control word do it here also 1776 if( Compile::current()->in_24_bit_fp_mode() ) { 1777 MacroAssembler masm(&cbuf); 1778 masm.fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 1779 } 1780 %} 1781 1782 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 1783 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 1784 // who we intended to call. 1785 cbuf.set_inst_mark(); 1786 $$$emit8$primary; 1787 if ( !_method ) { 1788 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1789 runtime_call_Relocation::spec(), RELOC_IMM32 ); 1790 } else if(_optimized_virtual) { 1791 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1792 opt_virtual_call_Relocation::spec(), RELOC_IMM32 ); 1793 } else { 1794 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1795 static_call_Relocation::spec(), RELOC_IMM32 ); 1796 } 1797 if( _method ) { // Emit stub for static call 1798 emit_java_to_interp(cbuf); 1799 } 1800 %} 1801 1802 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 1803 // !!!!! 1804 // Generate "Mov EAX,0x00", placeholder instruction to load oop-info 1805 // emit_call_dynamic_prologue( cbuf ); 1806 cbuf.set_inst_mark(); 1807 emit_opcode(cbuf, 0xB8 + EAX_enc); // mov EAX,-1 1808 emit_d32_reloc(cbuf, (int)Universe::non_oop_word(), oop_Relocation::spec_for_immediate(), RELOC_IMM32); 1809 address virtual_call_oop_addr = cbuf.inst_mark(); 1810 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 1811 // who we intended to call. 1812 cbuf.set_inst_mark(); 1813 $$$emit8$primary; 1814 emit_d32_reloc(cbuf, ($meth$$method - (int)(cbuf.code_end()) - 4), 1815 virtual_call_Relocation::spec(virtual_call_oop_addr), RELOC_IMM32 ); 1816 %} 1817 1818 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 1819 int disp = in_bytes(methodOopDesc::from_compiled_offset()); 1820 assert( -128 <= disp && disp <= 127, "compiled_code_offset isn't small"); 1821 1822 // CALL *[EAX+in_bytes(methodOopDesc::from_compiled_code_entry_point_offset())] 1823 cbuf.set_inst_mark(); 1824 $$$emit8$primary; 1825 emit_rm(cbuf, 0x01, $secondary, EAX_enc ); // R/M byte 1826 emit_d8(cbuf, disp); // Displacement 1827 1828 %} 1829 1830 enc_class Xor_Reg (eRegI dst) %{ 1831 emit_opcode(cbuf, 0x33); 1832 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); 1833 %} 1834 1835// Following encoding is no longer used, but may be restored if calling 1836// convention changes significantly. 1837// Became: Xor_Reg(EBP), Java_To_Runtime( labl ) 1838// 1839// enc_class Java_Interpreter_Call (label labl) %{ // JAVA INTERPRETER CALL 1840// // int ic_reg = Matcher::inline_cache_reg(); 1841// // int ic_encode = Matcher::_regEncode[ic_reg]; 1842// // int imo_reg = Matcher::interpreter_method_oop_reg(); 1843// // int imo_encode = Matcher::_regEncode[imo_reg]; 1844// 1845// // // Interpreter expects method_oop in EBX, currently a callee-saved register, 1846// // // so we load it immediately before the call 1847// // emit_opcode(cbuf, 0x8B); // MOV imo_reg,ic_reg # method_oop 1848// // emit_rm(cbuf, 0x03, imo_encode, ic_encode ); // R/M byte 1849// 1850// // xor rbp,ebp 1851// emit_opcode(cbuf, 0x33); 1852// emit_rm(cbuf, 0x3, EBP_enc, EBP_enc); 1853// 1854// // CALL to interpreter. 1855// cbuf.set_inst_mark(); 1856// $$$emit8$primary; 1857// emit_d32_reloc(cbuf, ($labl$$label - (int)(cbuf.code_end()) - 4), 1858// runtime_call_Relocation::spec(), RELOC_IMM32 ); 1859// %} 1860 1861 enc_class RegOpcImm (eRegI dst, immI8 shift) %{ // SHL, SAR, SHR 1862 $$$emit8$primary; 1863 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 1864 $$$emit8$shift$$constant; 1865 %} 1866 1867 enc_class LdImmI (eRegI dst, immI src) %{ // Load Immediate 1868 // Load immediate does not have a zero or sign extended version 1869 // for 8-bit immediates 1870 emit_opcode(cbuf, 0xB8 + $dst$$reg); 1871 $$$emit32$src$$constant; 1872 %} 1873 1874 enc_class LdImmP (eRegI dst, immI src) %{ // Load Immediate 1875 // Load immediate does not have a zero or sign extended version 1876 // for 8-bit immediates 1877 emit_opcode(cbuf, $primary + $dst$$reg); 1878 $$$emit32$src$$constant; 1879 %} 1880 1881 enc_class LdImmL_Lo( eRegL dst, immL src) %{ // Load Immediate 1882 // Load immediate does not have a zero or sign extended version 1883 // for 8-bit immediates 1884 int dst_enc = $dst$$reg; 1885 int src_con = $src$$constant & 0x0FFFFFFFFL; 1886 if (src_con == 0) { 1887 // xor dst, dst 1888 emit_opcode(cbuf, 0x33); 1889 emit_rm(cbuf, 0x3, dst_enc, dst_enc); 1890 } else { 1891 emit_opcode(cbuf, $primary + dst_enc); 1892 emit_d32(cbuf, src_con); 1893 } 1894 %} 1895 1896 enc_class LdImmL_Hi( eRegL dst, immL src) %{ // Load Immediate 1897 // Load immediate does not have a zero or sign extended version 1898 // for 8-bit immediates 1899 int dst_enc = $dst$$reg + 2; 1900 int src_con = ((julong)($src$$constant)) >> 32; 1901 if (src_con == 0) { 1902 // xor dst, dst 1903 emit_opcode(cbuf, 0x33); 1904 emit_rm(cbuf, 0x3, dst_enc, dst_enc); 1905 } else { 1906 emit_opcode(cbuf, $primary + dst_enc); 1907 emit_d32(cbuf, src_con); 1908 } 1909 %} 1910 1911 1912 enc_class LdImmD (immD src) %{ // Load Immediate 1913 if( is_positive_zero_double($src$$constant)) { 1914 // FLDZ 1915 emit_opcode(cbuf,0xD9); 1916 emit_opcode(cbuf,0xEE); 1917 } else if( is_positive_one_double($src$$constant)) { 1918 // FLD1 1919 emit_opcode(cbuf,0xD9); 1920 emit_opcode(cbuf,0xE8); 1921 } else { 1922 emit_opcode(cbuf,0xDD); 1923 emit_rm(cbuf, 0x0, 0x0, 0x5); 1924 emit_double_constant(cbuf, $src$$constant); 1925 } 1926 %} 1927 1928 1929 enc_class LdImmF (immF src) %{ // Load Immediate 1930 if( is_positive_zero_float($src$$constant)) { 1931 emit_opcode(cbuf,0xD9); 1932 emit_opcode(cbuf,0xEE); 1933 } else if( is_positive_one_float($src$$constant)) { 1934 emit_opcode(cbuf,0xD9); 1935 emit_opcode(cbuf,0xE8); 1936 } else { 1937 $$$emit8$primary; 1938 // Load immediate does not have a zero or sign extended version 1939 // for 8-bit immediates 1940 // First load to TOS, then move to dst 1941 emit_rm(cbuf, 0x0, 0x0, 0x5); 1942 emit_float_constant(cbuf, $src$$constant); 1943 } 1944 %} 1945 1946 enc_class LdImmX (regX dst, immXF con) %{ // Load Immediate 1947 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 1948 emit_float_constant(cbuf, $con$$constant); 1949 %} 1950 1951 enc_class LdImmXD (regXD dst, immXD con) %{ // Load Immediate 1952 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 1953 emit_double_constant(cbuf, $con$$constant); 1954 %} 1955 1956 enc_class load_conXD (regXD dst, immXD con) %{ // Load double constant 1957 // UseXmmLoadAndClearUpper ? movsd(dst, con) : movlpd(dst, con) 1958 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 1959 emit_opcode(cbuf, 0x0F); 1960 emit_opcode(cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); 1961 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 1962 emit_double_constant(cbuf, $con$$constant); 1963 %} 1964 1965 enc_class Opc_MemImm_F(immF src) %{ 1966 cbuf.set_inst_mark(); 1967 $$$emit8$primary; 1968 emit_rm(cbuf, 0x0, $secondary, 0x5); 1969 emit_float_constant(cbuf, $src$$constant); 1970 %} 1971 1972 1973 enc_class MovI2X_reg(regX dst, eRegI src) %{ 1974 emit_opcode(cbuf, 0x66 ); // MOVD dst,src 1975 emit_opcode(cbuf, 0x0F ); 1976 emit_opcode(cbuf, 0x6E ); 1977 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1978 %} 1979 1980 enc_class MovX2I_reg(eRegI dst, regX src) %{ 1981 emit_opcode(cbuf, 0x66 ); // MOVD dst,src 1982 emit_opcode(cbuf, 0x0F ); 1983 emit_opcode(cbuf, 0x7E ); 1984 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg); 1985 %} 1986 1987 enc_class MovL2XD_reg(regXD dst, eRegL src, regXD tmp) %{ 1988 { // MOVD $dst,$src.lo 1989 emit_opcode(cbuf,0x66); 1990 emit_opcode(cbuf,0x0F); 1991 emit_opcode(cbuf,0x6E); 1992 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 1993 } 1994 { // MOVD $tmp,$src.hi 1995 emit_opcode(cbuf,0x66); 1996 emit_opcode(cbuf,0x0F); 1997 emit_opcode(cbuf,0x6E); 1998 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); 1999 } 2000 { // PUNPCKLDQ $dst,$tmp 2001 emit_opcode(cbuf,0x66); 2002 emit_opcode(cbuf,0x0F); 2003 emit_opcode(cbuf,0x62); 2004 emit_rm(cbuf, 0x3, $dst$$reg, $tmp$$reg); 2005 } 2006 %} 2007 2008 enc_class MovXD2L_reg(eRegL dst, regXD src, regXD tmp) %{ 2009 { // MOVD $dst.lo,$src 2010 emit_opcode(cbuf,0x66); 2011 emit_opcode(cbuf,0x0F); 2012 emit_opcode(cbuf,0x7E); 2013 emit_rm(cbuf, 0x3, $src$$reg, $dst$$reg); 2014 } 2015 { // PSHUFLW $tmp,$src,0x4E (01001110b) 2016 emit_opcode(cbuf,0xF2); 2017 emit_opcode(cbuf,0x0F); 2018 emit_opcode(cbuf,0x70); 2019 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); 2020 emit_d8(cbuf, 0x4E); 2021 } 2022 { // MOVD $dst.hi,$tmp 2023 emit_opcode(cbuf,0x66); 2024 emit_opcode(cbuf,0x0F); 2025 emit_opcode(cbuf,0x7E); 2026 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg)); 2027 } 2028 %} 2029 2030 2031 // Encode a reg-reg copy. If it is useless, then empty encoding. 2032 enc_class enc_Copy( eRegI dst, eRegI src ) %{ 2033 encode_Copy( cbuf, $dst$$reg, $src$$reg ); 2034 %} 2035 2036 enc_class enc_CopyL_Lo( eRegI dst, eRegL src ) %{ 2037 encode_Copy( cbuf, $dst$$reg, $src$$reg ); 2038 %} 2039 2040 // Encode xmm reg-reg copy. If it is useless, then empty encoding. 2041 enc_class enc_CopyXD( RegXD dst, RegXD src ) %{ 2042 encode_CopyXD( cbuf, $dst$$reg, $src$$reg ); 2043 %} 2044 2045 enc_class RegReg (eRegI dst, eRegI src) %{ // RegReg(Many) 2046 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2047 %} 2048 2049 enc_class RegReg_Lo(eRegL dst, eRegL src) %{ // RegReg(Many) 2050 $$$emit8$primary; 2051 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2052 %} 2053 2054 enc_class RegReg_Hi(eRegL dst, eRegL src) %{ // RegReg(Many) 2055 $$$emit8$secondary; 2056 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); 2057 %} 2058 2059 enc_class RegReg_Lo2(eRegL dst, eRegL src) %{ // RegReg(Many) 2060 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2061 %} 2062 2063 enc_class RegReg_Hi2(eRegL dst, eRegL src) %{ // RegReg(Many) 2064 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg)); 2065 %} 2066 2067 enc_class RegReg_HiLo( eRegL src, eRegI dst ) %{ 2068 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($src$$reg)); 2069 %} 2070 2071 enc_class Con32 (immI src) %{ // Con32(storeImmI) 2072 // Output immediate 2073 $$$emit32$src$$constant; 2074 %} 2075 2076 enc_class Con32F_as_bits(immF src) %{ // storeF_imm 2077 // Output Float immediate bits 2078 jfloat jf = $src$$constant; 2079 int jf_as_bits = jint_cast( jf ); 2080 emit_d32(cbuf, jf_as_bits); 2081 %} 2082 2083 enc_class Con32XF_as_bits(immXF src) %{ // storeX_imm 2084 // Output Float immediate bits 2085 jfloat jf = $src$$constant; 2086 int jf_as_bits = jint_cast( jf ); 2087 emit_d32(cbuf, jf_as_bits); 2088 %} 2089 2090 enc_class Con16 (immI src) %{ // Con16(storeImmI) 2091 // Output immediate 2092 $$$emit16$src$$constant; 2093 %} 2094 2095 enc_class Con_d32(immI src) %{ 2096 emit_d32(cbuf,$src$$constant); 2097 %} 2098 2099 enc_class conmemref (eRegP t1) %{ // Con32(storeImmI) 2100 // Output immediate memory reference 2101 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 ); 2102 emit_d32(cbuf, 0x00); 2103 %} 2104 2105 enc_class lock_prefix( ) %{ 2106 if( os::is_MP() ) 2107 emit_opcode(cbuf,0xF0); // [Lock] 2108 %} 2109 2110 // Cmp-xchg long value. 2111 // Note: we need to swap rbx, and rcx before and after the 2112 // cmpxchg8 instruction because the instruction uses 2113 // rcx as the high order word of the new value to store but 2114 // our register encoding uses rbx,. 2115 enc_class enc_cmpxchg8(eSIRegP mem_ptr) %{ 2116 2117 // XCHG rbx,ecx 2118 emit_opcode(cbuf,0x87); 2119 emit_opcode(cbuf,0xD9); 2120 // [Lock] 2121 if( os::is_MP() ) 2122 emit_opcode(cbuf,0xF0); 2123 // CMPXCHG8 [Eptr] 2124 emit_opcode(cbuf,0x0F); 2125 emit_opcode(cbuf,0xC7); 2126 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); 2127 // XCHG rbx,ecx 2128 emit_opcode(cbuf,0x87); 2129 emit_opcode(cbuf,0xD9); 2130 %} 2131 2132 enc_class enc_cmpxchg(eSIRegP mem_ptr) %{ 2133 // [Lock] 2134 if( os::is_MP() ) 2135 emit_opcode(cbuf,0xF0); 2136 2137 // CMPXCHG [Eptr] 2138 emit_opcode(cbuf,0x0F); 2139 emit_opcode(cbuf,0xB1); 2140 emit_rm( cbuf, 0x0, 1, $mem_ptr$$reg ); 2141 %} 2142 2143 enc_class enc_flags_ne_to_boolean( iRegI res ) %{ 2144 int res_encoding = $res$$reg; 2145 2146 // MOV res,0 2147 emit_opcode( cbuf, 0xB8 + res_encoding); 2148 emit_d32( cbuf, 0 ); 2149 // JNE,s fail 2150 emit_opcode(cbuf,0x75); 2151 emit_d8(cbuf, 5 ); 2152 // MOV res,1 2153 emit_opcode( cbuf, 0xB8 + res_encoding); 2154 emit_d32( cbuf, 1 ); 2155 // fail: 2156 %} 2157 2158 enc_class set_instruction_start( ) %{ 2159 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand 2160 %} 2161 2162 enc_class RegMem (eRegI ereg, memory mem) %{ // emit_reg_mem 2163 int reg_encoding = $ereg$$reg; 2164 int base = $mem$$base; 2165 int index = $mem$$index; 2166 int scale = $mem$$scale; 2167 int displace = $mem$$disp; 2168 bool disp_is_oop = $mem->disp_is_oop(); 2169 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2170 %} 2171 2172 enc_class RegMem_Hi(eRegL ereg, memory mem) %{ // emit_reg_mem 2173 int reg_encoding = HIGH_FROM_LOW($ereg$$reg); // Hi register of pair, computed from lo 2174 int base = $mem$$base; 2175 int index = $mem$$index; 2176 int scale = $mem$$scale; 2177 int displace = $mem$$disp + 4; // Offset is 4 further in memory 2178 assert( !$mem->disp_is_oop(), "Cannot add 4 to oop" ); 2179 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, false/*disp_is_oop*/); 2180 %} 2181 2182 enc_class move_long_small_shift( eRegL dst, immI_1_31 cnt ) %{ 2183 int r1, r2; 2184 if( $tertiary == 0xA4 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } 2185 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } 2186 emit_opcode(cbuf,0x0F); 2187 emit_opcode(cbuf,$tertiary); 2188 emit_rm(cbuf, 0x3, r1, r2); 2189 emit_d8(cbuf,$cnt$$constant); 2190 emit_d8(cbuf,$primary); 2191 emit_rm(cbuf, 0x3, $secondary, r1); 2192 emit_d8(cbuf,$cnt$$constant); 2193 %} 2194 2195 enc_class move_long_big_shift_sign( eRegL dst, immI_32_63 cnt ) %{ 2196 emit_opcode( cbuf, 0x8B ); // Move 2197 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); 2198 emit_d8(cbuf,$primary); 2199 emit_rm(cbuf, 0x3, $secondary, $dst$$reg); 2200 emit_d8(cbuf,$cnt$$constant-32); 2201 emit_d8(cbuf,$primary); 2202 emit_rm(cbuf, 0x3, $secondary, HIGH_FROM_LOW($dst$$reg)); 2203 emit_d8(cbuf,31); 2204 %} 2205 2206 enc_class move_long_big_shift_clr( eRegL dst, immI_32_63 cnt ) %{ 2207 int r1, r2; 2208 if( $secondary == 0x5 ) { r1 = $dst$$reg; r2 = HIGH_FROM_LOW($dst$$reg); } 2209 else { r2 = $dst$$reg; r1 = HIGH_FROM_LOW($dst$$reg); } 2210 2211 emit_opcode( cbuf, 0x8B ); // Move r1,r2 2212 emit_rm(cbuf, 0x3, r1, r2); 2213 if( $cnt$$constant > 32 ) { // Shift, if not by zero 2214 emit_opcode(cbuf,$primary); 2215 emit_rm(cbuf, 0x3, $secondary, r1); 2216 emit_d8(cbuf,$cnt$$constant-32); 2217 } 2218 emit_opcode(cbuf,0x33); // XOR r2,r2 2219 emit_rm(cbuf, 0x3, r2, r2); 2220 %} 2221 2222 // Clone of RegMem but accepts an extra parameter to access each 2223 // half of a double in memory; it never needs relocation info. 2224 enc_class Mov_MemD_half_to_Reg (immI opcode, memory mem, immI disp_for_half, eRegI rm_reg) %{ 2225 emit_opcode(cbuf,$opcode$$constant); 2226 int reg_encoding = $rm_reg$$reg; 2227 int base = $mem$$base; 2228 int index = $mem$$index; 2229 int scale = $mem$$scale; 2230 int displace = $mem$$disp + $disp_for_half$$constant; 2231 bool disp_is_oop = false; 2232 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2233 %} 2234 2235 // !!!!! Special Custom Code used by MemMove, and stack access instructions !!!!! 2236 // 2237 // Clone of RegMem except the RM-byte's reg/opcode field is an ADLC-time constant 2238 // and it never needs relocation information. 2239 // Frequently used to move data between FPU's Stack Top and memory. 2240 enc_class RMopc_Mem_no_oop (immI rm_opcode, memory mem) %{ 2241 int rm_byte_opcode = $rm_opcode$$constant; 2242 int base = $mem$$base; 2243 int index = $mem$$index; 2244 int scale = $mem$$scale; 2245 int displace = $mem$$disp; 2246 assert( !$mem->disp_is_oop(), "No oops here because no relo info allowed" ); 2247 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, false); 2248 %} 2249 2250 enc_class RMopc_Mem (immI rm_opcode, memory mem) %{ 2251 int rm_byte_opcode = $rm_opcode$$constant; 2252 int base = $mem$$base; 2253 int index = $mem$$index; 2254 int scale = $mem$$scale; 2255 int displace = $mem$$disp; 2256 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 2257 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 2258 %} 2259 2260 enc_class RegLea (eRegI dst, eRegI src0, immI src1 ) %{ // emit_reg_lea 2261 int reg_encoding = $dst$$reg; 2262 int base = $src0$$reg; // 0xFFFFFFFF indicates no base 2263 int index = 0x04; // 0x04 indicates no index 2264 int scale = 0x00; // 0x00 indicates no scale 2265 int displace = $src1$$constant; // 0x00 indicates no displacement 2266 bool disp_is_oop = false; 2267 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2268 %} 2269 2270 enc_class min_enc (eRegI dst, eRegI src) %{ // MIN 2271 // Compare dst,src 2272 emit_opcode(cbuf,0x3B); 2273 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2274 // jmp dst < src around move 2275 emit_opcode(cbuf,0x7C); 2276 emit_d8(cbuf,2); 2277 // move dst,src 2278 emit_opcode(cbuf,0x8B); 2279 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2280 %} 2281 2282 enc_class max_enc (eRegI dst, eRegI src) %{ // MAX 2283 // Compare dst,src 2284 emit_opcode(cbuf,0x3B); 2285 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2286 // jmp dst > src around move 2287 emit_opcode(cbuf,0x7F); 2288 emit_d8(cbuf,2); 2289 // move dst,src 2290 emit_opcode(cbuf,0x8B); 2291 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 2292 %} 2293 2294 enc_class enc_FP_store(memory mem, regD src) %{ 2295 // If src is FPR1, we can just FST to store it. 2296 // Else we need to FLD it to FPR1, then FSTP to store/pop it. 2297 int reg_encoding = 0x2; // Just store 2298 int base = $mem$$base; 2299 int index = $mem$$index; 2300 int scale = $mem$$scale; 2301 int displace = $mem$$disp; 2302 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 2303 if( $src$$reg != FPR1L_enc ) { 2304 reg_encoding = 0x3; // Store & pop 2305 emit_opcode( cbuf, 0xD9 ); // FLD (i.e., push it) 2306 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2307 } 2308 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand 2309 emit_opcode(cbuf,$primary); 2310 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2311 %} 2312 2313 enc_class neg_reg(eRegI dst) %{ 2314 // NEG $dst 2315 emit_opcode(cbuf,0xF7); 2316 emit_rm(cbuf, 0x3, 0x03, $dst$$reg ); 2317 %} 2318 2319 enc_class setLT_reg(eCXRegI dst) %{ 2320 // SETLT $dst 2321 emit_opcode(cbuf,0x0F); 2322 emit_opcode(cbuf,0x9C); 2323 emit_rm( cbuf, 0x3, 0x4, $dst$$reg ); 2324 %} 2325 2326 enc_class enc_cmpLTP(ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp) %{ // cadd_cmpLT 2327 int tmpReg = $tmp$$reg; 2328 2329 // SUB $p,$q 2330 emit_opcode(cbuf,0x2B); 2331 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); 2332 // SBB $tmp,$tmp 2333 emit_opcode(cbuf,0x1B); 2334 emit_rm(cbuf, 0x3, tmpReg, tmpReg); 2335 // AND $tmp,$y 2336 emit_opcode(cbuf,0x23); 2337 emit_rm(cbuf, 0x3, tmpReg, $y$$reg); 2338 // ADD $p,$tmp 2339 emit_opcode(cbuf,0x03); 2340 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); 2341 %} 2342 2343 enc_class enc_cmpLTP_mem(eRegI p, eRegI q, memory mem, eCXRegI tmp) %{ // cadd_cmpLT 2344 int tmpReg = $tmp$$reg; 2345 2346 // SUB $p,$q 2347 emit_opcode(cbuf,0x2B); 2348 emit_rm(cbuf, 0x3, $p$$reg, $q$$reg); 2349 // SBB $tmp,$tmp 2350 emit_opcode(cbuf,0x1B); 2351 emit_rm(cbuf, 0x3, tmpReg, tmpReg); 2352 // AND $tmp,$y 2353 cbuf.set_inst_mark(); // Mark start of opcode for reloc info in mem operand 2354 emit_opcode(cbuf,0x23); 2355 int reg_encoding = tmpReg; 2356 int base = $mem$$base; 2357 int index = $mem$$index; 2358 int scale = $mem$$scale; 2359 int displace = $mem$$disp; 2360 bool disp_is_oop = $mem->disp_is_oop(); 2361 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace, disp_is_oop); 2362 // ADD $p,$tmp 2363 emit_opcode(cbuf,0x03); 2364 emit_rm(cbuf, 0x3, $p$$reg, tmpReg); 2365 %} 2366 2367 enc_class shift_left_long( eRegL dst, eCXRegI shift ) %{ 2368 // TEST shift,32 2369 emit_opcode(cbuf,0xF7); 2370 emit_rm(cbuf, 0x3, 0, ECX_enc); 2371 emit_d32(cbuf,0x20); 2372 // JEQ,s small 2373 emit_opcode(cbuf, 0x74); 2374 emit_d8(cbuf, 0x04); 2375 // MOV $dst.hi,$dst.lo 2376 emit_opcode( cbuf, 0x8B ); 2377 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); 2378 // CLR $dst.lo 2379 emit_opcode(cbuf, 0x33); 2380 emit_rm(cbuf, 0x3, $dst$$reg, $dst$$reg); 2381// small: 2382 // SHLD $dst.hi,$dst.lo,$shift 2383 emit_opcode(cbuf,0x0F); 2384 emit_opcode(cbuf,0xA5); 2385 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg)); 2386 // SHL $dst.lo,$shift" 2387 emit_opcode(cbuf,0xD3); 2388 emit_rm(cbuf, 0x3, 0x4, $dst$$reg ); 2389 %} 2390 2391 enc_class shift_right_long( eRegL dst, eCXRegI shift ) %{ 2392 // TEST shift,32 2393 emit_opcode(cbuf,0xF7); 2394 emit_rm(cbuf, 0x3, 0, ECX_enc); 2395 emit_d32(cbuf,0x20); 2396 // JEQ,s small 2397 emit_opcode(cbuf, 0x74); 2398 emit_d8(cbuf, 0x04); 2399 // MOV $dst.lo,$dst.hi 2400 emit_opcode( cbuf, 0x8B ); 2401 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); 2402 // CLR $dst.hi 2403 emit_opcode(cbuf, 0x33); 2404 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($dst$$reg)); 2405// small: 2406 // SHRD $dst.lo,$dst.hi,$shift 2407 emit_opcode(cbuf,0x0F); 2408 emit_opcode(cbuf,0xAD); 2409 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); 2410 // SHR $dst.hi,$shift" 2411 emit_opcode(cbuf,0xD3); 2412 emit_rm(cbuf, 0x3, 0x5, HIGH_FROM_LOW($dst$$reg) ); 2413 %} 2414 2415 enc_class shift_right_arith_long( eRegL dst, eCXRegI shift ) %{ 2416 // TEST shift,32 2417 emit_opcode(cbuf,0xF7); 2418 emit_rm(cbuf, 0x3, 0, ECX_enc); 2419 emit_d32(cbuf,0x20); 2420 // JEQ,s small 2421 emit_opcode(cbuf, 0x74); 2422 emit_d8(cbuf, 0x05); 2423 // MOV $dst.lo,$dst.hi 2424 emit_opcode( cbuf, 0x8B ); 2425 emit_rm(cbuf, 0x3, $dst$$reg, HIGH_FROM_LOW($dst$$reg) ); 2426 // SAR $dst.hi,31 2427 emit_opcode(cbuf, 0xC1); 2428 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW($dst$$reg) ); 2429 emit_d8(cbuf, 0x1F ); 2430// small: 2431 // SHRD $dst.lo,$dst.hi,$shift 2432 emit_opcode(cbuf,0x0F); 2433 emit_opcode(cbuf,0xAD); 2434 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg); 2435 // SAR $dst.hi,$shift" 2436 emit_opcode(cbuf,0xD3); 2437 emit_rm(cbuf, 0x3, 0x7, HIGH_FROM_LOW($dst$$reg) ); 2438 %} 2439 2440 2441 // ----------------- Encodings for floating point unit ----------------- 2442 // May leave result in FPU-TOS or FPU reg depending on opcodes 2443 enc_class OpcReg_F (regF src) %{ // FMUL, FDIV 2444 $$$emit8$primary; 2445 emit_rm(cbuf, 0x3, $secondary, $src$$reg ); 2446 %} 2447 2448 // Pop argument in FPR0 with FSTP ST(0) 2449 enc_class PopFPU() %{ 2450 emit_opcode( cbuf, 0xDD ); 2451 emit_d8( cbuf, 0xD8 ); 2452 %} 2453 2454 // !!!!! equivalent to Pop_Reg_F 2455 enc_class Pop_Reg_D( regD dst ) %{ 2456 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) 2457 emit_d8( cbuf, 0xD8+$dst$$reg ); 2458 %} 2459 2460 enc_class Push_Reg_D( regD dst ) %{ 2461 emit_opcode( cbuf, 0xD9 ); 2462 emit_d8( cbuf, 0xC0-1+$dst$$reg ); // FLD ST(i-1) 2463 %} 2464 2465 enc_class strictfp_bias1( regD dst ) %{ 2466 emit_opcode( cbuf, 0xDB ); // FLD m80real 2467 emit_opcode( cbuf, 0x2D ); 2468 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias1() ); 2469 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 2470 emit_opcode( cbuf, 0xC8+$dst$$reg ); 2471 %} 2472 2473 enc_class strictfp_bias2( regD dst ) %{ 2474 emit_opcode( cbuf, 0xDB ); // FLD m80real 2475 emit_opcode( cbuf, 0x2D ); 2476 emit_d32( cbuf, (int)StubRoutines::addr_fpu_subnormal_bias2() ); 2477 emit_opcode( cbuf, 0xDE ); // FMULP ST(dst), ST0 2478 emit_opcode( cbuf, 0xC8+$dst$$reg ); 2479 %} 2480 2481 // Special case for moving an integer register to a stack slot. 2482 enc_class OpcPRegSS( stackSlotI dst, eRegI src ) %{ // RegSS 2483 store_to_stackslot( cbuf, $primary, $src$$reg, $dst$$disp ); 2484 %} 2485 2486 // Special case for moving a register to a stack slot. 2487 enc_class RegSS( stackSlotI dst, eRegI src ) %{ // RegSS 2488 // Opcode already emitted 2489 emit_rm( cbuf, 0x02, $src$$reg, ESP_enc ); // R/M byte 2490 emit_rm( cbuf, 0x00, ESP_enc, ESP_enc); // SIB byte 2491 emit_d32(cbuf, $dst$$disp); // Displacement 2492 %} 2493 2494 // Push the integer in stackSlot 'src' onto FP-stack 2495 enc_class Push_Mem_I( memory src ) %{ // FILD [ESP+src] 2496 store_to_stackslot( cbuf, $primary, $secondary, $src$$disp ); 2497 %} 2498 2499 // Push the float in stackSlot 'src' onto FP-stack 2500 enc_class Push_Mem_F( memory src ) %{ // FLD_S [ESP+src] 2501 store_to_stackslot( cbuf, 0xD9, 0x00, $src$$disp ); 2502 %} 2503 2504 // Push the double in stackSlot 'src' onto FP-stack 2505 enc_class Push_Mem_D( memory src ) %{ // FLD_D [ESP+src] 2506 store_to_stackslot( cbuf, 0xDD, 0x00, $src$$disp ); 2507 %} 2508 2509 // Push FPU's TOS float to a stack-slot, and pop FPU-stack 2510 enc_class Pop_Mem_F( stackSlotF dst ) %{ // FSTP_S [ESP+dst] 2511 store_to_stackslot( cbuf, 0xD9, 0x03, $dst$$disp ); 2512 %} 2513 2514 // Same as Pop_Mem_F except for opcode 2515 // Push FPU's TOS double to a stack-slot, and pop FPU-stack 2516 enc_class Pop_Mem_D( stackSlotD dst ) %{ // FSTP_D [ESP+dst] 2517 store_to_stackslot( cbuf, 0xDD, 0x03, $dst$$disp ); 2518 %} 2519 2520 enc_class Pop_Reg_F( regF dst ) %{ 2521 emit_opcode( cbuf, 0xDD ); // FSTP ST(i) 2522 emit_d8( cbuf, 0xD8+$dst$$reg ); 2523 %} 2524 2525 enc_class Push_Reg_F( regF dst ) %{ 2526 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2527 emit_d8( cbuf, 0xC0-1+$dst$$reg ); 2528 %} 2529 2530 // Push FPU's float to a stack-slot, and pop FPU-stack 2531 enc_class Pop_Mem_Reg_F( stackSlotF dst, regF src ) %{ 2532 int pop = 0x02; 2533 if ($src$$reg != FPR1L_enc) { 2534 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2535 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2536 pop = 0x03; 2537 } 2538 store_to_stackslot( cbuf, 0xD9, pop, $dst$$disp ); // FST<P>_S [ESP+dst] 2539 %} 2540 2541 // Push FPU's double to a stack-slot, and pop FPU-stack 2542 enc_class Pop_Mem_Reg_D( stackSlotD dst, regD src ) %{ 2543 int pop = 0x02; 2544 if ($src$$reg != FPR1L_enc) { 2545 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 2546 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2547 pop = 0x03; 2548 } 2549 store_to_stackslot( cbuf, 0xDD, pop, $dst$$disp ); // FST<P>_D [ESP+dst] 2550 %} 2551 2552 // Push FPU's double to a FPU-stack-slot, and pop FPU-stack 2553 enc_class Pop_Reg_Reg_D( regD dst, regF src ) %{ 2554 int pop = 0xD0 - 1; // -1 since we skip FLD 2555 if ($src$$reg != FPR1L_enc) { 2556 emit_opcode( cbuf, 0xD9 ); // FLD ST(src-1) 2557 emit_d8( cbuf, 0xC0-1+$src$$reg ); 2558 pop = 0xD8; 2559 } 2560 emit_opcode( cbuf, 0xDD ); 2561 emit_d8( cbuf, pop+$dst$$reg ); // FST<P> ST(i) 2562 %} 2563 2564 2565 enc_class Mul_Add_F( regF dst, regF src, regF src1, regF src2 ) %{ 2566 MacroAssembler masm(&cbuf); 2567 masm.fld_s( $src1$$reg-1); // nothing at TOS, load TOS from src1.reg 2568 masm.fmul( $src2$$reg+0); // value at TOS 2569 masm.fadd( $src$$reg+0); // value at TOS 2570 masm.fstp_d( $dst$$reg+0); // value at TOS, popped off after store 2571 %} 2572 2573 2574 enc_class Push_Reg_Mod_D( regD dst, regD src) %{ 2575 // load dst in FPR0 2576 emit_opcode( cbuf, 0xD9 ); 2577 emit_d8( cbuf, 0xC0-1+$dst$$reg ); 2578 if ($src$$reg != FPR1L_enc) { 2579 // fincstp 2580 emit_opcode (cbuf, 0xD9); 2581 emit_opcode (cbuf, 0xF7); 2582 // swap src with FPR1: 2583 // FXCH FPR1 with src 2584 emit_opcode(cbuf, 0xD9); 2585 emit_d8(cbuf, 0xC8-1+$src$$reg ); 2586 // fdecstp 2587 emit_opcode (cbuf, 0xD9); 2588 emit_opcode (cbuf, 0xF6); 2589 } 2590 %} 2591 2592 enc_class Push_ModD_encoding( regXD src0, regXD src1) %{ 2593 // Allocate a word 2594 emit_opcode(cbuf,0x83); // SUB ESP,8 2595 emit_opcode(cbuf,0xEC); 2596 emit_d8(cbuf,0x08); 2597 2598 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src1 2599 emit_opcode (cbuf, 0x0F ); 2600 emit_opcode (cbuf, 0x11 ); 2601 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false); 2602 2603 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 2604 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2605 2606 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src0 2607 emit_opcode (cbuf, 0x0F ); 2608 emit_opcode (cbuf, 0x11 ); 2609 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false); 2610 2611 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 2612 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2613 2614 %} 2615 2616 enc_class Push_ModX_encoding( regX src0, regX src1) %{ 2617 // Allocate a word 2618 emit_opcode(cbuf,0x83); // SUB ESP,4 2619 emit_opcode(cbuf,0xEC); 2620 emit_d8(cbuf,0x04); 2621 2622 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src1 2623 emit_opcode (cbuf, 0x0F ); 2624 emit_opcode (cbuf, 0x11 ); 2625 encode_RegMem(cbuf, $src1$$reg, ESP_enc, 0x4, 0, 0, false); 2626 2627 emit_opcode(cbuf,0xD9 ); // FLD [ESP] 2628 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2629 2630 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src0 2631 emit_opcode (cbuf, 0x0F ); 2632 emit_opcode (cbuf, 0x11 ); 2633 encode_RegMem(cbuf, $src0$$reg, ESP_enc, 0x4, 0, 0, false); 2634 2635 emit_opcode(cbuf,0xD9 ); // FLD [ESP] 2636 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2637 2638 %} 2639 2640 enc_class Push_ResultXD(regXD dst) %{ 2641 store_to_stackslot( cbuf, 0xDD, 0x03, 0 ); //FSTP [ESP] 2642 2643 // UseXmmLoadAndClearUpper ? movsd dst,[esp] : movlpd dst,[esp] 2644 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 2645 emit_opcode (cbuf, 0x0F ); 2646 emit_opcode (cbuf, UseXmmLoadAndClearUpper ? 0x10 : 0x12); 2647 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); 2648 2649 emit_opcode(cbuf,0x83); // ADD ESP,8 2650 emit_opcode(cbuf,0xC4); 2651 emit_d8(cbuf,0x08); 2652 %} 2653 2654 enc_class Push_ResultX(regX dst, immI d8) %{ 2655 store_to_stackslot( cbuf, 0xD9, 0x03, 0 ); //FSTP_S [ESP] 2656 2657 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP] 2658 emit_opcode (cbuf, 0x0F ); 2659 emit_opcode (cbuf, 0x10 ); 2660 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); 2661 2662 emit_opcode(cbuf,0x83); // ADD ESP,d8 (4 or 8) 2663 emit_opcode(cbuf,0xC4); 2664 emit_d8(cbuf,$d8$$constant); 2665 %} 2666 2667 enc_class Push_SrcXD(regXD src) %{ 2668 // Allocate a word 2669 emit_opcode(cbuf,0x83); // SUB ESP,8 2670 emit_opcode(cbuf,0xEC); 2671 emit_d8(cbuf,0x08); 2672 2673 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src 2674 emit_opcode (cbuf, 0x0F ); 2675 emit_opcode (cbuf, 0x11 ); 2676 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 2677 2678 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 2679 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2680 %} 2681 2682 enc_class push_stack_temp_qword() %{ 2683 emit_opcode(cbuf,0x83); // SUB ESP,8 2684 emit_opcode(cbuf,0xEC); 2685 emit_d8 (cbuf,0x08); 2686 %} 2687 2688 enc_class pop_stack_temp_qword() %{ 2689 emit_opcode(cbuf,0x83); // ADD ESP,8 2690 emit_opcode(cbuf,0xC4); 2691 emit_d8 (cbuf,0x08); 2692 %} 2693 2694 enc_class push_xmm_to_fpr1( regXD xmm_src ) %{ 2695 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], xmm_src 2696 emit_opcode (cbuf, 0x0F ); 2697 emit_opcode (cbuf, 0x11 ); 2698 encode_RegMem(cbuf, $xmm_src$$reg, ESP_enc, 0x4, 0, 0, false); 2699 2700 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 2701 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2702 %} 2703 2704 // Compute X^Y using Intel's fast hardware instructions, if possible. 2705 // Otherwise return a NaN. 2706 enc_class pow_exp_core_encoding %{ 2707 // FPR1 holds Y*ln2(X). Compute FPR1 = 2^(Y*ln2(X)) 2708 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xC0); // fdup = fld st(0) Q Q 2709 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xFC); // frndint int(Q) Q 2710 emit_opcode(cbuf,0xDC); emit_opcode(cbuf,0xE9); // fsub st(1) -= st(0); int(Q) frac(Q) 2711 emit_opcode(cbuf,0xDB); // FISTP [ESP] frac(Q) 2712 emit_opcode(cbuf,0x1C); 2713 emit_d8(cbuf,0x24); 2714 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xF0); // f2xm1 2^frac(Q)-1 2715 emit_opcode(cbuf,0xD9); emit_opcode(cbuf,0xE8); // fld1 1 2^frac(Q)-1 2716 emit_opcode(cbuf,0xDE); emit_opcode(cbuf,0xC1); // faddp 2^frac(Q) 2717 emit_opcode(cbuf,0x8B); // mov rax,[esp+0]=int(Q) 2718 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 0, false); 2719 emit_opcode(cbuf,0xC7); // mov rcx,0xFFFFF800 - overflow mask 2720 emit_rm(cbuf, 0x3, 0x0, ECX_enc); 2721 emit_d32(cbuf,0xFFFFF800); 2722 emit_opcode(cbuf,0x81); // add rax,1023 - the double exponent bias 2723 emit_rm(cbuf, 0x3, 0x0, EAX_enc); 2724 emit_d32(cbuf,1023); 2725 emit_opcode(cbuf,0x8B); // mov rbx,eax 2726 emit_rm(cbuf, 0x3, EBX_enc, EAX_enc); 2727 emit_opcode(cbuf,0xC1); // shl rax,20 - Slide to exponent position 2728 emit_rm(cbuf,0x3,0x4,EAX_enc); 2729 emit_d8(cbuf,20); 2730 emit_opcode(cbuf,0x85); // test rbx,ecx - check for overflow 2731 emit_rm(cbuf, 0x3, EBX_enc, ECX_enc); 2732 emit_opcode(cbuf,0x0F); emit_opcode(cbuf,0x45); // CMOVne rax,ecx - overflow; stuff NAN into EAX 2733 emit_rm(cbuf, 0x3, EAX_enc, ECX_enc); 2734 emit_opcode(cbuf,0x89); // mov [esp+4],eax - Store as part of double word 2735 encode_RegMem(cbuf, EAX_enc, ESP_enc, 0x4, 0, 4, false); 2736 emit_opcode(cbuf,0xC7); // mov [esp+0],0 - [ESP] = (double)(1<<int(Q)) = 2^int(Q) 2737 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 2738 emit_d32(cbuf,0); 2739 emit_opcode(cbuf,0xDC); // fmul dword st(0),[esp+0]; FPR1 = 2^int(Q)*2^frac(Q) = 2^Q 2740 encode_RegMem(cbuf, 0x1, ESP_enc, 0x4, 0, 0, false); 2741 %} 2742 2743// enc_class Pop_Reg_Mod_D( regD dst, regD src) 2744// was replaced by Push_Result_Mod_D followed by Pop_Reg_X() or Pop_Mem_X() 2745 2746 enc_class Push_Result_Mod_D( regD src) %{ 2747 if ($src$$reg != FPR1L_enc) { 2748 // fincstp 2749 emit_opcode (cbuf, 0xD9); 2750 emit_opcode (cbuf, 0xF7); 2751 // FXCH FPR1 with src 2752 emit_opcode(cbuf, 0xD9); 2753 emit_d8(cbuf, 0xC8-1+$src$$reg ); 2754 // fdecstp 2755 emit_opcode (cbuf, 0xD9); 2756 emit_opcode (cbuf, 0xF6); 2757 } 2758 // // following asm replaced with Pop_Reg_F or Pop_Mem_F 2759 // // FSTP FPR$dst$$reg 2760 // emit_opcode( cbuf, 0xDD ); 2761 // emit_d8( cbuf, 0xD8+$dst$$reg ); 2762 %} 2763 2764 enc_class fnstsw_sahf_skip_parity() %{ 2765 // fnstsw ax 2766 emit_opcode( cbuf, 0xDF ); 2767 emit_opcode( cbuf, 0xE0 ); 2768 // sahf 2769 emit_opcode( cbuf, 0x9E ); 2770 // jnp ::skip 2771 emit_opcode( cbuf, 0x7B ); 2772 emit_opcode( cbuf, 0x05 ); 2773 %} 2774 2775 enc_class emitModD() %{ 2776 // fprem must be iterative 2777 // :: loop 2778 // fprem 2779 emit_opcode( cbuf, 0xD9 ); 2780 emit_opcode( cbuf, 0xF8 ); 2781 // wait 2782 emit_opcode( cbuf, 0x9b ); 2783 // fnstsw ax 2784 emit_opcode( cbuf, 0xDF ); 2785 emit_opcode( cbuf, 0xE0 ); 2786 // sahf 2787 emit_opcode( cbuf, 0x9E ); 2788 // jp ::loop 2789 emit_opcode( cbuf, 0x0F ); 2790 emit_opcode( cbuf, 0x8A ); 2791 emit_opcode( cbuf, 0xF4 ); 2792 emit_opcode( cbuf, 0xFF ); 2793 emit_opcode( cbuf, 0xFF ); 2794 emit_opcode( cbuf, 0xFF ); 2795 %} 2796 2797 enc_class fpu_flags() %{ 2798 // fnstsw_ax 2799 emit_opcode( cbuf, 0xDF); 2800 emit_opcode( cbuf, 0xE0); 2801 // test ax,0x0400 2802 emit_opcode( cbuf, 0x66 ); // operand-size prefix for 16-bit immediate 2803 emit_opcode( cbuf, 0xA9 ); 2804 emit_d16 ( cbuf, 0x0400 ); 2805 // // // This sequence works, but stalls for 12-16 cycles on PPro 2806 // // test rax,0x0400 2807 // emit_opcode( cbuf, 0xA9 ); 2808 // emit_d32 ( cbuf, 0x00000400 ); 2809 // 2810 // jz exit (no unordered comparison) 2811 emit_opcode( cbuf, 0x74 ); 2812 emit_d8 ( cbuf, 0x02 ); 2813 // mov ah,1 - treat as LT case (set carry flag) 2814 emit_opcode( cbuf, 0xB4 ); 2815 emit_d8 ( cbuf, 0x01 ); 2816 // sahf 2817 emit_opcode( cbuf, 0x9E); 2818 %} 2819 2820 enc_class cmpF_P6_fixup() %{ 2821 // Fixup the integer flags in case comparison involved a NaN 2822 // 2823 // JNP exit (no unordered comparison, P-flag is set by NaN) 2824 emit_opcode( cbuf, 0x7B ); 2825 emit_d8 ( cbuf, 0x03 ); 2826 // MOV AH,1 - treat as LT case (set carry flag) 2827 emit_opcode( cbuf, 0xB4 ); 2828 emit_d8 ( cbuf, 0x01 ); 2829 // SAHF 2830 emit_opcode( cbuf, 0x9E); 2831 // NOP // target for branch to avoid branch to branch 2832 emit_opcode( cbuf, 0x90); 2833 %} 2834 2835// fnstsw_ax(); 2836// sahf(); 2837// movl(dst, nan_result); 2838// jcc(Assembler::parity, exit); 2839// movl(dst, less_result); 2840// jcc(Assembler::below, exit); 2841// movl(dst, equal_result); 2842// jcc(Assembler::equal, exit); 2843// movl(dst, greater_result); 2844 2845// less_result = 1; 2846// greater_result = -1; 2847// equal_result = 0; 2848// nan_result = -1; 2849 2850 enc_class CmpF_Result(eRegI dst) %{ 2851 // fnstsw_ax(); 2852 emit_opcode( cbuf, 0xDF); 2853 emit_opcode( cbuf, 0xE0); 2854 // sahf 2855 emit_opcode( cbuf, 0x9E); 2856 // movl(dst, nan_result); 2857 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2858 emit_d32( cbuf, -1 ); 2859 // jcc(Assembler::parity, exit); 2860 emit_opcode( cbuf, 0x7A ); 2861 emit_d8 ( cbuf, 0x13 ); 2862 // movl(dst, less_result); 2863 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2864 emit_d32( cbuf, -1 ); 2865 // jcc(Assembler::below, exit); 2866 emit_opcode( cbuf, 0x72 ); 2867 emit_d8 ( cbuf, 0x0C ); 2868 // movl(dst, equal_result); 2869 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2870 emit_d32( cbuf, 0 ); 2871 // jcc(Assembler::equal, exit); 2872 emit_opcode( cbuf, 0x74 ); 2873 emit_d8 ( cbuf, 0x05 ); 2874 // movl(dst, greater_result); 2875 emit_opcode( cbuf, 0xB8 + $dst$$reg); 2876 emit_d32( cbuf, 1 ); 2877 %} 2878 2879 2880 // XMM version of CmpF_Result. Because the XMM compare 2881 // instructions set the EFLAGS directly. It becomes simpler than 2882 // the float version above. 2883 enc_class CmpX_Result(eRegI dst) %{ 2884 MacroAssembler _masm(&cbuf); 2885 Label nan, inc, done; 2886 2887 __ jccb(Assembler::parity, nan); 2888 __ jccb(Assembler::equal, done); 2889 __ jccb(Assembler::above, inc); 2890 __ bind(nan); 2891 __ decrement(as_Register($dst$$reg)); 2892 __ jmpb(done); 2893 __ bind(inc); 2894 __ increment(as_Register($dst$$reg)); 2895 __ bind(done); 2896 %} 2897 2898 // Compare the longs and set flags 2899 // BROKEN! Do Not use as-is 2900 enc_class cmpl_test( eRegL src1, eRegL src2 ) %{ 2901 // CMP $src1.hi,$src2.hi 2902 emit_opcode( cbuf, 0x3B ); 2903 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); 2904 // JNE,s done 2905 emit_opcode(cbuf,0x75); 2906 emit_d8(cbuf, 2 ); 2907 // CMP $src1.lo,$src2.lo 2908 emit_opcode( cbuf, 0x3B ); 2909 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 2910// done: 2911 %} 2912 2913 enc_class convert_int_long( regL dst, eRegI src ) %{ 2914 // mov $dst.lo,$src 2915 int dst_encoding = $dst$$reg; 2916 int src_encoding = $src$$reg; 2917 encode_Copy( cbuf, dst_encoding , src_encoding ); 2918 // mov $dst.hi,$src 2919 encode_Copy( cbuf, HIGH_FROM_LOW(dst_encoding), src_encoding ); 2920 // sar $dst.hi,31 2921 emit_opcode( cbuf, 0xC1 ); 2922 emit_rm(cbuf, 0x3, 7, HIGH_FROM_LOW(dst_encoding) ); 2923 emit_d8(cbuf, 0x1F ); 2924 %} 2925 2926 enc_class convert_long_double( eRegL src ) %{ 2927 // push $src.hi 2928 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); 2929 // push $src.lo 2930 emit_opcode(cbuf, 0x50+$src$$reg ); 2931 // fild 64-bits at [SP] 2932 emit_opcode(cbuf,0xdf); 2933 emit_d8(cbuf, 0x6C); 2934 emit_d8(cbuf, 0x24); 2935 emit_d8(cbuf, 0x00); 2936 // pop stack 2937 emit_opcode(cbuf, 0x83); // add SP, #8 2938 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 2939 emit_d8(cbuf, 0x8); 2940 %} 2941 2942 enc_class multiply_con_and_shift_high( eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr ) %{ 2943 // IMUL EDX:EAX,$src1 2944 emit_opcode( cbuf, 0xF7 ); 2945 emit_rm( cbuf, 0x3, 0x5, $src1$$reg ); 2946 // SAR EDX,$cnt-32 2947 int shift_count = ((int)$cnt$$constant) - 32; 2948 if (shift_count > 0) { 2949 emit_opcode(cbuf, 0xC1); 2950 emit_rm(cbuf, 0x3, 7, $dst$$reg ); 2951 emit_d8(cbuf, shift_count); 2952 } 2953 %} 2954 2955 // this version doesn't have add sp, 8 2956 enc_class convert_long_double2( eRegL src ) %{ 2957 // push $src.hi 2958 emit_opcode(cbuf, 0x50+HIGH_FROM_LOW($src$$reg)); 2959 // push $src.lo 2960 emit_opcode(cbuf, 0x50+$src$$reg ); 2961 // fild 64-bits at [SP] 2962 emit_opcode(cbuf,0xdf); 2963 emit_d8(cbuf, 0x6C); 2964 emit_d8(cbuf, 0x24); 2965 emit_d8(cbuf, 0x00); 2966 %} 2967 2968 enc_class long_int_multiply( eADXRegL dst, nadxRegI src) %{ 2969 // Basic idea: long = (long)int * (long)int 2970 // IMUL EDX:EAX, src 2971 emit_opcode( cbuf, 0xF7 ); 2972 emit_rm( cbuf, 0x3, 0x5, $src$$reg); 2973 %} 2974 2975 enc_class long_uint_multiply( eADXRegL dst, nadxRegI src) %{ 2976 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) 2977 // MUL EDX:EAX, src 2978 emit_opcode( cbuf, 0xF7 ); 2979 emit_rm( cbuf, 0x3, 0x4, $src$$reg); 2980 %} 2981 2982 enc_class long_multiply( eADXRegL dst, eRegL src, eRegI tmp ) %{ 2983 // Basic idea: lo(result) = lo(x_lo * y_lo) 2984 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 2985 // MOV $tmp,$src.lo 2986 encode_Copy( cbuf, $tmp$$reg, $src$$reg ); 2987 // IMUL $tmp,EDX 2988 emit_opcode( cbuf, 0x0F ); 2989 emit_opcode( cbuf, 0xAF ); 2990 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 2991 // MOV EDX,$src.hi 2992 encode_Copy( cbuf, HIGH_FROM_LOW($dst$$reg), HIGH_FROM_LOW($src$$reg) ); 2993 // IMUL EDX,EAX 2994 emit_opcode( cbuf, 0x0F ); 2995 emit_opcode( cbuf, 0xAF ); 2996 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $dst$$reg ); 2997 // ADD $tmp,EDX 2998 emit_opcode( cbuf, 0x03 ); 2999 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 3000 // MUL EDX:EAX,$src.lo 3001 emit_opcode( cbuf, 0xF7 ); 3002 emit_rm( cbuf, 0x3, 0x4, $src$$reg ); 3003 // ADD EDX,ESI 3004 emit_opcode( cbuf, 0x03 ); 3005 emit_rm( cbuf, 0x3, HIGH_FROM_LOW($dst$$reg), $tmp$$reg ); 3006 %} 3007 3008 enc_class long_multiply_con( eADXRegL dst, immL_127 src, eRegI tmp ) %{ 3009 // Basic idea: lo(result) = lo(src * y_lo) 3010 // hi(result) = hi(src * y_lo) + lo(src * y_hi) 3011 // IMUL $tmp,EDX,$src 3012 emit_opcode( cbuf, 0x6B ); 3013 emit_rm( cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg) ); 3014 emit_d8( cbuf, (int)$src$$constant ); 3015 // MOV EDX,$src 3016 emit_opcode(cbuf, 0xB8 + EDX_enc); 3017 emit_d32( cbuf, (int)$src$$constant ); 3018 // MUL EDX:EAX,EDX 3019 emit_opcode( cbuf, 0xF7 ); 3020 emit_rm( cbuf, 0x3, 0x4, EDX_enc ); 3021 // ADD EDX,ESI 3022 emit_opcode( cbuf, 0x03 ); 3023 emit_rm( cbuf, 0x3, EDX_enc, $tmp$$reg ); 3024 %} 3025 3026 enc_class long_div( eRegL src1, eRegL src2 ) %{ 3027 // PUSH src1.hi 3028 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); 3029 // PUSH src1.lo 3030 emit_opcode(cbuf, 0x50+$src1$$reg ); 3031 // PUSH src2.hi 3032 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); 3033 // PUSH src2.lo 3034 emit_opcode(cbuf, 0x50+$src2$$reg ); 3035 // CALL directly to the runtime 3036 cbuf.set_inst_mark(); 3037 emit_opcode(cbuf,0xE8); // Call into runtime 3038 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::ldiv) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3039 // Restore stack 3040 emit_opcode(cbuf, 0x83); // add SP, #framesize 3041 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 3042 emit_d8(cbuf, 4*4); 3043 %} 3044 3045 enc_class long_mod( eRegL src1, eRegL src2 ) %{ 3046 // PUSH src1.hi 3047 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src1$$reg) ); 3048 // PUSH src1.lo 3049 emit_opcode(cbuf, 0x50+$src1$$reg ); 3050 // PUSH src2.hi 3051 emit_opcode(cbuf, HIGH_FROM_LOW(0x50+$src2$$reg) ); 3052 // PUSH src2.lo 3053 emit_opcode(cbuf, 0x50+$src2$$reg ); 3054 // CALL directly to the runtime 3055 cbuf.set_inst_mark(); 3056 emit_opcode(cbuf,0xE8); // Call into runtime 3057 emit_d32_reloc(cbuf, (CAST_FROM_FN_PTR(address, SharedRuntime::lrem ) - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3058 // Restore stack 3059 emit_opcode(cbuf, 0x83); // add SP, #framesize 3060 emit_rm(cbuf, 0x3, 0x00, ESP_enc); 3061 emit_d8(cbuf, 4*4); 3062 %} 3063 3064 enc_class long_cmp_flags0( eRegL src, eRegI tmp ) %{ 3065 // MOV $tmp,$src.lo 3066 emit_opcode(cbuf, 0x8B); 3067 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); 3068 // OR $tmp,$src.hi 3069 emit_opcode(cbuf, 0x0B); 3070 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg)); 3071 %} 3072 3073 enc_class long_cmp_flags1( eRegL src1, eRegL src2 ) %{ 3074 // CMP $src1.lo,$src2.lo 3075 emit_opcode( cbuf, 0x3B ); 3076 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 3077 // JNE,s skip 3078 emit_cc(cbuf, 0x70, 0x5); 3079 emit_d8(cbuf,2); 3080 // CMP $src1.hi,$src2.hi 3081 emit_opcode( cbuf, 0x3B ); 3082 emit_rm(cbuf, 0x3, HIGH_FROM_LOW($src1$$reg), HIGH_FROM_LOW($src2$$reg) ); 3083 %} 3084 3085 enc_class long_cmp_flags2( eRegL src1, eRegL src2, eRegI tmp ) %{ 3086 // CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits 3087 emit_opcode( cbuf, 0x3B ); 3088 emit_rm(cbuf, 0x3, $src1$$reg, $src2$$reg ); 3089 // MOV $tmp,$src1.hi 3090 emit_opcode( cbuf, 0x8B ); 3091 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src1$$reg) ); 3092 // SBB $tmp,$src2.hi\t! Compute flags for long compare 3093 emit_opcode( cbuf, 0x1B ); 3094 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src2$$reg) ); 3095 %} 3096 3097 enc_class long_cmp_flags3( eRegL src, eRegI tmp ) %{ 3098 // XOR $tmp,$tmp 3099 emit_opcode(cbuf,0x33); // XOR 3100 emit_rm(cbuf,0x3, $tmp$$reg, $tmp$$reg); 3101 // CMP $tmp,$src.lo 3102 emit_opcode( cbuf, 0x3B ); 3103 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg ); 3104 // SBB $tmp,$src.hi 3105 emit_opcode( cbuf, 0x1B ); 3106 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($src$$reg) ); 3107 %} 3108 3109 // Sniff, sniff... smells like Gnu Superoptimizer 3110 enc_class neg_long( eRegL dst ) %{ 3111 emit_opcode(cbuf,0xF7); // NEG hi 3112 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); 3113 emit_opcode(cbuf,0xF7); // NEG lo 3114 emit_rm (cbuf,0x3, 0x3, $dst$$reg ); 3115 emit_opcode(cbuf,0x83); // SBB hi,0 3116 emit_rm (cbuf,0x3, 0x3, HIGH_FROM_LOW($dst$$reg)); 3117 emit_d8 (cbuf,0 ); 3118 %} 3119 3120 enc_class movq_ld(regXD dst, memory mem) %{ 3121 MacroAssembler _masm(&cbuf); 3122 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); 3123 __ movq(as_XMMRegister($dst$$reg), madr); 3124 %} 3125 3126 enc_class movq_st(memory mem, regXD src) %{ 3127 MacroAssembler _masm(&cbuf); 3128 Address madr = Address::make_raw($mem$$base, $mem$$index, $mem$$scale, $mem$$disp); 3129 __ movq(madr, as_XMMRegister($src$$reg)); 3130 %} 3131 3132 enc_class pshufd_8x8(regX dst, regX src) %{ 3133 MacroAssembler _masm(&cbuf); 3134 3135 encode_CopyXD(cbuf, $dst$$reg, $src$$reg); 3136 __ punpcklbw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg)); 3137 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($dst$$reg), 0x00); 3138 %} 3139 3140 enc_class pshufd_4x16(regX dst, regX src) %{ 3141 MacroAssembler _masm(&cbuf); 3142 3143 __ pshuflw(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), 0x00); 3144 %} 3145 3146 enc_class pshufd(regXD dst, regXD src, int mode) %{ 3147 MacroAssembler _masm(&cbuf); 3148 3149 __ pshufd(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg), $mode); 3150 %} 3151 3152 enc_class pxor(regXD dst, regXD src) %{ 3153 MacroAssembler _masm(&cbuf); 3154 3155 __ pxor(as_XMMRegister($dst$$reg), as_XMMRegister($src$$reg)); 3156 %} 3157 3158 enc_class mov_i2x(regXD dst, eRegI src) %{ 3159 MacroAssembler _masm(&cbuf); 3160 3161 __ movd(as_XMMRegister($dst$$reg), as_Register($src$$reg)); 3162 %} 3163 3164 3165 // Because the transitions from emitted code to the runtime 3166 // monitorenter/exit helper stubs are so slow it's critical that 3167 // we inline both the stack-locking fast-path and the inflated fast path. 3168 // 3169 // See also: cmpFastLock and cmpFastUnlock. 3170 // 3171 // What follows is a specialized inline transliteration of the code 3172 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 3173 // another option would be to emit TrySlowEnter and TrySlowExit methods 3174 // at startup-time. These methods would accept arguments as 3175 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 3176 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 3177 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 3178 // In practice, however, the # of lock sites is bounded and is usually small. 3179 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 3180 // if the processor uses simple bimodal branch predictors keyed by EIP 3181 // Since the helper routines would be called from multiple synchronization 3182 // sites. 3183 // 3184 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 3185 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 3186 // to those specialized methods. That'd give us a mostly platform-independent 3187 // implementation that the JITs could optimize and inline at their pleasure. 3188 // Done correctly, the only time we'd need to cross to native could would be 3189 // to park() or unpark() threads. We'd also need a few more unsafe operators 3190 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 3191 // (b) explicit barriers or fence operations. 3192 // 3193 // TODO: 3194 // 3195 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 3196 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 3197 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 3198 // the lock operators would typically be faster than reifying Self. 3199 // 3200 // * Ideally I'd define the primitives as: 3201 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 3202 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 3203 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 3204 // Instead, we're stuck with a rather awkward and brittle register assignments below. 3205 // Furthermore the register assignments are overconstrained, possibly resulting in 3206 // sub-optimal code near the synchronization site. 3207 // 3208 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 3209 // Alternately, use a better sp-proximity test. 3210 // 3211 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 3212 // Either one is sufficient to uniquely identify a thread. 3213 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 3214 // 3215 // * Intrinsify notify() and notifyAll() for the common cases where the 3216 // object is locked by the calling thread but the waitlist is empty. 3217 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 3218 // 3219 // * use jccb and jmpb instead of jcc and jmp to improve code density. 3220 // But beware of excessive branch density on AMD Opterons. 3221 // 3222 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 3223 // or failure of the fast-path. If the fast-path fails then we pass 3224 // control to the slow-path, typically in C. In Fast_Lock and 3225 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 3226 // will emit a conditional branch immediately after the node. 3227 // So we have branches to branches and lots of ICC.ZF games. 3228 // Instead, it might be better to have C2 pass a "FailureLabel" 3229 // into Fast_Lock and Fast_Unlock. In the case of success, control 3230 // will drop through the node. ICC.ZF is undefined at exit. 3231 // In the case of failure, the node will branch directly to the 3232 // FailureLabel 3233 3234 3235 // obj: object to lock 3236 // box: on-stack box address (displaced header location) - KILLED 3237 // rax,: tmp -- KILLED 3238 // scr: tmp -- KILLED 3239 enc_class Fast_Lock( eRegP obj, eRegP box, eAXRegI tmp, eRegP scr ) %{ 3240 3241 Register objReg = as_Register($obj$$reg); 3242 Register boxReg = as_Register($box$$reg); 3243 Register tmpReg = as_Register($tmp$$reg); 3244 Register scrReg = as_Register($scr$$reg); 3245 3246 // Ensure the register assignents are disjoint 3247 guarantee (objReg != boxReg, "") ; 3248 guarantee (objReg != tmpReg, "") ; 3249 guarantee (objReg != scrReg, "") ; 3250 guarantee (boxReg != tmpReg, "") ; 3251 guarantee (boxReg != scrReg, "") ; 3252 guarantee (tmpReg == as_Register(EAX_enc), "") ; 3253 3254 MacroAssembler masm(&cbuf); 3255 3256 if (_counters != NULL) { 3257 masm.atomic_incl(ExternalAddress((address) _counters->total_entry_count_addr())); 3258 } 3259 if (EmitSync & 1) { 3260 // set box->dhw = unused_mark (3) 3261 // Force all sync thru slow-path: slow_enter() and slow_exit() 3262 masm.movl (Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())) ; 3263 masm.cmpl (rsp, 0) ; 3264 } else 3265 if (EmitSync & 2) { 3266 Label DONE_LABEL ; 3267 if (UseBiasedLocking) { 3268 // Note: tmpReg maps to the swap_reg argument and scrReg to the tmp_reg argument. 3269 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); 3270 } 3271 3272 masm.movl (tmpReg, Address(objReg, 0)) ; // fetch markword 3273 masm.orl (tmpReg, 0x1); 3274 masm.movl (Address(boxReg, 0), tmpReg); // Anticipate successful CAS 3275 if (os::is_MP()) { masm.lock(); } 3276 masm.cmpxchg(boxReg, Address(objReg, 0)); // Updates tmpReg 3277 masm.jcc(Assembler::equal, DONE_LABEL); 3278 // Recursive locking 3279 masm.subl(tmpReg, rsp); 3280 masm.andl(tmpReg, 0xFFFFF003 ); 3281 masm.movl(Address(boxReg, 0), tmpReg); 3282 masm.bind(DONE_LABEL) ; 3283 } else { 3284 // Possible cases that we'll encounter in fast_lock 3285 // ------------------------------------------------ 3286 // * Inflated 3287 // -- unlocked 3288 // -- Locked 3289 // = by self 3290 // = by other 3291 // * biased 3292 // -- by Self 3293 // -- by other 3294 // * neutral 3295 // * stack-locked 3296 // -- by self 3297 // = sp-proximity test hits 3298 // = sp-proximity test generates false-negative 3299 // -- by other 3300 // 3301 3302 Label IsInflated, DONE_LABEL, PopDone ; 3303 3304 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 3305 // order to reduce the number of conditional branches in the most common cases. 3306 // Beware -- there's a subtle invariant that fetch of the markword 3307 // at [FETCH], below, will never observe a biased encoding (*101b). 3308 // If this invariant is not held we risk exclusion (safety) failure. 3309 if (UseBiasedLocking) { 3310 masm.biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, _counters); 3311 } 3312 3313 masm.movl (tmpReg, Address(objReg, 0)) ; // [FETCH] 3314 masm.testl (tmpReg, 0x02) ; // Inflated v (Stack-locked or neutral) 3315 masm.jccb (Assembler::notZero, IsInflated) ; 3316 3317 // Attempt stack-locking ... 3318 masm.orl (tmpReg, 0x1); 3319 masm.movl (Address(boxReg, 0), tmpReg); // Anticipate successful CAS 3320 if (os::is_MP()) { masm.lock(); } 3321 masm.cmpxchg(boxReg, Address(objReg, 0)); // Updates tmpReg 3322 if (_counters != NULL) { 3323 masm.cond_inc32(Assembler::equal, 3324 ExternalAddress((address)_counters->fast_path_entry_count_addr())); 3325 } 3326 masm.jccb (Assembler::equal, DONE_LABEL); 3327 3328 // Recursive locking 3329 masm.subl(tmpReg, rsp); 3330 masm.andl(tmpReg, 0xFFFFF003 ); 3331 masm.movl(Address(boxReg, 0), tmpReg); 3332 if (_counters != NULL) { 3333 masm.cond_inc32(Assembler::equal, 3334 ExternalAddress((address)_counters->fast_path_entry_count_addr())); 3335 } 3336 masm.jmp (DONE_LABEL) ; 3337 3338 masm.bind (IsInflated) ; 3339 3340 // The object is inflated. 3341 // 3342 // TODO-FIXME: eliminate the ugly use of manifest constants: 3343 // Use markOopDesc::monitor_value instead of "2". 3344 // use markOop::unused_mark() instead of "3". 3345 // The tmpReg value is an objectMonitor reference ORed with 3346 // markOopDesc::monitor_value (2). We can either convert tmpReg to an 3347 // objectmonitor pointer by masking off the "2" bit or we can just 3348 // use tmpReg as an objectmonitor pointer but bias the objectmonitor 3349 // field offsets with "-2" to compensate for and annul the low-order tag bit. 3350 // 3351 // I use the latter as it avoids AGI stalls. 3352 // As such, we write "mov r, [tmpReg+OFFSETOF(Owner)-2]" 3353 // instead of "mov r, [tmpReg+OFFSETOF(Owner)]". 3354 // 3355 #define OFFSET_SKEWED(f) ((ObjectMonitor::f ## _offset_in_bytes())-2) 3356 3357 // boxReg refers to the on-stack BasicLock in the current frame. 3358 // We'd like to write: 3359 // set box->_displaced_header = markOop::unused_mark(). Any non-0 value suffices. 3360 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 3361 // additional latency as we have another ST in the store buffer that must drain. 3362 3363 if (EmitSync & 8192) { 3364 masm.movl (Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty 3365 masm.get_thread (scrReg) ; 3366 masm.movl (boxReg, tmpReg); // consider: LEA box, [tmp-2] 3367 masm.movl (tmpReg, 0); // consider: xor vs mov 3368 if (os::is_MP()) { masm.lock(); } 3369 masm.cmpxchg (scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3370 } else 3371 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 3372 masm.movl (scrReg, boxReg) ; 3373 masm.movl (boxReg, tmpReg); // consider: LEA box, [tmp-2] 3374 3375 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 3376 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) { 3377 // prefetchw [eax + Offset(_owner)-2] 3378 masm.emit_raw (0x0F) ; 3379 masm.emit_raw (0x0D) ; 3380 masm.emit_raw (0x48) ; 3381 masm.emit_raw (ObjectMonitor::owner_offset_in_bytes()-2) ; 3382 } 3383 3384 if ((EmitSync & 64) == 0) { 3385 // Optimistic form: consider XORL tmpReg,tmpReg 3386 masm.movl (tmpReg, 0 ) ; 3387 } else { 3388 // Can suffer RTS->RTO upgrades on shared or cold $ lines 3389 // Test-And-CAS instead of CAS 3390 masm.movl (tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner 3391 masm.testl (tmpReg, tmpReg) ; // Locked ? 3392 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3393 } 3394 3395 // Appears unlocked - try to swing _owner from null to non-null. 3396 // Ideally, I'd manifest "Self" with get_thread and then attempt 3397 // to CAS the register containing Self into m->Owner. 3398 // But we don't have enough registers, so instead we can either try to CAS 3399 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 3400 // we later store "Self" into m->Owner. Transiently storing a stack address 3401 // (rsp or the address of the box) into m->owner is harmless. 3402 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 3403 if (os::is_MP()) { masm.lock(); } 3404 masm.cmpxchg (scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3405 masm.movl (Address(scrReg, 0), 3) ; // box->_displaced_header = 3 3406 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3407 masm.get_thread (scrReg) ; // beware: clobbers ICCs 3408 masm.movl (Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2), scrReg) ; 3409 masm.xorl (boxReg, boxReg) ; // set icc.ZFlag = 1 to indicate success 3410 3411 // If the CAS fails we can either retry or pass control to the slow-path. 3412 // We use the latter tactic. 3413 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 3414 // If the CAS was successful ... 3415 // Self has acquired the lock 3416 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 3417 // Intentional fall-through into DONE_LABEL ... 3418 } else { 3419 masm.movl (Address(boxReg, 0), 3) ; // results in ST-before-CAS penalty 3420 masm.movl (boxReg, tmpReg) ; 3421 3422 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 3423 if ((EmitSync & 2048) && VM_Version::supports_3dnow() && os::is_MP()) { 3424 // prefetchw [eax + Offset(_owner)-2] 3425 masm.emit_raw (0x0F) ; 3426 masm.emit_raw (0x0D) ; 3427 masm.emit_raw (0x48) ; 3428 masm.emit_raw (ObjectMonitor::owner_offset_in_bytes()-2) ; 3429 } 3430 3431 if ((EmitSync & 64) == 0) { 3432 // Optimistic form 3433 masm.xorl (tmpReg, tmpReg) ; 3434 } else { 3435 // Can suffer RTS->RTO upgrades on shared or cold $ lines 3436 masm.movl (tmpReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; // rax, = m->_owner 3437 masm.testl (tmpReg, tmpReg) ; // Locked ? 3438 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3439 } 3440 3441 // Appears unlocked - try to swing _owner from null to non-null. 3442 // Use either "Self" (in scr) or rsp as thread identity in _owner. 3443 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 3444 masm.get_thread (scrReg) ; 3445 if (os::is_MP()) { masm.lock(); } 3446 masm.cmpxchg (scrReg, Address(boxReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3447 3448 // If the CAS fails we can either retry or pass control to the slow-path. 3449 // We use the latter tactic. 3450 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 3451 // If the CAS was successful ... 3452 // Self has acquired the lock 3453 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 3454 // Intentional fall-through into DONE_LABEL ... 3455 } 3456 3457 // DONE_LABEL is a hot target - we'd really like to place it at the 3458 // start of cache line by padding with NOPs. 3459 // See the AMD and Intel software optimization manuals for the 3460 // most efficient "long" NOP encodings. 3461 // Unfortunately none of our alignment mechanisms suffice. 3462 masm.bind(DONE_LABEL); 3463 3464 // Avoid branch-to-branch on AMD processors 3465 // This appears to be superstition. 3466 if (EmitSync & 32) masm.nop() ; 3467 3468 3469 // At DONE_LABEL the icc ZFlag is set as follows ... 3470 // Fast_Unlock uses the same protocol. 3471 // ZFlag == 1 -> Success 3472 // ZFlag == 0 -> Failure - force control through the slow-path 3473 } 3474 %} 3475 3476 // obj: object to unlock 3477 // box: box address (displaced header location), killed. Must be EAX. 3478 // rbx,: killed tmp; cannot be obj nor box. 3479 // 3480 // Some commentary on balanced locking: 3481 // 3482 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 3483 // Methods that don't have provably balanced locking are forced to run in the 3484 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 3485 // The interpreter provides two properties: 3486 // I1: At return-time the interpreter automatically and quietly unlocks any 3487 // objects acquired the current activation (frame). Recall that the 3488 // interpreter maintains an on-stack list of locks currently held by 3489 // a frame. 3490 // I2: If a method attempts to unlock an object that is not held by the 3491 // the frame the interpreter throws IMSX. 3492 // 3493 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 3494 // B() doesn't have provably balanced locking so it runs in the interpreter. 3495 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 3496 // is still locked by A(). 3497 // 3498 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 3499 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 3500 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 3501 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 3502 3503 enc_class Fast_Unlock( nabxRegP obj, eAXRegP box, eRegP tmp) %{ 3504 3505 Register objReg = as_Register($obj$$reg); 3506 Register boxReg = as_Register($box$$reg); 3507 Register tmpReg = as_Register($tmp$$reg); 3508 3509 guarantee (objReg != boxReg, "") ; 3510 guarantee (objReg != tmpReg, "") ; 3511 guarantee (boxReg != tmpReg, "") ; 3512 guarantee (boxReg == as_Register(EAX_enc), "") ; 3513 MacroAssembler masm(&cbuf); 3514 3515 if (EmitSync & 4) { 3516 // Disable - inhibit all inlining. Force control through the slow-path 3517 masm.cmpl (rsp, 0) ; 3518 } else 3519 if (EmitSync & 8) { 3520 Label DONE_LABEL ; 3521 if (UseBiasedLocking) { 3522 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); 3523 } 3524 // classic stack-locking code ... 3525 masm.movl (tmpReg, Address(boxReg, 0)) ; 3526 masm.testl (tmpReg, tmpReg) ; 3527 masm.jcc (Assembler::zero, DONE_LABEL) ; 3528 if (os::is_MP()) { masm.lock(); } 3529 masm.cmpxchg(tmpReg, Address(objReg, 0)); // Uses EAX which is box 3530 masm.bind(DONE_LABEL); 3531 } else { 3532 Label DONE_LABEL, Stacked, CheckSucc, Inflated ; 3533 3534 // Critically, the biased locking test must have precedence over 3535 // and appear before the (box->dhw == 0) recursive stack-lock test. 3536 if (UseBiasedLocking) { 3537 masm.biased_locking_exit(objReg, tmpReg, DONE_LABEL); 3538 } 3539 3540 masm.cmpl (Address(boxReg, 0), 0) ; // Examine the displaced header 3541 masm.movl (tmpReg, Address(objReg, 0)) ; // Examine the object's markword 3542 masm.jccb (Assembler::zero, DONE_LABEL) ; // 0 indicates recursive stack-lock 3543 3544 masm.testl (tmpReg, 0x02) ; // Inflated? 3545 masm.jccb (Assembler::zero, Stacked) ; 3546 3547 masm.bind (Inflated) ; 3548 // It's inflated. 3549 // Despite our balanced locking property we still check that m->_owner == Self 3550 // as java routines or native JNI code called by this thread might 3551 // have released the lock. 3552 // Refer to the comments in synchronizer.cpp for how we might encode extra 3553 // state in _succ so we can avoid fetching EntryList|cxq. 3554 // 3555 // I'd like to add more cases in fast_lock() and fast_unlock() -- 3556 // such as recursive enter and exit -- but we have to be wary of 3557 // I$ bloat, T$ effects and BP$ effects. 3558 // 3559 // If there's no contention try a 1-0 exit. That is, exit without 3560 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 3561 // we detect and recover from the race that the 1-0 exit admits. 3562 // 3563 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 3564 // before it STs null into _owner, releasing the lock. Updates 3565 // to data protected by the critical section must be visible before 3566 // we drop the lock (and thus before any other thread could acquire 3567 // the lock and observe the fields protected by the lock). 3568 // IA32's memory-model is SPO, so STs are ordered with respect to 3569 // each other and there's no need for an explicit barrier (fence). 3570 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 3571 3572 masm.get_thread (boxReg) ; 3573 if ((EmitSync & 4096) && VM_Version::supports_3dnow() && os::is_MP()) { 3574 // prefetchw [ebx + Offset(_owner)-2] 3575 masm.emit_raw (0x0F) ; 3576 masm.emit_raw (0x0D) ; 3577 masm.emit_raw (0x4B) ; 3578 masm.emit_raw (ObjectMonitor::owner_offset_in_bytes()-2) ; 3579 } 3580 3581 // Note that we could employ various encoding schemes to reduce 3582 // the number of loads below (currently 4) to just 2 or 3. 3583 // Refer to the comments in synchronizer.cpp. 3584 // In practice the chain of fetches doesn't seem to impact performance, however. 3585 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 3586 // Attempt to reduce branch density - AMD's branch predictor. 3587 masm.xorl (boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3588 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; 3589 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 3590 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 3591 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3592 masm.movl (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ; 3593 masm.jmpb (DONE_LABEL) ; 3594 } else { 3595 masm.xorl (boxReg, Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3596 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::recursions_offset_in_bytes()-2)) ; 3597 masm.jccb (Assembler::notZero, DONE_LABEL) ; 3598 masm.movl (boxReg, Address (tmpReg, ObjectMonitor::EntryList_offset_in_bytes()-2)) ; 3599 masm.orl (boxReg, Address (tmpReg, ObjectMonitor::cxq_offset_in_bytes()-2)) ; 3600 masm.jccb (Assembler::notZero, CheckSucc) ; 3601 masm.movl (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ; 3602 masm.jmpb (DONE_LABEL) ; 3603 } 3604 3605 // The Following code fragment (EmitSync & 65536) improves the performance of 3606 // contended applications and contended synchronization microbenchmarks. 3607 // Unfortunately the emission of the code - even though not executed - causes regressions 3608 // in scimark and jetstream, evidently because of $ effects. Replacing the code 3609 // with an equal number of never-executed NOPs results in the same regression. 3610 // We leave it off by default. 3611 3612 if ((EmitSync & 65536) != 0) { 3613 Label LSuccess, LGoSlowPath ; 3614 3615 masm.bind (CheckSucc) ; 3616 3617 // Optional pre-test ... it's safe to elide this 3618 if ((EmitSync & 16) == 0) { 3619 masm.cmpl (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 3620 masm.jccb (Assembler::zero, LGoSlowPath) ; 3621 } 3622 3623 // We have a classic Dekker-style idiom: 3624 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 3625 // There are a number of ways to implement the barrier: 3626 // (1) lock:andl &m->_owner, 0 3627 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 3628 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 3629 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 3630 // (2) If supported, an explicit MFENCE is appealing. 3631 // In older IA32 processors MFENCE is slower than lock:add or xchg 3632 // particularly if the write-buffer is full as might be the case if 3633 // if stores closely precede the fence or fence-equivalent instruction. 3634 // In more modern implementations MFENCE appears faster, however. 3635 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 3636 // The $lines underlying the top-of-stack should be in M-state. 3637 // The locked add instruction is serializing, of course. 3638 // (4) Use xchg, which is serializing 3639 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 3640 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 3641 // The integer condition codes will tell us if succ was 0. 3642 // Since _succ and _owner should reside in the same $line and 3643 // we just stored into _owner, it's likely that the $line 3644 // remains in M-state for the lock:orl. 3645 // 3646 // We currently use (3), although it's likely that switching to (2) 3647 // is correct for the future. 3648 3649 masm.movl (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), 0) ; 3650 if (os::is_MP()) { 3651 if (VM_Version::supports_sse2() && 1 == FenceInstruction) { 3652 masm.emit_raw (0x0F) ; // MFENCE ... 3653 masm.emit_raw (0xAE) ; 3654 masm.emit_raw (0xF0) ; 3655 } else { 3656 masm.lock () ; masm.addl (Address(rsp, 0), 0) ; 3657 } 3658 } 3659 // Ratify _succ remains non-null 3660 masm.cmpl (Address (tmpReg, ObjectMonitor::succ_offset_in_bytes()-2), 0) ; 3661 masm.jccb (Assembler::notZero, LSuccess) ; 3662 3663 masm.xorl (boxReg, boxReg) ; // box is really EAX 3664 if (os::is_MP()) { masm.lock(); } 3665 masm.cmpxchg(rsp, Address(tmpReg, ObjectMonitor::owner_offset_in_bytes()-2)); 3666 masm.jccb (Assembler::notEqual, LSuccess) ; 3667 // Since we're low on registers we installed rsp as a placeholding in _owner. 3668 // Now install Self over rsp. This is safe as we're transitioning from 3669 // non-null to non=null 3670 masm.get_thread (boxReg) ; 3671 masm.movl (Address (tmpReg, ObjectMonitor::owner_offset_in_bytes()-2), boxReg) ; 3672 // Intentional fall-through into LGoSlowPath ... 3673 3674 masm.bind (LGoSlowPath) ; 3675 masm.orl (boxReg, 1) ; // set ICC.ZF=0 to indicate failure 3676 masm.jmpb (DONE_LABEL) ; 3677 3678 masm.bind (LSuccess) ; 3679 masm.xorl (boxReg, boxReg) ; // set ICC.ZF=1 to indicate success 3680 masm.jmpb (DONE_LABEL) ; 3681 } 3682 3683 masm.bind (Stacked) ; 3684 // It's not inflated and it's not recursively stack-locked and it's not biased. 3685 // It must be stack-locked. 3686 // Try to reset the header to displaced header. 3687 // The "box" value on the stack is stable, so we can reload 3688 // and be assured we observe the same value as above. 3689 masm.movl (tmpReg, Address(boxReg, 0)) ; 3690 if (os::is_MP()) { masm.lock(); } 3691 masm.cmpxchg(tmpReg, Address(objReg, 0)); // Uses EAX which is box 3692 // Intention fall-thru into DONE_LABEL 3693 3694 3695 // DONE_LABEL is a hot target - we'd really like to place it at the 3696 // start of cache line by padding with NOPs. 3697 // See the AMD and Intel software optimization manuals for the 3698 // most efficient "long" NOP encodings. 3699 // Unfortunately none of our alignment mechanisms suffice. 3700 if ((EmitSync & 65536) == 0) { 3701 masm.bind (CheckSucc) ; 3702 } 3703 masm.bind(DONE_LABEL); 3704 3705 // Avoid branch to branch on AMD processors 3706 if (EmitSync & 32768) { masm.nop() ; } 3707 } 3708 %} 3709 3710 enc_class enc_String_Compare() %{ 3711 Label ECX_GOOD_LABEL, LENGTH_DIFF_LABEL, 3712 POP_LABEL, DONE_LABEL, CONT_LABEL, 3713 WHILE_HEAD_LABEL; 3714 MacroAssembler masm(&cbuf); 3715 3716 // Get the first character position in both strings 3717 // [8] char array, [12] offset, [16] count 3718 int value_offset = java_lang_String::value_offset_in_bytes(); 3719 int offset_offset = java_lang_String::offset_offset_in_bytes(); 3720 int count_offset = java_lang_String::count_offset_in_bytes(); 3721 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 3722 3723 masm.movl(rax, Address(rsi, value_offset)); 3724 masm.movl(rcx, Address(rsi, offset_offset)); 3725 masm.leal(rax, Address(rax, rcx, Address::times_2, base_offset)); 3726 masm.movl(rbx, Address(rdi, value_offset)); 3727 masm.movl(rcx, Address(rdi, offset_offset)); 3728 masm.leal(rbx, Address(rbx, rcx, Address::times_2, base_offset)); 3729 3730 // Compute the minimum of the string lengths(rsi) and the 3731 // difference of the string lengths (stack) 3732 3733 3734 if (VM_Version::supports_cmov()) { 3735 masm.movl(rdi, Address(rdi, count_offset)); 3736 masm.movl(rsi, Address(rsi, count_offset)); 3737 masm.movl(rcx, rdi); 3738 masm.subl(rdi, rsi); 3739 masm.pushl(rdi); 3740 masm.cmovl(Assembler::lessEqual, rsi, rcx); 3741 } else { 3742 masm.movl(rdi, Address(rdi, count_offset)); 3743 masm.movl(rcx, Address(rsi, count_offset)); 3744 masm.movl(rsi, rdi); 3745 masm.subl(rdi, rcx); 3746 masm.pushl(rdi); 3747 masm.jcc(Assembler::lessEqual, ECX_GOOD_LABEL); 3748 masm.movl(rsi, rcx); 3749 // rsi holds min, rcx is unused 3750 } 3751 3752 // Is the minimum length zero? 3753 masm.bind(ECX_GOOD_LABEL); 3754 masm.testl(rsi, rsi); 3755 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL); 3756 3757 // Load first characters 3758 masm.load_unsigned_word(rcx, Address(rbx, 0)); 3759 masm.load_unsigned_word(rdi, Address(rax, 0)); 3760 3761 // Compare first characters 3762 masm.subl(rcx, rdi); 3763 masm.jcc(Assembler::notZero, POP_LABEL); 3764 masm.decrement(rsi); 3765 masm.jcc(Assembler::zero, LENGTH_DIFF_LABEL); 3766 3767 { 3768 // Check after comparing first character to see if strings are equivalent 3769 Label LSkip2; 3770 // Check if the strings start at same location 3771 masm.cmpl(rbx,rax); 3772 masm.jcc(Assembler::notEqual, LSkip2); 3773 3774 // Check if the length difference is zero (from stack) 3775 masm.cmpl(Address(rsp, 0), 0x0); 3776 masm.jcc(Assembler::equal, LENGTH_DIFF_LABEL); 3777 3778 // Strings might not be equivalent 3779 masm.bind(LSkip2); 3780 } 3781 3782 // Shift rax, and rbx, to the end of the arrays, negate min 3783 masm.leal(rax, Address(rax, rsi, Address::times_2, 2)); 3784 masm.leal(rbx, Address(rbx, rsi, Address::times_2, 2)); 3785 masm.negl(rsi); 3786 3787 // Compare the rest of the characters 3788 masm.bind(WHILE_HEAD_LABEL); 3789 masm.load_unsigned_word(rcx, Address(rbx, rsi, Address::times_2, 0)); 3790 masm.load_unsigned_word(rdi, Address(rax, rsi, Address::times_2, 0)); 3791 masm.subl(rcx, rdi); 3792 masm.jcc(Assembler::notZero, POP_LABEL); 3793 masm.increment(rsi); 3794 masm.jcc(Assembler::notZero, WHILE_HEAD_LABEL); 3795 3796 // Strings are equal up to min length. Return the length difference. 3797 masm.bind(LENGTH_DIFF_LABEL); 3798 masm.popl(rcx); 3799 masm.jmp(DONE_LABEL); 3800 3801 // Discard the stored length difference 3802 masm.bind(POP_LABEL); 3803 masm.addl(rsp, 4); 3804 3805 // That's it 3806 masm.bind(DONE_LABEL); 3807 %} 3808 3809 enc_class enc_pop_rdx() %{ 3810 emit_opcode(cbuf,0x5A); 3811 %} 3812 3813 enc_class enc_rethrow() %{ 3814 cbuf.set_inst_mark(); 3815 emit_opcode(cbuf, 0xE9); // jmp entry 3816 emit_d32_reloc(cbuf, (int)OptoRuntime::rethrow_stub() - ((int)cbuf.code_end())-4, 3817 runtime_call_Relocation::spec(), RELOC_IMM32 ); 3818 %} 3819 3820 3821 // Convert a double to an int. Java semantics require we do complex 3822 // manglelations in the corner cases. So we set the rounding mode to 3823 // 'zero', store the darned double down as an int, and reset the 3824 // rounding mode to 'nearest'. The hardware throws an exception which 3825 // patches up the correct value directly to the stack. 3826 enc_class D2I_encoding( regD src ) %{ 3827 // Flip to round-to-zero mode. We attempted to allow invalid-op 3828 // exceptions here, so that a NAN or other corner-case value will 3829 // thrown an exception (but normal values get converted at full speed). 3830 // However, I2C adapters and other float-stack manglers leave pending 3831 // invalid-op exceptions hanging. We would have to clear them before 3832 // enabling them and that is more expensive than just testing for the 3833 // invalid value Intel stores down in the corner cases. 3834 emit_opcode(cbuf,0xD9); // FLDCW trunc 3835 emit_opcode(cbuf,0x2D); 3836 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 3837 // Allocate a word 3838 emit_opcode(cbuf,0x83); // SUB ESP,4 3839 emit_opcode(cbuf,0xEC); 3840 emit_d8(cbuf,0x04); 3841 // Encoding assumes a double has been pushed into FPR0. 3842 // Store down the double as an int, popping the FPU stack 3843 emit_opcode(cbuf,0xDB); // FISTP [ESP] 3844 emit_opcode(cbuf,0x1C); 3845 emit_d8(cbuf,0x24); 3846 // Restore the rounding mode; mask the exception 3847 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 3848 emit_opcode(cbuf,0x2D); 3849 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 3850 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 3851 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 3852 3853 // Load the converted int; adjust CPU stack 3854 emit_opcode(cbuf,0x58); // POP EAX 3855 emit_opcode(cbuf,0x3D); // CMP EAX,imm 3856 emit_d32 (cbuf,0x80000000); // 0x80000000 3857 emit_opcode(cbuf,0x75); // JNE around_slow_call 3858 emit_d8 (cbuf,0x07); // Size of slow_call 3859 // Push src onto stack slow-path 3860 emit_opcode(cbuf,0xD9 ); // FLD ST(i) 3861 emit_d8 (cbuf,0xC0-1+$src$$reg ); 3862 // CALL directly to the runtime 3863 cbuf.set_inst_mark(); 3864 emit_opcode(cbuf,0xE8); // Call into runtime 3865 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3866 // Carry on here... 3867 %} 3868 3869 enc_class D2L_encoding( regD src ) %{ 3870 emit_opcode(cbuf,0xD9); // FLDCW trunc 3871 emit_opcode(cbuf,0x2D); 3872 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 3873 // Allocate a word 3874 emit_opcode(cbuf,0x83); // SUB ESP,8 3875 emit_opcode(cbuf,0xEC); 3876 emit_d8(cbuf,0x08); 3877 // Encoding assumes a double has been pushed into FPR0. 3878 // Store down the double as a long, popping the FPU stack 3879 emit_opcode(cbuf,0xDF); // FISTP [ESP] 3880 emit_opcode(cbuf,0x3C); 3881 emit_d8(cbuf,0x24); 3882 // Restore the rounding mode; mask the exception 3883 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 3884 emit_opcode(cbuf,0x2D); 3885 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 3886 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 3887 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 3888 3889 // Load the converted int; adjust CPU stack 3890 emit_opcode(cbuf,0x58); // POP EAX 3891 emit_opcode(cbuf,0x5A); // POP EDX 3892 emit_opcode(cbuf,0x81); // CMP EDX,imm 3893 emit_d8 (cbuf,0xFA); // rdx 3894 emit_d32 (cbuf,0x80000000); // 0x80000000 3895 emit_opcode(cbuf,0x75); // JNE around_slow_call 3896 emit_d8 (cbuf,0x07+4); // Size of slow_call 3897 emit_opcode(cbuf,0x85); // TEST EAX,EAX 3898 emit_opcode(cbuf,0xC0); // 2/rax,/rax, 3899 emit_opcode(cbuf,0x75); // JNE around_slow_call 3900 emit_d8 (cbuf,0x07); // Size of slow_call 3901 // Push src onto stack slow-path 3902 emit_opcode(cbuf,0xD9 ); // FLD ST(i) 3903 emit_d8 (cbuf,0xC0-1+$src$$reg ); 3904 // CALL directly to the runtime 3905 cbuf.set_inst_mark(); 3906 emit_opcode(cbuf,0xE8); // Call into runtime 3907 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3908 // Carry on here... 3909 %} 3910 3911 enc_class X2L_encoding( regX src ) %{ 3912 // Allocate a word 3913 emit_opcode(cbuf,0x83); // SUB ESP,8 3914 emit_opcode(cbuf,0xEC); 3915 emit_d8(cbuf,0x08); 3916 3917 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src 3918 emit_opcode (cbuf, 0x0F ); 3919 emit_opcode (cbuf, 0x11 ); 3920 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 3921 3922 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] 3923 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 3924 3925 emit_opcode(cbuf,0xD9); // FLDCW trunc 3926 emit_opcode(cbuf,0x2D); 3927 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 3928 3929 // Encoding assumes a double has been pushed into FPR0. 3930 // Store down the double as a long, popping the FPU stack 3931 emit_opcode(cbuf,0xDF); // FISTP [ESP] 3932 emit_opcode(cbuf,0x3C); 3933 emit_d8(cbuf,0x24); 3934 3935 // Restore the rounding mode; mask the exception 3936 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 3937 emit_opcode(cbuf,0x2D); 3938 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 3939 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 3940 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 3941 3942 // Load the converted int; adjust CPU stack 3943 emit_opcode(cbuf,0x58); // POP EAX 3944 3945 emit_opcode(cbuf,0x5A); // POP EDX 3946 3947 emit_opcode(cbuf,0x81); // CMP EDX,imm 3948 emit_d8 (cbuf,0xFA); // rdx 3949 emit_d32 (cbuf,0x80000000);// 0x80000000 3950 3951 emit_opcode(cbuf,0x75); // JNE around_slow_call 3952 emit_d8 (cbuf,0x13+4); // Size of slow_call 3953 3954 emit_opcode(cbuf,0x85); // TEST EAX,EAX 3955 emit_opcode(cbuf,0xC0); // 2/rax,/rax, 3956 3957 emit_opcode(cbuf,0x75); // JNE around_slow_call 3958 emit_d8 (cbuf,0x13); // Size of slow_call 3959 3960 // Allocate a word 3961 emit_opcode(cbuf,0x83); // SUB ESP,4 3962 emit_opcode(cbuf,0xEC); 3963 emit_d8(cbuf,0x04); 3964 3965 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], src 3966 emit_opcode (cbuf, 0x0F ); 3967 emit_opcode (cbuf, 0x11 ); 3968 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 3969 3970 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] 3971 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 3972 3973 emit_opcode(cbuf,0x83); // ADD ESP,4 3974 emit_opcode(cbuf,0xC4); 3975 emit_d8(cbuf,0x04); 3976 3977 // CALL directly to the runtime 3978 cbuf.set_inst_mark(); 3979 emit_opcode(cbuf,0xE8); // Call into runtime 3980 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 3981 // Carry on here... 3982 %} 3983 3984 enc_class XD2L_encoding( regXD src ) %{ 3985 // Allocate a word 3986 emit_opcode(cbuf,0x83); // SUB ESP,8 3987 emit_opcode(cbuf,0xEC); 3988 emit_d8(cbuf,0x08); 3989 3990 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src 3991 emit_opcode (cbuf, 0x0F ); 3992 emit_opcode (cbuf, 0x11 ); 3993 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 3994 3995 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 3996 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 3997 3998 emit_opcode(cbuf,0xD9); // FLDCW trunc 3999 emit_opcode(cbuf,0x2D); 4000 emit_d32(cbuf,(int)StubRoutines::addr_fpu_cntrl_wrd_trunc()); 4001 4002 // Encoding assumes a double has been pushed into FPR0. 4003 // Store down the double as a long, popping the FPU stack 4004 emit_opcode(cbuf,0xDF); // FISTP [ESP] 4005 emit_opcode(cbuf,0x3C); 4006 emit_d8(cbuf,0x24); 4007 4008 // Restore the rounding mode; mask the exception 4009 emit_opcode(cbuf,0xD9); // FLDCW std/24-bit mode 4010 emit_opcode(cbuf,0x2D); 4011 emit_d32( cbuf, Compile::current()->in_24_bit_fp_mode() 4012 ? (int)StubRoutines::addr_fpu_cntrl_wrd_24() 4013 : (int)StubRoutines::addr_fpu_cntrl_wrd_std()); 4014 4015 // Load the converted int; adjust CPU stack 4016 emit_opcode(cbuf,0x58); // POP EAX 4017 4018 emit_opcode(cbuf,0x5A); // POP EDX 4019 4020 emit_opcode(cbuf,0x81); // CMP EDX,imm 4021 emit_d8 (cbuf,0xFA); // rdx 4022 emit_d32 (cbuf,0x80000000); // 0x80000000 4023 4024 emit_opcode(cbuf,0x75); // JNE around_slow_call 4025 emit_d8 (cbuf,0x13+4); // Size of slow_call 4026 4027 emit_opcode(cbuf,0x85); // TEST EAX,EAX 4028 emit_opcode(cbuf,0xC0); // 2/rax,/rax, 4029 4030 emit_opcode(cbuf,0x75); // JNE around_slow_call 4031 emit_d8 (cbuf,0x13); // Size of slow_call 4032 4033 // Push src onto stack slow-path 4034 // Allocate a word 4035 emit_opcode(cbuf,0x83); // SUB ESP,8 4036 emit_opcode(cbuf,0xEC); 4037 emit_d8(cbuf,0x08); 4038 4039 emit_opcode (cbuf, 0xF2 ); // MOVSD [ESP], src 4040 emit_opcode (cbuf, 0x0F ); 4041 emit_opcode (cbuf, 0x11 ); 4042 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 4043 4044 emit_opcode(cbuf,0xDD ); // FLD_D [ESP] 4045 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 4046 4047 emit_opcode(cbuf,0x83); // ADD ESP,8 4048 emit_opcode(cbuf,0xC4); 4049 emit_d8(cbuf,0x08); 4050 4051 // CALL directly to the runtime 4052 cbuf.set_inst_mark(); 4053 emit_opcode(cbuf,0xE8); // Call into runtime 4054 emit_d32_reloc(cbuf, (StubRoutines::d2l_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 4055 // Carry on here... 4056 %} 4057 4058 enc_class D2X_encoding( regX dst, regD src ) %{ 4059 // Allocate a word 4060 emit_opcode(cbuf,0x83); // SUB ESP,4 4061 emit_opcode(cbuf,0xEC); 4062 emit_d8(cbuf,0x04); 4063 int pop = 0x02; 4064 if ($src$$reg != FPR1L_enc) { 4065 emit_opcode( cbuf, 0xD9 ); // FLD ST(i-1) 4066 emit_d8( cbuf, 0xC0-1+$src$$reg ); 4067 pop = 0x03; 4068 } 4069 store_to_stackslot( cbuf, 0xD9, pop, 0 ); // FST<P>_S [ESP] 4070 4071 emit_opcode (cbuf, 0xF3 ); // MOVSS dst(xmm), [ESP] 4072 emit_opcode (cbuf, 0x0F ); 4073 emit_opcode (cbuf, 0x10 ); 4074 encode_RegMem(cbuf, $dst$$reg, ESP_enc, 0x4, 0, 0, false); 4075 4076 emit_opcode(cbuf,0x83); // ADD ESP,4 4077 emit_opcode(cbuf,0xC4); 4078 emit_d8(cbuf,0x04); 4079 // Carry on here... 4080 %} 4081 4082 enc_class FX2I_encoding( regX src, eRegI dst ) %{ 4083 emit_rm(cbuf, 0x3, $dst$$reg, $src$$reg); 4084 4085 // Compare the result to see if we need to go to the slow path 4086 emit_opcode(cbuf,0x81); // CMP dst,imm 4087 emit_rm (cbuf,0x3,0x7,$dst$$reg); 4088 emit_d32 (cbuf,0x80000000); // 0x80000000 4089 4090 emit_opcode(cbuf,0x75); // JNE around_slow_call 4091 emit_d8 (cbuf,0x13); // Size of slow_call 4092 // Store xmm to a temp memory 4093 // location and push it onto stack. 4094 4095 emit_opcode(cbuf,0x83); // SUB ESP,4 4096 emit_opcode(cbuf,0xEC); 4097 emit_d8(cbuf, $primary ? 0x8 : 0x4); 4098 4099 emit_opcode (cbuf, $primary ? 0xF2 : 0xF3 ); // MOVSS [ESP], xmm 4100 emit_opcode (cbuf, 0x0F ); 4101 emit_opcode (cbuf, 0x11 ); 4102 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 4103 4104 emit_opcode(cbuf, $primary ? 0xDD : 0xD9 ); // FLD [ESP] 4105 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 4106 4107 emit_opcode(cbuf,0x83); // ADD ESP,4 4108 emit_opcode(cbuf,0xC4); 4109 emit_d8(cbuf, $primary ? 0x8 : 0x4); 4110 4111 // CALL directly to the runtime 4112 cbuf.set_inst_mark(); 4113 emit_opcode(cbuf,0xE8); // Call into runtime 4114 emit_d32_reloc(cbuf, (StubRoutines::d2i_wrapper() - cbuf.code_end()) - 4, runtime_call_Relocation::spec(), RELOC_IMM32 ); 4115 4116 // Carry on here... 4117 %} 4118 4119 enc_class X2D_encoding( regD dst, regX src ) %{ 4120 // Allocate a word 4121 emit_opcode(cbuf,0x83); // SUB ESP,4 4122 emit_opcode(cbuf,0xEC); 4123 emit_d8(cbuf,0x04); 4124 4125 emit_opcode (cbuf, 0xF3 ); // MOVSS [ESP], xmm 4126 emit_opcode (cbuf, 0x0F ); 4127 emit_opcode (cbuf, 0x11 ); 4128 encode_RegMem(cbuf, $src$$reg, ESP_enc, 0x4, 0, 0, false); 4129 4130 emit_opcode(cbuf,0xD9 ); // FLD_S [ESP] 4131 encode_RegMem(cbuf, 0x0, ESP_enc, 0x4, 0, 0, false); 4132 4133 emit_opcode(cbuf,0x83); // ADD ESP,4 4134 emit_opcode(cbuf,0xC4); 4135 emit_d8(cbuf,0x04); 4136 4137 // Carry on here... 4138 %} 4139 4140 enc_class AbsXF_encoding(regX dst) %{ 4141 address signmask_address=(address)float_signmask_pool; 4142 // andpd:\tANDPS $dst,[signconst] 4143 emit_opcode(cbuf, 0x0F); 4144 emit_opcode(cbuf, 0x54); 4145 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 4146 emit_d32(cbuf, (int)signmask_address); 4147 %} 4148 4149 enc_class AbsXD_encoding(regXD dst) %{ 4150 address signmask_address=(address)double_signmask_pool; 4151 // andpd:\tANDPD $dst,[signconst] 4152 emit_opcode(cbuf, 0x66); 4153 emit_opcode(cbuf, 0x0F); 4154 emit_opcode(cbuf, 0x54); 4155 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 4156 emit_d32(cbuf, (int)signmask_address); 4157 %} 4158 4159 enc_class NegXF_encoding(regX dst) %{ 4160 address signmask_address=(address)float_signflip_pool; 4161 // andpd:\tXORPS $dst,[signconst] 4162 emit_opcode(cbuf, 0x0F); 4163 emit_opcode(cbuf, 0x57); 4164 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 4165 emit_d32(cbuf, (int)signmask_address); 4166 %} 4167 4168 enc_class NegXD_encoding(regXD dst) %{ 4169 address signmask_address=(address)double_signflip_pool; 4170 // andpd:\tXORPD $dst,[signconst] 4171 emit_opcode(cbuf, 0x66); 4172 emit_opcode(cbuf, 0x0F); 4173 emit_opcode(cbuf, 0x57); 4174 emit_rm(cbuf, 0x0, $dst$$reg, 0x5); 4175 emit_d32(cbuf, (int)signmask_address); 4176 %} 4177 4178 enc_class FMul_ST_reg( eRegF src1 ) %{ 4179 // Operand was loaded from memory into fp ST (stack top) 4180 // FMUL ST,$src /* D8 C8+i */ 4181 emit_opcode(cbuf, 0xD8); 4182 emit_opcode(cbuf, 0xC8 + $src1$$reg); 4183 %} 4184 4185 enc_class FAdd_ST_reg( eRegF src2 ) %{ 4186 // FADDP ST,src2 /* D8 C0+i */ 4187 emit_opcode(cbuf, 0xD8); 4188 emit_opcode(cbuf, 0xC0 + $src2$$reg); 4189 //could use FADDP src2,fpST /* DE C0+i */ 4190 %} 4191 4192 enc_class FAddP_reg_ST( eRegF src2 ) %{ 4193 // FADDP src2,ST /* DE C0+i */ 4194 emit_opcode(cbuf, 0xDE); 4195 emit_opcode(cbuf, 0xC0 + $src2$$reg); 4196 %} 4197 4198 enc_class subF_divF_encode( eRegF src1, eRegF src2) %{ 4199 // Operand has been loaded into fp ST (stack top) 4200 // FSUB ST,$src1 4201 emit_opcode(cbuf, 0xD8); 4202 emit_opcode(cbuf, 0xE0 + $src1$$reg); 4203 4204 // FDIV 4205 emit_opcode(cbuf, 0xD8); 4206 emit_opcode(cbuf, 0xF0 + $src2$$reg); 4207 %} 4208 4209 enc_class MulFAddF (eRegF src1, eRegF src2) %{ 4210 // Operand was loaded from memory into fp ST (stack top) 4211 // FADD ST,$src /* D8 C0+i */ 4212 emit_opcode(cbuf, 0xD8); 4213 emit_opcode(cbuf, 0xC0 + $src1$$reg); 4214 4215 // FMUL ST,src2 /* D8 C*+i */ 4216 emit_opcode(cbuf, 0xD8); 4217 emit_opcode(cbuf, 0xC8 + $src2$$reg); 4218 %} 4219 4220 4221 enc_class MulFAddFreverse (eRegF src1, eRegF src2) %{ 4222 // Operand was loaded from memory into fp ST (stack top) 4223 // FADD ST,$src /* D8 C0+i */ 4224 emit_opcode(cbuf, 0xD8); 4225 emit_opcode(cbuf, 0xC0 + $src1$$reg); 4226 4227 // FMULP src2,ST /* DE C8+i */ 4228 emit_opcode(cbuf, 0xDE); 4229 emit_opcode(cbuf, 0xC8 + $src2$$reg); 4230 %} 4231 4232 enc_class enc_membar_acquire %{ 4233 // Doug Lea believes this is not needed with current Sparcs and TSO. 4234 // MacroAssembler masm(&cbuf); 4235 // masm.membar(); 4236 %} 4237 4238 enc_class enc_membar_release %{ 4239 // Doug Lea believes this is not needed with current Sparcs and TSO. 4240 // MacroAssembler masm(&cbuf); 4241 // masm.membar(); 4242 %} 4243 4244 enc_class enc_membar_volatile %{ 4245 MacroAssembler masm(&cbuf); 4246 masm.membar(); 4247 %} 4248 4249 // Atomically load the volatile long 4250 enc_class enc_loadL_volatile( memory mem, stackSlotL dst ) %{ 4251 emit_opcode(cbuf,0xDF); 4252 int rm_byte_opcode = 0x05; 4253 int base = $mem$$base; 4254 int index = $mem$$index; 4255 int scale = $mem$$scale; 4256 int displace = $mem$$disp; 4257 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4258 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 4259 store_to_stackslot( cbuf, 0x0DF, 0x07, $dst$$disp ); 4260 %} 4261 4262 enc_class enc_loadLX_volatile( memory mem, stackSlotL dst, regXD tmp ) %{ 4263 { // Atomic long load 4264 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem 4265 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 4266 emit_opcode(cbuf,0x0F); 4267 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); 4268 int base = $mem$$base; 4269 int index = $mem$$index; 4270 int scale = $mem$$scale; 4271 int displace = $mem$$disp; 4272 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4273 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4274 } 4275 { // MOVSD $dst,$tmp ! atomic long store 4276 emit_opcode(cbuf,0xF2); 4277 emit_opcode(cbuf,0x0F); 4278 emit_opcode(cbuf,0x11); 4279 int base = $dst$$base; 4280 int index = $dst$$index; 4281 int scale = $dst$$scale; 4282 int displace = $dst$$disp; 4283 bool disp_is_oop = $dst->disp_is_oop(); // disp-as-oop when working with static globals 4284 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4285 } 4286 %} 4287 4288 enc_class enc_loadLX_reg_volatile( memory mem, eRegL dst, regXD tmp ) %{ 4289 { // Atomic long load 4290 // UseXmmLoadAndClearUpper ? movsd $tmp,$mem : movlpd $tmp,$mem 4291 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 4292 emit_opcode(cbuf,0x0F); 4293 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); 4294 int base = $mem$$base; 4295 int index = $mem$$index; 4296 int scale = $mem$$scale; 4297 int displace = $mem$$disp; 4298 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4299 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4300 } 4301 { // MOVD $dst.lo,$tmp 4302 emit_opcode(cbuf,0x66); 4303 emit_opcode(cbuf,0x0F); 4304 emit_opcode(cbuf,0x7E); 4305 emit_rm(cbuf, 0x3, $tmp$$reg, $dst$$reg); 4306 } 4307 { // PSRLQ $tmp,32 4308 emit_opcode(cbuf,0x66); 4309 emit_opcode(cbuf,0x0F); 4310 emit_opcode(cbuf,0x73); 4311 emit_rm(cbuf, 0x3, 0x02, $tmp$$reg); 4312 emit_d8(cbuf, 0x20); 4313 } 4314 { // MOVD $dst.hi,$tmp 4315 emit_opcode(cbuf,0x66); 4316 emit_opcode(cbuf,0x0F); 4317 emit_opcode(cbuf,0x7E); 4318 emit_rm(cbuf, 0x3, $tmp$$reg, HIGH_FROM_LOW($dst$$reg)); 4319 } 4320 %} 4321 4322 // Volatile Store Long. Must be atomic, so move it into 4323 // the FP TOS and then do a 64-bit FIST. Has to probe the 4324 // target address before the store (for null-ptr checks) 4325 // so the memory operand is used twice in the encoding. 4326 enc_class enc_storeL_volatile( memory mem, stackSlotL src ) %{ 4327 store_to_stackslot( cbuf, 0x0DF, 0x05, $src$$disp ); 4328 cbuf.set_inst_mark(); // Mark start of FIST in case $mem has an oop 4329 emit_opcode(cbuf,0xDF); 4330 int rm_byte_opcode = 0x07; 4331 int base = $mem$$base; 4332 int index = $mem$$index; 4333 int scale = $mem$$scale; 4334 int displace = $mem$$disp; 4335 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4336 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace, disp_is_oop); 4337 %} 4338 4339 enc_class enc_storeLX_volatile( memory mem, stackSlotL src, regXD tmp) %{ 4340 { // Atomic long load 4341 // UseXmmLoadAndClearUpper ? movsd $tmp,[$src] : movlpd $tmp,[$src] 4342 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0xF2 : 0x66); 4343 emit_opcode(cbuf,0x0F); 4344 emit_opcode(cbuf,UseXmmLoadAndClearUpper ? 0x10 : 0x12); 4345 int base = $src$$base; 4346 int index = $src$$index; 4347 int scale = $src$$scale; 4348 int displace = $src$$disp; 4349 bool disp_is_oop = $src->disp_is_oop(); // disp-as-oop when working with static globals 4350 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4351 } 4352 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop 4353 { // MOVSD $mem,$tmp ! atomic long store 4354 emit_opcode(cbuf,0xF2); 4355 emit_opcode(cbuf,0x0F); 4356 emit_opcode(cbuf,0x11); 4357 int base = $mem$$base; 4358 int index = $mem$$index; 4359 int scale = $mem$$scale; 4360 int displace = $mem$$disp; 4361 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4362 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4363 } 4364 %} 4365 4366 enc_class enc_storeLX_reg_volatile( memory mem, eRegL src, regXD tmp, regXD tmp2) %{ 4367 { // MOVD $tmp,$src.lo 4368 emit_opcode(cbuf,0x66); 4369 emit_opcode(cbuf,0x0F); 4370 emit_opcode(cbuf,0x6E); 4371 emit_rm(cbuf, 0x3, $tmp$$reg, $src$$reg); 4372 } 4373 { // MOVD $tmp2,$src.hi 4374 emit_opcode(cbuf,0x66); 4375 emit_opcode(cbuf,0x0F); 4376 emit_opcode(cbuf,0x6E); 4377 emit_rm(cbuf, 0x3, $tmp2$$reg, HIGH_FROM_LOW($src$$reg)); 4378 } 4379 { // PUNPCKLDQ $tmp,$tmp2 4380 emit_opcode(cbuf,0x66); 4381 emit_opcode(cbuf,0x0F); 4382 emit_opcode(cbuf,0x62); 4383 emit_rm(cbuf, 0x3, $tmp$$reg, $tmp2$$reg); 4384 } 4385 cbuf.set_inst_mark(); // Mark start of MOVSD in case $mem has an oop 4386 { // MOVSD $mem,$tmp ! atomic long store 4387 emit_opcode(cbuf,0xF2); 4388 emit_opcode(cbuf,0x0F); 4389 emit_opcode(cbuf,0x11); 4390 int base = $mem$$base; 4391 int index = $mem$$index; 4392 int scale = $mem$$scale; 4393 int displace = $mem$$disp; 4394 bool disp_is_oop = $mem->disp_is_oop(); // disp-as-oop when working with static globals 4395 encode_RegMem(cbuf, $tmp$$reg, base, index, scale, displace, disp_is_oop); 4396 } 4397 %} 4398 4399 // Safepoint Poll. This polls the safepoint page, and causes an 4400 // exception if it is not readable. Unfortunately, it kills the condition code 4401 // in the process 4402 // We current use TESTL [spp],EDI 4403 // A better choice might be TESTB [spp + pagesize() - CacheLineSize()],0 4404 4405 enc_class Safepoint_Poll() %{ 4406 cbuf.relocate(cbuf.inst_mark(), relocInfo::poll_type, 0); 4407 emit_opcode(cbuf,0x85); 4408 emit_rm (cbuf, 0x0, 0x7, 0x5); 4409 emit_d32(cbuf, (intptr_t)os::get_polling_page()); 4410 %} 4411%} 4412 4413 4414//----------FRAME-------------------------------------------------------------- 4415// Definition of frame structure and management information. 4416// 4417// S T A C K L A Y O U T Allocators stack-slot number 4418// | (to get allocators register number 4419// G Owned by | | v add OptoReg::stack0()) 4420// r CALLER | | 4421// o | +--------+ pad to even-align allocators stack-slot 4422// w V | pad0 | numbers; owned by CALLER 4423// t -----------+--------+----> Matcher::_in_arg_limit, unaligned 4424// h ^ | in | 5 4425// | | args | 4 Holes in incoming args owned by SELF 4426// | | | | 3 4427// | | +--------+ 4428// V | | old out| Empty on Intel, window on Sparc 4429// | old |preserve| Must be even aligned. 4430// | SP-+--------+----> Matcher::_old_SP, even aligned 4431// | | in | 3 area for Intel ret address 4432// Owned by |preserve| Empty on Sparc. 4433// SELF +--------+ 4434// | | pad2 | 2 pad to align old SP 4435// | +--------+ 1 4436// | | locks | 0 4437// | +--------+----> OptoReg::stack0(), even aligned 4438// | | pad1 | 11 pad to align new SP 4439// | +--------+ 4440// | | | 10 4441// | | spills | 9 spills 4442// V | | 8 (pad0 slot for callee) 4443// -----------+--------+----> Matcher::_out_arg_limit, unaligned 4444// ^ | out | 7 4445// | | args | 6 Holes in outgoing args owned by CALLEE 4446// Owned by +--------+ 4447// CALLEE | new out| 6 Empty on Intel, window on Sparc 4448// | new |preserve| Must be even-aligned. 4449// | SP-+--------+----> Matcher::_new_SP, even aligned 4450// | | | 4451// 4452// Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 4453// known from SELF's arguments and the Java calling convention. 4454// Region 6-7 is determined per call site. 4455// Note 2: If the calling convention leaves holes in the incoming argument 4456// area, those holes are owned by SELF. Holes in the outgoing area 4457// are owned by the CALLEE. Holes should not be nessecary in the 4458// incoming area, as the Java calling convention is completely under 4459// the control of the AD file. Doubles can be sorted and packed to 4460// avoid holes. Holes in the outgoing arguments may be nessecary for 4461// varargs C calling conventions. 4462// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 4463// even aligned with pad0 as needed. 4464// Region 6 is even aligned. Region 6-7 is NOT even aligned; 4465// region 6-11 is even aligned; it may be padded out more so that 4466// the region from SP to FP meets the minimum stack alignment. 4467 4468frame %{ 4469 // What direction does stack grow in (assumed to be same for C & Java) 4470 stack_direction(TOWARDS_LOW); 4471 4472 // These three registers define part of the calling convention 4473 // between compiled code and the interpreter. 4474 inline_cache_reg(EAX); // Inline Cache Register 4475 interpreter_method_oop_reg(EBX); // Method Oop Register when calling interpreter 4476 4477 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 4478 cisc_spilling_operand_name(indOffset32); 4479 4480 // Number of stack slots consumed by locking an object 4481 sync_stack_slots(1); 4482 4483 // Compiled code's Frame Pointer 4484 frame_pointer(ESP); 4485 // Interpreter stores its frame pointer in a register which is 4486 // stored to the stack by I2CAdaptors. 4487 // I2CAdaptors convert from interpreted java to compiled java. 4488 interpreter_frame_pointer(EBP); 4489 4490 // Stack alignment requirement 4491 // Alignment size in bytes (128-bit -> 16 bytes) 4492 stack_alignment(StackAlignmentInBytes); 4493 4494 // Number of stack slots between incoming argument block and the start of 4495 // a new frame. The PROLOG must add this many slots to the stack. The 4496 // EPILOG must remove this many slots. Intel needs one slot for 4497 // return address and one for rbp, (must save rbp) 4498 in_preserve_stack_slots(2+VerifyStackAtCalls); 4499 4500 // Number of outgoing stack slots killed above the out_preserve_stack_slots 4501 // for calls to C. Supports the var-args backing area for register parms. 4502 varargs_C_out_slots_killed(0); 4503 4504 // The after-PROLOG location of the return address. Location of 4505 // return address specifies a type (REG or STACK) and a number 4506 // representing the register number (i.e. - use a register name) or 4507 // stack slot. 4508 // Ret Addr is on stack in slot 0 if no locks or verification or alignment. 4509 // Otherwise, it is above the locks and verification slot and alignment word 4510 return_addr(STACK - 1 + 4511 round_to(1+VerifyStackAtCalls+ 4512 Compile::current()->fixed_slots(), 4513 (StackAlignmentInBytes/wordSize))); 4514 4515 // Body of function which returns an integer array locating 4516 // arguments either in registers or in stack slots. Passed an array 4517 // of ideal registers called "sig" and a "length" count. Stack-slot 4518 // offsets are based on outgoing arguments, i.e. a CALLER setting up 4519 // arguments for a CALLEE. Incoming stack arguments are 4520 // automatically biased by the preserve_stack_slots field above. 4521 calling_convention %{ 4522 // No difference between ingoing/outgoing just pass false 4523 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 4524 %} 4525 4526 4527 // Body of function which returns an integer array locating 4528 // arguments either in registers or in stack slots. Passed an array 4529 // of ideal registers called "sig" and a "length" count. Stack-slot 4530 // offsets are based on outgoing arguments, i.e. a CALLER setting up 4531 // arguments for a CALLEE. Incoming stack arguments are 4532 // automatically biased by the preserve_stack_slots field above. 4533 c_calling_convention %{ 4534 // This is obviously always outgoing 4535 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); 4536 %} 4537 4538 // Location of C & interpreter return values 4539 c_return_value %{ 4540 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 4541 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; 4542 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; 4543 4544 // in SSE2+ mode we want to keep the FPU stack clean so pretend 4545 // that C functions return float and double results in XMM0. 4546 if( ideal_reg == Op_RegD && UseSSE>=2 ) 4547 return OptoRegPair(XMM0b_num,XMM0a_num); 4548 if( ideal_reg == Op_RegF && UseSSE>=2 ) 4549 return OptoRegPair(OptoReg::Bad,XMM0a_num); 4550 4551 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); 4552 %} 4553 4554 // Location of return values 4555 return_value %{ 4556 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 4557 static int lo[Op_RegL+1] = { 0, 0, OptoReg::Bad, EAX_num, EAX_num, FPR1L_num, FPR1L_num, EAX_num }; 4558 static int hi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, FPR1H_num, EDX_num }; 4559 if( ideal_reg == Op_RegD && UseSSE>=2 ) 4560 return OptoRegPair(XMM0b_num,XMM0a_num); 4561 if( ideal_reg == Op_RegF && UseSSE>=1 ) 4562 return OptoRegPair(OptoReg::Bad,XMM0a_num); 4563 return OptoRegPair(hi[ideal_reg],lo[ideal_reg]); 4564 %} 4565 4566%} 4567 4568//----------ATTRIBUTES--------------------------------------------------------- 4569//----------Operand Attributes------------------------------------------------- 4570op_attrib op_cost(0); // Required cost attribute 4571 4572//----------Instruction Attributes--------------------------------------------- 4573ins_attrib ins_cost(100); // Required cost attribute 4574ins_attrib ins_size(8); // Required size attribute (in bits) 4575ins_attrib ins_pc_relative(0); // Required PC Relative flag 4576ins_attrib ins_short_branch(0); // Required flag: is this instruction a 4577 // non-matching short branch variant of some 4578 // long branch? 4579ins_attrib ins_alignment(1); // Required alignment attribute (must be a power of 2) 4580 // specifies the alignment that some part of the instruction (not 4581 // necessarily the start) requires. If > 1, a compute_padding() 4582 // function must be provided for the instruction 4583 4584//----------OPERANDS----------------------------------------------------------- 4585// Operand definitions must precede instruction definitions for correct parsing 4586// in the ADLC because operands constitute user defined types which are used in 4587// instruction definitions. 4588 4589//----------Simple Operands---------------------------------------------------- 4590// Immediate Operands 4591// Integer Immediate 4592operand immI() %{ 4593 match(ConI); 4594 4595 op_cost(10); 4596 format %{ %} 4597 interface(CONST_INTER); 4598%} 4599 4600// Constant for test vs zero 4601operand immI0() %{ 4602 predicate(n->get_int() == 0); 4603 match(ConI); 4604 4605 op_cost(0); 4606 format %{ %} 4607 interface(CONST_INTER); 4608%} 4609 4610// Constant for increment 4611operand immI1() %{ 4612 predicate(n->get_int() == 1); 4613 match(ConI); 4614 4615 op_cost(0); 4616 format %{ %} 4617 interface(CONST_INTER); 4618%} 4619 4620// Constant for decrement 4621operand immI_M1() %{ 4622 predicate(n->get_int() == -1); 4623 match(ConI); 4624 4625 op_cost(0); 4626 format %{ %} 4627 interface(CONST_INTER); 4628%} 4629 4630// Valid scale values for addressing modes 4631operand immI2() %{ 4632 predicate(0 <= n->get_int() && (n->get_int() <= 3)); 4633 match(ConI); 4634 4635 format %{ %} 4636 interface(CONST_INTER); 4637%} 4638 4639operand immI8() %{ 4640 predicate((-128 <= n->get_int()) && (n->get_int() <= 127)); 4641 match(ConI); 4642 4643 op_cost(5); 4644 format %{ %} 4645 interface(CONST_INTER); 4646%} 4647 4648operand immI16() %{ 4649 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767)); 4650 match(ConI); 4651 4652 op_cost(10); 4653 format %{ %} 4654 interface(CONST_INTER); 4655%} 4656 4657// Constant for long shifts 4658operand immI_32() %{ 4659 predicate( n->get_int() == 32 ); 4660 match(ConI); 4661 4662 op_cost(0); 4663 format %{ %} 4664 interface(CONST_INTER); 4665%} 4666 4667operand immI_1_31() %{ 4668 predicate( n->get_int() >= 1 && n->get_int() <= 31 ); 4669 match(ConI); 4670 4671 op_cost(0); 4672 format %{ %} 4673 interface(CONST_INTER); 4674%} 4675 4676operand immI_32_63() %{ 4677 predicate( n->get_int() >= 32 && n->get_int() <= 63 ); 4678 match(ConI); 4679 op_cost(0); 4680 4681 format %{ %} 4682 interface(CONST_INTER); 4683%} 4684 4685// Pointer Immediate 4686operand immP() %{ 4687 match(ConP); 4688 4689 op_cost(10); 4690 format %{ %} 4691 interface(CONST_INTER); 4692%} 4693 4694// NULL Pointer Immediate 4695operand immP0() %{ 4696 predicate( n->get_ptr() == 0 ); 4697 match(ConP); 4698 op_cost(0); 4699 4700 format %{ %} 4701 interface(CONST_INTER); 4702%} 4703 4704// Long Immediate 4705operand immL() %{ 4706 match(ConL); 4707 4708 op_cost(20); 4709 format %{ %} 4710 interface(CONST_INTER); 4711%} 4712 4713// Long Immediate zero 4714operand immL0() %{ 4715 predicate( n->get_long() == 0L ); 4716 match(ConL); 4717 op_cost(0); 4718 4719 format %{ %} 4720 interface(CONST_INTER); 4721%} 4722 4723// Long immediate from 0 to 127. 4724// Used for a shorter form of long mul by 10. 4725operand immL_127() %{ 4726 predicate((0 <= n->get_long()) && (n->get_long() <= 127)); 4727 match(ConL); 4728 op_cost(0); 4729 4730 format %{ %} 4731 interface(CONST_INTER); 4732%} 4733 4734// Long Immediate: low 32-bit mask 4735operand immL_32bits() %{ 4736 predicate(n->get_long() == 0xFFFFFFFFL); 4737 match(ConL); 4738 op_cost(0); 4739 4740 format %{ %} 4741 interface(CONST_INTER); 4742%} 4743 4744// Long Immediate: low 32-bit mask 4745operand immL32() %{ 4746 predicate(n->get_long() == (int)(n->get_long())); 4747 match(ConL); 4748 op_cost(20); 4749 4750 format %{ %} 4751 interface(CONST_INTER); 4752%} 4753 4754//Double Immediate zero 4755operand immD0() %{ 4756 // Do additional (and counter-intuitive) test against NaN to work around VC++ 4757 // bug that generates code such that NaNs compare equal to 0.0 4758 predicate( UseSSE<=1 && n->getd() == 0.0 && !g_isnan(n->getd()) ); 4759 match(ConD); 4760 4761 op_cost(5); 4762 format %{ %} 4763 interface(CONST_INTER); 4764%} 4765 4766// Double Immediate 4767operand immD1() %{ 4768 predicate( UseSSE<=1 && n->getd() == 1.0 ); 4769 match(ConD); 4770 4771 op_cost(5); 4772 format %{ %} 4773 interface(CONST_INTER); 4774%} 4775 4776// Double Immediate 4777operand immD() %{ 4778 predicate(UseSSE<=1); 4779 match(ConD); 4780 4781 op_cost(5); 4782 format %{ %} 4783 interface(CONST_INTER); 4784%} 4785 4786operand immXD() %{ 4787 predicate(UseSSE>=2); 4788 match(ConD); 4789 4790 op_cost(5); 4791 format %{ %} 4792 interface(CONST_INTER); 4793%} 4794 4795// Double Immediate zero 4796operand immXD0() %{ 4797 // Do additional (and counter-intuitive) test against NaN to work around VC++ 4798 // bug that generates code such that NaNs compare equal to 0.0 AND do not 4799 // compare equal to -0.0. 4800 predicate( UseSSE>=2 && jlong_cast(n->getd()) == 0 ); 4801 match(ConD); 4802 4803 format %{ %} 4804 interface(CONST_INTER); 4805%} 4806 4807// Float Immediate zero 4808operand immF0() %{ 4809 predicate( UseSSE == 0 && n->getf() == 0.0 ); 4810 match(ConF); 4811 4812 op_cost(5); 4813 format %{ %} 4814 interface(CONST_INTER); 4815%} 4816 4817// Float Immediate 4818operand immF() %{ 4819 predicate( UseSSE == 0 ); 4820 match(ConF); 4821 4822 op_cost(5); 4823 format %{ %} 4824 interface(CONST_INTER); 4825%} 4826 4827// Float Immediate 4828operand immXF() %{ 4829 predicate(UseSSE >= 1); 4830 match(ConF); 4831 4832 op_cost(5); 4833 format %{ %} 4834 interface(CONST_INTER); 4835%} 4836 4837// Float Immediate zero. Zero and not -0.0 4838operand immXF0() %{ 4839 predicate( UseSSE >= 1 && jint_cast(n->getf()) == 0 ); 4840 match(ConF); 4841 4842 op_cost(5); 4843 format %{ %} 4844 interface(CONST_INTER); 4845%} 4846 4847// Immediates for special shifts (sign extend) 4848 4849// Constants for increment 4850operand immI_16() %{ 4851 predicate( n->get_int() == 16 ); 4852 match(ConI); 4853 4854 format %{ %} 4855 interface(CONST_INTER); 4856%} 4857 4858operand immI_24() %{ 4859 predicate( n->get_int() == 24 ); 4860 match(ConI); 4861 4862 format %{ %} 4863 interface(CONST_INTER); 4864%} 4865 4866// Constant for byte-wide masking 4867operand immI_255() %{ 4868 predicate( n->get_int() == 255 ); 4869 match(ConI); 4870 4871 format %{ %} 4872 interface(CONST_INTER); 4873%} 4874 4875// Register Operands 4876// Integer Register 4877operand eRegI() %{ 4878 constraint(ALLOC_IN_RC(e_reg)); 4879 match(RegI); 4880 match(xRegI); 4881 match(eAXRegI); 4882 match(eBXRegI); 4883 match(eCXRegI); 4884 match(eDXRegI); 4885 match(eDIRegI); 4886 match(eSIRegI); 4887 4888 format %{ %} 4889 interface(REG_INTER); 4890%} 4891 4892// Subset of Integer Register 4893operand xRegI(eRegI reg) %{ 4894 constraint(ALLOC_IN_RC(x_reg)); 4895 match(reg); 4896 match(eAXRegI); 4897 match(eBXRegI); 4898 match(eCXRegI); 4899 match(eDXRegI); 4900 4901 format %{ %} 4902 interface(REG_INTER); 4903%} 4904 4905// Special Registers 4906operand eAXRegI(xRegI reg) %{ 4907 constraint(ALLOC_IN_RC(eax_reg)); 4908 match(reg); 4909 match(eRegI); 4910 4911 format %{ "EAX" %} 4912 interface(REG_INTER); 4913%} 4914 4915// Special Registers 4916operand eBXRegI(xRegI reg) %{ 4917 constraint(ALLOC_IN_RC(ebx_reg)); 4918 match(reg); 4919 match(eRegI); 4920 4921 format %{ "EBX" %} 4922 interface(REG_INTER); 4923%} 4924 4925operand eCXRegI(xRegI reg) %{ 4926 constraint(ALLOC_IN_RC(ecx_reg)); 4927 match(reg); 4928 match(eRegI); 4929 4930 format %{ "ECX" %} 4931 interface(REG_INTER); 4932%} 4933 4934operand eDXRegI(xRegI reg) %{ 4935 constraint(ALLOC_IN_RC(edx_reg)); 4936 match(reg); 4937 match(eRegI); 4938 4939 format %{ "EDX" %} 4940 interface(REG_INTER); 4941%} 4942 4943operand eDIRegI(xRegI reg) %{ 4944 constraint(ALLOC_IN_RC(edi_reg)); 4945 match(reg); 4946 match(eRegI); 4947 4948 format %{ "EDI" %} 4949 interface(REG_INTER); 4950%} 4951 4952operand naxRegI() %{ 4953 constraint(ALLOC_IN_RC(nax_reg)); 4954 match(RegI); 4955 match(eCXRegI); 4956 match(eDXRegI); 4957 match(eSIRegI); 4958 match(eDIRegI); 4959 4960 format %{ %} 4961 interface(REG_INTER); 4962%} 4963 4964operand nadxRegI() %{ 4965 constraint(ALLOC_IN_RC(nadx_reg)); 4966 match(RegI); 4967 match(eBXRegI); 4968 match(eCXRegI); 4969 match(eSIRegI); 4970 match(eDIRegI); 4971 4972 format %{ %} 4973 interface(REG_INTER); 4974%} 4975 4976operand ncxRegI() %{ 4977 constraint(ALLOC_IN_RC(ncx_reg)); 4978 match(RegI); 4979 match(eAXRegI); 4980 match(eDXRegI); 4981 match(eSIRegI); 4982 match(eDIRegI); 4983 4984 format %{ %} 4985 interface(REG_INTER); 4986%} 4987 4988// // This operand was used by cmpFastUnlock, but conflicted with 'object' reg 4989// // 4990operand eSIRegI(xRegI reg) %{ 4991 constraint(ALLOC_IN_RC(esi_reg)); 4992 match(reg); 4993 match(eRegI); 4994 4995 format %{ "ESI" %} 4996 interface(REG_INTER); 4997%} 4998 4999// Pointer Register 5000operand anyRegP() %{ 5001 constraint(ALLOC_IN_RC(any_reg)); 5002 match(RegP); 5003 match(eAXRegP); 5004 match(eBXRegP); 5005 match(eCXRegP); 5006 match(eDIRegP); 5007 match(eRegP); 5008 5009 format %{ %} 5010 interface(REG_INTER); 5011%} 5012 5013operand eRegP() %{ 5014 constraint(ALLOC_IN_RC(e_reg)); 5015 match(RegP); 5016 match(eAXRegP); 5017 match(eBXRegP); 5018 match(eCXRegP); 5019 match(eDIRegP); 5020 5021 format %{ %} 5022 interface(REG_INTER); 5023%} 5024 5025// On windows95, EBP is not safe to use for implicit null tests. 5026operand eRegP_no_EBP() %{ 5027 constraint(ALLOC_IN_RC(e_reg_no_rbp)); 5028 match(RegP); 5029 match(eAXRegP); 5030 match(eBXRegP); 5031 match(eCXRegP); 5032 match(eDIRegP); 5033 5034 op_cost(100); 5035 format %{ %} 5036 interface(REG_INTER); 5037%} 5038 5039operand naxRegP() %{ 5040 constraint(ALLOC_IN_RC(nax_reg)); 5041 match(RegP); 5042 match(eBXRegP); 5043 match(eDXRegP); 5044 match(eCXRegP); 5045 match(eSIRegP); 5046 match(eDIRegP); 5047 5048 format %{ %} 5049 interface(REG_INTER); 5050%} 5051 5052operand nabxRegP() %{ 5053 constraint(ALLOC_IN_RC(nabx_reg)); 5054 match(RegP); 5055 match(eCXRegP); 5056 match(eDXRegP); 5057 match(eSIRegP); 5058 match(eDIRegP); 5059 5060 format %{ %} 5061 interface(REG_INTER); 5062%} 5063 5064operand pRegP() %{ 5065 constraint(ALLOC_IN_RC(p_reg)); 5066 match(RegP); 5067 match(eBXRegP); 5068 match(eDXRegP); 5069 match(eSIRegP); 5070 match(eDIRegP); 5071 5072 format %{ %} 5073 interface(REG_INTER); 5074%} 5075 5076// Special Registers 5077// Return a pointer value 5078operand eAXRegP(eRegP reg) %{ 5079 constraint(ALLOC_IN_RC(eax_reg)); 5080 match(reg); 5081 format %{ "EAX" %} 5082 interface(REG_INTER); 5083%} 5084 5085// Used in AtomicAdd 5086operand eBXRegP(eRegP reg) %{ 5087 constraint(ALLOC_IN_RC(ebx_reg)); 5088 match(reg); 5089 format %{ "EBX" %} 5090 interface(REG_INTER); 5091%} 5092 5093// Tail-call (interprocedural jump) to interpreter 5094operand eCXRegP(eRegP reg) %{ 5095 constraint(ALLOC_IN_RC(ecx_reg)); 5096 match(reg); 5097 format %{ "ECX" %} 5098 interface(REG_INTER); 5099%} 5100 5101operand eSIRegP(eRegP reg) %{ 5102 constraint(ALLOC_IN_RC(esi_reg)); 5103 match(reg); 5104 format %{ "ESI" %} 5105 interface(REG_INTER); 5106%} 5107 5108// Used in rep stosw 5109operand eDIRegP(eRegP reg) %{ 5110 constraint(ALLOC_IN_RC(edi_reg)); 5111 match(reg); 5112 format %{ "EDI" %} 5113 interface(REG_INTER); 5114%} 5115 5116operand eBPRegP() %{ 5117 constraint(ALLOC_IN_RC(ebp_reg)); 5118 match(RegP); 5119 format %{ "EBP" %} 5120 interface(REG_INTER); 5121%} 5122 5123operand eRegL() %{ 5124 constraint(ALLOC_IN_RC(long_reg)); 5125 match(RegL); 5126 match(eADXRegL); 5127 5128 format %{ %} 5129 interface(REG_INTER); 5130%} 5131 5132operand eADXRegL( eRegL reg ) %{ 5133 constraint(ALLOC_IN_RC(eadx_reg)); 5134 match(reg); 5135 5136 format %{ "EDX:EAX" %} 5137 interface(REG_INTER); 5138%} 5139 5140operand eBCXRegL( eRegL reg ) %{ 5141 constraint(ALLOC_IN_RC(ebcx_reg)); 5142 match(reg); 5143 5144 format %{ "EBX:ECX" %} 5145 interface(REG_INTER); 5146%} 5147 5148// Special case for integer high multiply 5149operand eADXRegL_low_only() %{ 5150 constraint(ALLOC_IN_RC(eadx_reg)); 5151 match(RegL); 5152 5153 format %{ "EAX" %} 5154 interface(REG_INTER); 5155%} 5156 5157// Flags register, used as output of compare instructions 5158operand eFlagsReg() %{ 5159 constraint(ALLOC_IN_RC(int_flags)); 5160 match(RegFlags); 5161 5162 format %{ "EFLAGS" %} 5163 interface(REG_INTER); 5164%} 5165 5166// Flags register, used as output of FLOATING POINT compare instructions 5167operand eFlagsRegU() %{ 5168 constraint(ALLOC_IN_RC(int_flags)); 5169 match(RegFlags); 5170 5171 format %{ "EFLAGS_U" %} 5172 interface(REG_INTER); 5173%} 5174 5175// Condition Code Register used by long compare 5176operand flagsReg_long_LTGE() %{ 5177 constraint(ALLOC_IN_RC(int_flags)); 5178 match(RegFlags); 5179 format %{ "FLAGS_LTGE" %} 5180 interface(REG_INTER); 5181%} 5182operand flagsReg_long_EQNE() %{ 5183 constraint(ALLOC_IN_RC(int_flags)); 5184 match(RegFlags); 5185 format %{ "FLAGS_EQNE" %} 5186 interface(REG_INTER); 5187%} 5188operand flagsReg_long_LEGT() %{ 5189 constraint(ALLOC_IN_RC(int_flags)); 5190 match(RegFlags); 5191 format %{ "FLAGS_LEGT" %} 5192 interface(REG_INTER); 5193%} 5194 5195// Float register operands 5196operand regD() %{ 5197 predicate( UseSSE < 2 ); 5198 constraint(ALLOC_IN_RC(dbl_reg)); 5199 match(RegD); 5200 match(regDPR1); 5201 match(regDPR2); 5202 format %{ %} 5203 interface(REG_INTER); 5204%} 5205 5206operand regDPR1(regD reg) %{ 5207 predicate( UseSSE < 2 ); 5208 constraint(ALLOC_IN_RC(dbl_reg0)); 5209 match(reg); 5210 format %{ "FPR1" %} 5211 interface(REG_INTER); 5212%} 5213 5214operand regDPR2(regD reg) %{ 5215 predicate( UseSSE < 2 ); 5216 constraint(ALLOC_IN_RC(dbl_reg1)); 5217 match(reg); 5218 format %{ "FPR2" %} 5219 interface(REG_INTER); 5220%} 5221 5222operand regnotDPR1(regD reg) %{ 5223 predicate( UseSSE < 2 ); 5224 constraint(ALLOC_IN_RC(dbl_notreg0)); 5225 match(reg); 5226 format %{ %} 5227 interface(REG_INTER); 5228%} 5229 5230// XMM Double register operands 5231operand regXD() %{ 5232 predicate( UseSSE>=2 ); 5233 constraint(ALLOC_IN_RC(xdb_reg)); 5234 match(RegD); 5235 match(regXD6); 5236 match(regXD7); 5237 format %{ %} 5238 interface(REG_INTER); 5239%} 5240 5241// XMM6 double register operands 5242operand regXD6(regXD reg) %{ 5243 predicate( UseSSE>=2 ); 5244 constraint(ALLOC_IN_RC(xdb_reg6)); 5245 match(reg); 5246 format %{ "XMM6" %} 5247 interface(REG_INTER); 5248%} 5249 5250// XMM7 double register operands 5251operand regXD7(regXD reg) %{ 5252 predicate( UseSSE>=2 ); 5253 constraint(ALLOC_IN_RC(xdb_reg7)); 5254 match(reg); 5255 format %{ "XMM7" %} 5256 interface(REG_INTER); 5257%} 5258 5259// Float register operands 5260operand regF() %{ 5261 predicate( UseSSE < 2 ); 5262 constraint(ALLOC_IN_RC(flt_reg)); 5263 match(RegF); 5264 match(regFPR1); 5265 format %{ %} 5266 interface(REG_INTER); 5267%} 5268 5269// Float register operands 5270operand regFPR1(regF reg) %{ 5271 predicate( UseSSE < 2 ); 5272 constraint(ALLOC_IN_RC(flt_reg0)); 5273 match(reg); 5274 format %{ "FPR1" %} 5275 interface(REG_INTER); 5276%} 5277 5278// XMM register operands 5279operand regX() %{ 5280 predicate( UseSSE>=1 ); 5281 constraint(ALLOC_IN_RC(xmm_reg)); 5282 match(RegF); 5283 format %{ %} 5284 interface(REG_INTER); 5285%} 5286 5287 5288//----------Memory Operands---------------------------------------------------- 5289// Direct Memory Operand 5290operand direct(immP addr) %{ 5291 match(addr); 5292 5293 format %{ "[$addr]" %} 5294 interface(MEMORY_INTER) %{ 5295 base(0xFFFFFFFF); 5296 index(0x4); 5297 scale(0x0); 5298 disp($addr); 5299 %} 5300%} 5301 5302// Indirect Memory Operand 5303operand indirect(eRegP reg) %{ 5304 constraint(ALLOC_IN_RC(e_reg)); 5305 match(reg); 5306 5307 format %{ "[$reg]" %} 5308 interface(MEMORY_INTER) %{ 5309 base($reg); 5310 index(0x4); 5311 scale(0x0); 5312 disp(0x0); 5313 %} 5314%} 5315 5316// Indirect Memory Plus Short Offset Operand 5317operand indOffset8(eRegP reg, immI8 off) %{ 5318 match(AddP reg off); 5319 5320 format %{ "[$reg + $off]" %} 5321 interface(MEMORY_INTER) %{ 5322 base($reg); 5323 index(0x4); 5324 scale(0x0); 5325 disp($off); 5326 %} 5327%} 5328 5329// Indirect Memory Plus Long Offset Operand 5330operand indOffset32(eRegP reg, immI off) %{ 5331 match(AddP reg off); 5332 5333 format %{ "[$reg + $off]" %} 5334 interface(MEMORY_INTER) %{ 5335 base($reg); 5336 index(0x4); 5337 scale(0x0); 5338 disp($off); 5339 %} 5340%} 5341 5342// Indirect Memory Plus Long Offset Operand 5343operand indOffset32X(eRegI reg, immP off) %{ 5344 match(AddP off reg); 5345 5346 format %{ "[$reg + $off]" %} 5347 interface(MEMORY_INTER) %{ 5348 base($reg); 5349 index(0x4); 5350 scale(0x0); 5351 disp($off); 5352 %} 5353%} 5354 5355// Indirect Memory Plus Index Register Plus Offset Operand 5356operand indIndexOffset(eRegP reg, eRegI ireg, immI off) %{ 5357 match(AddP (AddP reg ireg) off); 5358 5359 op_cost(10); 5360 format %{"[$reg + $off + $ireg]" %} 5361 interface(MEMORY_INTER) %{ 5362 base($reg); 5363 index($ireg); 5364 scale(0x0); 5365 disp($off); 5366 %} 5367%} 5368 5369// Indirect Memory Plus Index Register Plus Offset Operand 5370operand indIndex(eRegP reg, eRegI ireg) %{ 5371 match(AddP reg ireg); 5372 5373 op_cost(10); 5374 format %{"[$reg + $ireg]" %} 5375 interface(MEMORY_INTER) %{ 5376 base($reg); 5377 index($ireg); 5378 scale(0x0); 5379 disp(0x0); 5380 %} 5381%} 5382 5383// // ------------------------------------------------------------------------- 5384// // 486 architecture doesn't support "scale * index + offset" with out a base 5385// // ------------------------------------------------------------------------- 5386// // Scaled Memory Operands 5387// // Indirect Memory Times Scale Plus Offset Operand 5388// operand indScaleOffset(immP off, eRegI ireg, immI2 scale) %{ 5389// match(AddP off (LShiftI ireg scale)); 5390// 5391// op_cost(10); 5392// format %{"[$off + $ireg << $scale]" %} 5393// interface(MEMORY_INTER) %{ 5394// base(0x4); 5395// index($ireg); 5396// scale($scale); 5397// disp($off); 5398// %} 5399// %} 5400 5401// Indirect Memory Times Scale Plus Index Register 5402operand indIndexScale(eRegP reg, eRegI ireg, immI2 scale) %{ 5403 match(AddP reg (LShiftI ireg scale)); 5404 5405 op_cost(10); 5406 format %{"[$reg + $ireg << $scale]" %} 5407 interface(MEMORY_INTER) %{ 5408 base($reg); 5409 index($ireg); 5410 scale($scale); 5411 disp(0x0); 5412 %} 5413%} 5414 5415// Indirect Memory Times Scale Plus Index Register Plus Offset Operand 5416operand indIndexScaleOffset(eRegP reg, immI off, eRegI ireg, immI2 scale) %{ 5417 match(AddP (AddP reg (LShiftI ireg scale)) off); 5418 5419 op_cost(10); 5420 format %{"[$reg + $off + $ireg << $scale]" %} 5421 interface(MEMORY_INTER) %{ 5422 base($reg); 5423 index($ireg); 5424 scale($scale); 5425 disp($off); 5426 %} 5427%} 5428 5429//----------Load Long Memory Operands------------------------------------------ 5430// The load-long idiom will use it's address expression again after loading 5431// the first word of the long. If the load-long destination overlaps with 5432// registers used in the addressing expression, the 2nd half will be loaded 5433// from a clobbered address. Fix this by requiring that load-long use 5434// address registers that do not overlap with the load-long target. 5435 5436// load-long support 5437operand load_long_RegP() %{ 5438 constraint(ALLOC_IN_RC(esi_reg)); 5439 match(RegP); 5440 match(eSIRegP); 5441 op_cost(100); 5442 format %{ %} 5443 interface(REG_INTER); 5444%} 5445 5446// Indirect Memory Operand Long 5447operand load_long_indirect(load_long_RegP reg) %{ 5448 constraint(ALLOC_IN_RC(esi_reg)); 5449 match(reg); 5450 5451 format %{ "[$reg]" %} 5452 interface(MEMORY_INTER) %{ 5453 base($reg); 5454 index(0x4); 5455 scale(0x0); 5456 disp(0x0); 5457 %} 5458%} 5459 5460// Indirect Memory Plus Long Offset Operand 5461operand load_long_indOffset32(load_long_RegP reg, immI off) %{ 5462 match(AddP reg off); 5463 5464 format %{ "[$reg + $off]" %} 5465 interface(MEMORY_INTER) %{ 5466 base($reg); 5467 index(0x4); 5468 scale(0x0); 5469 disp($off); 5470 %} 5471%} 5472 5473opclass load_long_memory(load_long_indirect, load_long_indOffset32); 5474 5475 5476//----------Special Memory Operands-------------------------------------------- 5477// Stack Slot Operand - This operand is used for loading and storing temporary 5478// values on the stack where a match requires a value to 5479// flow through memory. 5480operand stackSlotP(sRegP reg) %{ 5481 constraint(ALLOC_IN_RC(stack_slots)); 5482 // No match rule because this operand is only generated in matching 5483 format %{ "[$reg]" %} 5484 interface(MEMORY_INTER) %{ 5485 base(0x4); // ESP 5486 index(0x4); // No Index 5487 scale(0x0); // No Scale 5488 disp($reg); // Stack Offset 5489 %} 5490%} 5491 5492operand stackSlotI(sRegI reg) %{ 5493 constraint(ALLOC_IN_RC(stack_slots)); 5494 // No match rule because this operand is only generated in matching 5495 format %{ "[$reg]" %} 5496 interface(MEMORY_INTER) %{ 5497 base(0x4); // ESP 5498 index(0x4); // No Index 5499 scale(0x0); // No Scale 5500 disp($reg); // Stack Offset 5501 %} 5502%} 5503 5504operand stackSlotF(sRegF reg) %{ 5505 constraint(ALLOC_IN_RC(stack_slots)); 5506 // No match rule because this operand is only generated in matching 5507 format %{ "[$reg]" %} 5508 interface(MEMORY_INTER) %{ 5509 base(0x4); // ESP 5510 index(0x4); // No Index 5511 scale(0x0); // No Scale 5512 disp($reg); // Stack Offset 5513 %} 5514%} 5515 5516operand stackSlotD(sRegD reg) %{ 5517 constraint(ALLOC_IN_RC(stack_slots)); 5518 // No match rule because this operand is only generated in matching 5519 format %{ "[$reg]" %} 5520 interface(MEMORY_INTER) %{ 5521 base(0x4); // ESP 5522 index(0x4); // No Index 5523 scale(0x0); // No Scale 5524 disp($reg); // Stack Offset 5525 %} 5526%} 5527 5528operand stackSlotL(sRegL reg) %{ 5529 constraint(ALLOC_IN_RC(stack_slots)); 5530 // No match rule because this operand is only generated in matching 5531 format %{ "[$reg]" %} 5532 interface(MEMORY_INTER) %{ 5533 base(0x4); // ESP 5534 index(0x4); // No Index 5535 scale(0x0); // No Scale 5536 disp($reg); // Stack Offset 5537 %} 5538%} 5539 5540//----------Memory Operands - Win95 Implicit Null Variants---------------- 5541// Indirect Memory Operand 5542operand indirect_win95_safe(eRegP_no_EBP reg) 5543%{ 5544 constraint(ALLOC_IN_RC(e_reg)); 5545 match(reg); 5546 5547 op_cost(100); 5548 format %{ "[$reg]" %} 5549 interface(MEMORY_INTER) %{ 5550 base($reg); 5551 index(0x4); 5552 scale(0x0); 5553 disp(0x0); 5554 %} 5555%} 5556 5557// Indirect Memory Plus Short Offset Operand 5558operand indOffset8_win95_safe(eRegP_no_EBP reg, immI8 off) 5559%{ 5560 match(AddP reg off); 5561 5562 op_cost(100); 5563 format %{ "[$reg + $off]" %} 5564 interface(MEMORY_INTER) %{ 5565 base($reg); 5566 index(0x4); 5567 scale(0x0); 5568 disp($off); 5569 %} 5570%} 5571 5572// Indirect Memory Plus Long Offset Operand 5573operand indOffset32_win95_safe(eRegP_no_EBP reg, immI off) 5574%{ 5575 match(AddP reg off); 5576 5577 op_cost(100); 5578 format %{ "[$reg + $off]" %} 5579 interface(MEMORY_INTER) %{ 5580 base($reg); 5581 index(0x4); 5582 scale(0x0); 5583 disp($off); 5584 %} 5585%} 5586 5587// Indirect Memory Plus Index Register Plus Offset Operand 5588operand indIndexOffset_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI off) 5589%{ 5590 match(AddP (AddP reg ireg) off); 5591 5592 op_cost(100); 5593 format %{"[$reg + $off + $ireg]" %} 5594 interface(MEMORY_INTER) %{ 5595 base($reg); 5596 index($ireg); 5597 scale(0x0); 5598 disp($off); 5599 %} 5600%} 5601 5602// Indirect Memory Times Scale Plus Index Register 5603operand indIndexScale_win95_safe(eRegP_no_EBP reg, eRegI ireg, immI2 scale) 5604%{ 5605 match(AddP reg (LShiftI ireg scale)); 5606 5607 op_cost(100); 5608 format %{"[$reg + $ireg << $scale]" %} 5609 interface(MEMORY_INTER) %{ 5610 base($reg); 5611 index($ireg); 5612 scale($scale); 5613 disp(0x0); 5614 %} 5615%} 5616 5617// Indirect Memory Times Scale Plus Index Register Plus Offset Operand 5618operand indIndexScaleOffset_win95_safe(eRegP_no_EBP reg, immI off, eRegI ireg, immI2 scale) 5619%{ 5620 match(AddP (AddP reg (LShiftI ireg scale)) off); 5621 5622 op_cost(100); 5623 format %{"[$reg + $off + $ireg << $scale]" %} 5624 interface(MEMORY_INTER) %{ 5625 base($reg); 5626 index($ireg); 5627 scale($scale); 5628 disp($off); 5629 %} 5630%} 5631 5632//----------Conditional Branch Operands---------------------------------------- 5633// Comparison Op - This is the operation of the comparison, and is limited to 5634// the following set of codes: 5635// L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 5636// 5637// Other attributes of the comparison, such as unsignedness, are specified 5638// by the comparison instruction that sets a condition code flags register. 5639// That result is represented by a flags operand whose subtype is appropriate 5640// to the unsignedness (etc.) of the comparison. 5641// 5642// Later, the instruction which matches both the Comparison Op (a Bool) and 5643// the flags (produced by the Cmp) specifies the coding of the comparison op 5644// by matching a specific subtype of Bool operand below, such as cmpOpU. 5645 5646// Comparision Code 5647operand cmpOp() %{ 5648 match(Bool); 5649 5650 format %{ "" %} 5651 interface(COND_INTER) %{ 5652 equal(0x4); 5653 not_equal(0x5); 5654 less(0xC); 5655 greater_equal(0xD); 5656 less_equal(0xE); 5657 greater(0xF); 5658 %} 5659%} 5660 5661// Comparison Code, unsigned compare. Used by FP also, with 5662// C2 (unordered) turned into GT or LT already. The other bits 5663// C0 and C3 are turned into Carry & Zero flags. 5664operand cmpOpU() %{ 5665 match(Bool); 5666 5667 format %{ "" %} 5668 interface(COND_INTER) %{ 5669 equal(0x4); 5670 not_equal(0x5); 5671 less(0x2); 5672 greater_equal(0x3); 5673 less_equal(0x6); 5674 greater(0x7); 5675 %} 5676%} 5677 5678// Comparison Code for FP conditional move 5679operand cmpOp_fcmov() %{ 5680 match(Bool); 5681 5682 format %{ "" %} 5683 interface(COND_INTER) %{ 5684 equal (0x0C8); 5685 not_equal (0x1C8); 5686 less (0x0C0); 5687 greater_equal(0x1C0); 5688 less_equal (0x0D0); 5689 greater (0x1D0); 5690 %} 5691%} 5692 5693// Comparision Code used in long compares 5694operand cmpOp_commute() %{ 5695 match(Bool); 5696 5697 format %{ "" %} 5698 interface(COND_INTER) %{ 5699 equal(0x4); 5700 not_equal(0x5); 5701 less(0xF); 5702 greater_equal(0xE); 5703 less_equal(0xD); 5704 greater(0xC); 5705 %} 5706%} 5707 5708//----------OPERAND CLASSES---------------------------------------------------- 5709// Operand Classes are groups of operands that are used as to simplify 5710// instruction definitions by not requiring the AD writer to specify seperate 5711// instructions for every form of operand when the instruction accepts 5712// multiple operand types with the same basic encoding and format. The classic 5713// case of this is memory operands. 5714 5715opclass memory(direct, indirect, indOffset8, indOffset32, indOffset32X, indIndexOffset, 5716 indIndex, indIndexScale, indIndexScaleOffset); 5717 5718// Long memory operations are encoded in 2 instructions and a +4 offset. 5719// This means some kind of offset is always required and you cannot use 5720// an oop as the offset (done when working on static globals). 5721opclass long_memory(direct, indirect, indOffset8, indOffset32, indIndexOffset, 5722 indIndex, indIndexScale, indIndexScaleOffset); 5723 5724 5725//----------PIPELINE----------------------------------------------------------- 5726// Rules which define the behavior of the target architectures pipeline. 5727pipeline %{ 5728 5729//----------ATTRIBUTES--------------------------------------------------------- 5730attributes %{ 5731 variable_size_instructions; // Fixed size instructions 5732 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle 5733 instruction_unit_size = 1; // An instruction is 1 bytes long 5734 instruction_fetch_unit_size = 16; // The processor fetches one line 5735 instruction_fetch_units = 1; // of 16 bytes 5736 5737 // List of nop instructions 5738 nops( MachNop ); 5739%} 5740 5741//----------RESOURCES---------------------------------------------------------- 5742// Resources are the functional units available to the machine 5743 5744// Generic P2/P3 pipeline 5745// 3 decoders, only D0 handles big operands; a "bundle" is the limit of 5746// 3 instructions decoded per cycle. 5747// 2 load/store ops per cycle, 1 branch, 1 FPU, 5748// 2 ALU op, only ALU0 handles mul/div instructions. 5749resources( D0, D1, D2, DECODE = D0 | D1 | D2, 5750 MS0, MS1, MEM = MS0 | MS1, 5751 BR, FPU, 5752 ALU0, ALU1, ALU = ALU0 | ALU1 ); 5753 5754//----------PIPELINE DESCRIPTION----------------------------------------------- 5755// Pipeline Description specifies the stages in the machine's pipeline 5756 5757// Generic P2/P3 pipeline 5758pipe_desc(S0, S1, S2, S3, S4, S5); 5759 5760//----------PIPELINE CLASSES--------------------------------------------------- 5761// Pipeline Classes describe the stages in which input and output are 5762// referenced by the hardware pipeline. 5763 5764// Naming convention: ialu or fpu 5765// Then: _reg 5766// Then: _reg if there is a 2nd register 5767// Then: _long if it's a pair of instructions implementing a long 5768// Then: _fat if it requires the big decoder 5769// Or: _mem if it requires the big decoder and a memory unit. 5770 5771// Integer ALU reg operation 5772pipe_class ialu_reg(eRegI dst) %{ 5773 single_instruction; 5774 dst : S4(write); 5775 dst : S3(read); 5776 DECODE : S0; // any decoder 5777 ALU : S3; // any alu 5778%} 5779 5780// Long ALU reg operation 5781pipe_class ialu_reg_long(eRegL dst) %{ 5782 instruction_count(2); 5783 dst : S4(write); 5784 dst : S3(read); 5785 DECODE : S0(2); // any 2 decoders 5786 ALU : S3(2); // both alus 5787%} 5788 5789// Integer ALU reg operation using big decoder 5790pipe_class ialu_reg_fat(eRegI dst) %{ 5791 single_instruction; 5792 dst : S4(write); 5793 dst : S3(read); 5794 D0 : S0; // big decoder only 5795 ALU : S3; // any alu 5796%} 5797 5798// Long ALU reg operation using big decoder 5799pipe_class ialu_reg_long_fat(eRegL dst) %{ 5800 instruction_count(2); 5801 dst : S4(write); 5802 dst : S3(read); 5803 D0 : S0(2); // big decoder only; twice 5804 ALU : S3(2); // any 2 alus 5805%} 5806 5807// Integer ALU reg-reg operation 5808pipe_class ialu_reg_reg(eRegI dst, eRegI src) %{ 5809 single_instruction; 5810 dst : S4(write); 5811 src : S3(read); 5812 DECODE : S0; // any decoder 5813 ALU : S3; // any alu 5814%} 5815 5816// Long ALU reg-reg operation 5817pipe_class ialu_reg_reg_long(eRegL dst, eRegL src) %{ 5818 instruction_count(2); 5819 dst : S4(write); 5820 src : S3(read); 5821 DECODE : S0(2); // any 2 decoders 5822 ALU : S3(2); // both alus 5823%} 5824 5825// Integer ALU reg-reg operation 5826pipe_class ialu_reg_reg_fat(eRegI dst, memory src) %{ 5827 single_instruction; 5828 dst : S4(write); 5829 src : S3(read); 5830 D0 : S0; // big decoder only 5831 ALU : S3; // any alu 5832%} 5833 5834// Long ALU reg-reg operation 5835pipe_class ialu_reg_reg_long_fat(eRegL dst, eRegL src) %{ 5836 instruction_count(2); 5837 dst : S4(write); 5838 src : S3(read); 5839 D0 : S0(2); // big decoder only; twice 5840 ALU : S3(2); // both alus 5841%} 5842 5843// Integer ALU reg-mem operation 5844pipe_class ialu_reg_mem(eRegI dst, memory mem) %{ 5845 single_instruction; 5846 dst : S5(write); 5847 mem : S3(read); 5848 D0 : S0; // big decoder only 5849 ALU : S4; // any alu 5850 MEM : S3; // any mem 5851%} 5852 5853// Long ALU reg-mem operation 5854pipe_class ialu_reg_long_mem(eRegL dst, load_long_memory mem) %{ 5855 instruction_count(2); 5856 dst : S5(write); 5857 mem : S3(read); 5858 D0 : S0(2); // big decoder only; twice 5859 ALU : S4(2); // any 2 alus 5860 MEM : S3(2); // both mems 5861%} 5862 5863// Integer mem operation (prefetch) 5864pipe_class ialu_mem(memory mem) 5865%{ 5866 single_instruction; 5867 mem : S3(read); 5868 D0 : S0; // big decoder only 5869 MEM : S3; // any mem 5870%} 5871 5872// Integer Store to Memory 5873pipe_class ialu_mem_reg(memory mem, eRegI src) %{ 5874 single_instruction; 5875 mem : S3(read); 5876 src : S5(read); 5877 D0 : S0; // big decoder only 5878 ALU : S4; // any alu 5879 MEM : S3; 5880%} 5881 5882// Long Store to Memory 5883pipe_class ialu_mem_long_reg(memory mem, eRegL src) %{ 5884 instruction_count(2); 5885 mem : S3(read); 5886 src : S5(read); 5887 D0 : S0(2); // big decoder only; twice 5888 ALU : S4(2); // any 2 alus 5889 MEM : S3(2); // Both mems 5890%} 5891 5892// Integer Store to Memory 5893pipe_class ialu_mem_imm(memory mem) %{ 5894 single_instruction; 5895 mem : S3(read); 5896 D0 : S0; // big decoder only 5897 ALU : S4; // any alu 5898 MEM : S3; 5899%} 5900 5901// Integer ALU0 reg-reg operation 5902pipe_class ialu_reg_reg_alu0(eRegI dst, eRegI src) %{ 5903 single_instruction; 5904 dst : S4(write); 5905 src : S3(read); 5906 D0 : S0; // Big decoder only 5907 ALU0 : S3; // only alu0 5908%} 5909 5910// Integer ALU0 reg-mem operation 5911pipe_class ialu_reg_mem_alu0(eRegI dst, memory mem) %{ 5912 single_instruction; 5913 dst : S5(write); 5914 mem : S3(read); 5915 D0 : S0; // big decoder only 5916 ALU0 : S4; // ALU0 only 5917 MEM : S3; // any mem 5918%} 5919 5920// Integer ALU reg-reg operation 5921pipe_class ialu_cr_reg_reg(eFlagsReg cr, eRegI src1, eRegI src2) %{ 5922 single_instruction; 5923 cr : S4(write); 5924 src1 : S3(read); 5925 src2 : S3(read); 5926 DECODE : S0; // any decoder 5927 ALU : S3; // any alu 5928%} 5929 5930// Integer ALU reg-imm operation 5931pipe_class ialu_cr_reg_imm(eFlagsReg cr, eRegI src1) %{ 5932 single_instruction; 5933 cr : S4(write); 5934 src1 : S3(read); 5935 DECODE : S0; // any decoder 5936 ALU : S3; // any alu 5937%} 5938 5939// Integer ALU reg-mem operation 5940pipe_class ialu_cr_reg_mem(eFlagsReg cr, eRegI src1, memory src2) %{ 5941 single_instruction; 5942 cr : S4(write); 5943 src1 : S3(read); 5944 src2 : S3(read); 5945 D0 : S0; // big decoder only 5946 ALU : S4; // any alu 5947 MEM : S3; 5948%} 5949 5950// Conditional move reg-reg 5951pipe_class pipe_cmplt( eRegI p, eRegI q, eRegI y ) %{ 5952 instruction_count(4); 5953 y : S4(read); 5954 q : S3(read); 5955 p : S3(read); 5956 DECODE : S0(4); // any decoder 5957%} 5958 5959// Conditional move reg-reg 5960pipe_class pipe_cmov_reg( eRegI dst, eRegI src, eFlagsReg cr ) %{ 5961 single_instruction; 5962 dst : S4(write); 5963 src : S3(read); 5964 cr : S3(read); 5965 DECODE : S0; // any decoder 5966%} 5967 5968// Conditional move reg-mem 5969pipe_class pipe_cmov_mem( eFlagsReg cr, eRegI dst, memory src) %{ 5970 single_instruction; 5971 dst : S4(write); 5972 src : S3(read); 5973 cr : S3(read); 5974 DECODE : S0; // any decoder 5975 MEM : S3; 5976%} 5977 5978// Conditional move reg-reg long 5979pipe_class pipe_cmov_reg_long( eFlagsReg cr, eRegL dst, eRegL src) %{ 5980 single_instruction; 5981 dst : S4(write); 5982 src : S3(read); 5983 cr : S3(read); 5984 DECODE : S0(2); // any 2 decoders 5985%} 5986 5987// Conditional move double reg-reg 5988pipe_class pipe_cmovD_reg( eFlagsReg cr, regDPR1 dst, regD src) %{ 5989 single_instruction; 5990 dst : S4(write); 5991 src : S3(read); 5992 cr : S3(read); 5993 DECODE : S0; // any decoder 5994%} 5995 5996// Float reg-reg operation 5997pipe_class fpu_reg(regD dst) %{ 5998 instruction_count(2); 5999 dst : S3(read); 6000 DECODE : S0(2); // any 2 decoders 6001 FPU : S3; 6002%} 6003 6004// Float reg-reg operation 6005pipe_class fpu_reg_reg(regD dst, regD src) %{ 6006 instruction_count(2); 6007 dst : S4(write); 6008 src : S3(read); 6009 DECODE : S0(2); // any 2 decoders 6010 FPU : S3; 6011%} 6012 6013// Float reg-reg operation 6014pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2) %{ 6015 instruction_count(3); 6016 dst : S4(write); 6017 src1 : S3(read); 6018 src2 : S3(read); 6019 DECODE : S0(3); // any 3 decoders 6020 FPU : S3(2); 6021%} 6022 6023// Float reg-reg operation 6024pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3) %{ 6025 instruction_count(4); 6026 dst : S4(write); 6027 src1 : S3(read); 6028 src2 : S3(read); 6029 src3 : S3(read); 6030 DECODE : S0(4); // any 3 decoders 6031 FPU : S3(2); 6032%} 6033 6034// Float reg-reg operation 6035pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3) %{ 6036 instruction_count(4); 6037 dst : S4(write); 6038 src1 : S3(read); 6039 src2 : S3(read); 6040 src3 : S3(read); 6041 DECODE : S1(3); // any 3 decoders 6042 D0 : S0; // Big decoder only 6043 FPU : S3(2); 6044 MEM : S3; 6045%} 6046 6047// Float reg-mem operation 6048pipe_class fpu_reg_mem(regD dst, memory mem) %{ 6049 instruction_count(2); 6050 dst : S5(write); 6051 mem : S3(read); 6052 D0 : S0; // big decoder only 6053 DECODE : S1; // any decoder for FPU POP 6054 FPU : S4; 6055 MEM : S3; // any mem 6056%} 6057 6058// Float reg-mem operation 6059pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem) %{ 6060 instruction_count(3); 6061 dst : S5(write); 6062 src1 : S3(read); 6063 mem : S3(read); 6064 D0 : S0; // big decoder only 6065 DECODE : S1(2); // any decoder for FPU POP 6066 FPU : S4; 6067 MEM : S3; // any mem 6068%} 6069 6070// Float mem-reg operation 6071pipe_class fpu_mem_reg(memory mem, regD src) %{ 6072 instruction_count(2); 6073 src : S5(read); 6074 mem : S3(read); 6075 DECODE : S0; // any decoder for FPU PUSH 6076 D0 : S1; // big decoder only 6077 FPU : S4; 6078 MEM : S3; // any mem 6079%} 6080 6081pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2) %{ 6082 instruction_count(3); 6083 src1 : S3(read); 6084 src2 : S3(read); 6085 mem : S3(read); 6086 DECODE : S0(2); // any decoder for FPU PUSH 6087 D0 : S1; // big decoder only 6088 FPU : S4; 6089 MEM : S3; // any mem 6090%} 6091 6092pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2) %{ 6093 instruction_count(3); 6094 src1 : S3(read); 6095 src2 : S3(read); 6096 mem : S4(read); 6097 DECODE : S0; // any decoder for FPU PUSH 6098 D0 : S0(2); // big decoder only 6099 FPU : S4; 6100 MEM : S3(2); // any mem 6101%} 6102 6103pipe_class fpu_mem_mem(memory dst, memory src1) %{ 6104 instruction_count(2); 6105 src1 : S3(read); 6106 dst : S4(read); 6107 D0 : S0(2); // big decoder only 6108 MEM : S3(2); // any mem 6109%} 6110 6111pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2) %{ 6112 instruction_count(3); 6113 src1 : S3(read); 6114 src2 : S3(read); 6115 dst : S4(read); 6116 D0 : S0(3); // big decoder only 6117 FPU : S4; 6118 MEM : S3(3); // any mem 6119%} 6120 6121pipe_class fpu_mem_reg_con(memory mem, regD src1) %{ 6122 instruction_count(3); 6123 src1 : S4(read); 6124 mem : S4(read); 6125 DECODE : S0; // any decoder for FPU PUSH 6126 D0 : S0(2); // big decoder only 6127 FPU : S4; 6128 MEM : S3(2); // any mem 6129%} 6130 6131// Float load constant 6132pipe_class fpu_reg_con(regD dst) %{ 6133 instruction_count(2); 6134 dst : S5(write); 6135 D0 : S0; // big decoder only for the load 6136 DECODE : S1; // any decoder for FPU POP 6137 FPU : S4; 6138 MEM : S3; // any mem 6139%} 6140 6141// Float load constant 6142pipe_class fpu_reg_reg_con(regD dst, regD src) %{ 6143 instruction_count(3); 6144 dst : S5(write); 6145 src : S3(read); 6146 D0 : S0; // big decoder only for the load 6147 DECODE : S1(2); // any decoder for FPU POP 6148 FPU : S4; 6149 MEM : S3; // any mem 6150%} 6151 6152// UnConditional branch 6153pipe_class pipe_jmp( label labl ) %{ 6154 single_instruction; 6155 BR : S3; 6156%} 6157 6158// Conditional branch 6159pipe_class pipe_jcc( cmpOp cmp, eFlagsReg cr, label labl ) %{ 6160 single_instruction; 6161 cr : S1(read); 6162 BR : S3; 6163%} 6164 6165// Allocation idiom 6166pipe_class pipe_cmpxchg( eRegP dst, eRegP heap_ptr ) %{ 6167 instruction_count(1); force_serialization; 6168 fixed_latency(6); 6169 heap_ptr : S3(read); 6170 DECODE : S0(3); 6171 D0 : S2; 6172 MEM : S3; 6173 ALU : S3(2); 6174 dst : S5(write); 6175 BR : S5; 6176%} 6177 6178// Generic big/slow expanded idiom 6179pipe_class pipe_slow( ) %{ 6180 instruction_count(10); multiple_bundles; force_serialization; 6181 fixed_latency(100); 6182 D0 : S0(2); 6183 MEM : S3(2); 6184%} 6185 6186// The real do-nothing guy 6187pipe_class empty( ) %{ 6188 instruction_count(0); 6189%} 6190 6191// Define the class for the Nop node 6192define %{ 6193 MachNop = empty; 6194%} 6195 6196%} 6197 6198//----------INSTRUCTIONS------------------------------------------------------- 6199// 6200// match -- States which machine-independent subtree may be replaced 6201// by this instruction. 6202// ins_cost -- The estimated cost of this instruction is used by instruction 6203// selection to identify a minimum cost tree of machine 6204// instructions that matches a tree of machine-independent 6205// instructions. 6206// format -- A string providing the disassembly for this instruction. 6207// The value of an instruction's operand may be inserted 6208// by referring to it with a '$' prefix. 6209// opcode -- Three instruction opcodes may be provided. These are referred 6210// to within an encode class as $primary, $secondary, and $tertiary 6211// respectively. The primary opcode is commonly used to 6212// indicate the type of machine instruction, while secondary 6213// and tertiary are often used for prefix options or addressing 6214// modes. 6215// ins_encode -- A list of encode classes with parameters. The encode class 6216// name must have been defined in an 'enc_class' specification 6217// in the encode section of the architecture description. 6218 6219//----------BSWAP-Instruction-------------------------------------------------- 6220instruct bytes_reverse_int(eRegI dst) %{ 6221 match(Set dst (ReverseBytesI dst)); 6222 6223 format %{ "BSWAP $dst" %} 6224 opcode(0x0F, 0xC8); 6225 ins_encode( OpcP, OpcSReg(dst) ); 6226 ins_pipe( ialu_reg ); 6227%} 6228 6229instruct bytes_reverse_long(eRegL dst) %{ 6230 match(Set dst (ReverseBytesL dst)); 6231 6232 format %{ "BSWAP $dst.lo\n\t" 6233 "BSWAP $dst.hi\n\t" 6234 "XCHG $dst.lo $dst.hi" %} 6235 6236 ins_cost(125); 6237 ins_encode( bswap_long_bytes(dst) ); 6238 ins_pipe( ialu_reg_reg); 6239%} 6240 6241 6242//----------Load/Store/Move Instructions--------------------------------------- 6243//----------Load Instructions-------------------------------------------------- 6244// Load Byte (8bit signed) 6245instruct loadB(xRegI dst, memory mem) %{ 6246 match(Set dst (LoadB mem)); 6247 6248 ins_cost(125); 6249 format %{ "MOVSX8 $dst,$mem" %} 6250 opcode(0xBE, 0x0F); 6251 ins_encode( OpcS, OpcP, RegMem(dst,mem)); 6252 ins_pipe( ialu_reg_mem ); 6253%} 6254 6255// Load Byte (8bit UNsigned) 6256instruct loadUB(xRegI dst, memory mem, immI_255 bytemask) %{ 6257 match(Set dst (AndI (LoadB mem) bytemask)); 6258 6259 ins_cost(125); 6260 format %{ "MOVZX8 $dst,$mem" %} 6261 opcode(0xB6, 0x0F); 6262 ins_encode( OpcS, OpcP, RegMem(dst,mem)); 6263 ins_pipe( ialu_reg_mem ); 6264%} 6265 6266// Load Char (16bit unsigned) 6267instruct loadC(eRegI dst, memory mem) %{ 6268 match(Set dst (LoadC mem)); 6269 6270 ins_cost(125); 6271 format %{ "MOVZX $dst,$mem" %} 6272 opcode(0xB7, 0x0F); 6273 ins_encode( OpcS, OpcP, RegMem(dst,mem)); 6274 ins_pipe( ialu_reg_mem ); 6275%} 6276 6277// Load Integer 6278instruct loadI(eRegI dst, memory mem) %{ 6279 match(Set dst (LoadI mem)); 6280 6281 ins_cost(125); 6282 format %{ "MOV $dst,$mem" %} 6283 opcode(0x8B); 6284 ins_encode( OpcP, RegMem(dst,mem)); 6285 ins_pipe( ialu_reg_mem ); 6286%} 6287 6288// Load Long. Cannot clobber address while loading, so restrict address 6289// register to ESI 6290instruct loadL(eRegL dst, load_long_memory mem) %{ 6291 predicate(!((LoadLNode*)n)->require_atomic_access()); 6292 match(Set dst (LoadL mem)); 6293 6294 ins_cost(250); 6295 format %{ "MOV $dst.lo,$mem\n\t" 6296 "MOV $dst.hi,$mem+4" %} 6297 opcode(0x8B, 0x8B); 6298 ins_encode( OpcP, RegMem(dst,mem), OpcS, RegMem_Hi(dst,mem)); 6299 ins_pipe( ialu_reg_long_mem ); 6300%} 6301 6302// Volatile Load Long. Must be atomic, so do 64-bit FILD 6303// then store it down to the stack and reload on the int 6304// side. 6305instruct loadL_volatile(stackSlotL dst, memory mem) %{ 6306 predicate(UseSSE<=1 && ((LoadLNode*)n)->require_atomic_access()); 6307 match(Set dst (LoadL mem)); 6308 6309 ins_cost(200); 6310 format %{ "FILD $mem\t# Atomic volatile long load\n\t" 6311 "FISTp $dst" %} 6312 ins_encode(enc_loadL_volatile(mem,dst)); 6313 ins_pipe( fpu_reg_mem ); 6314%} 6315 6316instruct loadLX_volatile(stackSlotL dst, memory mem, regXD tmp) %{ 6317 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); 6318 match(Set dst (LoadL mem)); 6319 effect(TEMP tmp); 6320 ins_cost(180); 6321 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 6322 "MOVSD $dst,$tmp" %} 6323 ins_encode(enc_loadLX_volatile(mem, dst, tmp)); 6324 ins_pipe( pipe_slow ); 6325%} 6326 6327instruct loadLX_reg_volatile(eRegL dst, memory mem, regXD tmp) %{ 6328 predicate(UseSSE>=2 && ((LoadLNode*)n)->require_atomic_access()); 6329 match(Set dst (LoadL mem)); 6330 effect(TEMP tmp); 6331 ins_cost(160); 6332 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 6333 "MOVD $dst.lo,$tmp\n\t" 6334 "PSRLQ $tmp,32\n\t" 6335 "MOVD $dst.hi,$tmp" %} 6336 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp)); 6337 ins_pipe( pipe_slow ); 6338%} 6339 6340// Load Range 6341instruct loadRange(eRegI dst, memory mem) %{ 6342 match(Set dst (LoadRange mem)); 6343 6344 ins_cost(125); 6345 format %{ "MOV $dst,$mem" %} 6346 opcode(0x8B); 6347 ins_encode( OpcP, RegMem(dst,mem)); 6348 ins_pipe( ialu_reg_mem ); 6349%} 6350 6351 6352// Load Pointer 6353instruct loadP(eRegP dst, memory mem) %{ 6354 match(Set dst (LoadP mem)); 6355 6356 ins_cost(125); 6357 format %{ "MOV $dst,$mem" %} 6358 opcode(0x8B); 6359 ins_encode( OpcP, RegMem(dst,mem)); 6360 ins_pipe( ialu_reg_mem ); 6361%} 6362 6363// Load Klass Pointer 6364instruct loadKlass(eRegP dst, memory mem) %{ 6365 match(Set dst (LoadKlass mem)); 6366 6367 ins_cost(125); 6368 format %{ "MOV $dst,$mem" %} 6369 opcode(0x8B); 6370 ins_encode( OpcP, RegMem(dst,mem)); 6371 ins_pipe( ialu_reg_mem ); 6372%} 6373 6374// Load Short (16bit signed) 6375instruct loadS(eRegI dst, memory mem) %{ 6376 match(Set dst (LoadS mem)); 6377 6378 ins_cost(125); 6379 format %{ "MOVSX $dst,$mem" %} 6380 opcode(0xBF, 0x0F); 6381 ins_encode( OpcS, OpcP, RegMem(dst,mem)); 6382 ins_pipe( ialu_reg_mem ); 6383%} 6384 6385// Load Double 6386instruct loadD(regD dst, memory mem) %{ 6387 predicate(UseSSE<=1); 6388 match(Set dst (LoadD mem)); 6389 6390 ins_cost(150); 6391 format %{ "FLD_D ST,$mem\n\t" 6392 "FSTP $dst" %} 6393 opcode(0xDD); /* DD /0 */ 6394 ins_encode( OpcP, RMopc_Mem(0x00,mem), 6395 Pop_Reg_D(dst) ); 6396 ins_pipe( fpu_reg_mem ); 6397%} 6398 6399// Load Double to XMM 6400instruct loadXD(regXD dst, memory mem) %{ 6401 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); 6402 match(Set dst (LoadD mem)); 6403 ins_cost(145); 6404 format %{ "MOVSD $dst,$mem" %} 6405 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem)); 6406 ins_pipe( pipe_slow ); 6407%} 6408 6409instruct loadXD_partial(regXD dst, memory mem) %{ 6410 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); 6411 match(Set dst (LoadD mem)); 6412 ins_cost(145); 6413 format %{ "MOVLPD $dst,$mem" %} 6414 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,mem)); 6415 ins_pipe( pipe_slow ); 6416%} 6417 6418// Load to XMM register (single-precision floating point) 6419// MOVSS instruction 6420instruct loadX(regX dst, memory mem) %{ 6421 predicate(UseSSE>=1); 6422 match(Set dst (LoadF mem)); 6423 ins_cost(145); 6424 format %{ "MOVSS $dst,$mem" %} 6425 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,mem)); 6426 ins_pipe( pipe_slow ); 6427%} 6428 6429// Load Float 6430instruct loadF(regF dst, memory mem) %{ 6431 predicate(UseSSE==0); 6432 match(Set dst (LoadF mem)); 6433 6434 ins_cost(150); 6435 format %{ "FLD_S ST,$mem\n\t" 6436 "FSTP $dst" %} 6437 opcode(0xD9); /* D9 /0 */ 6438 ins_encode( OpcP, RMopc_Mem(0x00,mem), 6439 Pop_Reg_F(dst) ); 6440 ins_pipe( fpu_reg_mem ); 6441%} 6442 6443// Load Aligned Packed Byte to XMM register 6444instruct loadA8B(regXD dst, memory mem) %{ 6445 predicate(UseSSE>=1); 6446 match(Set dst (Load8B mem)); 6447 ins_cost(125); 6448 format %{ "MOVQ $dst,$mem\t! packed8B" %} 6449 ins_encode( movq_ld(dst, mem)); 6450 ins_pipe( pipe_slow ); 6451%} 6452 6453// Load Aligned Packed Short to XMM register 6454instruct loadA4S(regXD dst, memory mem) %{ 6455 predicate(UseSSE>=1); 6456 match(Set dst (Load4S mem)); 6457 ins_cost(125); 6458 format %{ "MOVQ $dst,$mem\t! packed4S" %} 6459 ins_encode( movq_ld(dst, mem)); 6460 ins_pipe( pipe_slow ); 6461%} 6462 6463// Load Aligned Packed Char to XMM register 6464instruct loadA4C(regXD dst, memory mem) %{ 6465 predicate(UseSSE>=1); 6466 match(Set dst (Load4C mem)); 6467 ins_cost(125); 6468 format %{ "MOVQ $dst,$mem\t! packed4C" %} 6469 ins_encode( movq_ld(dst, mem)); 6470 ins_pipe( pipe_slow ); 6471%} 6472 6473// Load Aligned Packed Integer to XMM register 6474instruct load2IU(regXD dst, memory mem) %{ 6475 predicate(UseSSE>=1); 6476 match(Set dst (Load2I mem)); 6477 ins_cost(125); 6478 format %{ "MOVQ $dst,$mem\t! packed2I" %} 6479 ins_encode( movq_ld(dst, mem)); 6480 ins_pipe( pipe_slow ); 6481%} 6482 6483// Load Aligned Packed Single to XMM 6484instruct loadA2F(regXD dst, memory mem) %{ 6485 predicate(UseSSE>=1); 6486 match(Set dst (Load2F mem)); 6487 ins_cost(145); 6488 format %{ "MOVQ $dst,$mem\t! packed2F" %} 6489 ins_encode( movq_ld(dst, mem)); 6490 ins_pipe( pipe_slow ); 6491%} 6492 6493// Load Effective Address 6494instruct leaP8(eRegP dst, indOffset8 mem) %{ 6495 match(Set dst mem); 6496 6497 ins_cost(110); 6498 format %{ "LEA $dst,$mem" %} 6499 opcode(0x8D); 6500 ins_encode( OpcP, RegMem(dst,mem)); 6501 ins_pipe( ialu_reg_reg_fat ); 6502%} 6503 6504instruct leaP32(eRegP dst, indOffset32 mem) %{ 6505 match(Set dst mem); 6506 6507 ins_cost(110); 6508 format %{ "LEA $dst,$mem" %} 6509 opcode(0x8D); 6510 ins_encode( OpcP, RegMem(dst,mem)); 6511 ins_pipe( ialu_reg_reg_fat ); 6512%} 6513 6514instruct leaPIdxOff(eRegP dst, indIndexOffset mem) %{ 6515 match(Set dst mem); 6516 6517 ins_cost(110); 6518 format %{ "LEA $dst,$mem" %} 6519 opcode(0x8D); 6520 ins_encode( OpcP, RegMem(dst,mem)); 6521 ins_pipe( ialu_reg_reg_fat ); 6522%} 6523 6524instruct leaPIdxScale(eRegP dst, indIndexScale mem) %{ 6525 match(Set dst mem); 6526 6527 ins_cost(110); 6528 format %{ "LEA $dst,$mem" %} 6529 opcode(0x8D); 6530 ins_encode( OpcP, RegMem(dst,mem)); 6531 ins_pipe( ialu_reg_reg_fat ); 6532%} 6533 6534instruct leaPIdxScaleOff(eRegP dst, indIndexScaleOffset mem) %{ 6535 match(Set dst mem); 6536 6537 ins_cost(110); 6538 format %{ "LEA $dst,$mem" %} 6539 opcode(0x8D); 6540 ins_encode( OpcP, RegMem(dst,mem)); 6541 ins_pipe( ialu_reg_reg_fat ); 6542%} 6543 6544// Load Constant 6545instruct loadConI(eRegI dst, immI src) %{ 6546 match(Set dst src); 6547 6548 format %{ "MOV $dst,$src" %} 6549 ins_encode( LdImmI(dst, src) ); 6550 ins_pipe( ialu_reg_fat ); 6551%} 6552 6553// Load Constant zero 6554instruct loadConI0(eRegI dst, immI0 src, eFlagsReg cr) %{ 6555 match(Set dst src); 6556 effect(KILL cr); 6557 6558 ins_cost(50); 6559 format %{ "XOR $dst,$dst" %} 6560 opcode(0x33); /* + rd */ 6561 ins_encode( OpcP, RegReg( dst, dst ) ); 6562 ins_pipe( ialu_reg ); 6563%} 6564 6565instruct loadConP(eRegP dst, immP src) %{ 6566 match(Set dst src); 6567 6568 format %{ "MOV $dst,$src" %} 6569 opcode(0xB8); /* + rd */ 6570 ins_encode( LdImmP(dst, src) ); 6571 ins_pipe( ialu_reg_fat ); 6572%} 6573 6574instruct loadConL(eRegL dst, immL src, eFlagsReg cr) %{ 6575 match(Set dst src); 6576 effect(KILL cr); 6577 ins_cost(200); 6578 format %{ "MOV $dst.lo,$src.lo\n\t" 6579 "MOV $dst.hi,$src.hi" %} 6580 opcode(0xB8); 6581 ins_encode( LdImmL_Lo(dst, src), LdImmL_Hi(dst, src) ); 6582 ins_pipe( ialu_reg_long_fat ); 6583%} 6584 6585instruct loadConL0(eRegL dst, immL0 src, eFlagsReg cr) %{ 6586 match(Set dst src); 6587 effect(KILL cr); 6588 ins_cost(150); 6589 format %{ "XOR $dst.lo,$dst.lo\n\t" 6590 "XOR $dst.hi,$dst.hi" %} 6591 opcode(0x33,0x33); 6592 ins_encode( RegReg_Lo(dst,dst), RegReg_Hi(dst, dst) ); 6593 ins_pipe( ialu_reg_long ); 6594%} 6595 6596// The instruction usage is guarded by predicate in operand immF(). 6597instruct loadConF(regF dst, immF src) %{ 6598 match(Set dst src); 6599 ins_cost(125); 6600 6601 format %{ "FLD_S ST,$src\n\t" 6602 "FSTP $dst" %} 6603 opcode(0xD9, 0x00); /* D9 /0 */ 6604 ins_encode(LdImmF(src), Pop_Reg_F(dst) ); 6605 ins_pipe( fpu_reg_con ); 6606%} 6607 6608// The instruction usage is guarded by predicate in operand immXF(). 6609instruct loadConX(regX dst, immXF con) %{ 6610 match(Set dst con); 6611 ins_cost(125); 6612 format %{ "MOVSS $dst,[$con]" %} 6613 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), LdImmX(dst, con)); 6614 ins_pipe( pipe_slow ); 6615%} 6616 6617// The instruction usage is guarded by predicate in operand immXF0(). 6618instruct loadConX0(regX dst, immXF0 src) %{ 6619 match(Set dst src); 6620 ins_cost(100); 6621 format %{ "XORPS $dst,$dst\t# float 0.0" %} 6622 ins_encode( Opcode(0x0F), Opcode(0x57), RegReg(dst,dst)); 6623 ins_pipe( pipe_slow ); 6624%} 6625 6626// The instruction usage is guarded by predicate in operand immD(). 6627instruct loadConD(regD dst, immD src) %{ 6628 match(Set dst src); 6629 ins_cost(125); 6630 6631 format %{ "FLD_D ST,$src\n\t" 6632 "FSTP $dst" %} 6633 ins_encode(LdImmD(src), Pop_Reg_D(dst) ); 6634 ins_pipe( fpu_reg_con ); 6635%} 6636 6637// The instruction usage is guarded by predicate in operand immXD(). 6638instruct loadConXD(regXD dst, immXD con) %{ 6639 match(Set dst con); 6640 ins_cost(125); 6641 format %{ "MOVSD $dst,[$con]" %} 6642 ins_encode(load_conXD(dst, con)); 6643 ins_pipe( pipe_slow ); 6644%} 6645 6646// The instruction usage is guarded by predicate in operand immXD0(). 6647instruct loadConXD0(regXD dst, immXD0 src) %{ 6648 match(Set dst src); 6649 ins_cost(100); 6650 format %{ "XORPD $dst,$dst\t# double 0.0" %} 6651 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x57), RegReg(dst,dst)); 6652 ins_pipe( pipe_slow ); 6653%} 6654 6655// Load Stack Slot 6656instruct loadSSI(eRegI dst, stackSlotI src) %{ 6657 match(Set dst src); 6658 ins_cost(125); 6659 6660 format %{ "MOV $dst,$src" %} 6661 opcode(0x8B); 6662 ins_encode( OpcP, RegMem(dst,src)); 6663 ins_pipe( ialu_reg_mem ); 6664%} 6665 6666instruct loadSSL(eRegL dst, stackSlotL src) %{ 6667 match(Set dst src); 6668 6669 ins_cost(200); 6670 format %{ "MOV $dst,$src.lo\n\t" 6671 "MOV $dst+4,$src.hi" %} 6672 opcode(0x8B, 0x8B); 6673 ins_encode( OpcP, RegMem( dst, src ), OpcS, RegMem_Hi( dst, src ) ); 6674 ins_pipe( ialu_mem_long_reg ); 6675%} 6676 6677// Load Stack Slot 6678instruct loadSSP(eRegP dst, stackSlotP src) %{ 6679 match(Set dst src); 6680 ins_cost(125); 6681 6682 format %{ "MOV $dst,$src" %} 6683 opcode(0x8B); 6684 ins_encode( OpcP, RegMem(dst,src)); 6685 ins_pipe( ialu_reg_mem ); 6686%} 6687 6688// Load Stack Slot 6689instruct loadSSF(regF dst, stackSlotF src) %{ 6690 match(Set dst src); 6691 ins_cost(125); 6692 6693 format %{ "FLD_S $src\n\t" 6694 "FSTP $dst" %} 6695 opcode(0xD9); /* D9 /0, FLD m32real */ 6696 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 6697 Pop_Reg_F(dst) ); 6698 ins_pipe( fpu_reg_mem ); 6699%} 6700 6701// Load Stack Slot 6702instruct loadSSD(regD dst, stackSlotD src) %{ 6703 match(Set dst src); 6704 ins_cost(125); 6705 6706 format %{ "FLD_D $src\n\t" 6707 "FSTP $dst" %} 6708 opcode(0xDD); /* DD /0, FLD m64real */ 6709 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 6710 Pop_Reg_D(dst) ); 6711 ins_pipe( fpu_reg_mem ); 6712%} 6713 6714// Prefetch instructions. 6715// Must be safe to execute with invalid address (cannot fault). 6716 6717instruct prefetchr0( memory mem ) %{ 6718 predicate(UseSSE==0 && !VM_Version::supports_3dnow()); 6719 match(PrefetchRead mem); 6720 ins_cost(0); 6721 size(0); 6722 format %{ "PREFETCHR (non-SSE is empty encoding)" %} 6723 ins_encode(); 6724 ins_pipe(empty); 6725%} 6726 6727instruct prefetchr( memory mem ) %{ 6728 predicate(UseSSE==0 && VM_Version::supports_3dnow() || ReadPrefetchInstr==3); 6729 match(PrefetchRead mem); 6730 ins_cost(100); 6731 6732 format %{ "PREFETCHR $mem\t! Prefetch into level 1 cache for read" %} 6733 opcode(0x0F, 0x0d); /* Opcode 0F 0d /0 */ 6734 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); 6735 ins_pipe(ialu_mem); 6736%} 6737 6738instruct prefetchrNTA( memory mem ) %{ 6739 predicate(UseSSE>=1 && ReadPrefetchInstr==0); 6740 match(PrefetchRead mem); 6741 ins_cost(100); 6742 6743 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for read" %} 6744 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ 6745 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); 6746 ins_pipe(ialu_mem); 6747%} 6748 6749instruct prefetchrT0( memory mem ) %{ 6750 predicate(UseSSE>=1 && ReadPrefetchInstr==1); 6751 match(PrefetchRead mem); 6752 ins_cost(100); 6753 6754 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for read" %} 6755 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ 6756 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); 6757 ins_pipe(ialu_mem); 6758%} 6759 6760instruct prefetchrT2( memory mem ) %{ 6761 predicate(UseSSE>=1 && ReadPrefetchInstr==2); 6762 match(PrefetchRead mem); 6763 ins_cost(100); 6764 6765 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for read" %} 6766 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ 6767 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); 6768 ins_pipe(ialu_mem); 6769%} 6770 6771instruct prefetchw0( memory mem ) %{ 6772 predicate(UseSSE==0 && !VM_Version::supports_3dnow()); 6773 match(PrefetchWrite mem); 6774 ins_cost(0); 6775 size(0); 6776 format %{ "Prefetch (non-SSE is empty encoding)" %} 6777 ins_encode(); 6778 ins_pipe(empty); 6779%} 6780 6781instruct prefetchw( memory mem ) %{ 6782 predicate(UseSSE==0 && VM_Version::supports_3dnow() || AllocatePrefetchInstr==3); 6783 match( PrefetchWrite mem ); 6784 ins_cost(100); 6785 6786 format %{ "PREFETCHW $mem\t! Prefetch into L1 cache and mark modified" %} 6787 opcode(0x0F, 0x0D); /* Opcode 0F 0D /1 */ 6788 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); 6789 ins_pipe(ialu_mem); 6790%} 6791 6792instruct prefetchwNTA( memory mem ) %{ 6793 predicate(UseSSE>=1 && AllocatePrefetchInstr==0); 6794 match(PrefetchWrite mem); 6795 ins_cost(100); 6796 6797 format %{ "PREFETCHNTA $mem\t! Prefetch into non-temporal cache for write" %} 6798 opcode(0x0F, 0x18); /* Opcode 0F 18 /0 */ 6799 ins_encode(OpcP, OpcS, RMopc_Mem(0x00,mem)); 6800 ins_pipe(ialu_mem); 6801%} 6802 6803instruct prefetchwT0( memory mem ) %{ 6804 predicate(UseSSE>=1 && AllocatePrefetchInstr==1); 6805 match(PrefetchWrite mem); 6806 ins_cost(100); 6807 6808 format %{ "PREFETCHT0 $mem\t! Prefetch into L1 and L2 caches for write" %} 6809 opcode(0x0F, 0x18); /* Opcode 0F 18 /1 */ 6810 ins_encode(OpcP, OpcS, RMopc_Mem(0x01,mem)); 6811 ins_pipe(ialu_mem); 6812%} 6813 6814instruct prefetchwT2( memory mem ) %{ 6815 predicate(UseSSE>=1 && AllocatePrefetchInstr==2); 6816 match(PrefetchWrite mem); 6817 ins_cost(100); 6818 6819 format %{ "PREFETCHT2 $mem\t! Prefetch into L2 cache for write" %} 6820 opcode(0x0F, 0x18); /* Opcode 0F 18 /3 */ 6821 ins_encode(OpcP, OpcS, RMopc_Mem(0x03,mem)); 6822 ins_pipe(ialu_mem); 6823%} 6824 6825//----------Store Instructions------------------------------------------------- 6826 6827// Store Byte 6828instruct storeB(memory mem, xRegI src) %{ 6829 match(Set mem (StoreB mem src)); 6830 6831 ins_cost(125); 6832 format %{ "MOV8 $mem,$src" %} 6833 opcode(0x88); 6834 ins_encode( OpcP, RegMem( src, mem ) ); 6835 ins_pipe( ialu_mem_reg ); 6836%} 6837 6838// Store Char/Short 6839instruct storeC(memory mem, eRegI src) %{ 6840 match(Set mem (StoreC mem src)); 6841 6842 ins_cost(125); 6843 format %{ "MOV16 $mem,$src" %} 6844 opcode(0x89, 0x66); 6845 ins_encode( OpcS, OpcP, RegMem( src, mem ) ); 6846 ins_pipe( ialu_mem_reg ); 6847%} 6848 6849// Store Integer 6850instruct storeI(memory mem, eRegI src) %{ 6851 match(Set mem (StoreI mem src)); 6852 6853 ins_cost(125); 6854 format %{ "MOV $mem,$src" %} 6855 opcode(0x89); 6856 ins_encode( OpcP, RegMem( src, mem ) ); 6857 ins_pipe( ialu_mem_reg ); 6858%} 6859 6860// Store Long 6861instruct storeL(long_memory mem, eRegL src) %{ 6862 predicate(!((StoreLNode*)n)->require_atomic_access()); 6863 match(Set mem (StoreL mem src)); 6864 6865 ins_cost(200); 6866 format %{ "MOV $mem,$src.lo\n\t" 6867 "MOV $mem+4,$src.hi" %} 6868 opcode(0x89, 0x89); 6869 ins_encode( OpcP, RegMem( src, mem ), OpcS, RegMem_Hi( src, mem ) ); 6870 ins_pipe( ialu_mem_long_reg ); 6871%} 6872 6873// Volatile Store Long. Must be atomic, so move it into 6874// the FP TOS and then do a 64-bit FIST. Has to probe the 6875// target address before the store (for null-ptr checks) 6876// so the memory operand is used twice in the encoding. 6877instruct storeL_volatile(memory mem, stackSlotL src, eFlagsReg cr ) %{ 6878 predicate(UseSSE<=1 && ((StoreLNode*)n)->require_atomic_access()); 6879 match(Set mem (StoreL mem src)); 6880 effect( KILL cr ); 6881 ins_cost(400); 6882 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 6883 "FILD $src\n\t" 6884 "FISTp $mem\t # 64-bit atomic volatile long store" %} 6885 opcode(0x3B); 6886 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeL_volatile(mem,src)); 6887 ins_pipe( fpu_reg_mem ); 6888%} 6889 6890instruct storeLX_volatile(memory mem, stackSlotL src, regXD tmp, eFlagsReg cr) %{ 6891 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); 6892 match(Set mem (StoreL mem src)); 6893 effect( TEMP tmp, KILL cr ); 6894 ins_cost(380); 6895 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 6896 "MOVSD $tmp,$src\n\t" 6897 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} 6898 opcode(0x3B); 6899 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_volatile(mem, src, tmp)); 6900 ins_pipe( pipe_slow ); 6901%} 6902 6903instruct storeLX_reg_volatile(memory mem, eRegL src, regXD tmp2, regXD tmp, eFlagsReg cr) %{ 6904 predicate(UseSSE>=2 && ((StoreLNode*)n)->require_atomic_access()); 6905 match(Set mem (StoreL mem src)); 6906 effect( TEMP tmp2 , TEMP tmp, KILL cr ); 6907 ins_cost(360); 6908 format %{ "CMP $mem,EAX\t# Probe address for implicit null check\n\t" 6909 "MOVD $tmp,$src.lo\n\t" 6910 "MOVD $tmp2,$src.hi\n\t" 6911 "PUNPCKLDQ $tmp,$tmp2\n\t" 6912 "MOVSD $mem,$tmp\t # 64-bit atomic volatile long store" %} 6913 opcode(0x3B); 6914 ins_encode( OpcP, RegMem( EAX, mem ), enc_storeLX_reg_volatile(mem, src, tmp, tmp2)); 6915 ins_pipe( pipe_slow ); 6916%} 6917 6918// Store Pointer; for storing unknown oops and raw pointers 6919instruct storeP(memory mem, anyRegP src) %{ 6920 match(Set mem (StoreP mem src)); 6921 6922 ins_cost(125); 6923 format %{ "MOV $mem,$src" %} 6924 opcode(0x89); 6925 ins_encode( OpcP, RegMem( src, mem ) ); 6926 ins_pipe( ialu_mem_reg ); 6927%} 6928 6929// Store Integer Immediate 6930instruct storeImmI(memory mem, immI src) %{ 6931 match(Set mem (StoreI mem src)); 6932 6933 ins_cost(150); 6934 format %{ "MOV $mem,$src" %} 6935 opcode(0xC7); /* C7 /0 */ 6936 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); 6937 ins_pipe( ialu_mem_imm ); 6938%} 6939 6940// Store Short/Char Immediate 6941instruct storeImmI16(memory mem, immI16 src) %{ 6942 predicate(UseStoreImmI16); 6943 match(Set mem (StoreC mem src)); 6944 6945 ins_cost(150); 6946 format %{ "MOV16 $mem,$src" %} 6947 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */ 6948 ins_encode( SizePrefix, OpcP, RMopc_Mem(0x00,mem), Con16( src )); 6949 ins_pipe( ialu_mem_imm ); 6950%} 6951 6952// Store Pointer Immediate; null pointers or constant oops that do not 6953// need card-mark barriers. 6954instruct storeImmP(memory mem, immP src) %{ 6955 match(Set mem (StoreP mem src)); 6956 6957 ins_cost(150); 6958 format %{ "MOV $mem,$src" %} 6959 opcode(0xC7); /* C7 /0 */ 6960 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32( src )); 6961 ins_pipe( ialu_mem_imm ); 6962%} 6963 6964// Store Byte Immediate 6965instruct storeImmB(memory mem, immI8 src) %{ 6966 match(Set mem (StoreB mem src)); 6967 6968 ins_cost(150); 6969 format %{ "MOV8 $mem,$src" %} 6970 opcode(0xC6); /* C6 /0 */ 6971 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); 6972 ins_pipe( ialu_mem_imm ); 6973%} 6974 6975// Store Aligned Packed Byte XMM register to memory 6976instruct storeA8B(memory mem, regXD src) %{ 6977 predicate(UseSSE>=1); 6978 match(Set mem (Store8B mem src)); 6979 ins_cost(145); 6980 format %{ "MOVQ $mem,$src\t! packed8B" %} 6981 ins_encode( movq_st(mem, src)); 6982 ins_pipe( pipe_slow ); 6983%} 6984 6985// Store Aligned Packed Char/Short XMM register to memory 6986instruct storeA4C(memory mem, regXD src) %{ 6987 predicate(UseSSE>=1); 6988 match(Set mem (Store4C mem src)); 6989 ins_cost(145); 6990 format %{ "MOVQ $mem,$src\t! packed4C" %} 6991 ins_encode( movq_st(mem, src)); 6992 ins_pipe( pipe_slow ); 6993%} 6994 6995// Store Aligned Packed Integer XMM register to memory 6996instruct storeA2I(memory mem, regXD src) %{ 6997 predicate(UseSSE>=1); 6998 match(Set mem (Store2I mem src)); 6999 ins_cost(145); 7000 format %{ "MOVQ $mem,$src\t! packed2I" %} 7001 ins_encode( movq_st(mem, src)); 7002 ins_pipe( pipe_slow ); 7003%} 7004 7005// Store CMS card-mark Immediate 7006instruct storeImmCM(memory mem, immI8 src) %{ 7007 match(Set mem (StoreCM mem src)); 7008 7009 ins_cost(150); 7010 format %{ "MOV8 $mem,$src\t! CMS card-mark imm0" %} 7011 opcode(0xC6); /* C6 /0 */ 7012 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con8or32( src )); 7013 ins_pipe( ialu_mem_imm ); 7014%} 7015 7016// Store Double 7017instruct storeD( memory mem, regDPR1 src) %{ 7018 predicate(UseSSE<=1); 7019 match(Set mem (StoreD mem src)); 7020 7021 ins_cost(100); 7022 format %{ "FST_D $mem,$src" %} 7023 opcode(0xDD); /* DD /2 */ 7024 ins_encode( enc_FP_store(mem,src) ); 7025 ins_pipe( fpu_mem_reg ); 7026%} 7027 7028// Store double does rounding on x86 7029instruct storeD_rounded( memory mem, regDPR1 src) %{ 7030 predicate(UseSSE<=1); 7031 match(Set mem (StoreD mem (RoundDouble src))); 7032 7033 ins_cost(100); 7034 format %{ "FST_D $mem,$src\t# round" %} 7035 opcode(0xDD); /* DD /2 */ 7036 ins_encode( enc_FP_store(mem,src) ); 7037 ins_pipe( fpu_mem_reg ); 7038%} 7039 7040// Store XMM register to memory (double-precision floating points) 7041// MOVSD instruction 7042instruct storeXD(memory mem, regXD src) %{ 7043 predicate(UseSSE>=2); 7044 match(Set mem (StoreD mem src)); 7045 ins_cost(95); 7046 format %{ "MOVSD $mem,$src" %} 7047 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src, mem)); 7048 ins_pipe( pipe_slow ); 7049%} 7050 7051// Store XMM register to memory (single-precision floating point) 7052// MOVSS instruction 7053instruct storeX(memory mem, regX src) %{ 7054 predicate(UseSSE>=1); 7055 match(Set mem (StoreF mem src)); 7056 ins_cost(95); 7057 format %{ "MOVSS $mem,$src" %} 7058 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, mem)); 7059 ins_pipe( pipe_slow ); 7060%} 7061 7062// Store Aligned Packed Single Float XMM register to memory 7063instruct storeA2F(memory mem, regXD src) %{ 7064 predicate(UseSSE>=1); 7065 match(Set mem (Store2F mem src)); 7066 ins_cost(145); 7067 format %{ "MOVQ $mem,$src\t! packed2F" %} 7068 ins_encode( movq_st(mem, src)); 7069 ins_pipe( pipe_slow ); 7070%} 7071 7072// Store Float 7073instruct storeF( memory mem, regFPR1 src) %{ 7074 predicate(UseSSE==0); 7075 match(Set mem (StoreF mem src)); 7076 7077 ins_cost(100); 7078 format %{ "FST_S $mem,$src" %} 7079 opcode(0xD9); /* D9 /2 */ 7080 ins_encode( enc_FP_store(mem,src) ); 7081 ins_pipe( fpu_mem_reg ); 7082%} 7083 7084// Store Float does rounding on x86 7085instruct storeF_rounded( memory mem, regFPR1 src) %{ 7086 predicate(UseSSE==0); 7087 match(Set mem (StoreF mem (RoundFloat src))); 7088 7089 ins_cost(100); 7090 format %{ "FST_S $mem,$src\t# round" %} 7091 opcode(0xD9); /* D9 /2 */ 7092 ins_encode( enc_FP_store(mem,src) ); 7093 ins_pipe( fpu_mem_reg ); 7094%} 7095 7096// Store Float does rounding on x86 7097instruct storeF_Drounded( memory mem, regDPR1 src) %{ 7098 predicate(UseSSE<=1); 7099 match(Set mem (StoreF mem (ConvD2F src))); 7100 7101 ins_cost(100); 7102 format %{ "FST_S $mem,$src\t# D-round" %} 7103 opcode(0xD9); /* D9 /2 */ 7104 ins_encode( enc_FP_store(mem,src) ); 7105 ins_pipe( fpu_mem_reg ); 7106%} 7107 7108// Store immediate Float value (it is faster than store from FPU register) 7109// The instruction usage is guarded by predicate in operand immF(). 7110instruct storeF_imm( memory mem, immF src) %{ 7111 match(Set mem (StoreF mem src)); 7112 7113 ins_cost(50); 7114 format %{ "MOV $mem,$src\t# store float" %} 7115 opcode(0xC7); /* C7 /0 */ 7116 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32F_as_bits( src )); 7117 ins_pipe( ialu_mem_imm ); 7118%} 7119 7120// Store immediate Float value (it is faster than store from XMM register) 7121// The instruction usage is guarded by predicate in operand immXF(). 7122instruct storeX_imm( memory mem, immXF src) %{ 7123 match(Set mem (StoreF mem src)); 7124 7125 ins_cost(50); 7126 format %{ "MOV $mem,$src\t# store float" %} 7127 opcode(0xC7); /* C7 /0 */ 7128 ins_encode( OpcP, RMopc_Mem(0x00,mem), Con32XF_as_bits( src )); 7129 ins_pipe( ialu_mem_imm ); 7130%} 7131 7132// Store Integer to stack slot 7133instruct storeSSI(stackSlotI dst, eRegI src) %{ 7134 match(Set dst src); 7135 7136 ins_cost(100); 7137 format %{ "MOV $dst,$src" %} 7138 opcode(0x89); 7139 ins_encode( OpcPRegSS( dst, src ) ); 7140 ins_pipe( ialu_mem_reg ); 7141%} 7142 7143// Store Integer to stack slot 7144instruct storeSSP(stackSlotP dst, eRegP src) %{ 7145 match(Set dst src); 7146 7147 ins_cost(100); 7148 format %{ "MOV $dst,$src" %} 7149 opcode(0x89); 7150 ins_encode( OpcPRegSS( dst, src ) ); 7151 ins_pipe( ialu_mem_reg ); 7152%} 7153 7154// Store Long to stack slot 7155instruct storeSSL(stackSlotL dst, eRegL src) %{ 7156 match(Set dst src); 7157 7158 ins_cost(200); 7159 format %{ "MOV $dst,$src.lo\n\t" 7160 "MOV $dst+4,$src.hi" %} 7161 opcode(0x89, 0x89); 7162 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); 7163 ins_pipe( ialu_mem_long_reg ); 7164%} 7165 7166//----------MemBar Instructions----------------------------------------------- 7167// Memory barrier flavors 7168 7169instruct membar_acquire() %{ 7170 match(MemBarAcquire); 7171 ins_cost(400); 7172 7173 size(0); 7174 format %{ "MEMBAR-acquire" %} 7175 ins_encode( enc_membar_acquire ); 7176 ins_pipe(pipe_slow); 7177%} 7178 7179instruct membar_acquire_lock() %{ 7180 match(MemBarAcquire); 7181 predicate(Matcher::prior_fast_lock(n)); 7182 ins_cost(0); 7183 7184 size(0); 7185 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %} 7186 ins_encode( ); 7187 ins_pipe(empty); 7188%} 7189 7190instruct membar_release() %{ 7191 match(MemBarRelease); 7192 ins_cost(400); 7193 7194 size(0); 7195 format %{ "MEMBAR-release" %} 7196 ins_encode( enc_membar_release ); 7197 ins_pipe(pipe_slow); 7198%} 7199 7200instruct membar_release_lock() %{ 7201 match(MemBarRelease); 7202 predicate(Matcher::post_fast_unlock(n)); 7203 ins_cost(0); 7204 7205 size(0); 7206 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %} 7207 ins_encode( ); 7208 ins_pipe(empty); 7209%} 7210 7211instruct membar_volatile() %{ 7212 match(MemBarVolatile); 7213 ins_cost(400); 7214 7215 format %{ "MEMBAR-volatile" %} 7216 ins_encode( enc_membar_volatile ); 7217 ins_pipe(pipe_slow); 7218%} 7219 7220instruct unnecessary_membar_volatile() %{ 7221 match(MemBarVolatile); 7222 predicate(Matcher::post_store_load_barrier(n)); 7223 ins_cost(0); 7224 7225 size(0); 7226 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %} 7227 ins_encode( ); 7228 ins_pipe(empty); 7229%} 7230 7231//----------Move Instructions-------------------------------------------------- 7232instruct castX2P(eAXRegP dst, eAXRegI src) %{ 7233 match(Set dst (CastX2P src)); 7234 format %{ "# X2P $dst, $src" %} 7235 ins_encode( /*empty encoding*/ ); 7236 ins_cost(0); 7237 ins_pipe(empty); 7238%} 7239 7240instruct castP2X(eRegI dst, eRegP src ) %{ 7241 match(Set dst (CastP2X src)); 7242 ins_cost(50); 7243 format %{ "MOV $dst, $src\t# CastP2X" %} 7244 ins_encode( enc_Copy( dst, src) ); 7245 ins_pipe( ialu_reg_reg ); 7246%} 7247 7248//----------Conditional Move--------------------------------------------------- 7249// Conditional move 7250instruct cmovI_reg(eRegI dst, eRegI src, eFlagsReg cr, cmpOp cop ) %{ 7251 predicate(VM_Version::supports_cmov() ); 7252 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7253 ins_cost(200); 7254 format %{ "CMOV$cop $dst,$src" %} 7255 opcode(0x0F,0x40); 7256 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7257 ins_pipe( pipe_cmov_reg ); 7258%} 7259 7260instruct cmovI_regU( eRegI dst, eRegI src, eFlagsRegU cr, cmpOpU cop ) %{ 7261 predicate(VM_Version::supports_cmov() ); 7262 match(Set dst (CMoveI (Binary cop cr) (Binary dst src))); 7263 ins_cost(200); 7264 format %{ "CMOV$cop $dst,$src" %} 7265 opcode(0x0F,0x40); 7266 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7267 ins_pipe( pipe_cmov_reg ); 7268%} 7269 7270// Conditional move 7271instruct cmovI_mem(cmpOp cop, eFlagsReg cr, eRegI dst, memory src) %{ 7272 predicate(VM_Version::supports_cmov() ); 7273 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 7274 ins_cost(250); 7275 format %{ "CMOV$cop $dst,$src" %} 7276 opcode(0x0F,0x40); 7277 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7278 ins_pipe( pipe_cmov_mem ); 7279%} 7280 7281// Conditional move 7282instruct cmovI_memu(cmpOpU cop, eFlagsRegU cr, eRegI dst, memory src) %{ 7283 predicate(VM_Version::supports_cmov() ); 7284 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src)))); 7285 ins_cost(250); 7286 format %{ "CMOV$cop $dst,$src" %} 7287 opcode(0x0F,0x40); 7288 ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7289 ins_pipe( pipe_cmov_mem ); 7290%} 7291 7292// Conditional move 7293instruct cmovP_reg(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ 7294 predicate(VM_Version::supports_cmov() ); 7295 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7296 ins_cost(200); 7297 format %{ "CMOV$cop $dst,$src\t# ptr" %} 7298 opcode(0x0F,0x40); 7299 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7300 ins_pipe( pipe_cmov_reg ); 7301%} 7302 7303// Conditional move (non-P6 version) 7304// Note: a CMoveP is generated for stubs and native wrappers 7305// regardless of whether we are on a P6, so we 7306// emulate a cmov here 7307instruct cmovP_reg_nonP6(eRegP dst, eRegP src, eFlagsReg cr, cmpOp cop ) %{ 7308 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7309 ins_cost(300); 7310 format %{ "Jn$cop skip\n\t" 7311 "MOV $dst,$src\t# pointer\n" 7312 "skip:" %} 7313 opcode(0x8b); 7314 ins_encode( enc_cmov_branch(cop, 0x2), OpcP, RegReg(dst, src)); 7315 ins_pipe( pipe_cmov_reg ); 7316%} 7317 7318// Conditional move 7319instruct cmovP_regU(eRegP dst, eRegP src, eFlagsRegU cr, cmpOpU cop ) %{ 7320 predicate(VM_Version::supports_cmov() ); 7321 match(Set dst (CMoveP (Binary cop cr) (Binary dst src))); 7322 ins_cost(200); 7323 format %{ "CMOV$cop $dst,$src\t# ptr" %} 7324 opcode(0x0F,0x40); 7325 ins_encode( enc_cmov(cop), RegReg( dst, src ) ); 7326 ins_pipe( pipe_cmov_reg ); 7327%} 7328 7329// DISABLED: Requires the ADLC to emit a bottom_type call that 7330// correctly meets the two pointer arguments; one is an incoming 7331// register but the other is a memory operand. ALSO appears to 7332// be buggy with implicit null checks. 7333// 7334//// Conditional move 7335//instruct cmovP_mem(cmpOp cop, eFlagsReg cr, eRegP dst, memory src) %{ 7336// predicate(VM_Version::supports_cmov() ); 7337// match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); 7338// ins_cost(250); 7339// format %{ "CMOV$cop $dst,$src\t# ptr" %} 7340// opcode(0x0F,0x40); 7341// ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7342// ins_pipe( pipe_cmov_mem ); 7343//%} 7344// 7345//// Conditional move 7346//instruct cmovP_memU(cmpOpU cop, eFlagsRegU cr, eRegP dst, memory src) %{ 7347// predicate(VM_Version::supports_cmov() ); 7348// match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src)))); 7349// ins_cost(250); 7350// format %{ "CMOV$cop $dst,$src\t# ptr" %} 7351// opcode(0x0F,0x40); 7352// ins_encode( enc_cmov(cop), RegMem( dst, src ) ); 7353// ins_pipe( pipe_cmov_mem ); 7354//%} 7355 7356// Conditional move 7357instruct fcmovD_regU(cmpOp_fcmov cop, eFlagsRegU cr, regDPR1 dst, regD src) %{ 7358 predicate(UseSSE<=1); 7359 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7360 ins_cost(200); 7361 format %{ "FCMOV$cop $dst,$src\t# double" %} 7362 opcode(0xDA); 7363 ins_encode( enc_cmov_d(cop,src) ); 7364 ins_pipe( pipe_cmovD_reg ); 7365%} 7366 7367// Conditional move 7368instruct fcmovF_regU(cmpOp_fcmov cop, eFlagsRegU cr, regFPR1 dst, regF src) %{ 7369 predicate(UseSSE==0); 7370 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7371 ins_cost(200); 7372 format %{ "FCMOV$cop $dst,$src\t# float" %} 7373 opcode(0xDA); 7374 ins_encode( enc_cmov_d(cop,src) ); 7375 ins_pipe( pipe_cmovD_reg ); 7376%} 7377 7378// Float CMOV on Intel doesn't handle *signed* compares, only unsigned. 7379instruct fcmovD_regS(cmpOp cop, eFlagsReg cr, regD dst, regD src) %{ 7380 predicate(UseSSE<=1); 7381 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7382 ins_cost(200); 7383 format %{ "Jn$cop skip\n\t" 7384 "MOV $dst,$src\t# double\n" 7385 "skip:" %} 7386 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ 7387 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_D(src), OpcP, RegOpc(dst) ); 7388 ins_pipe( pipe_cmovD_reg ); 7389%} 7390 7391// Float CMOV on Intel doesn't handle *signed* compares, only unsigned. 7392instruct fcmovF_regS(cmpOp cop, eFlagsReg cr, regF dst, regF src) %{ 7393 predicate(UseSSE==0); 7394 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7395 ins_cost(200); 7396 format %{ "Jn$cop skip\n\t" 7397 "MOV $dst,$src\t# float\n" 7398 "skip:" %} 7399 opcode (0xdd, 0x3); /* DD D8+i or DD /3 */ 7400 ins_encode( enc_cmov_branch( cop, 0x4 ), Push_Reg_F(src), OpcP, RegOpc(dst) ); 7401 ins_pipe( pipe_cmovD_reg ); 7402%} 7403 7404// No CMOVE with SSE/SSE2 7405instruct fcmovX_regS(cmpOp cop, eFlagsReg cr, regX dst, regX src) %{ 7406 predicate (UseSSE>=1); 7407 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7408 ins_cost(200); 7409 format %{ "Jn$cop skip\n\t" 7410 "MOVSS $dst,$src\t# float\n" 7411 "skip:" %} 7412 ins_encode %{ 7413 Label skip; 7414 // Invert sense of branch from sense of CMOV 7415 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7416 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 7417 __ bind(skip); 7418 %} 7419 ins_pipe( pipe_slow ); 7420%} 7421 7422// No CMOVE with SSE/SSE2 7423instruct fcmovXD_regS(cmpOp cop, eFlagsReg cr, regXD dst, regXD src) %{ 7424 predicate (UseSSE>=2); 7425 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7426 ins_cost(200); 7427 format %{ "Jn$cop skip\n\t" 7428 "MOVSD $dst,$src\t# float\n" 7429 "skip:" %} 7430 ins_encode %{ 7431 Label skip; 7432 // Invert sense of branch from sense of CMOV 7433 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7434 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 7435 __ bind(skip); 7436 %} 7437 ins_pipe( pipe_slow ); 7438%} 7439 7440// unsigned version 7441instruct fcmovX_regU(cmpOpU cop, eFlagsRegU cr, regX dst, regX src) %{ 7442 predicate (UseSSE>=1); 7443 match(Set dst (CMoveF (Binary cop cr) (Binary dst src))); 7444 ins_cost(200); 7445 format %{ "Jn$cop skip\n\t" 7446 "MOVSS $dst,$src\t# float\n" 7447 "skip:" %} 7448 ins_encode %{ 7449 Label skip; 7450 // Invert sense of branch from sense of CMOV 7451 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7452 __ movflt($dst$$XMMRegister, $src$$XMMRegister); 7453 __ bind(skip); 7454 %} 7455 ins_pipe( pipe_slow ); 7456%} 7457 7458// unsigned version 7459instruct fcmovXD_regU(cmpOpU cop, eFlagsRegU cr, regXD dst, regXD src) %{ 7460 predicate (UseSSE>=2); 7461 match(Set dst (CMoveD (Binary cop cr) (Binary dst src))); 7462 ins_cost(200); 7463 format %{ "Jn$cop skip\n\t" 7464 "MOVSD $dst,$src\t# float\n" 7465 "skip:" %} 7466 ins_encode %{ 7467 Label skip; 7468 // Invert sense of branch from sense of CMOV 7469 __ jccb((Assembler::Condition)($cop$$cmpcode^1), skip); 7470 __ movdbl($dst$$XMMRegister, $src$$XMMRegister); 7471 __ bind(skip); 7472 %} 7473 ins_pipe( pipe_slow ); 7474%} 7475 7476instruct cmovL_reg(cmpOp cop, eFlagsReg cr, eRegL dst, eRegL src) %{ 7477 predicate(VM_Version::supports_cmov() ); 7478 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 7479 ins_cost(200); 7480 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" 7481 "CMOV$cop $dst.hi,$src.hi" %} 7482 opcode(0x0F,0x40); 7483 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); 7484 ins_pipe( pipe_cmov_reg_long ); 7485%} 7486 7487instruct cmovL_regU(cmpOpU cop, eFlagsRegU cr, eRegL dst, eRegL src) %{ 7488 predicate(VM_Version::supports_cmov() ); 7489 match(Set dst (CMoveL (Binary cop cr) (Binary dst src))); 7490 ins_cost(200); 7491 format %{ "CMOV$cop $dst.lo,$src.lo\n\t" 7492 "CMOV$cop $dst.hi,$src.hi" %} 7493 opcode(0x0F,0x40); 7494 ins_encode( enc_cmov(cop), RegReg_Lo2( dst, src ), enc_cmov(cop), RegReg_Hi2( dst, src ) ); 7495 ins_pipe( pipe_cmov_reg_long ); 7496%} 7497 7498//----------Arithmetic Instructions-------------------------------------------- 7499//----------Addition Instructions---------------------------------------------- 7500// Integer Addition Instructions 7501instruct addI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 7502 match(Set dst (AddI dst src)); 7503 effect(KILL cr); 7504 7505 size(2); 7506 format %{ "ADD $dst,$src" %} 7507 opcode(0x03); 7508 ins_encode( OpcP, RegReg( dst, src) ); 7509 ins_pipe( ialu_reg_reg ); 7510%} 7511 7512instruct addI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 7513 match(Set dst (AddI dst src)); 7514 effect(KILL cr); 7515 7516 format %{ "ADD $dst,$src" %} 7517 opcode(0x81, 0x00); /* /0 id */ 7518 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 7519 ins_pipe( ialu_reg ); 7520%} 7521 7522instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 7523 predicate(UseIncDec); 7524 match(Set dst (AddI dst src)); 7525 effect(KILL cr); 7526 7527 size(1); 7528 format %{ "INC $dst" %} 7529 opcode(0x40); /* */ 7530 ins_encode( Opc_plus( primary, dst ) ); 7531 ins_pipe( ialu_reg ); 7532%} 7533 7534instruct leaI_eReg_immI(eRegI dst, eRegI src0, immI src1) %{ 7535 match(Set dst (AddI src0 src1)); 7536 ins_cost(110); 7537 7538 format %{ "LEA $dst,[$src0 + $src1]" %} 7539 opcode(0x8D); /* 0x8D /r */ 7540 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); 7541 ins_pipe( ialu_reg_reg ); 7542%} 7543 7544instruct leaP_eReg_immI(eRegP dst, eRegP src0, immI src1) %{ 7545 match(Set dst (AddP src0 src1)); 7546 ins_cost(110); 7547 7548 format %{ "LEA $dst,[$src0 + $src1]\t# ptr" %} 7549 opcode(0x8D); /* 0x8D /r */ 7550 ins_encode( OpcP, RegLea( dst, src0, src1 ) ); 7551 ins_pipe( ialu_reg_reg ); 7552%} 7553 7554instruct decI_eReg(eRegI dst, immI_M1 src, eFlagsReg cr) %{ 7555 predicate(UseIncDec); 7556 match(Set dst (AddI dst src)); 7557 effect(KILL cr); 7558 7559 size(1); 7560 format %{ "DEC $dst" %} 7561 opcode(0x48); /* */ 7562 ins_encode( Opc_plus( primary, dst ) ); 7563 ins_pipe( ialu_reg ); 7564%} 7565 7566instruct addP_eReg(eRegP dst, eRegI src, eFlagsReg cr) %{ 7567 match(Set dst (AddP dst src)); 7568 effect(KILL cr); 7569 7570 size(2); 7571 format %{ "ADD $dst,$src" %} 7572 opcode(0x03); 7573 ins_encode( OpcP, RegReg( dst, src) ); 7574 ins_pipe( ialu_reg_reg ); 7575%} 7576 7577instruct addP_eReg_imm(eRegP dst, immI src, eFlagsReg cr) %{ 7578 match(Set dst (AddP dst src)); 7579 effect(KILL cr); 7580 7581 format %{ "ADD $dst,$src" %} 7582 opcode(0x81,0x00); /* Opcode 81 /0 id */ 7583 // ins_encode( RegImm( dst, src) ); 7584 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 7585 ins_pipe( ialu_reg ); 7586%} 7587 7588instruct addI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 7589 match(Set dst (AddI dst (LoadI src))); 7590 effect(KILL cr); 7591 7592 ins_cost(125); 7593 format %{ "ADD $dst,$src" %} 7594 opcode(0x03); 7595 ins_encode( OpcP, RegMem( dst, src) ); 7596 ins_pipe( ialu_reg_mem ); 7597%} 7598 7599instruct addI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 7600 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7601 effect(KILL cr); 7602 7603 ins_cost(150); 7604 format %{ "ADD $dst,$src" %} 7605 opcode(0x01); /* Opcode 01 /r */ 7606 ins_encode( OpcP, RegMem( src, dst ) ); 7607 ins_pipe( ialu_mem_reg ); 7608%} 7609 7610// Add Memory with Immediate 7611instruct addI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 7612 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7613 effect(KILL cr); 7614 7615 ins_cost(125); 7616 format %{ "ADD $dst,$src" %} 7617 opcode(0x81); /* Opcode 81 /0 id */ 7618 ins_encode( OpcSE( src ), RMopc_Mem(0x00,dst), Con8or32( src ) ); 7619 ins_pipe( ialu_mem_imm ); 7620%} 7621 7622instruct incI_mem(memory dst, immI1 src, eFlagsReg cr) %{ 7623 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7624 effect(KILL cr); 7625 7626 ins_cost(125); 7627 format %{ "INC $dst" %} 7628 opcode(0xFF); /* Opcode FF /0 */ 7629 ins_encode( OpcP, RMopc_Mem(0x00,dst)); 7630 ins_pipe( ialu_mem_imm ); 7631%} 7632 7633instruct decI_mem(memory dst, immI_M1 src, eFlagsReg cr) %{ 7634 match(Set dst (StoreI dst (AddI (LoadI dst) src))); 7635 effect(KILL cr); 7636 7637 ins_cost(125); 7638 format %{ "DEC $dst" %} 7639 opcode(0xFF); /* Opcode FF /1 */ 7640 ins_encode( OpcP, RMopc_Mem(0x01,dst)); 7641 ins_pipe( ialu_mem_imm ); 7642%} 7643 7644 7645instruct checkCastPP( eRegP dst ) %{ 7646 match(Set dst (CheckCastPP dst)); 7647 7648 size(0); 7649 format %{ "#checkcastPP of $dst" %} 7650 ins_encode( /*empty encoding*/ ); 7651 ins_pipe( empty ); 7652%} 7653 7654instruct castPP( eRegP dst ) %{ 7655 match(Set dst (CastPP dst)); 7656 format %{ "#castPP of $dst" %} 7657 ins_encode( /*empty encoding*/ ); 7658 ins_pipe( empty ); 7659%} 7660 7661instruct castII( eRegI dst ) %{ 7662 match(Set dst (CastII dst)); 7663 format %{ "#castII of $dst" %} 7664 ins_encode( /*empty encoding*/ ); 7665 ins_cost(0); 7666 ins_pipe( empty ); 7667%} 7668 7669 7670// Load-locked - same as a regular pointer load when used with compare-swap 7671instruct loadPLocked(eRegP dst, memory mem) %{ 7672 match(Set dst (LoadPLocked mem)); 7673 7674 ins_cost(125); 7675 format %{ "MOV $dst,$mem\t# Load ptr. locked" %} 7676 opcode(0x8B); 7677 ins_encode( OpcP, RegMem(dst,mem)); 7678 ins_pipe( ialu_reg_mem ); 7679%} 7680 7681// LoadLong-locked - same as a volatile long load when used with compare-swap 7682instruct loadLLocked(stackSlotL dst, load_long_memory mem) %{ 7683 predicate(UseSSE<=1); 7684 match(Set dst (LoadLLocked mem)); 7685 7686 ins_cost(200); 7687 format %{ "FILD $mem\t# Atomic volatile long load\n\t" 7688 "FISTp $dst" %} 7689 ins_encode(enc_loadL_volatile(mem,dst)); 7690 ins_pipe( fpu_reg_mem ); 7691%} 7692 7693instruct loadLX_Locked(stackSlotL dst, load_long_memory mem, regXD tmp) %{ 7694 predicate(UseSSE>=2); 7695 match(Set dst (LoadLLocked mem)); 7696 effect(TEMP tmp); 7697 ins_cost(180); 7698 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 7699 "MOVSD $dst,$tmp" %} 7700 ins_encode(enc_loadLX_volatile(mem, dst, tmp)); 7701 ins_pipe( pipe_slow ); 7702%} 7703 7704instruct loadLX_reg_Locked(eRegL dst, load_long_memory mem, regXD tmp) %{ 7705 predicate(UseSSE>=2); 7706 match(Set dst (LoadLLocked mem)); 7707 effect(TEMP tmp); 7708 ins_cost(160); 7709 format %{ "MOVSD $tmp,$mem\t# Atomic volatile long load\n\t" 7710 "MOVD $dst.lo,$tmp\n\t" 7711 "PSRLQ $tmp,32\n\t" 7712 "MOVD $dst.hi,$tmp" %} 7713 ins_encode(enc_loadLX_reg_volatile(mem, dst, tmp)); 7714 ins_pipe( pipe_slow ); 7715%} 7716 7717// Conditional-store of the updated heap-top. 7718// Used during allocation of the shared heap. 7719// Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel. 7720instruct storePConditional( memory heap_top_ptr, eAXRegP oldval, eRegP newval, eFlagsReg cr ) %{ 7721 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval))); 7722 // EAX is killed if there is contention, but then it's also unused. 7723 // In the common case of no contention, EAX holds the new oop address. 7724 format %{ "CMPXCHG $heap_top_ptr,$newval\t# If EAX==$heap_top_ptr Then store $newval into $heap_top_ptr" %} 7725 ins_encode( lock_prefix, Opcode(0x0F), Opcode(0xB1), RegMem(newval,heap_top_ptr) ); 7726 ins_pipe( pipe_cmpxchg ); 7727%} 7728 7729// Conditional-store of a long value 7730// Returns a boolean value (0/1) on success. Implemented with a CMPXCHG8 on Intel. 7731// mem_ptr can actually be in either ESI or EDI 7732instruct storeLConditional( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ 7733 match(Set res (StoreLConditional mem_ptr (Binary oldval newval))); 7734 effect(KILL cr); 7735 // EDX:EAX is killed if there is contention, but then it's also unused. 7736 // In the common case of no contention, EDX:EAX holds the new oop address. 7737 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 7738 "MOV $res,0\n\t" 7739 "JNE,s fail\n\t" 7740 "MOV $res,1\n" 7741 "fail:" %} 7742 ins_encode( enc_cmpxchg8(mem_ptr), 7743 enc_flags_ne_to_boolean(res) ); 7744 ins_pipe( pipe_cmpxchg ); 7745%} 7746 7747// Conditional-store of a long value 7748// ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG8 on Intel. 7749// mem_ptr can actually be in either ESI or EDI 7750instruct storeLConditional_flags( eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr, immI0 zero ) %{ 7751 match(Set cr (CmpI (StoreLConditional mem_ptr (Binary oldval newval)) zero)); 7752 // EDX:EAX is killed if there is contention, but then it's also unused. 7753 // In the common case of no contention, EDX:EAX holds the new oop address. 7754 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" %} 7755 ins_encode( enc_cmpxchg8(mem_ptr) ); 7756 ins_pipe( pipe_cmpxchg ); 7757%} 7758 7759// No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7760 7761instruct compareAndSwapL( eRegI res, eSIRegP mem_ptr, eADXRegL oldval, eBCXRegL newval, eFlagsReg cr ) %{ 7762 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 7763 effect(KILL cr, KILL oldval); 7764 format %{ "CMPXCHG8 [$mem_ptr],$newval\t# If EDX:EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 7765 "MOV $res,0\n\t" 7766 "JNE,s fail\n\t" 7767 "MOV $res,1\n" 7768 "fail:" %} 7769 ins_encode( enc_cmpxchg8(mem_ptr), 7770 enc_flags_ne_to_boolean(res) ); 7771 ins_pipe( pipe_cmpxchg ); 7772%} 7773 7774instruct compareAndSwapP( eRegI res, pRegP mem_ptr, eAXRegP oldval, eCXRegP newval, eFlagsReg cr) %{ 7775 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 7776 effect(KILL cr, KILL oldval); 7777 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 7778 "MOV $res,0\n\t" 7779 "JNE,s fail\n\t" 7780 "MOV $res,1\n" 7781 "fail:" %} 7782 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); 7783 ins_pipe( pipe_cmpxchg ); 7784%} 7785 7786instruct compareAndSwapI( eRegI res, pRegP mem_ptr, eAXRegI oldval, eCXRegI newval, eFlagsReg cr) %{ 7787 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 7788 effect(KILL cr, KILL oldval); 7789 format %{ "CMPXCHG [$mem_ptr],$newval\t# If EAX==[$mem_ptr] Then store $newval into [$mem_ptr]\n\t" 7790 "MOV $res,0\n\t" 7791 "JNE,s fail\n\t" 7792 "MOV $res,1\n" 7793 "fail:" %} 7794 ins_encode( enc_cmpxchg(mem_ptr), enc_flags_ne_to_boolean(res) ); 7795 ins_pipe( pipe_cmpxchg ); 7796%} 7797 7798//----------Subtraction Instructions------------------------------------------- 7799// Integer Subtraction Instructions 7800instruct subI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 7801 match(Set dst (SubI dst src)); 7802 effect(KILL cr); 7803 7804 size(2); 7805 format %{ "SUB $dst,$src" %} 7806 opcode(0x2B); 7807 ins_encode( OpcP, RegReg( dst, src) ); 7808 ins_pipe( ialu_reg_reg ); 7809%} 7810 7811instruct subI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 7812 match(Set dst (SubI dst src)); 7813 effect(KILL cr); 7814 7815 format %{ "SUB $dst,$src" %} 7816 opcode(0x81,0x05); /* Opcode 81 /5 */ 7817 // ins_encode( RegImm( dst, src) ); 7818 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 7819 ins_pipe( ialu_reg ); 7820%} 7821 7822instruct subI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 7823 match(Set dst (SubI dst (LoadI src))); 7824 effect(KILL cr); 7825 7826 ins_cost(125); 7827 format %{ "SUB $dst,$src" %} 7828 opcode(0x2B); 7829 ins_encode( OpcP, RegMem( dst, src) ); 7830 ins_pipe( ialu_reg_mem ); 7831%} 7832 7833instruct subI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 7834 match(Set dst (StoreI dst (SubI (LoadI dst) src))); 7835 effect(KILL cr); 7836 7837 ins_cost(150); 7838 format %{ "SUB $dst,$src" %} 7839 opcode(0x29); /* Opcode 29 /r */ 7840 ins_encode( OpcP, RegMem( src, dst ) ); 7841 ins_pipe( ialu_mem_reg ); 7842%} 7843 7844// Subtract from a pointer 7845instruct subP_eReg(eRegP dst, eRegI src, immI0 zero, eFlagsReg cr) %{ 7846 match(Set dst (AddP dst (SubI zero src))); 7847 effect(KILL cr); 7848 7849 size(2); 7850 format %{ "SUB $dst,$src" %} 7851 opcode(0x2B); 7852 ins_encode( OpcP, RegReg( dst, src) ); 7853 ins_pipe( ialu_reg_reg ); 7854%} 7855 7856instruct negI_eReg(eRegI dst, immI0 zero, eFlagsReg cr) %{ 7857 match(Set dst (SubI zero dst)); 7858 effect(KILL cr); 7859 7860 size(2); 7861 format %{ "NEG $dst" %} 7862 opcode(0xF7,0x03); // Opcode F7 /3 7863 ins_encode( OpcP, RegOpc( dst ) ); 7864 ins_pipe( ialu_reg ); 7865%} 7866 7867 7868//----------Multiplication/Division Instructions------------------------------- 7869// Integer Multiplication Instructions 7870// Multiply Register 7871instruct mulI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 7872 match(Set dst (MulI dst src)); 7873 effect(KILL cr); 7874 7875 size(3); 7876 ins_cost(300); 7877 format %{ "IMUL $dst,$src" %} 7878 opcode(0xAF, 0x0F); 7879 ins_encode( OpcS, OpcP, RegReg( dst, src) ); 7880 ins_pipe( ialu_reg_reg_alu0 ); 7881%} 7882 7883// Multiply 32-bit Immediate 7884instruct mulI_eReg_imm(eRegI dst, eRegI src, immI imm, eFlagsReg cr) %{ 7885 match(Set dst (MulI src imm)); 7886 effect(KILL cr); 7887 7888 ins_cost(300); 7889 format %{ "IMUL $dst,$src,$imm" %} 7890 opcode(0x69); /* 69 /r id */ 7891 ins_encode( OpcSE(imm), RegReg( dst, src ), Con8or32( imm ) ); 7892 ins_pipe( ialu_reg_reg_alu0 ); 7893%} 7894 7895instruct loadConL_low_only(eADXRegL_low_only dst, immL32 src, eFlagsReg cr) %{ 7896 match(Set dst src); 7897 effect(KILL cr); 7898 7899 // Note that this is artificially increased to make it more expensive than loadConL 7900 ins_cost(250); 7901 format %{ "MOV EAX,$src\t// low word only" %} 7902 opcode(0xB8); 7903 ins_encode( LdImmL_Lo(dst, src) ); 7904 ins_pipe( ialu_reg_fat ); 7905%} 7906 7907// Multiply by 32-bit Immediate, taking the shifted high order results 7908// (special case for shift by 32) 7909instruct mulI_imm_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32 cnt, eFlagsReg cr) %{ 7910 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); 7911 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && 7912 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && 7913 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); 7914 effect(USE src1, KILL cr); 7915 7916 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only 7917 ins_cost(0*100 + 1*400 - 150); 7918 format %{ "IMUL EDX:EAX,$src1" %} 7919 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); 7920 ins_pipe( pipe_slow ); 7921%} 7922 7923// Multiply by 32-bit Immediate, taking the shifted high order results 7924instruct mulI_imm_RShift_high(eDXRegI dst, nadxRegI src1, eADXRegL_low_only src2, immI_32_63 cnt, eFlagsReg cr) %{ 7925 match(Set dst (ConvL2I (RShiftL (MulL (ConvI2L src1) src2) cnt))); 7926 predicate( _kids[0]->_kids[0]->_kids[1]->_leaf->Opcode() == Op_ConL && 7927 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() >= min_jint && 7928 _kids[0]->_kids[0]->_kids[1]->_leaf->as_Type()->type()->is_long()->get_con() <= max_jint ); 7929 effect(USE src1, KILL cr); 7930 7931 // Note that this is adjusted by 150 to compensate for the overcosting of loadConL_low_only 7932 ins_cost(1*100 + 1*400 - 150); 7933 format %{ "IMUL EDX:EAX,$src1\n\t" 7934 "SAR EDX,$cnt-32" %} 7935 ins_encode( multiply_con_and_shift_high( dst, src1, src2, cnt, cr ) ); 7936 ins_pipe( pipe_slow ); 7937%} 7938 7939// Multiply Memory 32-bit Immediate 7940instruct mulI_mem_imm(eRegI dst, memory src, immI imm, eFlagsReg cr) %{ 7941 match(Set dst (MulI (LoadI src) imm)); 7942 effect(KILL cr); 7943 7944 ins_cost(300); 7945 format %{ "IMUL $dst,$src,$imm" %} 7946 opcode(0x69); /* 69 /r id */ 7947 ins_encode( OpcSE(imm), RegMem( dst, src ), Con8or32( imm ) ); 7948 ins_pipe( ialu_reg_mem_alu0 ); 7949%} 7950 7951// Multiply Memory 7952instruct mulI(eRegI dst, memory src, eFlagsReg cr) %{ 7953 match(Set dst (MulI dst (LoadI src))); 7954 effect(KILL cr); 7955 7956 ins_cost(350); 7957 format %{ "IMUL $dst,$src" %} 7958 opcode(0xAF, 0x0F); 7959 ins_encode( OpcS, OpcP, RegMem( dst, src) ); 7960 ins_pipe( ialu_reg_mem_alu0 ); 7961%} 7962 7963// Multiply Register Int to Long 7964instruct mulI2L(eADXRegL dst, eAXRegI src, nadxRegI src1, eFlagsReg flags) %{ 7965 // Basic Idea: long = (long)int * (long)int 7966 match(Set dst (MulL (ConvI2L src) (ConvI2L src1))); 7967 effect(DEF dst, USE src, USE src1, KILL flags); 7968 7969 ins_cost(300); 7970 format %{ "IMUL $dst,$src1" %} 7971 7972 ins_encode( long_int_multiply( dst, src1 ) ); 7973 ins_pipe( ialu_reg_reg_alu0 ); 7974%} 7975 7976instruct mulIS_eReg(eADXRegL dst, immL_32bits mask, eFlagsReg flags, eAXRegI src, nadxRegI src1) %{ 7977 // Basic Idea: long = (int & 0xffffffffL) * (int & 0xffffffffL) 7978 match(Set dst (MulL (AndL (ConvI2L src) mask) (AndL (ConvI2L src1) mask))); 7979 effect(KILL flags); 7980 7981 ins_cost(300); 7982 format %{ "MUL $dst,$src1" %} 7983 7984 ins_encode( long_uint_multiply(dst, src1) ); 7985 ins_pipe( ialu_reg_reg_alu0 ); 7986%} 7987 7988// Multiply Register Long 7989instruct mulL_eReg(eADXRegL dst, eRegL src, eRegI tmp, eFlagsReg cr) %{ 7990 match(Set dst (MulL dst src)); 7991 effect(KILL cr, TEMP tmp); 7992 ins_cost(4*100+3*400); 7993// Basic idea: lo(result) = lo(x_lo * y_lo) 7994// hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 7995 format %{ "MOV $tmp,$src.lo\n\t" 7996 "IMUL $tmp,EDX\n\t" 7997 "MOV EDX,$src.hi\n\t" 7998 "IMUL EDX,EAX\n\t" 7999 "ADD $tmp,EDX\n\t" 8000 "MUL EDX:EAX,$src.lo\n\t" 8001 "ADD EDX,$tmp" %} 8002 ins_encode( long_multiply( dst, src, tmp ) ); 8003 ins_pipe( pipe_slow ); 8004%} 8005 8006// Multiply Register Long by small constant 8007instruct mulL_eReg_con(eADXRegL dst, immL_127 src, eRegI tmp, eFlagsReg cr) %{ 8008 match(Set dst (MulL dst src)); 8009 effect(KILL cr, TEMP tmp); 8010 ins_cost(2*100+2*400); 8011 size(12); 8012// Basic idea: lo(result) = lo(src * EAX) 8013// hi(result) = hi(src * EAX) + lo(src * EDX) 8014 format %{ "IMUL $tmp,EDX,$src\n\t" 8015 "MOV EDX,$src\n\t" 8016 "MUL EDX\t# EDX*EAX -> EDX:EAX\n\t" 8017 "ADD EDX,$tmp" %} 8018 ins_encode( long_multiply_con( dst, src, tmp ) ); 8019 ins_pipe( pipe_slow ); 8020%} 8021 8022// Integer DIV with Register 8023instruct divI_eReg(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ 8024 match(Set rax (DivI rax div)); 8025 effect(KILL rdx, KILL cr); 8026 size(26); 8027 ins_cost(30*100+10*100); 8028 format %{ "CMP EAX,0x80000000\n\t" 8029 "JNE,s normal\n\t" 8030 "XOR EDX,EDX\n\t" 8031 "CMP ECX,-1\n\t" 8032 "JE,s done\n" 8033 "normal: CDQ\n\t" 8034 "IDIV $div\n\t" 8035 "done:" %} 8036 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8037 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8038 ins_pipe( ialu_reg_reg_alu0 ); 8039%} 8040 8041// Divide Register Long 8042instruct divL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ 8043 match(Set dst (DivL src1 src2)); 8044 effect( KILL cr, KILL cx, KILL bx ); 8045 ins_cost(10000); 8046 format %{ "PUSH $src1.hi\n\t" 8047 "PUSH $src1.lo\n\t" 8048 "PUSH $src2.hi\n\t" 8049 "PUSH $src2.lo\n\t" 8050 "CALL SharedRuntime::ldiv\n\t" 8051 "ADD ESP,16" %} 8052 ins_encode( long_div(src1,src2) ); 8053 ins_pipe( pipe_slow ); 8054%} 8055 8056// Integer DIVMOD with Register, both quotient and mod results 8057instruct divModI_eReg_divmod(eAXRegI rax, eDXRegI rdx, eCXRegI div, eFlagsReg cr) %{ 8058 match(DivModI rax div); 8059 effect(KILL cr); 8060 size(26); 8061 ins_cost(30*100+10*100); 8062 format %{ "CMP EAX,0x80000000\n\t" 8063 "JNE,s normal\n\t" 8064 "XOR EDX,EDX\n\t" 8065 "CMP ECX,-1\n\t" 8066 "JE,s done\n" 8067 "normal: CDQ\n\t" 8068 "IDIV $div\n\t" 8069 "done:" %} 8070 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8071 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8072 ins_pipe( pipe_slow ); 8073%} 8074 8075// Integer MOD with Register 8076instruct modI_eReg(eDXRegI rdx, eAXRegI rax, eCXRegI div, eFlagsReg cr) %{ 8077 match(Set rdx (ModI rax div)); 8078 effect(KILL rax, KILL cr); 8079 8080 size(26); 8081 ins_cost(300); 8082 format %{ "CDQ\n\t" 8083 "IDIV $div" %} 8084 opcode(0xF7, 0x7); /* Opcode F7 /7 */ 8085 ins_encode( cdq_enc, OpcP, RegOpc(div) ); 8086 ins_pipe( ialu_reg_reg_alu0 ); 8087%} 8088 8089// Remainder Register Long 8090instruct modL_eReg( eADXRegL dst, eRegL src1, eRegL src2, eFlagsReg cr, eCXRegI cx, eBXRegI bx ) %{ 8091 match(Set dst (ModL src1 src2)); 8092 effect( KILL cr, KILL cx, KILL bx ); 8093 ins_cost(10000); 8094 format %{ "PUSH $src1.hi\n\t" 8095 "PUSH $src1.lo\n\t" 8096 "PUSH $src2.hi\n\t" 8097 "PUSH $src2.lo\n\t" 8098 "CALL SharedRuntime::lrem\n\t" 8099 "ADD ESP,16" %} 8100 ins_encode( long_mod(src1,src2) ); 8101 ins_pipe( pipe_slow ); 8102%} 8103 8104// Integer Shift Instructions 8105// Shift Left by one 8106instruct shlI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8107 match(Set dst (LShiftI dst shift)); 8108 effect(KILL cr); 8109 8110 size(2); 8111 format %{ "SHL $dst,$shift" %} 8112 opcode(0xD1, 0x4); /* D1 /4 */ 8113 ins_encode( OpcP, RegOpc( dst ) ); 8114 ins_pipe( ialu_reg ); 8115%} 8116 8117// Shift Left by 8-bit immediate 8118instruct salI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8119 match(Set dst (LShiftI dst shift)); 8120 effect(KILL cr); 8121 8122 size(3); 8123 format %{ "SHL $dst,$shift" %} 8124 opcode(0xC1, 0x4); /* C1 /4 ib */ 8125 ins_encode( RegOpcImm( dst, shift) ); 8126 ins_pipe( ialu_reg ); 8127%} 8128 8129// Shift Left by variable 8130instruct salI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8131 match(Set dst (LShiftI dst shift)); 8132 effect(KILL cr); 8133 8134 size(2); 8135 format %{ "SHL $dst,$shift" %} 8136 opcode(0xD3, 0x4); /* D3 /4 */ 8137 ins_encode( OpcP, RegOpc( dst ) ); 8138 ins_pipe( ialu_reg_reg ); 8139%} 8140 8141// Arithmetic shift right by one 8142instruct sarI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8143 match(Set dst (RShiftI dst shift)); 8144 effect(KILL cr); 8145 8146 size(2); 8147 format %{ "SAR $dst,$shift" %} 8148 opcode(0xD1, 0x7); /* D1 /7 */ 8149 ins_encode( OpcP, RegOpc( dst ) ); 8150 ins_pipe( ialu_reg ); 8151%} 8152 8153// Arithmetic shift right by one 8154instruct sarI_mem_1(memory dst, immI1 shift, eFlagsReg cr) %{ 8155 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); 8156 effect(KILL cr); 8157 format %{ "SAR $dst,$shift" %} 8158 opcode(0xD1, 0x7); /* D1 /7 */ 8159 ins_encode( OpcP, RMopc_Mem(secondary,dst) ); 8160 ins_pipe( ialu_mem_imm ); 8161%} 8162 8163// Arithmetic Shift Right by 8-bit immediate 8164instruct sarI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8165 match(Set dst (RShiftI dst shift)); 8166 effect(KILL cr); 8167 8168 size(3); 8169 format %{ "SAR $dst,$shift" %} 8170 opcode(0xC1, 0x7); /* C1 /7 ib */ 8171 ins_encode( RegOpcImm( dst, shift ) ); 8172 ins_pipe( ialu_mem_imm ); 8173%} 8174 8175// Arithmetic Shift Right by 8-bit immediate 8176instruct sarI_mem_imm(memory dst, immI8 shift, eFlagsReg cr) %{ 8177 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift))); 8178 effect(KILL cr); 8179 8180 format %{ "SAR $dst,$shift" %} 8181 opcode(0xC1, 0x7); /* C1 /7 ib */ 8182 ins_encode( OpcP, RMopc_Mem(secondary, dst ), Con8or32( shift ) ); 8183 ins_pipe( ialu_mem_imm ); 8184%} 8185 8186// Arithmetic Shift Right by variable 8187instruct sarI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8188 match(Set dst (RShiftI dst shift)); 8189 effect(KILL cr); 8190 8191 size(2); 8192 format %{ "SAR $dst,$shift" %} 8193 opcode(0xD3, 0x7); /* D3 /7 */ 8194 ins_encode( OpcP, RegOpc( dst ) ); 8195 ins_pipe( ialu_reg_reg ); 8196%} 8197 8198// Logical shift right by one 8199instruct shrI_eReg_1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8200 match(Set dst (URShiftI dst shift)); 8201 effect(KILL cr); 8202 8203 size(2); 8204 format %{ "SHR $dst,$shift" %} 8205 opcode(0xD1, 0x5); /* D1 /5 */ 8206 ins_encode( OpcP, RegOpc( dst ) ); 8207 ins_pipe( ialu_reg ); 8208%} 8209 8210// Logical Shift Right by 8-bit immediate 8211instruct shrI_eReg_imm(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8212 match(Set dst (URShiftI dst shift)); 8213 effect(KILL cr); 8214 8215 size(3); 8216 format %{ "SHR $dst,$shift" %} 8217 opcode(0xC1, 0x5); /* C1 /5 ib */ 8218 ins_encode( RegOpcImm( dst, shift) ); 8219 ins_pipe( ialu_reg ); 8220%} 8221 8222// Logical Shift Right by 24, followed by Arithmetic Shift Left by 24. 8223// This idiom is used by the compiler for the i2b bytecode. 8224instruct i2b(eRegI dst, xRegI src, immI_24 twentyfour, eFlagsReg cr) %{ 8225 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour)); 8226 effect(KILL cr); 8227 8228 size(3); 8229 format %{ "MOVSX $dst,$src :8" %} 8230 opcode(0xBE, 0x0F); 8231 ins_encode( OpcS, OpcP, RegReg( dst, src)); 8232 ins_pipe( ialu_reg_reg ); 8233%} 8234 8235// Logical Shift Right by 16, followed by Arithmetic Shift Left by 16. 8236// This idiom is used by the compiler the i2s bytecode. 8237instruct i2s(eRegI dst, xRegI src, immI_16 sixteen, eFlagsReg cr) %{ 8238 match(Set dst (RShiftI (LShiftI src sixteen) sixteen)); 8239 effect(KILL cr); 8240 8241 size(3); 8242 format %{ "MOVSX $dst,$src :16" %} 8243 opcode(0xBF, 0x0F); 8244 ins_encode( OpcS, OpcP, RegReg( dst, src)); 8245 ins_pipe( ialu_reg_reg ); 8246%} 8247 8248 8249// Logical Shift Right by variable 8250instruct shrI_eReg_CL(eRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8251 match(Set dst (URShiftI dst shift)); 8252 effect(KILL cr); 8253 8254 size(2); 8255 format %{ "SHR $dst,$shift" %} 8256 opcode(0xD3, 0x5); /* D3 /5 */ 8257 ins_encode( OpcP, RegOpc( dst ) ); 8258 ins_pipe( ialu_reg_reg ); 8259%} 8260 8261 8262//----------Logical Instructions----------------------------------------------- 8263//----------Integer Logical Instructions--------------------------------------- 8264// And Instructions 8265// And Register with Register 8266instruct andI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8267 match(Set dst (AndI dst src)); 8268 effect(KILL cr); 8269 8270 size(2); 8271 format %{ "AND $dst,$src" %} 8272 opcode(0x23); 8273 ins_encode( OpcP, RegReg( dst, src) ); 8274 ins_pipe( ialu_reg_reg ); 8275%} 8276 8277// And Register with Immediate 8278instruct andI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8279 match(Set dst (AndI dst src)); 8280 effect(KILL cr); 8281 8282 format %{ "AND $dst,$src" %} 8283 opcode(0x81,0x04); /* Opcode 81 /4 */ 8284 // ins_encode( RegImm( dst, src) ); 8285 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8286 ins_pipe( ialu_reg ); 8287%} 8288 8289// And Register with Memory 8290instruct andI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 8291 match(Set dst (AndI dst (LoadI src))); 8292 effect(KILL cr); 8293 8294 ins_cost(125); 8295 format %{ "AND $dst,$src" %} 8296 opcode(0x23); 8297 ins_encode( OpcP, RegMem( dst, src) ); 8298 ins_pipe( ialu_reg_mem ); 8299%} 8300 8301// And Memory with Register 8302instruct andI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 8303 match(Set dst (StoreI dst (AndI (LoadI dst) src))); 8304 effect(KILL cr); 8305 8306 ins_cost(150); 8307 format %{ "AND $dst,$src" %} 8308 opcode(0x21); /* Opcode 21 /r */ 8309 ins_encode( OpcP, RegMem( src, dst ) ); 8310 ins_pipe( ialu_mem_reg ); 8311%} 8312 8313// And Memory with Immediate 8314instruct andI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 8315 match(Set dst (StoreI dst (AndI (LoadI dst) src))); 8316 effect(KILL cr); 8317 8318 ins_cost(125); 8319 format %{ "AND $dst,$src" %} 8320 opcode(0x81, 0x4); /* Opcode 81 /4 id */ 8321 // ins_encode( MemImm( dst, src) ); 8322 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 8323 ins_pipe( ialu_mem_imm ); 8324%} 8325 8326// Or Instructions 8327// Or Register with Register 8328instruct orI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8329 match(Set dst (OrI dst src)); 8330 effect(KILL cr); 8331 8332 size(2); 8333 format %{ "OR $dst,$src" %} 8334 opcode(0x0B); 8335 ins_encode( OpcP, RegReg( dst, src) ); 8336 ins_pipe( ialu_reg_reg ); 8337%} 8338 8339// Or Register with Immediate 8340instruct orI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8341 match(Set dst (OrI dst src)); 8342 effect(KILL cr); 8343 8344 format %{ "OR $dst,$src" %} 8345 opcode(0x81,0x01); /* Opcode 81 /1 id */ 8346 // ins_encode( RegImm( dst, src) ); 8347 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8348 ins_pipe( ialu_reg ); 8349%} 8350 8351// Or Register with Memory 8352instruct orI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 8353 match(Set dst (OrI dst (LoadI src))); 8354 effect(KILL cr); 8355 8356 ins_cost(125); 8357 format %{ "OR $dst,$src" %} 8358 opcode(0x0B); 8359 ins_encode( OpcP, RegMem( dst, src) ); 8360 ins_pipe( ialu_reg_mem ); 8361%} 8362 8363// Or Memory with Register 8364instruct orI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 8365 match(Set dst (StoreI dst (OrI (LoadI dst) src))); 8366 effect(KILL cr); 8367 8368 ins_cost(150); 8369 format %{ "OR $dst,$src" %} 8370 opcode(0x09); /* Opcode 09 /r */ 8371 ins_encode( OpcP, RegMem( src, dst ) ); 8372 ins_pipe( ialu_mem_reg ); 8373%} 8374 8375// Or Memory with Immediate 8376instruct orI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 8377 match(Set dst (StoreI dst (OrI (LoadI dst) src))); 8378 effect(KILL cr); 8379 8380 ins_cost(125); 8381 format %{ "OR $dst,$src" %} 8382 opcode(0x81,0x1); /* Opcode 81 /1 id */ 8383 // ins_encode( MemImm( dst, src) ); 8384 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 8385 ins_pipe( ialu_mem_imm ); 8386%} 8387 8388// ROL/ROR 8389// ROL expand 8390instruct rolI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8391 effect(USE_DEF dst, USE shift, KILL cr); 8392 8393 format %{ "ROL $dst, $shift" %} 8394 opcode(0xD1, 0x0); /* Opcode D1 /0 */ 8395 ins_encode( OpcP, RegOpc( dst )); 8396 ins_pipe( ialu_reg ); 8397%} 8398 8399instruct rolI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8400 effect(USE_DEF dst, USE shift, KILL cr); 8401 8402 format %{ "ROL $dst, $shift" %} 8403 opcode(0xC1, 0x0); /*Opcode /C1 /0 */ 8404 ins_encode( RegOpcImm(dst, shift) ); 8405 ins_pipe(ialu_reg); 8406%} 8407 8408instruct rolI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr) %{ 8409 effect(USE_DEF dst, USE shift, KILL cr); 8410 8411 format %{ "ROL $dst, $shift" %} 8412 opcode(0xD3, 0x0); /* Opcode D3 /0 */ 8413 ins_encode(OpcP, RegOpc(dst)); 8414 ins_pipe( ialu_reg_reg ); 8415%} 8416// end of ROL expand 8417 8418// ROL 32bit by one once 8419instruct rolI_eReg_i1(eRegI dst, immI1 lshift, immI_M1 rshift, eFlagsReg cr) %{ 8420 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); 8421 8422 expand %{ 8423 rolI_eReg_imm1(dst, lshift, cr); 8424 %} 8425%} 8426 8427// ROL 32bit var by imm8 once 8428instruct rolI_eReg_i8(eRegI dst, immI8 lshift, immI8 rshift, eFlagsReg cr) %{ 8429 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8430 match(Set dst ( OrI (LShiftI dst lshift) (URShiftI dst rshift))); 8431 8432 expand %{ 8433 rolI_eReg_imm8(dst, lshift, cr); 8434 %} 8435%} 8436 8437// ROL 32bit var by var once 8438instruct rolI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ 8439 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift)))); 8440 8441 expand %{ 8442 rolI_eReg_CL(dst, shift, cr); 8443 %} 8444%} 8445 8446// ROL 32bit var by var once 8447instruct rolI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ 8448 match(Set dst ( OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift)))); 8449 8450 expand %{ 8451 rolI_eReg_CL(dst, shift, cr); 8452 %} 8453%} 8454 8455// ROR expand 8456instruct rorI_eReg_imm1(eRegI dst, immI1 shift, eFlagsReg cr) %{ 8457 effect(USE_DEF dst, USE shift, KILL cr); 8458 8459 format %{ "ROR $dst, $shift" %} 8460 opcode(0xD1,0x1); /* Opcode D1 /1 */ 8461 ins_encode( OpcP, RegOpc( dst ) ); 8462 ins_pipe( ialu_reg ); 8463%} 8464 8465instruct rorI_eReg_imm8(eRegI dst, immI8 shift, eFlagsReg cr) %{ 8466 effect (USE_DEF dst, USE shift, KILL cr); 8467 8468 format %{ "ROR $dst, $shift" %} 8469 opcode(0xC1, 0x1); /* Opcode /C1 /1 ib */ 8470 ins_encode( RegOpcImm(dst, shift) ); 8471 ins_pipe( ialu_reg ); 8472%} 8473 8474instruct rorI_eReg_CL(ncxRegI dst, eCXRegI shift, eFlagsReg cr)%{ 8475 effect(USE_DEF dst, USE shift, KILL cr); 8476 8477 format %{ "ROR $dst, $shift" %} 8478 opcode(0xD3, 0x1); /* Opcode D3 /1 */ 8479 ins_encode(OpcP, RegOpc(dst)); 8480 ins_pipe( ialu_reg_reg ); 8481%} 8482// end of ROR expand 8483 8484// ROR right once 8485instruct rorI_eReg_i1(eRegI dst, immI1 rshift, immI_M1 lshift, eFlagsReg cr) %{ 8486 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); 8487 8488 expand %{ 8489 rorI_eReg_imm1(dst, rshift, cr); 8490 %} 8491%} 8492 8493// ROR 32bit by immI8 once 8494instruct rorI_eReg_i8(eRegI dst, immI8 rshift, immI8 lshift, eFlagsReg cr) %{ 8495 predicate( 0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8496 match(Set dst ( OrI (URShiftI dst rshift) (LShiftI dst lshift))); 8497 8498 expand %{ 8499 rorI_eReg_imm8(dst, rshift, cr); 8500 %} 8501%} 8502 8503// ROR 32bit var by var once 8504instruct rorI_eReg_Var_C0(ncxRegI dst, eCXRegI shift, immI0 zero, eFlagsReg cr) %{ 8505 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift)))); 8506 8507 expand %{ 8508 rorI_eReg_CL(dst, shift, cr); 8509 %} 8510%} 8511 8512// ROR 32bit var by var once 8513instruct rorI_eReg_Var_C32(ncxRegI dst, eCXRegI shift, immI_32 c32, eFlagsReg cr) %{ 8514 match(Set dst ( OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift)))); 8515 8516 expand %{ 8517 rorI_eReg_CL(dst, shift, cr); 8518 %} 8519%} 8520 8521// Xor Instructions 8522// Xor Register with Register 8523instruct xorI_eReg(eRegI dst, eRegI src, eFlagsReg cr) %{ 8524 match(Set dst (XorI dst src)); 8525 effect(KILL cr); 8526 8527 size(2); 8528 format %{ "XOR $dst,$src" %} 8529 opcode(0x33); 8530 ins_encode( OpcP, RegReg( dst, src) ); 8531 ins_pipe( ialu_reg_reg ); 8532%} 8533 8534// Xor Register with Immediate 8535instruct xorI_eReg_imm(eRegI dst, immI src, eFlagsReg cr) %{ 8536 match(Set dst (XorI dst src)); 8537 effect(KILL cr); 8538 8539 format %{ "XOR $dst,$src" %} 8540 opcode(0x81,0x06); /* Opcode 81 /6 id */ 8541 // ins_encode( RegImm( dst, src) ); 8542 ins_encode( OpcSErm( dst, src ), Con8or32( src ) ); 8543 ins_pipe( ialu_reg ); 8544%} 8545 8546// Xor Register with Memory 8547instruct xorI_eReg_mem(eRegI dst, memory src, eFlagsReg cr) %{ 8548 match(Set dst (XorI dst (LoadI src))); 8549 effect(KILL cr); 8550 8551 ins_cost(125); 8552 format %{ "XOR $dst,$src" %} 8553 opcode(0x33); 8554 ins_encode( OpcP, RegMem(dst, src) ); 8555 ins_pipe( ialu_reg_mem ); 8556%} 8557 8558// Xor Memory with Register 8559instruct xorI_mem_eReg(memory dst, eRegI src, eFlagsReg cr) %{ 8560 match(Set dst (StoreI dst (XorI (LoadI dst) src))); 8561 effect(KILL cr); 8562 8563 ins_cost(150); 8564 format %{ "XOR $dst,$src" %} 8565 opcode(0x31); /* Opcode 31 /r */ 8566 ins_encode( OpcP, RegMem( src, dst ) ); 8567 ins_pipe( ialu_mem_reg ); 8568%} 8569 8570// Xor Memory with Immediate 8571instruct xorI_mem_imm(memory dst, immI src, eFlagsReg cr) %{ 8572 match(Set dst (StoreI dst (XorI (LoadI dst) src))); 8573 effect(KILL cr); 8574 8575 ins_cost(125); 8576 format %{ "XOR $dst,$src" %} 8577 opcode(0x81,0x6); /* Opcode 81 /6 id */ 8578 ins_encode( OpcSE( src ), RMopc_Mem(secondary, dst ), Con8or32( src ) ); 8579 ins_pipe( ialu_mem_imm ); 8580%} 8581 8582//----------Convert Int to Boolean--------------------------------------------- 8583 8584instruct movI_nocopy(eRegI dst, eRegI src) %{ 8585 effect( DEF dst, USE src ); 8586 format %{ "MOV $dst,$src" %} 8587 ins_encode( enc_Copy( dst, src) ); 8588 ins_pipe( ialu_reg_reg ); 8589%} 8590 8591instruct ci2b( eRegI dst, eRegI src, eFlagsReg cr ) %{ 8592 effect( USE_DEF dst, USE src, KILL cr ); 8593 8594 size(4); 8595 format %{ "NEG $dst\n\t" 8596 "ADC $dst,$src" %} 8597 ins_encode( neg_reg(dst), 8598 OpcRegReg(0x13,dst,src) ); 8599 ins_pipe( ialu_reg_reg_long ); 8600%} 8601 8602instruct convI2B( eRegI dst, eRegI src, eFlagsReg cr ) %{ 8603 match(Set dst (Conv2B src)); 8604 8605 expand %{ 8606 movI_nocopy(dst,src); 8607 ci2b(dst,src,cr); 8608 %} 8609%} 8610 8611instruct movP_nocopy(eRegI dst, eRegP src) %{ 8612 effect( DEF dst, USE src ); 8613 format %{ "MOV $dst,$src" %} 8614 ins_encode( enc_Copy( dst, src) ); 8615 ins_pipe( ialu_reg_reg ); 8616%} 8617 8618instruct cp2b( eRegI dst, eRegP src, eFlagsReg cr ) %{ 8619 effect( USE_DEF dst, USE src, KILL cr ); 8620 format %{ "NEG $dst\n\t" 8621 "ADC $dst,$src" %} 8622 ins_encode( neg_reg(dst), 8623 OpcRegReg(0x13,dst,src) ); 8624 ins_pipe( ialu_reg_reg_long ); 8625%} 8626 8627instruct convP2B( eRegI dst, eRegP src, eFlagsReg cr ) %{ 8628 match(Set dst (Conv2B src)); 8629 8630 expand %{ 8631 movP_nocopy(dst,src); 8632 cp2b(dst,src,cr); 8633 %} 8634%} 8635 8636instruct cmpLTMask( eCXRegI dst, ncxRegI p, ncxRegI q, eFlagsReg cr ) %{ 8637 match(Set dst (CmpLTMask p q)); 8638 effect( KILL cr ); 8639 ins_cost(400); 8640 8641 // SETlt can only use low byte of EAX,EBX, ECX, or EDX as destination 8642 format %{ "XOR $dst,$dst\n\t" 8643 "CMP $p,$q\n\t" 8644 "SETlt $dst\n\t" 8645 "NEG $dst" %} 8646 ins_encode( OpcRegReg(0x33,dst,dst), 8647 OpcRegReg(0x3B,p,q), 8648 setLT_reg(dst), neg_reg(dst) ); 8649 ins_pipe( pipe_slow ); 8650%} 8651 8652instruct cmpLTMask0( eRegI dst, immI0 zero, eFlagsReg cr ) %{ 8653 match(Set dst (CmpLTMask dst zero)); 8654 effect( DEF dst, KILL cr ); 8655 ins_cost(100); 8656 8657 format %{ "SAR $dst,31" %} 8658 opcode(0xC1, 0x7); /* C1 /7 ib */ 8659 ins_encode( RegOpcImm( dst, 0x1F ) ); 8660 ins_pipe( ialu_reg ); 8661%} 8662 8663 8664instruct cadd_cmpLTMask( ncxRegI p, ncxRegI q, ncxRegI y, eCXRegI tmp, eFlagsReg cr ) %{ 8665 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 8666 effect( KILL tmp, KILL cr ); 8667 ins_cost(400); 8668 // annoyingly, $tmp has no edges so you cant ask for it in 8669 // any format or encoding 8670 format %{ "SUB $p,$q\n\t" 8671 "SBB ECX,ECX\n\t" 8672 "AND ECX,$y\n\t" 8673 "ADD $p,ECX" %} 8674 ins_encode( enc_cmpLTP(p,q,y,tmp) ); 8675 ins_pipe( pipe_cmplt ); 8676%} 8677 8678/* If I enable this, I encourage spilling in the inner loop of compress. 8679instruct cadd_cmpLTMask_mem( ncxRegI p, ncxRegI q, memory y, eCXRegI tmp, eFlagsReg cr ) %{ 8680 match(Set p (AddI (AndI (CmpLTMask p q) (LoadI y)) (SubI p q))); 8681 effect( USE_KILL tmp, KILL cr ); 8682 ins_cost(400); 8683 8684 format %{ "SUB $p,$q\n\t" 8685 "SBB ECX,ECX\n\t" 8686 "AND ECX,$y\n\t" 8687 "ADD $p,ECX" %} 8688 ins_encode( enc_cmpLTP_mem(p,q,y,tmp) ); 8689%} 8690*/ 8691 8692//----------Long Instructions------------------------------------------------ 8693// Add Long Register with Register 8694instruct addL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 8695 match(Set dst (AddL dst src)); 8696 effect(KILL cr); 8697 ins_cost(200); 8698 format %{ "ADD $dst.lo,$src.lo\n\t" 8699 "ADC $dst.hi,$src.hi" %} 8700 opcode(0x03, 0x13); 8701 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); 8702 ins_pipe( ialu_reg_reg_long ); 8703%} 8704 8705// Add Long Register with Immediate 8706instruct addL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 8707 match(Set dst (AddL dst src)); 8708 effect(KILL cr); 8709 format %{ "ADD $dst.lo,$src.lo\n\t" 8710 "ADC $dst.hi,$src.hi" %} 8711 opcode(0x81,0x00,0x02); /* Opcode 81 /0, 81 /2 */ 8712 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 8713 ins_pipe( ialu_reg_long ); 8714%} 8715 8716// Add Long Register with Memory 8717instruct addL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 8718 match(Set dst (AddL dst (LoadL mem))); 8719 effect(KILL cr); 8720 ins_cost(125); 8721 format %{ "ADD $dst.lo,$mem\n\t" 8722 "ADC $dst.hi,$mem+4" %} 8723 opcode(0x03, 0x13); 8724 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 8725 ins_pipe( ialu_reg_long_mem ); 8726%} 8727 8728// Subtract Long Register with Register. 8729instruct subL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 8730 match(Set dst (SubL dst src)); 8731 effect(KILL cr); 8732 ins_cost(200); 8733 format %{ "SUB $dst.lo,$src.lo\n\t" 8734 "SBB $dst.hi,$src.hi" %} 8735 opcode(0x2B, 0x1B); 8736 ins_encode( RegReg_Lo(dst, src), RegReg_Hi(dst,src) ); 8737 ins_pipe( ialu_reg_reg_long ); 8738%} 8739 8740// Subtract Long Register with Immediate 8741instruct subL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 8742 match(Set dst (SubL dst src)); 8743 effect(KILL cr); 8744 format %{ "SUB $dst.lo,$src.lo\n\t" 8745 "SBB $dst.hi,$src.hi" %} 8746 opcode(0x81,0x05,0x03); /* Opcode 81 /5, 81 /3 */ 8747 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 8748 ins_pipe( ialu_reg_long ); 8749%} 8750 8751// Subtract Long Register with Memory 8752instruct subL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 8753 match(Set dst (SubL dst (LoadL mem))); 8754 effect(KILL cr); 8755 ins_cost(125); 8756 format %{ "SUB $dst.lo,$mem\n\t" 8757 "SBB $dst.hi,$mem+4" %} 8758 opcode(0x2B, 0x1B); 8759 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 8760 ins_pipe( ialu_reg_long_mem ); 8761%} 8762 8763instruct negL_eReg(eRegL dst, immL0 zero, eFlagsReg cr) %{ 8764 match(Set dst (SubL zero dst)); 8765 effect(KILL cr); 8766 ins_cost(300); 8767 format %{ "NEG $dst.hi\n\tNEG $dst.lo\n\tSBB $dst.hi,0" %} 8768 ins_encode( neg_long(dst) ); 8769 ins_pipe( ialu_reg_reg_long ); 8770%} 8771 8772// And Long Register with Register 8773instruct andL_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 8774 match(Set dst (AndL dst src)); 8775 effect(KILL cr); 8776 format %{ "AND $dst.lo,$src.lo\n\t" 8777 "AND $dst.hi,$src.hi" %} 8778 opcode(0x23,0x23); 8779 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 8780 ins_pipe( ialu_reg_reg_long ); 8781%} 8782 8783// And Long Register with Immediate 8784instruct andL_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 8785 match(Set dst (AndL dst src)); 8786 effect(KILL cr); 8787 format %{ "AND $dst.lo,$src.lo\n\t" 8788 "AND $dst.hi,$src.hi" %} 8789 opcode(0x81,0x04,0x04); /* Opcode 81 /4, 81 /4 */ 8790 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 8791 ins_pipe( ialu_reg_long ); 8792%} 8793 8794// And Long Register with Memory 8795instruct andL_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 8796 match(Set dst (AndL dst (LoadL mem))); 8797 effect(KILL cr); 8798 ins_cost(125); 8799 format %{ "AND $dst.lo,$mem\n\t" 8800 "AND $dst.hi,$mem+4" %} 8801 opcode(0x23, 0x23); 8802 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 8803 ins_pipe( ialu_reg_long_mem ); 8804%} 8805 8806// Or Long Register with Register 8807instruct orl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 8808 match(Set dst (OrL dst src)); 8809 effect(KILL cr); 8810 format %{ "OR $dst.lo,$src.lo\n\t" 8811 "OR $dst.hi,$src.hi" %} 8812 opcode(0x0B,0x0B); 8813 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 8814 ins_pipe( ialu_reg_reg_long ); 8815%} 8816 8817// Or Long Register with Immediate 8818instruct orl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 8819 match(Set dst (OrL dst src)); 8820 effect(KILL cr); 8821 format %{ "OR $dst.lo,$src.lo\n\t" 8822 "OR $dst.hi,$src.hi" %} 8823 opcode(0x81,0x01,0x01); /* Opcode 81 /1, 81 /1 */ 8824 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 8825 ins_pipe( ialu_reg_long ); 8826%} 8827 8828// Or Long Register with Memory 8829instruct orl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 8830 match(Set dst (OrL dst (LoadL mem))); 8831 effect(KILL cr); 8832 ins_cost(125); 8833 format %{ "OR $dst.lo,$mem\n\t" 8834 "OR $dst.hi,$mem+4" %} 8835 opcode(0x0B,0x0B); 8836 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 8837 ins_pipe( ialu_reg_long_mem ); 8838%} 8839 8840// Xor Long Register with Register 8841instruct xorl_eReg(eRegL dst, eRegL src, eFlagsReg cr) %{ 8842 match(Set dst (XorL dst src)); 8843 effect(KILL cr); 8844 format %{ "XOR $dst.lo,$src.lo\n\t" 8845 "XOR $dst.hi,$src.hi" %} 8846 opcode(0x33,0x33); 8847 ins_encode( RegReg_Lo( dst, src), RegReg_Hi( dst, src) ); 8848 ins_pipe( ialu_reg_reg_long ); 8849%} 8850 8851// Xor Long Register with Immediate 8852instruct xorl_eReg_imm(eRegL dst, immL src, eFlagsReg cr) %{ 8853 match(Set dst (XorL dst src)); 8854 effect(KILL cr); 8855 format %{ "XOR $dst.lo,$src.lo\n\t" 8856 "XOR $dst.hi,$src.hi" %} 8857 opcode(0x81,0x06,0x06); /* Opcode 81 /6, 81 /6 */ 8858 ins_encode( Long_OpcSErm_Lo( dst, src ), Long_OpcSErm_Hi( dst, src ) ); 8859 ins_pipe( ialu_reg_long ); 8860%} 8861 8862// Xor Long Register with Memory 8863instruct xorl_eReg_mem(eRegL dst, load_long_memory mem, eFlagsReg cr) %{ 8864 match(Set dst (XorL dst (LoadL mem))); 8865 effect(KILL cr); 8866 ins_cost(125); 8867 format %{ "XOR $dst.lo,$mem\n\t" 8868 "XOR $dst.hi,$mem+4" %} 8869 opcode(0x33,0x33); 8870 ins_encode( OpcP, RegMem( dst, mem), OpcS, RegMem_Hi(dst,mem) ); 8871 ins_pipe( ialu_reg_long_mem ); 8872%} 8873 8874// Shift Left Long by 1-31 8875instruct shlL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 8876 match(Set dst (LShiftL dst cnt)); 8877 effect(KILL cr); 8878 ins_cost(200); 8879 format %{ "SHLD $dst.hi,$dst.lo,$cnt\n\t" 8880 "SHL $dst.lo,$cnt" %} 8881 opcode(0xC1, 0x4, 0xA4); /* 0F/A4, then C1 /4 ib */ 8882 ins_encode( move_long_small_shift(dst,cnt) ); 8883 ins_pipe( ialu_reg_long ); 8884%} 8885 8886// Shift Left Long by 32-63 8887instruct shlL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 8888 match(Set dst (LShiftL dst cnt)); 8889 effect(KILL cr); 8890 ins_cost(300); 8891 format %{ "MOV $dst.hi,$dst.lo\n" 8892 "\tSHL $dst.hi,$cnt-32\n" 8893 "\tXOR $dst.lo,$dst.lo" %} 8894 opcode(0xC1, 0x4); /* C1 /4 ib */ 8895 ins_encode( move_long_big_shift_clr(dst,cnt) ); 8896 ins_pipe( ialu_reg_long ); 8897%} 8898 8899// Shift Left Long by variable 8900instruct salL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 8901 match(Set dst (LShiftL dst shift)); 8902 effect(KILL cr); 8903 ins_cost(500+200); 8904 size(17); 8905 format %{ "TEST $shift,32\n\t" 8906 "JEQ,s small\n\t" 8907 "MOV $dst.hi,$dst.lo\n\t" 8908 "XOR $dst.lo,$dst.lo\n" 8909 "small:\tSHLD $dst.hi,$dst.lo,$shift\n\t" 8910 "SHL $dst.lo,$shift" %} 8911 ins_encode( shift_left_long( dst, shift ) ); 8912 ins_pipe( pipe_slow ); 8913%} 8914 8915// Shift Right Long by 1-31 8916instruct shrL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 8917 match(Set dst (URShiftL dst cnt)); 8918 effect(KILL cr); 8919 ins_cost(200); 8920 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" 8921 "SHR $dst.hi,$cnt" %} 8922 opcode(0xC1, 0x5, 0xAC); /* 0F/AC, then C1 /5 ib */ 8923 ins_encode( move_long_small_shift(dst,cnt) ); 8924 ins_pipe( ialu_reg_long ); 8925%} 8926 8927// Shift Right Long by 32-63 8928instruct shrL_eReg_32_63(eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 8929 match(Set dst (URShiftL dst cnt)); 8930 effect(KILL cr); 8931 ins_cost(300); 8932 format %{ "MOV $dst.lo,$dst.hi\n" 8933 "\tSHR $dst.lo,$cnt-32\n" 8934 "\tXOR $dst.hi,$dst.hi" %} 8935 opcode(0xC1, 0x5); /* C1 /5 ib */ 8936 ins_encode( move_long_big_shift_clr(dst,cnt) ); 8937 ins_pipe( ialu_reg_long ); 8938%} 8939 8940// Shift Right Long by variable 8941instruct shrL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 8942 match(Set dst (URShiftL dst shift)); 8943 effect(KILL cr); 8944 ins_cost(600); 8945 size(17); 8946 format %{ "TEST $shift,32\n\t" 8947 "JEQ,s small\n\t" 8948 "MOV $dst.lo,$dst.hi\n\t" 8949 "XOR $dst.hi,$dst.hi\n" 8950 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" 8951 "SHR $dst.hi,$shift" %} 8952 ins_encode( shift_right_long( dst, shift ) ); 8953 ins_pipe( pipe_slow ); 8954%} 8955 8956// Shift Right Long by 1-31 8957instruct sarL_eReg_1_31(eRegL dst, immI_1_31 cnt, eFlagsReg cr) %{ 8958 match(Set dst (RShiftL dst cnt)); 8959 effect(KILL cr); 8960 ins_cost(200); 8961 format %{ "SHRD $dst.lo,$dst.hi,$cnt\n\t" 8962 "SAR $dst.hi,$cnt" %} 8963 opcode(0xC1, 0x7, 0xAC); /* 0F/AC, then C1 /7 ib */ 8964 ins_encode( move_long_small_shift(dst,cnt) ); 8965 ins_pipe( ialu_reg_long ); 8966%} 8967 8968// Shift Right Long by 32-63 8969instruct sarL_eReg_32_63( eRegL dst, immI_32_63 cnt, eFlagsReg cr) %{ 8970 match(Set dst (RShiftL dst cnt)); 8971 effect(KILL cr); 8972 ins_cost(300); 8973 format %{ "MOV $dst.lo,$dst.hi\n" 8974 "\tSAR $dst.lo,$cnt-32\n" 8975 "\tSAR $dst.hi,31" %} 8976 opcode(0xC1, 0x7); /* C1 /7 ib */ 8977 ins_encode( move_long_big_shift_sign(dst,cnt) ); 8978 ins_pipe( ialu_reg_long ); 8979%} 8980 8981// Shift Right arithmetic Long by variable 8982instruct sarL_eReg_CL(eRegL dst, eCXRegI shift, eFlagsReg cr) %{ 8983 match(Set dst (RShiftL dst shift)); 8984 effect(KILL cr); 8985 ins_cost(600); 8986 size(18); 8987 format %{ "TEST $shift,32\n\t" 8988 "JEQ,s small\n\t" 8989 "MOV $dst.lo,$dst.hi\n\t" 8990 "SAR $dst.hi,31\n" 8991 "small:\tSHRD $dst.lo,$dst.hi,$shift\n\t" 8992 "SAR $dst.hi,$shift" %} 8993 ins_encode( shift_right_arith_long( dst, shift ) ); 8994 ins_pipe( pipe_slow ); 8995%} 8996 8997 8998//----------Double Instructions------------------------------------------------ 8999// Double Math 9000 9001// Compare & branch 9002 9003// P6 version of float compare, sets condition codes in EFLAGS 9004instruct cmpD_cc_P6(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{ 9005 predicate(VM_Version::supports_cmov() && UseSSE <=1); 9006 match(Set cr (CmpD src1 src2)); 9007 effect(KILL rax); 9008 ins_cost(150); 9009 format %{ "FLD $src1\n\t" 9010 "FUCOMIP ST,$src2 // P6 instruction\n\t" 9011 "JNP exit\n\t" 9012 "MOV ah,1 // saw a NaN, set CF\n\t" 9013 "SAHF\n" 9014 "exit:\tNOP // avoid branch to branch" %} 9015 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 9016 ins_encode( Push_Reg_D(src1), 9017 OpcP, RegOpc(src2), 9018 cmpF_P6_fixup ); 9019 ins_pipe( pipe_slow ); 9020%} 9021 9022// Compare & branch 9023instruct cmpD_cc(eFlagsRegU cr, regD src1, regD src2, eAXRegI rax) %{ 9024 predicate(UseSSE<=1); 9025 match(Set cr (CmpD src1 src2)); 9026 effect(KILL rax); 9027 ins_cost(200); 9028 format %{ "FLD $src1\n\t" 9029 "FCOMp $src2\n\t" 9030 "FNSTSW AX\n\t" 9031 "TEST AX,0x400\n\t" 9032 "JZ,s flags\n\t" 9033 "MOV AH,1\t# unordered treat as LT\n" 9034 "flags:\tSAHF" %} 9035 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 9036 ins_encode( Push_Reg_D(src1), 9037 OpcP, RegOpc(src2), 9038 fpu_flags); 9039 ins_pipe( pipe_slow ); 9040%} 9041 9042// Compare vs zero into -1,0,1 9043instruct cmpD_0(eRegI dst, regD src1, immD0 zero, eAXRegI rax, eFlagsReg cr) %{ 9044 predicate(UseSSE<=1); 9045 match(Set dst (CmpD3 src1 zero)); 9046 effect(KILL cr, KILL rax); 9047 ins_cost(280); 9048 format %{ "FTSTD $dst,$src1" %} 9049 opcode(0xE4, 0xD9); 9050 ins_encode( Push_Reg_D(src1), 9051 OpcS, OpcP, PopFPU, 9052 CmpF_Result(dst)); 9053 ins_pipe( pipe_slow ); 9054%} 9055 9056// Compare into -1,0,1 9057instruct cmpD_reg(eRegI dst, regD src1, regD src2, eAXRegI rax, eFlagsReg cr) %{ 9058 predicate(UseSSE<=1); 9059 match(Set dst (CmpD3 src1 src2)); 9060 effect(KILL cr, KILL rax); 9061 ins_cost(300); 9062 format %{ "FCMPD $dst,$src1,$src2" %} 9063 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 9064 ins_encode( Push_Reg_D(src1), 9065 OpcP, RegOpc(src2), 9066 CmpF_Result(dst)); 9067 ins_pipe( pipe_slow ); 9068%} 9069 9070// float compare and set condition codes in EFLAGS by XMM regs 9071instruct cmpXD_cc(eFlagsRegU cr, regXD dst, regXD src, eAXRegI rax) %{ 9072 predicate(UseSSE>=2); 9073 match(Set cr (CmpD dst src)); 9074 effect(KILL rax); 9075 ins_cost(125); 9076 format %{ "COMISD $dst,$src\n" 9077 "\tJNP exit\n" 9078 "\tMOV ah,1 // saw a NaN, set CF\n" 9079 "\tSAHF\n" 9080 "exit:\tNOP // avoid branch to branch" %} 9081 opcode(0x66, 0x0F, 0x2F); 9082 ins_encode(OpcP, OpcS, Opcode(tertiary), RegReg(dst, src), cmpF_P6_fixup); 9083 ins_pipe( pipe_slow ); 9084%} 9085 9086// float compare and set condition codes in EFLAGS by XMM regs 9087instruct cmpXD_ccmem(eFlagsRegU cr, regXD dst, memory src, eAXRegI rax) %{ 9088 predicate(UseSSE>=2); 9089 match(Set cr (CmpD dst (LoadD src))); 9090 effect(KILL rax); 9091 ins_cost(145); 9092 format %{ "COMISD $dst,$src\n" 9093 "\tJNP exit\n" 9094 "\tMOV ah,1 // saw a NaN, set CF\n" 9095 "\tSAHF\n" 9096 "exit:\tNOP // avoid branch to branch" %} 9097 opcode(0x66, 0x0F, 0x2F); 9098 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(dst, src), cmpF_P6_fixup); 9099 ins_pipe( pipe_slow ); 9100%} 9101 9102// Compare into -1,0,1 in XMM 9103instruct cmpXD_reg(eRegI dst, regXD src1, regXD src2, eFlagsReg cr) %{ 9104 predicate(UseSSE>=2); 9105 match(Set dst (CmpD3 src1 src2)); 9106 effect(KILL cr); 9107 ins_cost(255); 9108 format %{ "XOR $dst,$dst\n" 9109 "\tCOMISD $src1,$src2\n" 9110 "\tJP,s nan\n" 9111 "\tJEQ,s exit\n" 9112 "\tJA,s inc\n" 9113 "nan:\tDEC $dst\n" 9114 "\tJMP,s exit\n" 9115 "inc:\tINC $dst\n" 9116 "exit:" 9117 %} 9118 opcode(0x66, 0x0F, 0x2F); 9119 ins_encode(Xor_Reg(dst), OpcP, OpcS, Opcode(tertiary), RegReg(src1, src2), 9120 CmpX_Result(dst)); 9121 ins_pipe( pipe_slow ); 9122%} 9123 9124// Compare into -1,0,1 in XMM and memory 9125instruct cmpXD_regmem(eRegI dst, regXD src1, memory mem, eFlagsReg cr) %{ 9126 predicate(UseSSE>=2); 9127 match(Set dst (CmpD3 src1 (LoadD mem))); 9128 effect(KILL cr); 9129 ins_cost(275); 9130 format %{ "COMISD $src1,$mem\n" 9131 "\tMOV $dst,0\t\t# do not blow flags\n" 9132 "\tJP,s nan\n" 9133 "\tJEQ,s exit\n" 9134 "\tJA,s inc\n" 9135 "nan:\tDEC $dst\n" 9136 "\tJMP,s exit\n" 9137 "inc:\tINC $dst\n" 9138 "exit:" 9139 %} 9140 opcode(0x66, 0x0F, 0x2F); 9141 ins_encode(OpcP, OpcS, Opcode(tertiary), RegMem(src1, mem), 9142 LdImmI(dst,0x0), CmpX_Result(dst)); 9143 ins_pipe( pipe_slow ); 9144%} 9145 9146 9147instruct subD_reg(regD dst, regD src) %{ 9148 predicate (UseSSE <=1); 9149 match(Set dst (SubD dst src)); 9150 9151 format %{ "FLD $src\n\t" 9152 "DSUBp $dst,ST" %} 9153 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ 9154 ins_cost(150); 9155 ins_encode( Push_Reg_D(src), 9156 OpcP, RegOpc(dst) ); 9157 ins_pipe( fpu_reg_reg ); 9158%} 9159 9160instruct subD_reg_round(stackSlotD dst, regD src1, regD src2) %{ 9161 predicate (UseSSE <=1); 9162 match(Set dst (RoundDouble (SubD src1 src2))); 9163 ins_cost(250); 9164 9165 format %{ "FLD $src2\n\t" 9166 "DSUB ST,$src1\n\t" 9167 "FSTP_D $dst\t# D-round" %} 9168 opcode(0xD8, 0x5); 9169 ins_encode( Push_Reg_D(src2), 9170 OpcP, RegOpc(src1), Pop_Mem_D(dst) ); 9171 ins_pipe( fpu_mem_reg_reg ); 9172%} 9173 9174 9175instruct subD_reg_mem(regD dst, memory src) %{ 9176 predicate (UseSSE <=1); 9177 match(Set dst (SubD dst (LoadD src))); 9178 ins_cost(150); 9179 9180 format %{ "FLD $src\n\t" 9181 "DSUBp $dst,ST" %} 9182 opcode(0xDE, 0x5, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ 9183 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 9184 OpcP, RegOpc(dst) ); 9185 ins_pipe( fpu_reg_mem ); 9186%} 9187 9188instruct absD_reg(regDPR1 dst, regDPR1 src) %{ 9189 predicate (UseSSE<=1); 9190 match(Set dst (AbsD src)); 9191 ins_cost(100); 9192 format %{ "FABS" %} 9193 opcode(0xE1, 0xD9); 9194 ins_encode( OpcS, OpcP ); 9195 ins_pipe( fpu_reg_reg ); 9196%} 9197 9198instruct absXD_reg( regXD dst ) %{ 9199 predicate(UseSSE>=2); 9200 match(Set dst (AbsD dst)); 9201 format %{ "ANDPD $dst,[0x7FFFFFFFFFFFFFFF]\t# ABS D by sign masking" %} 9202 ins_encode( AbsXD_encoding(dst)); 9203 ins_pipe( pipe_slow ); 9204%} 9205 9206instruct negD_reg(regDPR1 dst, regDPR1 src) %{ 9207 predicate(UseSSE<=1); 9208 match(Set dst (NegD src)); 9209 ins_cost(100); 9210 format %{ "FCHS" %} 9211 opcode(0xE0, 0xD9); 9212 ins_encode( OpcS, OpcP ); 9213 ins_pipe( fpu_reg_reg ); 9214%} 9215 9216instruct negXD_reg( regXD dst ) %{ 9217 predicate(UseSSE>=2); 9218 match(Set dst (NegD dst)); 9219 format %{ "XORPD $dst,[0x8000000000000000]\t# CHS D by sign flipping" %} 9220 ins_encode %{ 9221 __ xorpd($dst$$XMMRegister, 9222 ExternalAddress((address)double_signflip_pool)); 9223 %} 9224 ins_pipe( pipe_slow ); 9225%} 9226 9227instruct addD_reg(regD dst, regD src) %{ 9228 predicate(UseSSE<=1); 9229 match(Set dst (AddD dst src)); 9230 format %{ "FLD $src\n\t" 9231 "DADD $dst,ST" %} 9232 size(4); 9233 ins_cost(150); 9234 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ 9235 ins_encode( Push_Reg_D(src), 9236 OpcP, RegOpc(dst) ); 9237 ins_pipe( fpu_reg_reg ); 9238%} 9239 9240 9241instruct addD_reg_round(stackSlotD dst, regD src1, regD src2) %{ 9242 predicate(UseSSE<=1); 9243 match(Set dst (RoundDouble (AddD src1 src2))); 9244 ins_cost(250); 9245 9246 format %{ "FLD $src2\n\t" 9247 "DADD ST,$src1\n\t" 9248 "FSTP_D $dst\t# D-round" %} 9249 opcode(0xD8, 0x0); /* D8 C0+i or D8 /0*/ 9250 ins_encode( Push_Reg_D(src2), 9251 OpcP, RegOpc(src1), Pop_Mem_D(dst) ); 9252 ins_pipe( fpu_mem_reg_reg ); 9253%} 9254 9255 9256instruct addD_reg_mem(regD dst, memory src) %{ 9257 predicate(UseSSE<=1); 9258 match(Set dst (AddD dst (LoadD src))); 9259 ins_cost(150); 9260 9261 format %{ "FLD $src\n\t" 9262 "DADDp $dst,ST" %} 9263 opcode(0xDE, 0x0, 0xDD); /* DE C0+i */ /* LoadD DD /0 */ 9264 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 9265 OpcP, RegOpc(dst) ); 9266 ins_pipe( fpu_reg_mem ); 9267%} 9268 9269// add-to-memory 9270instruct addD_mem_reg(memory dst, regD src) %{ 9271 predicate(UseSSE<=1); 9272 match(Set dst (StoreD dst (RoundDouble (AddD (LoadD dst) src)))); 9273 ins_cost(150); 9274 9275 format %{ "FLD_D $dst\n\t" 9276 "DADD ST,$src\n\t" 9277 "FST_D $dst" %} 9278 opcode(0xDD, 0x0); 9279 ins_encode( Opcode(0xDD), RMopc_Mem(0x00,dst), 9280 Opcode(0xD8), RegOpc(src), 9281 set_instruction_start, 9282 Opcode(0xDD), RMopc_Mem(0x03,dst) ); 9283 ins_pipe( fpu_reg_mem ); 9284%} 9285 9286instruct addD_reg_imm1(regD dst, immD1 src) %{ 9287 predicate(UseSSE<=1); 9288 match(Set dst (AddD dst src)); 9289 ins_cost(125); 9290 format %{ "FLD1\n\t" 9291 "DADDp $dst,ST" %} 9292 opcode(0xDE, 0x00); 9293 ins_encode( LdImmD(src), 9294 OpcP, RegOpc(dst) ); 9295 ins_pipe( fpu_reg ); 9296%} 9297 9298instruct addD_reg_imm(regD dst, immD src) %{ 9299 predicate(UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); 9300 match(Set dst (AddD dst src)); 9301 ins_cost(200); 9302 format %{ "FLD_D [$src]\n\t" 9303 "DADDp $dst,ST" %} 9304 opcode(0xDE, 0x00); /* DE /0 */ 9305 ins_encode( LdImmD(src), 9306 OpcP, RegOpc(dst)); 9307 ins_pipe( fpu_reg_mem ); 9308%} 9309 9310instruct addD_reg_imm_round(stackSlotD dst, regD src, immD con) %{ 9311 predicate(UseSSE<=1 && _kids[0]->_kids[1]->_leaf->getd() != 0.0 && _kids[0]->_kids[1]->_leaf->getd() != 1.0 ); 9312 match(Set dst (RoundDouble (AddD src con))); 9313 ins_cost(200); 9314 format %{ "FLD_D [$con]\n\t" 9315 "DADD ST,$src\n\t" 9316 "FSTP_D $dst\t# D-round" %} 9317 opcode(0xD8, 0x00); /* D8 /0 */ 9318 ins_encode( LdImmD(con), 9319 OpcP, RegOpc(src), Pop_Mem_D(dst)); 9320 ins_pipe( fpu_mem_reg_con ); 9321%} 9322 9323// Add two double precision floating point values in xmm 9324instruct addXD_reg(regXD dst, regXD src) %{ 9325 predicate(UseSSE>=2); 9326 match(Set dst (AddD dst src)); 9327 format %{ "ADDSD $dst,$src" %} 9328 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegReg(dst, src)); 9329 ins_pipe( pipe_slow ); 9330%} 9331 9332instruct addXD_imm(regXD dst, immXD con) %{ 9333 predicate(UseSSE>=2); 9334 match(Set dst (AddD dst con)); 9335 format %{ "ADDSD $dst,[$con]" %} 9336 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), LdImmXD(dst, con) ); 9337 ins_pipe( pipe_slow ); 9338%} 9339 9340instruct addXD_mem(regXD dst, memory mem) %{ 9341 predicate(UseSSE>=2); 9342 match(Set dst (AddD dst (LoadD mem))); 9343 format %{ "ADDSD $dst,$mem" %} 9344 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x58), RegMem(dst,mem)); 9345 ins_pipe( pipe_slow ); 9346%} 9347 9348// Sub two double precision floating point values in xmm 9349instruct subXD_reg(regXD dst, regXD src) %{ 9350 predicate(UseSSE>=2); 9351 match(Set dst (SubD dst src)); 9352 format %{ "SUBSD $dst,$src" %} 9353 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src)); 9354 ins_pipe( pipe_slow ); 9355%} 9356 9357instruct subXD_imm(regXD dst, immXD con) %{ 9358 predicate(UseSSE>=2); 9359 match(Set dst (SubD dst con)); 9360 format %{ "SUBSD $dst,[$con]" %} 9361 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), LdImmXD(dst, con) ); 9362 ins_pipe( pipe_slow ); 9363%} 9364 9365instruct subXD_mem(regXD dst, memory mem) %{ 9366 predicate(UseSSE>=2); 9367 match(Set dst (SubD dst (LoadD mem))); 9368 format %{ "SUBSD $dst,$mem" %} 9369 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem)); 9370 ins_pipe( pipe_slow ); 9371%} 9372 9373// Mul two double precision floating point values in xmm 9374instruct mulXD_reg(regXD dst, regXD src) %{ 9375 predicate(UseSSE>=2); 9376 match(Set dst (MulD dst src)); 9377 format %{ "MULSD $dst,$src" %} 9378 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegReg(dst, src)); 9379 ins_pipe( pipe_slow ); 9380%} 9381 9382instruct mulXD_imm(regXD dst, immXD con) %{ 9383 predicate(UseSSE>=2); 9384 match(Set dst (MulD dst con)); 9385 format %{ "MULSD $dst,[$con]" %} 9386 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), LdImmXD(dst, con) ); 9387 ins_pipe( pipe_slow ); 9388%} 9389 9390instruct mulXD_mem(regXD dst, memory mem) %{ 9391 predicate(UseSSE>=2); 9392 match(Set dst (MulD dst (LoadD mem))); 9393 format %{ "MULSD $dst,$mem" %} 9394 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem)); 9395 ins_pipe( pipe_slow ); 9396%} 9397 9398// Div two double precision floating point values in xmm 9399instruct divXD_reg(regXD dst, regXD src) %{ 9400 predicate(UseSSE>=2); 9401 match(Set dst (DivD dst src)); 9402 format %{ "DIVSD $dst,$src" %} 9403 opcode(0xF2, 0x0F, 0x5E); 9404 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src)); 9405 ins_pipe( pipe_slow ); 9406%} 9407 9408instruct divXD_imm(regXD dst, immXD con) %{ 9409 predicate(UseSSE>=2); 9410 match(Set dst (DivD dst con)); 9411 format %{ "DIVSD $dst,[$con]" %} 9412 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), LdImmXD(dst, con)); 9413 ins_pipe( pipe_slow ); 9414%} 9415 9416instruct divXD_mem(regXD dst, memory mem) %{ 9417 predicate(UseSSE>=2); 9418 match(Set dst (DivD dst (LoadD mem))); 9419 format %{ "DIVSD $dst,$mem" %} 9420 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem)); 9421 ins_pipe( pipe_slow ); 9422%} 9423 9424 9425instruct mulD_reg(regD dst, regD src) %{ 9426 predicate(UseSSE<=1); 9427 match(Set dst (MulD dst src)); 9428 format %{ "FLD $src\n\t" 9429 "DMULp $dst,ST" %} 9430 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ 9431 ins_cost(150); 9432 ins_encode( Push_Reg_D(src), 9433 OpcP, RegOpc(dst) ); 9434 ins_pipe( fpu_reg_reg ); 9435%} 9436 9437// Strict FP instruction biases argument before multiply then 9438// biases result to avoid double rounding of subnormals. 9439// 9440// scale arg1 by multiplying arg1 by 2^(-15360) 9441// load arg2 9442// multiply scaled arg1 by arg2 9443// rescale product by 2^(15360) 9444// 9445instruct strictfp_mulD_reg(regDPR1 dst, regnotDPR1 src) %{ 9446 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); 9447 match(Set dst (MulD dst src)); 9448 ins_cost(1); // Select this instruction for all strict FP double multiplies 9449 9450 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" 9451 "DMULp $dst,ST\n\t" 9452 "FLD $src\n\t" 9453 "DMULp $dst,ST\n\t" 9454 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" 9455 "DMULp $dst,ST\n\t" %} 9456 opcode(0xDE, 0x1); /* DE C8+i or DE /1*/ 9457 ins_encode( strictfp_bias1(dst), 9458 Push_Reg_D(src), 9459 OpcP, RegOpc(dst), 9460 strictfp_bias2(dst) ); 9461 ins_pipe( fpu_reg_reg ); 9462%} 9463 9464instruct mulD_reg_imm(regD dst, immD src) %{ 9465 predicate( UseSSE<=1 && _kids[1]->_leaf->getd() != 0.0 && _kids[1]->_leaf->getd() != 1.0 ); 9466 match(Set dst (MulD dst src)); 9467 ins_cost(200); 9468 format %{ "FLD_D [$src]\n\t" 9469 "DMULp $dst,ST" %} 9470 opcode(0xDE, 0x1); /* DE /1 */ 9471 ins_encode( LdImmD(src), 9472 OpcP, RegOpc(dst) ); 9473 ins_pipe( fpu_reg_mem ); 9474%} 9475 9476 9477instruct mulD_reg_mem(regD dst, memory src) %{ 9478 predicate( UseSSE<=1 ); 9479 match(Set dst (MulD dst (LoadD src))); 9480 ins_cost(200); 9481 format %{ "FLD_D $src\n\t" 9482 "DMULp $dst,ST" %} 9483 opcode(0xDE, 0x1, 0xDD); /* DE C8+i or DE /1*/ /* LoadD DD /0 */ 9484 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 9485 OpcP, RegOpc(dst) ); 9486 ins_pipe( fpu_reg_mem ); 9487%} 9488 9489// 9490// Cisc-alternate to reg-reg multiply 9491instruct mulD_reg_mem_cisc(regD dst, regD src, memory mem) %{ 9492 predicate( UseSSE<=1 ); 9493 match(Set dst (MulD src (LoadD mem))); 9494 ins_cost(250); 9495 format %{ "FLD_D $mem\n\t" 9496 "DMUL ST,$src\n\t" 9497 "FSTP_D $dst" %} 9498 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadD D9 /0 */ 9499 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem), 9500 OpcReg_F(src), 9501 Pop_Reg_D(dst) ); 9502 ins_pipe( fpu_reg_reg_mem ); 9503%} 9504 9505 9506// MACRO3 -- addD a mulD 9507// This instruction is a '2-address' instruction in that the result goes 9508// back to src2. This eliminates a move from the macro; possibly the 9509// register allocator will have to add it back (and maybe not). 9510instruct addD_mulD_reg(regD src2, regD src1, regD src0) %{ 9511 predicate( UseSSE<=1 ); 9512 match(Set src2 (AddD (MulD src0 src1) src2)); 9513 format %{ "FLD $src0\t# ===MACRO3d===\n\t" 9514 "DMUL ST,$src1\n\t" 9515 "DADDp $src2,ST" %} 9516 ins_cost(250); 9517 opcode(0xDD); /* LoadD DD /0 */ 9518 ins_encode( Push_Reg_F(src0), 9519 FMul_ST_reg(src1), 9520 FAddP_reg_ST(src2) ); 9521 ins_pipe( fpu_reg_reg_reg ); 9522%} 9523 9524 9525// MACRO3 -- subD a mulD 9526instruct subD_mulD_reg(regD src2, regD src1, regD src0) %{ 9527 predicate( UseSSE<=1 ); 9528 match(Set src2 (SubD (MulD src0 src1) src2)); 9529 format %{ "FLD $src0\t# ===MACRO3d===\n\t" 9530 "DMUL ST,$src1\n\t" 9531 "DSUBRp $src2,ST" %} 9532 ins_cost(250); 9533 ins_encode( Push_Reg_F(src0), 9534 FMul_ST_reg(src1), 9535 Opcode(0xDE), Opc_plus(0xE0,src2)); 9536 ins_pipe( fpu_reg_reg_reg ); 9537%} 9538 9539 9540instruct divD_reg(regD dst, regD src) %{ 9541 predicate( UseSSE<=1 ); 9542 match(Set dst (DivD dst src)); 9543 9544 format %{ "FLD $src\n\t" 9545 "FDIVp $dst,ST" %} 9546 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 9547 ins_cost(150); 9548 ins_encode( Push_Reg_D(src), 9549 OpcP, RegOpc(dst) ); 9550 ins_pipe( fpu_reg_reg ); 9551%} 9552 9553// Strict FP instruction biases argument before division then 9554// biases result, to avoid double rounding of subnormals. 9555// 9556// scale dividend by multiplying dividend by 2^(-15360) 9557// load divisor 9558// divide scaled dividend by divisor 9559// rescale quotient by 2^(15360) 9560// 9561instruct strictfp_divD_reg(regDPR1 dst, regnotDPR1 src) %{ 9562 predicate (UseSSE<=1); 9563 match(Set dst (DivD dst src)); 9564 predicate( UseSSE<=1 && Compile::current()->has_method() && Compile::current()->method()->is_strict() ); 9565 ins_cost(01); 9566 9567 format %{ "FLD StubRoutines::_fpu_subnormal_bias1\n\t" 9568 "DMULp $dst,ST\n\t" 9569 "FLD $src\n\t" 9570 "FDIVp $dst,ST\n\t" 9571 "FLD StubRoutines::_fpu_subnormal_bias2\n\t" 9572 "DMULp $dst,ST\n\t" %} 9573 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 9574 ins_encode( strictfp_bias1(dst), 9575 Push_Reg_D(src), 9576 OpcP, RegOpc(dst), 9577 strictfp_bias2(dst) ); 9578 ins_pipe( fpu_reg_reg ); 9579%} 9580 9581instruct divD_reg_round(stackSlotD dst, regD src1, regD src2) %{ 9582 predicate( UseSSE<=1 && !(Compile::current()->has_method() && Compile::current()->method()->is_strict()) ); 9583 match(Set dst (RoundDouble (DivD src1 src2))); 9584 9585 format %{ "FLD $src1\n\t" 9586 "FDIV ST,$src2\n\t" 9587 "FSTP_D $dst\t# D-round" %} 9588 opcode(0xD8, 0x6); /* D8 F0+i or D8 /6 */ 9589 ins_encode( Push_Reg_D(src1), 9590 OpcP, RegOpc(src2), Pop_Mem_D(dst) ); 9591 ins_pipe( fpu_mem_reg_reg ); 9592%} 9593 9594 9595instruct modD_reg(regD dst, regD src, eAXRegI rax, eFlagsReg cr) %{ 9596 predicate(UseSSE<=1); 9597 match(Set dst (ModD dst src)); 9598 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS 9599 9600 format %{ "DMOD $dst,$src" %} 9601 ins_cost(250); 9602 ins_encode(Push_Reg_Mod_D(dst, src), 9603 emitModD(), 9604 Push_Result_Mod_D(src), 9605 Pop_Reg_D(dst)); 9606 ins_pipe( pipe_slow ); 9607%} 9608 9609instruct modXD_reg(regXD dst, regXD src0, regXD src1, eAXRegI rax, eFlagsReg cr) %{ 9610 predicate(UseSSE>=2); 9611 match(Set dst (ModD src0 src1)); 9612 effect(KILL rax, KILL cr); 9613 9614 format %{ "SUB ESP,8\t # DMOD\n" 9615 "\tMOVSD [ESP+0],$src1\n" 9616 "\tFLD_D [ESP+0]\n" 9617 "\tMOVSD [ESP+0],$src0\n" 9618 "\tFLD_D [ESP+0]\n" 9619 "loop:\tFPREM\n" 9620 "\tFWAIT\n" 9621 "\tFNSTSW AX\n" 9622 "\tSAHF\n" 9623 "\tJP loop\n" 9624 "\tFSTP_D [ESP+0]\n" 9625 "\tMOVSD $dst,[ESP+0]\n" 9626 "\tADD ESP,8\n" 9627 "\tFSTP ST0\t # Restore FPU Stack" 9628 %} 9629 ins_cost(250); 9630 ins_encode( Push_ModD_encoding(src0, src1), emitModD(), Push_ResultXD(dst), PopFPU); 9631 ins_pipe( pipe_slow ); 9632%} 9633 9634instruct sinD_reg(regDPR1 dst, regDPR1 src) %{ 9635 predicate (UseSSE<=1); 9636 match(Set dst (SinD src)); 9637 ins_cost(1800); 9638 format %{ "DSIN $dst" %} 9639 opcode(0xD9, 0xFE); 9640 ins_encode( OpcP, OpcS ); 9641 ins_pipe( pipe_slow ); 9642%} 9643 9644instruct sinXD_reg(regXD dst, eFlagsReg cr) %{ 9645 predicate (UseSSE>=2); 9646 match(Set dst (SinD dst)); 9647 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" 9648 ins_cost(1800); 9649 format %{ "DSIN $dst" %} 9650 opcode(0xD9, 0xFE); 9651 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); 9652 ins_pipe( pipe_slow ); 9653%} 9654 9655instruct cosD_reg(regDPR1 dst, regDPR1 src) %{ 9656 predicate (UseSSE<=1); 9657 match(Set dst (CosD src)); 9658 ins_cost(1800); 9659 format %{ "DCOS $dst" %} 9660 opcode(0xD9, 0xFF); 9661 ins_encode( OpcP, OpcS ); 9662 ins_pipe( pipe_slow ); 9663%} 9664 9665instruct cosXD_reg(regXD dst, eFlagsReg cr) %{ 9666 predicate (UseSSE>=2); 9667 match(Set dst (CosD dst)); 9668 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" 9669 ins_cost(1800); 9670 format %{ "DCOS $dst" %} 9671 opcode(0xD9, 0xFF); 9672 ins_encode( Push_SrcXD(dst), OpcP, OpcS, Push_ResultXD(dst) ); 9673 ins_pipe( pipe_slow ); 9674%} 9675 9676instruct tanD_reg(regDPR1 dst, regDPR1 src) %{ 9677 predicate (UseSSE<=1); 9678 match(Set dst(TanD src)); 9679 format %{ "DTAN $dst" %} 9680 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan 9681 Opcode(0xDD), Opcode(0xD8)); // fstp st 9682 ins_pipe( pipe_slow ); 9683%} 9684 9685instruct tanXD_reg(regXD dst, eFlagsReg cr) %{ 9686 predicate (UseSSE>=2); 9687 match(Set dst(TanD dst)); 9688 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" 9689 format %{ "DTAN $dst" %} 9690 ins_encode( Push_SrcXD(dst), 9691 Opcode(0xD9), Opcode(0xF2), // fptan 9692 Opcode(0xDD), Opcode(0xD8), // fstp st 9693 Push_ResultXD(dst) ); 9694 ins_pipe( pipe_slow ); 9695%} 9696 9697instruct atanD_reg(regD dst, regD src) %{ 9698 predicate (UseSSE<=1); 9699 match(Set dst(AtanD dst src)); 9700 format %{ "DATA $dst,$src" %} 9701 opcode(0xD9, 0xF3); 9702 ins_encode( Push_Reg_D(src), 9703 OpcP, OpcS, RegOpc(dst) ); 9704 ins_pipe( pipe_slow ); 9705%} 9706 9707instruct atanXD_reg(regXD dst, regXD src, eFlagsReg cr) %{ 9708 predicate (UseSSE>=2); 9709 match(Set dst(AtanD dst src)); 9710 effect(KILL cr); // Push_{Src|Result}XD() uses "{SUB|ADD} ESP,8" 9711 format %{ "DATA $dst,$src" %} 9712 opcode(0xD9, 0xF3); 9713 ins_encode( Push_SrcXD(src), 9714 OpcP, OpcS, Push_ResultXD(dst) ); 9715 ins_pipe( pipe_slow ); 9716%} 9717 9718instruct sqrtD_reg(regD dst, regD src) %{ 9719 predicate (UseSSE<=1); 9720 match(Set dst (SqrtD src)); 9721 format %{ "DSQRT $dst,$src" %} 9722 opcode(0xFA, 0xD9); 9723 ins_encode( Push_Reg_D(src), 9724 OpcS, OpcP, Pop_Reg_D(dst) ); 9725 ins_pipe( pipe_slow ); 9726%} 9727 9728instruct powD_reg(regD X, regDPR1 Y, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ 9729 predicate (UseSSE<=1); 9730 match(Set Y (PowD X Y)); // Raise X to the Yth power 9731 effect(KILL rax, KILL rbx, KILL rcx); 9732 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" 9733 "FLD_D $X\n\t" 9734 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" 9735 9736 "FDUP \t\t\t# Q Q\n\t" 9737 "FRNDINT\t\t\t# int(Q) Q\n\t" 9738 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 9739 "FISTP dword [ESP]\n\t" 9740 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 9741 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 9742 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 9743 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 9744 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 9745 "ADD EAX,1023\t\t# Double exponent bias\n\t" 9746 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 9747 "SHL EAX,20\t\t# Shift exponent into place\n\t" 9748 "TEST EBX,ECX\t\t# Check for overflow\n\t" 9749 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 9750 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 9751 "MOV [ESP+0],0\n\t" 9752 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 9753 9754 "ADD ESP,8" 9755 %} 9756 ins_encode( push_stack_temp_qword, 9757 Push_Reg_D(X), 9758 Opcode(0xD9), Opcode(0xF1), // fyl2x 9759 pow_exp_core_encoding, 9760 pop_stack_temp_qword); 9761 ins_pipe( pipe_slow ); 9762%} 9763 9764instruct powXD_reg(regXD dst, regXD src0, regXD src1, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx ) %{ 9765 predicate (UseSSE>=2); 9766 match(Set dst (PowD src0 src1)); // Raise src0 to the src1'th power 9767 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx ); 9768 format %{ "SUB ESP,8\t\t# Fast-path POW encoding\n\t" 9769 "MOVSD [ESP],$src1\n\t" 9770 "FLD FPR1,$src1\n\t" 9771 "MOVSD [ESP],$src0\n\t" 9772 "FLD FPR1,$src0\n\t" 9773 "FYL2X \t\t\t# Q=Y*ln2(X)\n\t" 9774 9775 "FDUP \t\t\t# Q Q\n\t" 9776 "FRNDINT\t\t\t# int(Q) Q\n\t" 9777 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 9778 "FISTP dword [ESP]\n\t" 9779 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 9780 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 9781 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 9782 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 9783 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 9784 "ADD EAX,1023\t\t# Double exponent bias\n\t" 9785 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 9786 "SHL EAX,20\t\t# Shift exponent into place\n\t" 9787 "TEST EBX,ECX\t\t# Check for overflow\n\t" 9788 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 9789 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 9790 "MOV [ESP+0],0\n\t" 9791 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 9792 9793 "FST_D [ESP]\n\t" 9794 "MOVSD $dst,[ESP]\n\t" 9795 "ADD ESP,8" 9796 %} 9797 ins_encode( push_stack_temp_qword, 9798 push_xmm_to_fpr1(src1), 9799 push_xmm_to_fpr1(src0), 9800 Opcode(0xD9), Opcode(0xF1), // fyl2x 9801 pow_exp_core_encoding, 9802 Push_ResultXD(dst) ); 9803 ins_pipe( pipe_slow ); 9804%} 9805 9806 9807instruct expD_reg(regDPR1 dpr1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ 9808 predicate (UseSSE<=1); 9809 match(Set dpr1 (ExpD dpr1)); 9810 effect(KILL rax, KILL rbx, KILL rcx); 9811 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding" 9812 "FLDL2E \t\t\t# Ld log2(e) X\n\t" 9813 "FMULP \t\t\t# Q=X*log2(e)\n\t" 9814 9815 "FDUP \t\t\t# Q Q\n\t" 9816 "FRNDINT\t\t\t# int(Q) Q\n\t" 9817 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 9818 "FISTP dword [ESP]\n\t" 9819 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 9820 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 9821 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 9822 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 9823 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 9824 "ADD EAX,1023\t\t# Double exponent bias\n\t" 9825 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 9826 "SHL EAX,20\t\t# Shift exponent into place\n\t" 9827 "TEST EBX,ECX\t\t# Check for overflow\n\t" 9828 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 9829 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 9830 "MOV [ESP+0],0\n\t" 9831 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 9832 9833 "ADD ESP,8" 9834 %} 9835 ins_encode( push_stack_temp_qword, 9836 Opcode(0xD9), Opcode(0xEA), // fldl2e 9837 Opcode(0xDE), Opcode(0xC9), // fmulp 9838 pow_exp_core_encoding, 9839 pop_stack_temp_qword); 9840 ins_pipe( pipe_slow ); 9841%} 9842 9843instruct expXD_reg(regXD dst, regXD src, regDPR1 tmp1, eAXRegI rax, eBXRegI rbx, eCXRegI rcx) %{ 9844 predicate (UseSSE>=2); 9845 match(Set dst (ExpD src)); 9846 effect(KILL tmp1, KILL rax, KILL rbx, KILL rcx); 9847 format %{ "SUB ESP,8\t\t# Fast-path EXP encoding\n\t" 9848 "MOVSD [ESP],$src\n\t" 9849 "FLDL2E \t\t\t# Ld log2(e) X\n\t" 9850 "FMULP \t\t\t# Q=X*log2(e) X\n\t" 9851 9852 "FDUP \t\t\t# Q Q\n\t" 9853 "FRNDINT\t\t\t# int(Q) Q\n\t" 9854 "FSUB ST(1),ST(0)\t# int(Q) frac(Q)\n\t" 9855 "FISTP dword [ESP]\n\t" 9856 "F2XM1 \t\t\t# 2^frac(Q)-1 int(Q)\n\t" 9857 "FLD1 \t\t\t# 1 2^frac(Q)-1 int(Q)\n\t" 9858 "FADDP \t\t\t# 2^frac(Q) int(Q)\n\t" // could use FADD [1.000] instead 9859 "MOV EAX,[ESP]\t# Pick up int(Q)\n\t" 9860 "MOV ECX,0xFFFFF800\t# Overflow mask\n\t" 9861 "ADD EAX,1023\t\t# Double exponent bias\n\t" 9862 "MOV EBX,EAX\t\t# Preshifted biased expo\n\t" 9863 "SHL EAX,20\t\t# Shift exponent into place\n\t" 9864 "TEST EBX,ECX\t\t# Check for overflow\n\t" 9865 "CMOVne EAX,ECX\t\t# If overflow, stuff NaN into EAX\n\t" 9866 "MOV [ESP+4],EAX\t# Marshal 64-bit scaling double\n\t" 9867 "MOV [ESP+0],0\n\t" 9868 "FMUL ST(0),[ESP+0]\t# Scale\n\t" 9869 9870 "FST_D [ESP]\n\t" 9871 "MOVSD $dst,[ESP]\n\t" 9872 "ADD ESP,8" 9873 %} 9874 ins_encode( Push_SrcXD(src), 9875 Opcode(0xD9), Opcode(0xEA), // fldl2e 9876 Opcode(0xDE), Opcode(0xC9), // fmulp 9877 pow_exp_core_encoding, 9878 Push_ResultXD(dst) ); 9879 ins_pipe( pipe_slow ); 9880%} 9881 9882 9883 9884instruct log10D_reg(regDPR1 dst, regDPR1 src) %{ 9885 predicate (UseSSE<=1); 9886 // The source Double operand on FPU stack 9887 match(Set dst (Log10D src)); 9888 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number 9889 // fxch ; swap ST(0) with ST(1) 9890 // fyl2x ; compute log_10(2) * log_2(x) 9891 format %{ "FLDLG2 \t\t\t#Log10\n\t" 9892 "FXCH \n\t" 9893 "FYL2X \t\t\t# Q=Log10*Log_2(x)" 9894 %} 9895 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 9896 Opcode(0xD9), Opcode(0xC9), // fxch 9897 Opcode(0xD9), Opcode(0xF1)); // fyl2x 9898 9899 ins_pipe( pipe_slow ); 9900%} 9901 9902instruct log10XD_reg(regXD dst, regXD src, eFlagsReg cr) %{ 9903 predicate (UseSSE>=2); 9904 effect(KILL cr); 9905 match(Set dst (Log10D src)); 9906 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number 9907 // fyl2x ; compute log_10(2) * log_2(x) 9908 format %{ "FLDLG2 \t\t\t#Log10\n\t" 9909 "FYL2X \t\t\t# Q=Log10*Log_2(x)" 9910 %} 9911 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2 9912 Push_SrcXD(src), 9913 Opcode(0xD9), Opcode(0xF1), // fyl2x 9914 Push_ResultXD(dst)); 9915 9916 ins_pipe( pipe_slow ); 9917%} 9918 9919instruct logD_reg(regDPR1 dst, regDPR1 src) %{ 9920 predicate (UseSSE<=1); 9921 // The source Double operand on FPU stack 9922 match(Set dst (LogD src)); 9923 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number 9924 // fxch ; swap ST(0) with ST(1) 9925 // fyl2x ; compute log_e(2) * log_2(x) 9926 format %{ "FLDLN2 \t\t\t#Log_e\n\t" 9927 "FXCH \n\t" 9928 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" 9929 %} 9930 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 9931 Opcode(0xD9), Opcode(0xC9), // fxch 9932 Opcode(0xD9), Opcode(0xF1)); // fyl2x 9933 9934 ins_pipe( pipe_slow ); 9935%} 9936 9937instruct logXD_reg(regXD dst, regXD src, eFlagsReg cr) %{ 9938 predicate (UseSSE>=2); 9939 effect(KILL cr); 9940 // The source and result Double operands in XMM registers 9941 match(Set dst (LogD src)); 9942 // fldln2 ; push log_e(2) on the FPU stack; full 80-bit number 9943 // fyl2x ; compute log_e(2) * log_2(x) 9944 format %{ "FLDLN2 \t\t\t#Log_e\n\t" 9945 "FYL2X \t\t\t# Q=Log_e*Log_2(x)" 9946 %} 9947 ins_encode( Opcode(0xD9), Opcode(0xED), // fldln2 9948 Push_SrcXD(src), 9949 Opcode(0xD9), Opcode(0xF1), // fyl2x 9950 Push_ResultXD(dst)); 9951 ins_pipe( pipe_slow ); 9952%} 9953 9954//-------------Float Instructions------------------------------- 9955// Float Math 9956 9957// Code for float compare: 9958// fcompp(); 9959// fwait(); fnstsw_ax(); 9960// sahf(); 9961// movl(dst, unordered_result); 9962// jcc(Assembler::parity, exit); 9963// movl(dst, less_result); 9964// jcc(Assembler::below, exit); 9965// movl(dst, equal_result); 9966// jcc(Assembler::equal, exit); 9967// movl(dst, greater_result); 9968// exit: 9969 9970// P6 version of float compare, sets condition codes in EFLAGS 9971instruct cmpF_cc_P6(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{ 9972 predicate(VM_Version::supports_cmov() && UseSSE == 0); 9973 match(Set cr (CmpF src1 src2)); 9974 effect(KILL rax); 9975 ins_cost(150); 9976 format %{ "FLD $src1\n\t" 9977 "FUCOMIP ST,$src2 // P6 instruction\n\t" 9978 "JNP exit\n\t" 9979 "MOV ah,1 // saw a NaN, set CF (treat as LT)\n\t" 9980 "SAHF\n" 9981 "exit:\tNOP // avoid branch to branch" %} 9982 opcode(0xDF, 0x05); /* DF E8+i or DF /5 */ 9983 ins_encode( Push_Reg_D(src1), 9984 OpcP, RegOpc(src2), 9985 cmpF_P6_fixup ); 9986 ins_pipe( pipe_slow ); 9987%} 9988 9989 9990// Compare & branch 9991instruct cmpF_cc(eFlagsRegU cr, regF src1, regF src2, eAXRegI rax) %{ 9992 predicate(UseSSE == 0); 9993 match(Set cr (CmpF src1 src2)); 9994 effect(KILL rax); 9995 ins_cost(200); 9996 format %{ "FLD $src1\n\t" 9997 "FCOMp $src2\n\t" 9998 "FNSTSW AX\n\t" 9999 "TEST AX,0x400\n\t" 10000 "JZ,s flags\n\t" 10001 "MOV AH,1\t# unordered treat as LT\n" 10002 "flags:\tSAHF" %} 10003 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 10004 ins_encode( Push_Reg_D(src1), 10005 OpcP, RegOpc(src2), 10006 fpu_flags); 10007 ins_pipe( pipe_slow ); 10008%} 10009 10010// Compare vs zero into -1,0,1 10011instruct cmpF_0(eRegI dst, regF src1, immF0 zero, eAXRegI rax, eFlagsReg cr) %{ 10012 predicate(UseSSE == 0); 10013 match(Set dst (CmpF3 src1 zero)); 10014 effect(KILL cr, KILL rax); 10015 ins_cost(280); 10016 format %{ "FTSTF $dst,$src1" %} 10017 opcode(0xE4, 0xD9); 10018 ins_encode( Push_Reg_D(src1), 10019 OpcS, OpcP, PopFPU, 10020 CmpF_Result(dst)); 10021 ins_pipe( pipe_slow ); 10022%} 10023 10024// Compare into -1,0,1 10025instruct cmpF_reg(eRegI dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{ 10026 predicate(UseSSE == 0); 10027 match(Set dst (CmpF3 src1 src2)); 10028 effect(KILL cr, KILL rax); 10029 ins_cost(300); 10030 format %{ "FCMPF $dst,$src1,$src2" %} 10031 opcode(0xD8, 0x3); /* D8 D8+i or D8 /3 */ 10032 ins_encode( Push_Reg_D(src1), 10033 OpcP, RegOpc(src2), 10034 CmpF_Result(dst)); 10035 ins_pipe( pipe_slow ); 10036%} 10037 10038// float compare and set condition codes in EFLAGS by XMM regs 10039instruct cmpX_cc(eFlagsRegU cr, regX dst, regX src, eAXRegI rax) %{ 10040 predicate(UseSSE>=1); 10041 match(Set cr (CmpF dst src)); 10042 effect(KILL rax); 10043 ins_cost(145); 10044 format %{ "COMISS $dst,$src\n" 10045 "\tJNP exit\n" 10046 "\tMOV ah,1 // saw a NaN, set CF\n" 10047 "\tSAHF\n" 10048 "exit:\tNOP // avoid branch to branch" %} 10049 opcode(0x0F, 0x2F); 10050 ins_encode(OpcP, OpcS, RegReg(dst, src), cmpF_P6_fixup); 10051 ins_pipe( pipe_slow ); 10052%} 10053 10054// float compare and set condition codes in EFLAGS by XMM regs 10055instruct cmpX_ccmem(eFlagsRegU cr, regX dst, memory src, eAXRegI rax) %{ 10056 predicate(UseSSE>=1); 10057 match(Set cr (CmpF dst (LoadF src))); 10058 effect(KILL rax); 10059 ins_cost(165); 10060 format %{ "COMISS $dst,$src\n" 10061 "\tJNP exit\n" 10062 "\tMOV ah,1 // saw a NaN, set CF\n" 10063 "\tSAHF\n" 10064 "exit:\tNOP // avoid branch to branch" %} 10065 opcode(0x0F, 0x2F); 10066 ins_encode(OpcP, OpcS, RegMem(dst, src), cmpF_P6_fixup); 10067 ins_pipe( pipe_slow ); 10068%} 10069 10070// Compare into -1,0,1 in XMM 10071instruct cmpX_reg(eRegI dst, regX src1, regX src2, eFlagsReg cr) %{ 10072 predicate(UseSSE>=1); 10073 match(Set dst (CmpF3 src1 src2)); 10074 effect(KILL cr); 10075 ins_cost(255); 10076 format %{ "XOR $dst,$dst\n" 10077 "\tCOMISS $src1,$src2\n" 10078 "\tJP,s nan\n" 10079 "\tJEQ,s exit\n" 10080 "\tJA,s inc\n" 10081 "nan:\tDEC $dst\n" 10082 "\tJMP,s exit\n" 10083 "inc:\tINC $dst\n" 10084 "exit:" 10085 %} 10086 opcode(0x0F, 0x2F); 10087 ins_encode(Xor_Reg(dst), OpcP, OpcS, RegReg(src1, src2), CmpX_Result(dst)); 10088 ins_pipe( pipe_slow ); 10089%} 10090 10091// Compare into -1,0,1 in XMM and memory 10092instruct cmpX_regmem(eRegI dst, regX src1, memory mem, eFlagsReg cr) %{ 10093 predicate(UseSSE>=1); 10094 match(Set dst (CmpF3 src1 (LoadF mem))); 10095 effect(KILL cr); 10096 ins_cost(275); 10097 format %{ "COMISS $src1,$mem\n" 10098 "\tMOV $dst,0\t\t# do not blow flags\n" 10099 "\tJP,s nan\n" 10100 "\tJEQ,s exit\n" 10101 "\tJA,s inc\n" 10102 "nan:\tDEC $dst\n" 10103 "\tJMP,s exit\n" 10104 "inc:\tINC $dst\n" 10105 "exit:" 10106 %} 10107 opcode(0x0F, 0x2F); 10108 ins_encode(OpcP, OpcS, RegMem(src1, mem), LdImmI(dst,0x0), CmpX_Result(dst)); 10109 ins_pipe( pipe_slow ); 10110%} 10111 10112// Spill to obtain 24-bit precision 10113instruct subF24_reg(stackSlotF dst, regF src1, regF src2) %{ 10114 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10115 match(Set dst (SubF src1 src2)); 10116 10117 format %{ "FSUB $dst,$src1 - $src2" %} 10118 opcode(0xD8, 0x4); /* D8 E0+i or D8 /4 mod==0x3 ;; result in TOS */ 10119 ins_encode( Push_Reg_F(src1), 10120 OpcReg_F(src2), 10121 Pop_Mem_F(dst) ); 10122 ins_pipe( fpu_mem_reg_reg ); 10123%} 10124// 10125// This instruction does not round to 24-bits 10126instruct subF_reg(regF dst, regF src) %{ 10127 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10128 match(Set dst (SubF dst src)); 10129 10130 format %{ "FSUB $dst,$src" %} 10131 opcode(0xDE, 0x5); /* DE E8+i or DE /5 */ 10132 ins_encode( Push_Reg_F(src), 10133 OpcP, RegOpc(dst) ); 10134 ins_pipe( fpu_reg_reg ); 10135%} 10136 10137// Spill to obtain 24-bit precision 10138instruct addF24_reg(stackSlotF dst, regF src1, regF src2) %{ 10139 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10140 match(Set dst (AddF src1 src2)); 10141 10142 format %{ "FADD $dst,$src1,$src2" %} 10143 opcode(0xD8, 0x0); /* D8 C0+i */ 10144 ins_encode( Push_Reg_F(src2), 10145 OpcReg_F(src1), 10146 Pop_Mem_F(dst) ); 10147 ins_pipe( fpu_mem_reg_reg ); 10148%} 10149// 10150// This instruction does not round to 24-bits 10151instruct addF_reg(regF dst, regF src) %{ 10152 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10153 match(Set dst (AddF dst src)); 10154 10155 format %{ "FLD $src\n\t" 10156 "FADDp $dst,ST" %} 10157 opcode(0xDE, 0x0); /* DE C0+i or DE /0*/ 10158 ins_encode( Push_Reg_F(src), 10159 OpcP, RegOpc(dst) ); 10160 ins_pipe( fpu_reg_reg ); 10161%} 10162 10163// Add two single precision floating point values in xmm 10164instruct addX_reg(regX dst, regX src) %{ 10165 predicate(UseSSE>=1); 10166 match(Set dst (AddF dst src)); 10167 format %{ "ADDSS $dst,$src" %} 10168 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegReg(dst, src)); 10169 ins_pipe( pipe_slow ); 10170%} 10171 10172instruct addX_imm(regX dst, immXF con) %{ 10173 predicate(UseSSE>=1); 10174 match(Set dst (AddF dst con)); 10175 format %{ "ADDSS $dst,[$con]" %} 10176 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), LdImmX(dst, con) ); 10177 ins_pipe( pipe_slow ); 10178%} 10179 10180instruct addX_mem(regX dst, memory mem) %{ 10181 predicate(UseSSE>=1); 10182 match(Set dst (AddF dst (LoadF mem))); 10183 format %{ "ADDSS $dst,$mem" %} 10184 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x58), RegMem(dst, mem)); 10185 ins_pipe( pipe_slow ); 10186%} 10187 10188// Subtract two single precision floating point values in xmm 10189instruct subX_reg(regX dst, regX src) %{ 10190 predicate(UseSSE>=1); 10191 match(Set dst (SubF dst src)); 10192 format %{ "SUBSS $dst,$src" %} 10193 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegReg(dst, src)); 10194 ins_pipe( pipe_slow ); 10195%} 10196 10197instruct subX_imm(regX dst, immXF con) %{ 10198 predicate(UseSSE>=1); 10199 match(Set dst (SubF dst con)); 10200 format %{ "SUBSS $dst,[$con]" %} 10201 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), LdImmX(dst, con) ); 10202 ins_pipe( pipe_slow ); 10203%} 10204 10205instruct subX_mem(regX dst, memory mem) %{ 10206 predicate(UseSSE>=1); 10207 match(Set dst (SubF dst (LoadF mem))); 10208 format %{ "SUBSS $dst,$mem" %} 10209 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5C), RegMem(dst,mem)); 10210 ins_pipe( pipe_slow ); 10211%} 10212 10213// Multiply two single precision floating point values in xmm 10214instruct mulX_reg(regX dst, regX src) %{ 10215 predicate(UseSSE>=1); 10216 match(Set dst (MulF dst src)); 10217 format %{ "MULSS $dst,$src" %} 10218 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegReg(dst, src)); 10219 ins_pipe( pipe_slow ); 10220%} 10221 10222instruct mulX_imm(regX dst, immXF con) %{ 10223 predicate(UseSSE>=1); 10224 match(Set dst (MulF dst con)); 10225 format %{ "MULSS $dst,[$con]" %} 10226 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), LdImmX(dst, con) ); 10227 ins_pipe( pipe_slow ); 10228%} 10229 10230instruct mulX_mem(regX dst, memory mem) %{ 10231 predicate(UseSSE>=1); 10232 match(Set dst (MulF dst (LoadF mem))); 10233 format %{ "MULSS $dst,$mem" %} 10234 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x59), RegMem(dst,mem)); 10235 ins_pipe( pipe_slow ); 10236%} 10237 10238// Divide two single precision floating point values in xmm 10239instruct divX_reg(regX dst, regX src) %{ 10240 predicate(UseSSE>=1); 10241 match(Set dst (DivF dst src)); 10242 format %{ "DIVSS $dst,$src" %} 10243 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegReg(dst, src)); 10244 ins_pipe( pipe_slow ); 10245%} 10246 10247instruct divX_imm(regX dst, immXF con) %{ 10248 predicate(UseSSE>=1); 10249 match(Set dst (DivF dst con)); 10250 format %{ "DIVSS $dst,[$con]" %} 10251 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), LdImmX(dst, con) ); 10252 ins_pipe( pipe_slow ); 10253%} 10254 10255instruct divX_mem(regX dst, memory mem) %{ 10256 predicate(UseSSE>=1); 10257 match(Set dst (DivF dst (LoadF mem))); 10258 format %{ "DIVSS $dst,$mem" %} 10259 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x5E), RegMem(dst,mem)); 10260 ins_pipe( pipe_slow ); 10261%} 10262 10263// Get the square root of a single precision floating point values in xmm 10264instruct sqrtX_reg(regX dst, regX src) %{ 10265 predicate(UseSSE>=1); 10266 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 10267 format %{ "SQRTSS $dst,$src" %} 10268 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegReg(dst, src)); 10269 ins_pipe( pipe_slow ); 10270%} 10271 10272instruct sqrtX_mem(regX dst, memory mem) %{ 10273 predicate(UseSSE>=1); 10274 match(Set dst (ConvD2F (SqrtD (ConvF2D (LoadF mem))))); 10275 format %{ "SQRTSS $dst,$mem" %} 10276 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem)); 10277 ins_pipe( pipe_slow ); 10278%} 10279 10280// Get the square root of a double precision floating point values in xmm 10281instruct sqrtXD_reg(regXD dst, regXD src) %{ 10282 predicate(UseSSE>=2); 10283 match(Set dst (SqrtD src)); 10284 format %{ "SQRTSD $dst,$src" %} 10285 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegReg(dst, src)); 10286 ins_pipe( pipe_slow ); 10287%} 10288 10289instruct sqrtXD_mem(regXD dst, memory mem) %{ 10290 predicate(UseSSE>=2); 10291 match(Set dst (SqrtD (LoadD mem))); 10292 format %{ "SQRTSD $dst,$mem" %} 10293 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x51), RegMem(dst, mem)); 10294 ins_pipe( pipe_slow ); 10295%} 10296 10297instruct absF_reg(regFPR1 dst, regFPR1 src) %{ 10298 predicate(UseSSE==0); 10299 match(Set dst (AbsF src)); 10300 ins_cost(100); 10301 format %{ "FABS" %} 10302 opcode(0xE1, 0xD9); 10303 ins_encode( OpcS, OpcP ); 10304 ins_pipe( fpu_reg_reg ); 10305%} 10306 10307instruct absX_reg(regX dst ) %{ 10308 predicate(UseSSE>=1); 10309 match(Set dst (AbsF dst)); 10310 format %{ "ANDPS $dst,[0x7FFFFFFF]\t# ABS F by sign masking" %} 10311 ins_encode( AbsXF_encoding(dst)); 10312 ins_pipe( pipe_slow ); 10313%} 10314 10315instruct negF_reg(regFPR1 dst, regFPR1 src) %{ 10316 predicate(UseSSE==0); 10317 match(Set dst (NegF src)); 10318 ins_cost(100); 10319 format %{ "FCHS" %} 10320 opcode(0xE0, 0xD9); 10321 ins_encode( OpcS, OpcP ); 10322 ins_pipe( fpu_reg_reg ); 10323%} 10324 10325instruct negX_reg( regX dst ) %{ 10326 predicate(UseSSE>=1); 10327 match(Set dst (NegF dst)); 10328 format %{ "XORPS $dst,[0x80000000]\t# CHS F by sign flipping" %} 10329 ins_encode( NegXF_encoding(dst)); 10330 ins_pipe( pipe_slow ); 10331%} 10332 10333// Cisc-alternate to addF_reg 10334// Spill to obtain 24-bit precision 10335instruct addF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{ 10336 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10337 match(Set dst (AddF src1 (LoadF src2))); 10338 10339 format %{ "FLD $src2\n\t" 10340 "FADD ST,$src1\n\t" 10341 "FSTP_S $dst" %} 10342 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 10343 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10344 OpcReg_F(src1), 10345 Pop_Mem_F(dst) ); 10346 ins_pipe( fpu_mem_reg_mem ); 10347%} 10348// 10349// Cisc-alternate to addF_reg 10350// This instruction does not round to 24-bits 10351instruct addF_reg_mem(regF dst, memory src) %{ 10352 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10353 match(Set dst (AddF dst (LoadF src))); 10354 10355 format %{ "FADD $dst,$src" %} 10356 opcode(0xDE, 0x0, 0xD9); /* DE C0+i or DE /0*/ /* LoadF D9 /0 */ 10357 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src), 10358 OpcP, RegOpc(dst) ); 10359 ins_pipe( fpu_reg_mem ); 10360%} 10361 10362// // Following two instructions for _222_mpegaudio 10363// Spill to obtain 24-bit precision 10364instruct addF24_mem_reg(stackSlotF dst, regF src2, memory src1 ) %{ 10365 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10366 match(Set dst (AddF src1 src2)); 10367 10368 format %{ "FADD $dst,$src1,$src2" %} 10369 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 10370 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src1), 10371 OpcReg_F(src2), 10372 Pop_Mem_F(dst) ); 10373 ins_pipe( fpu_mem_reg_mem ); 10374%} 10375 10376// Cisc-spill variant 10377// Spill to obtain 24-bit precision 10378instruct addF24_mem_cisc(stackSlotF dst, memory src1, memory src2) %{ 10379 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10380 match(Set dst (AddF src1 (LoadF src2))); 10381 10382 format %{ "FADD $dst,$src1,$src2 cisc" %} 10383 opcode(0xD8, 0x0, 0xD9); /* D8 C0+i */ /* LoadF D9 /0 */ 10384 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10385 set_instruction_start, 10386 OpcP, RMopc_Mem(secondary,src1), 10387 Pop_Mem_F(dst) ); 10388 ins_pipe( fpu_mem_mem_mem ); 10389%} 10390 10391// Spill to obtain 24-bit precision 10392instruct addF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ 10393 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10394 match(Set dst (AddF src1 src2)); 10395 10396 format %{ "FADD $dst,$src1,$src2" %} 10397 opcode(0xD8, 0x0, 0xD9); /* D8 /0 */ /* LoadF D9 /0 */ 10398 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10399 set_instruction_start, 10400 OpcP, RMopc_Mem(secondary,src1), 10401 Pop_Mem_F(dst) ); 10402 ins_pipe( fpu_mem_mem_mem ); 10403%} 10404 10405 10406// Spill to obtain 24-bit precision 10407instruct addF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{ 10408 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10409 match(Set dst (AddF src1 src2)); 10410 format %{ "FLD $src1\n\t" 10411 "FADD $src2\n\t" 10412 "FSTP_S $dst" %} 10413 opcode(0xD8, 0x00); /* D8 /0 */ 10414 ins_encode( Push_Reg_F(src1), 10415 Opc_MemImm_F(src2), 10416 Pop_Mem_F(dst)); 10417 ins_pipe( fpu_mem_reg_con ); 10418%} 10419// 10420// This instruction does not round to 24-bits 10421instruct addF_reg_imm(regF dst, regF src1, immF src2) %{ 10422 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10423 match(Set dst (AddF src1 src2)); 10424 format %{ "FLD $src1\n\t" 10425 "FADD $src2\n\t" 10426 "FSTP_S $dst" %} 10427 opcode(0xD8, 0x00); /* D8 /0 */ 10428 ins_encode( Push_Reg_F(src1), 10429 Opc_MemImm_F(src2), 10430 Pop_Reg_F(dst)); 10431 ins_pipe( fpu_reg_reg_con ); 10432%} 10433 10434// Spill to obtain 24-bit precision 10435instruct mulF24_reg(stackSlotF dst, regF src1, regF src2) %{ 10436 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10437 match(Set dst (MulF src1 src2)); 10438 10439 format %{ "FLD $src1\n\t" 10440 "FMUL $src2\n\t" 10441 "FSTP_S $dst" %} 10442 opcode(0xD8, 0x1); /* D8 C8+i or D8 /1 ;; result in TOS */ 10443 ins_encode( Push_Reg_F(src1), 10444 OpcReg_F(src2), 10445 Pop_Mem_F(dst) ); 10446 ins_pipe( fpu_mem_reg_reg ); 10447%} 10448// 10449// This instruction does not round to 24-bits 10450instruct mulF_reg(regF dst, regF src1, regF src2) %{ 10451 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10452 match(Set dst (MulF src1 src2)); 10453 10454 format %{ "FLD $src1\n\t" 10455 "FMUL $src2\n\t" 10456 "FSTP_S $dst" %} 10457 opcode(0xD8, 0x1); /* D8 C8+i */ 10458 ins_encode( Push_Reg_F(src2), 10459 OpcReg_F(src1), 10460 Pop_Reg_F(dst) ); 10461 ins_pipe( fpu_reg_reg_reg ); 10462%} 10463 10464 10465// Spill to obtain 24-bit precision 10466// Cisc-alternate to reg-reg multiply 10467instruct mulF24_reg_mem(stackSlotF dst, regF src1, memory src2) %{ 10468 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10469 match(Set dst (MulF src1 (LoadF src2))); 10470 10471 format %{ "FLD_S $src2\n\t" 10472 "FMUL $src1\n\t" 10473 "FSTP_S $dst" %} 10474 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or DE /1*/ /* LoadF D9 /0 */ 10475 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10476 OpcReg_F(src1), 10477 Pop_Mem_F(dst) ); 10478 ins_pipe( fpu_mem_reg_mem ); 10479%} 10480// 10481// This instruction does not round to 24-bits 10482// Cisc-alternate to reg-reg multiply 10483instruct mulF_reg_mem(regF dst, regF src1, memory src2) %{ 10484 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10485 match(Set dst (MulF src1 (LoadF src2))); 10486 10487 format %{ "FMUL $dst,$src1,$src2" %} 10488 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i */ /* LoadF D9 /0 */ 10489 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10490 OpcReg_F(src1), 10491 Pop_Reg_F(dst) ); 10492 ins_pipe( fpu_reg_reg_mem ); 10493%} 10494 10495// Spill to obtain 24-bit precision 10496instruct mulF24_mem_mem(stackSlotF dst, memory src1, memory src2) %{ 10497 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10498 match(Set dst (MulF src1 src2)); 10499 10500 format %{ "FMUL $dst,$src1,$src2" %} 10501 opcode(0xD8, 0x1, 0xD9); /* D8 /1 */ /* LoadF D9 /0 */ 10502 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,src2), 10503 set_instruction_start, 10504 OpcP, RMopc_Mem(secondary,src1), 10505 Pop_Mem_F(dst) ); 10506 ins_pipe( fpu_mem_mem_mem ); 10507%} 10508 10509// Spill to obtain 24-bit precision 10510instruct mulF24_reg_imm(stackSlotF dst, regF src1, immF src2) %{ 10511 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10512 match(Set dst (MulF src1 src2)); 10513 10514 format %{ "FMULc $dst,$src1,$src2" %} 10515 opcode(0xD8, 0x1); /* D8 /1*/ 10516 ins_encode( Push_Reg_F(src1), 10517 Opc_MemImm_F(src2), 10518 Pop_Mem_F(dst)); 10519 ins_pipe( fpu_mem_reg_con ); 10520%} 10521// 10522// This instruction does not round to 24-bits 10523instruct mulF_reg_imm(regF dst, regF src1, immF src2) %{ 10524 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10525 match(Set dst (MulF src1 src2)); 10526 10527 format %{ "FMULc $dst. $src1, $src2" %} 10528 opcode(0xD8, 0x1); /* D8 /1*/ 10529 ins_encode( Push_Reg_F(src1), 10530 Opc_MemImm_F(src2), 10531 Pop_Reg_F(dst)); 10532 ins_pipe( fpu_reg_reg_con ); 10533%} 10534 10535 10536// 10537// MACRO1 -- subsume unshared load into mulF 10538// This instruction does not round to 24-bits 10539instruct mulF_reg_load1(regF dst, regF src, memory mem1 ) %{ 10540 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10541 match(Set dst (MulF (LoadF mem1) src)); 10542 10543 format %{ "FLD $mem1 ===MACRO1===\n\t" 10544 "FMUL ST,$src\n\t" 10545 "FSTP $dst" %} 10546 opcode(0xD8, 0x1, 0xD9); /* D8 C8+i or D8 /1 */ /* LoadF D9 /0 */ 10547 ins_encode( Opcode(tertiary), RMopc_Mem(0x00,mem1), 10548 OpcReg_F(src), 10549 Pop_Reg_F(dst) ); 10550 ins_pipe( fpu_reg_reg_mem ); 10551%} 10552// 10553// MACRO2 -- addF a mulF which subsumed an unshared load 10554// This instruction does not round to 24-bits 10555instruct addF_mulF_reg_load1(regF dst, memory mem1, regF src1, regF src2) %{ 10556 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10557 match(Set dst (AddF (MulF (LoadF mem1) src1) src2)); 10558 ins_cost(95); 10559 10560 format %{ "FLD $mem1 ===MACRO2===\n\t" 10561 "FMUL ST,$src1 subsume mulF left load\n\t" 10562 "FADD ST,$src2\n\t" 10563 "FSTP $dst" %} 10564 opcode(0xD9); /* LoadF D9 /0 */ 10565 ins_encode( OpcP, RMopc_Mem(0x00,mem1), 10566 FMul_ST_reg(src1), 10567 FAdd_ST_reg(src2), 10568 Pop_Reg_F(dst) ); 10569 ins_pipe( fpu_reg_mem_reg_reg ); 10570%} 10571 10572// MACRO3 -- addF a mulF 10573// This instruction does not round to 24-bits. It is a '2-address' 10574// instruction in that the result goes back to src2. This eliminates 10575// a move from the macro; possibly the register allocator will have 10576// to add it back (and maybe not). 10577instruct addF_mulF_reg(regF src2, regF src1, regF src0) %{ 10578 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10579 match(Set src2 (AddF (MulF src0 src1) src2)); 10580 10581 format %{ "FLD $src0 ===MACRO3===\n\t" 10582 "FMUL ST,$src1\n\t" 10583 "FADDP $src2,ST" %} 10584 opcode(0xD9); /* LoadF D9 /0 */ 10585 ins_encode( Push_Reg_F(src0), 10586 FMul_ST_reg(src1), 10587 FAddP_reg_ST(src2) ); 10588 ins_pipe( fpu_reg_reg_reg ); 10589%} 10590 10591// MACRO4 -- divF subF 10592// This instruction does not round to 24-bits 10593instruct subF_divF_reg(regF dst, regF src1, regF src2, regF src3) %{ 10594 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10595 match(Set dst (DivF (SubF src2 src1) src3)); 10596 10597 format %{ "FLD $src2 ===MACRO4===\n\t" 10598 "FSUB ST,$src1\n\t" 10599 "FDIV ST,$src3\n\t" 10600 "FSTP $dst" %} 10601 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 10602 ins_encode( Push_Reg_F(src2), 10603 subF_divF_encode(src1,src3), 10604 Pop_Reg_F(dst) ); 10605 ins_pipe( fpu_reg_reg_reg_reg ); 10606%} 10607 10608// Spill to obtain 24-bit precision 10609instruct divF24_reg(stackSlotF dst, regF src1, regF src2) %{ 10610 predicate(UseSSE==0 && Compile::current()->select_24_bit_instr()); 10611 match(Set dst (DivF src1 src2)); 10612 10613 format %{ "FDIV $dst,$src1,$src2" %} 10614 opcode(0xD8, 0x6); /* D8 F0+i or DE /6*/ 10615 ins_encode( Push_Reg_F(src1), 10616 OpcReg_F(src2), 10617 Pop_Mem_F(dst) ); 10618 ins_pipe( fpu_mem_reg_reg ); 10619%} 10620// 10621// This instruction does not round to 24-bits 10622instruct divF_reg(regF dst, regF src) %{ 10623 predicate(UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10624 match(Set dst (DivF dst src)); 10625 10626 format %{ "FDIV $dst,$src" %} 10627 opcode(0xDE, 0x7); /* DE F8+i or DE /7*/ 10628 ins_encode( Push_Reg_F(src), 10629 OpcP, RegOpc(dst) ); 10630 ins_pipe( fpu_reg_reg ); 10631%} 10632 10633 10634// Spill to obtain 24-bit precision 10635instruct modF24_reg(stackSlotF dst, regF src1, regF src2, eAXRegI rax, eFlagsReg cr) %{ 10636 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 10637 match(Set dst (ModF src1 src2)); 10638 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS 10639 10640 format %{ "FMOD $dst,$src1,$src2" %} 10641 ins_encode( Push_Reg_Mod_D(src1, src2), 10642 emitModD(), 10643 Push_Result_Mod_D(src2), 10644 Pop_Mem_F(dst)); 10645 ins_pipe( pipe_slow ); 10646%} 10647// 10648// This instruction does not round to 24-bits 10649instruct modF_reg(regF dst, regF src, eAXRegI rax, eFlagsReg cr) %{ 10650 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 10651 match(Set dst (ModF dst src)); 10652 effect(KILL rax, KILL cr); // emitModD() uses EAX and EFLAGS 10653 10654 format %{ "FMOD $dst,$src" %} 10655 ins_encode(Push_Reg_Mod_D(dst, src), 10656 emitModD(), 10657 Push_Result_Mod_D(src), 10658 Pop_Reg_F(dst)); 10659 ins_pipe( pipe_slow ); 10660%} 10661 10662instruct modX_reg(regX dst, regX src0, regX src1, eAXRegI rax, eFlagsReg cr) %{ 10663 predicate(UseSSE>=1); 10664 match(Set dst (ModF src0 src1)); 10665 effect(KILL rax, KILL cr); 10666 format %{ "SUB ESP,4\t # FMOD\n" 10667 "\tMOVSS [ESP+0],$src1\n" 10668 "\tFLD_S [ESP+0]\n" 10669 "\tMOVSS [ESP+0],$src0\n" 10670 "\tFLD_S [ESP+0]\n" 10671 "loop:\tFPREM\n" 10672 "\tFWAIT\n" 10673 "\tFNSTSW AX\n" 10674 "\tSAHF\n" 10675 "\tJP loop\n" 10676 "\tFSTP_S [ESP+0]\n" 10677 "\tMOVSS $dst,[ESP+0]\n" 10678 "\tADD ESP,4\n" 10679 "\tFSTP ST0\t # Restore FPU Stack" 10680 %} 10681 ins_cost(250); 10682 ins_encode( Push_ModX_encoding(src0, src1), emitModD(), Push_ResultX(dst,0x4), PopFPU); 10683 ins_pipe( pipe_slow ); 10684%} 10685 10686 10687//----------Arithmetic Conversion Instructions--------------------------------- 10688// The conversions operations are all Alpha sorted. Please keep it that way! 10689 10690instruct roundFloat_mem_reg(stackSlotF dst, regF src) %{ 10691 predicate(UseSSE==0); 10692 match(Set dst (RoundFloat src)); 10693 ins_cost(125); 10694 format %{ "FST_S $dst,$src\t# F-round" %} 10695 ins_encode( Pop_Mem_Reg_F(dst, src) ); 10696 ins_pipe( fpu_mem_reg ); 10697%} 10698 10699instruct roundDouble_mem_reg(stackSlotD dst, regD src) %{ 10700 predicate(UseSSE<=1); 10701 match(Set dst (RoundDouble src)); 10702 ins_cost(125); 10703 format %{ "FST_D $dst,$src\t# D-round" %} 10704 ins_encode( Pop_Mem_Reg_D(dst, src) ); 10705 ins_pipe( fpu_mem_reg ); 10706%} 10707 10708// Force rounding to 24-bit precision and 6-bit exponent 10709instruct convD2F_reg(stackSlotF dst, regD src) %{ 10710 predicate(UseSSE==0); 10711 match(Set dst (ConvD2F src)); 10712 format %{ "FST_S $dst,$src\t# F-round" %} 10713 expand %{ 10714 roundFloat_mem_reg(dst,src); 10715 %} 10716%} 10717 10718// Force rounding to 24-bit precision and 6-bit exponent 10719instruct convD2X_reg(regX dst, regD src, eFlagsReg cr) %{ 10720 predicate(UseSSE==1); 10721 match(Set dst (ConvD2F src)); 10722 effect( KILL cr ); 10723 format %{ "SUB ESP,4\n\t" 10724 "FST_S [ESP],$src\t# F-round\n\t" 10725 "MOVSS $dst,[ESP]\n\t" 10726 "ADD ESP,4" %} 10727 ins_encode( D2X_encoding(dst, src) ); 10728 ins_pipe( pipe_slow ); 10729%} 10730 10731// Force rounding double precision to single precision 10732instruct convXD2X_reg(regX dst, regXD src) %{ 10733 predicate(UseSSE>=2); 10734 match(Set dst (ConvD2F src)); 10735 format %{ "CVTSD2SS $dst,$src\t# F-round" %} 10736 opcode(0xF2, 0x0F, 0x5A); 10737 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 10738 ins_pipe( pipe_slow ); 10739%} 10740 10741instruct convF2D_reg_reg(regD dst, regF src) %{ 10742 predicate(UseSSE==0); 10743 match(Set dst (ConvF2D src)); 10744 format %{ "FST_S $dst,$src\t# D-round" %} 10745 ins_encode( Pop_Reg_Reg_D(dst, src)); 10746 ins_pipe( fpu_reg_reg ); 10747%} 10748 10749instruct convF2D_reg(stackSlotD dst, regF src) %{ 10750 predicate(UseSSE==1); 10751 match(Set dst (ConvF2D src)); 10752 format %{ "FST_D $dst,$src\t# D-round" %} 10753 expand %{ 10754 roundDouble_mem_reg(dst,src); 10755 %} 10756%} 10757 10758instruct convX2D_reg(regD dst, regX src, eFlagsReg cr) %{ 10759 predicate(UseSSE==1); 10760 match(Set dst (ConvF2D src)); 10761 effect( KILL cr ); 10762 format %{ "SUB ESP,4\n\t" 10763 "MOVSS [ESP] $src\n\t" 10764 "FLD_S [ESP]\n\t" 10765 "ADD ESP,4\n\t" 10766 "FSTP $dst\t# D-round" %} 10767 ins_encode( X2D_encoding(dst, src), Pop_Reg_D(dst)); 10768 ins_pipe( pipe_slow ); 10769%} 10770 10771instruct convX2XD_reg(regXD dst, regX src) %{ 10772 predicate(UseSSE>=2); 10773 match(Set dst (ConvF2D src)); 10774 format %{ "CVTSS2SD $dst,$src\t# D-round" %} 10775 opcode(0xF3, 0x0F, 0x5A); 10776 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 10777 ins_pipe( pipe_slow ); 10778%} 10779 10780// Convert a double to an int. If the double is a NAN, stuff a zero in instead. 10781instruct convD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regD src, eFlagsReg cr ) %{ 10782 predicate(UseSSE<=1); 10783 match(Set dst (ConvD2I src)); 10784 effect( KILL tmp, KILL cr ); 10785 format %{ "FLD $src\t# Convert double to int \n\t" 10786 "FLDCW trunc mode\n\t" 10787 "SUB ESP,4\n\t" 10788 "FISTp [ESP + #0]\n\t" 10789 "FLDCW std/24-bit mode\n\t" 10790 "POP EAX\n\t" 10791 "CMP EAX,0x80000000\n\t" 10792 "JNE,s fast\n\t" 10793 "FLD_D $src\n\t" 10794 "CALL d2i_wrapper\n" 10795 "fast:" %} 10796 ins_encode( Push_Reg_D(src), D2I_encoding(src) ); 10797 ins_pipe( pipe_slow ); 10798%} 10799 10800// Convert a double to an int. If the double is a NAN, stuff a zero in instead. 10801instruct convXD2I_reg_reg( eAXRegI dst, eDXRegI tmp, regXD src, eFlagsReg cr ) %{ 10802 predicate(UseSSE>=2); 10803 match(Set dst (ConvD2I src)); 10804 effect( KILL tmp, KILL cr ); 10805 format %{ "CVTTSD2SI $dst, $src\n\t" 10806 "CMP $dst,0x80000000\n\t" 10807 "JNE,s fast\n\t" 10808 "SUB ESP, 8\n\t" 10809 "MOVSD [ESP], $src\n\t" 10810 "FLD_D [ESP]\n\t" 10811 "ADD ESP, 8\n\t" 10812 "CALL d2i_wrapper\n" 10813 "fast:" %} 10814 opcode(0x1); // double-precision conversion 10815 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst)); 10816 ins_pipe( pipe_slow ); 10817%} 10818 10819instruct convD2L_reg_reg( eADXRegL dst, regD src, eFlagsReg cr ) %{ 10820 predicate(UseSSE<=1); 10821 match(Set dst (ConvD2L src)); 10822 effect( KILL cr ); 10823 format %{ "FLD $src\t# Convert double to long\n\t" 10824 "FLDCW trunc mode\n\t" 10825 "SUB ESP,8\n\t" 10826 "FISTp [ESP + #0]\n\t" 10827 "FLDCW std/24-bit mode\n\t" 10828 "POP EAX\n\t" 10829 "POP EDX\n\t" 10830 "CMP EDX,0x80000000\n\t" 10831 "JNE,s fast\n\t" 10832 "TEST EAX,EAX\n\t" 10833 "JNE,s fast\n\t" 10834 "FLD $src\n\t" 10835 "CALL d2l_wrapper\n" 10836 "fast:" %} 10837 ins_encode( Push_Reg_D(src), D2L_encoding(src) ); 10838 ins_pipe( pipe_slow ); 10839%} 10840 10841// XMM lacks a float/double->long conversion, so use the old FPU stack. 10842instruct convXD2L_reg_reg( eADXRegL dst, regXD src, eFlagsReg cr ) %{ 10843 predicate (UseSSE>=2); 10844 match(Set dst (ConvD2L src)); 10845 effect( KILL cr ); 10846 format %{ "SUB ESP,8\t# Convert double to long\n\t" 10847 "MOVSD [ESP],$src\n\t" 10848 "FLD_D [ESP]\n\t" 10849 "FLDCW trunc mode\n\t" 10850 "FISTp [ESP + #0]\n\t" 10851 "FLDCW std/24-bit mode\n\t" 10852 "POP EAX\n\t" 10853 "POP EDX\n\t" 10854 "CMP EDX,0x80000000\n\t" 10855 "JNE,s fast\n\t" 10856 "TEST EAX,EAX\n\t" 10857 "JNE,s fast\n\t" 10858 "SUB ESP,8\n\t" 10859 "MOVSD [ESP],$src\n\t" 10860 "FLD_D [ESP]\n\t" 10861 "CALL d2l_wrapper\n" 10862 "fast:" %} 10863 ins_encode( XD2L_encoding(src) ); 10864 ins_pipe( pipe_slow ); 10865%} 10866 10867// Convert a double to an int. Java semantics require we do complex 10868// manglations in the corner cases. So we set the rounding mode to 10869// 'zero', store the darned double down as an int, and reset the 10870// rounding mode to 'nearest'. The hardware stores a flag value down 10871// if we would overflow or converted a NAN; we check for this and 10872// and go the slow path if needed. 10873instruct convF2I_reg_reg(eAXRegI dst, eDXRegI tmp, regF src, eFlagsReg cr ) %{ 10874 predicate(UseSSE==0); 10875 match(Set dst (ConvF2I src)); 10876 effect( KILL tmp, KILL cr ); 10877 format %{ "FLD $src\t# Convert float to int \n\t" 10878 "FLDCW trunc mode\n\t" 10879 "SUB ESP,4\n\t" 10880 "FISTp [ESP + #0]\n\t" 10881 "FLDCW std/24-bit mode\n\t" 10882 "POP EAX\n\t" 10883 "CMP EAX,0x80000000\n\t" 10884 "JNE,s fast\n\t" 10885 "FLD $src\n\t" 10886 "CALL d2i_wrapper\n" 10887 "fast:" %} 10888 // D2I_encoding works for F2I 10889 ins_encode( Push_Reg_F(src), D2I_encoding(src) ); 10890 ins_pipe( pipe_slow ); 10891%} 10892 10893// Convert a float in xmm to an int reg. 10894instruct convX2I_reg(eAXRegI dst, eDXRegI tmp, regX src, eFlagsReg cr ) %{ 10895 predicate(UseSSE>=1); 10896 match(Set dst (ConvF2I src)); 10897 effect( KILL tmp, KILL cr ); 10898 format %{ "CVTTSS2SI $dst, $src\n\t" 10899 "CMP $dst,0x80000000\n\t" 10900 "JNE,s fast\n\t" 10901 "SUB ESP, 4\n\t" 10902 "MOVSS [ESP], $src\n\t" 10903 "FLD [ESP]\n\t" 10904 "ADD ESP, 4\n\t" 10905 "CALL d2i_wrapper\n" 10906 "fast:" %} 10907 opcode(0x0); // single-precision conversion 10908 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x2C), FX2I_encoding(src,dst)); 10909 ins_pipe( pipe_slow ); 10910%} 10911 10912instruct convF2L_reg_reg( eADXRegL dst, regF src, eFlagsReg cr ) %{ 10913 predicate(UseSSE==0); 10914 match(Set dst (ConvF2L src)); 10915 effect( KILL cr ); 10916 format %{ "FLD $src\t# Convert float to long\n\t" 10917 "FLDCW trunc mode\n\t" 10918 "SUB ESP,8\n\t" 10919 "FISTp [ESP + #0]\n\t" 10920 "FLDCW std/24-bit mode\n\t" 10921 "POP EAX\n\t" 10922 "POP EDX\n\t" 10923 "CMP EDX,0x80000000\n\t" 10924 "JNE,s fast\n\t" 10925 "TEST EAX,EAX\n\t" 10926 "JNE,s fast\n\t" 10927 "FLD $src\n\t" 10928 "CALL d2l_wrapper\n" 10929 "fast:" %} 10930 // D2L_encoding works for F2L 10931 ins_encode( Push_Reg_F(src), D2L_encoding(src) ); 10932 ins_pipe( pipe_slow ); 10933%} 10934 10935// XMM lacks a float/double->long conversion, so use the old FPU stack. 10936instruct convX2L_reg_reg( eADXRegL dst, regX src, eFlagsReg cr ) %{ 10937 predicate (UseSSE>=1); 10938 match(Set dst (ConvF2L src)); 10939 effect( KILL cr ); 10940 format %{ "SUB ESP,8\t# Convert float to long\n\t" 10941 "MOVSS [ESP],$src\n\t" 10942 "FLD_S [ESP]\n\t" 10943 "FLDCW trunc mode\n\t" 10944 "FISTp [ESP + #0]\n\t" 10945 "FLDCW std/24-bit mode\n\t" 10946 "POP EAX\n\t" 10947 "POP EDX\n\t" 10948 "CMP EDX,0x80000000\n\t" 10949 "JNE,s fast\n\t" 10950 "TEST EAX,EAX\n\t" 10951 "JNE,s fast\n\t" 10952 "SUB ESP,4\t# Convert float to long\n\t" 10953 "MOVSS [ESP],$src\n\t" 10954 "FLD_S [ESP]\n\t" 10955 "ADD ESP,4\n\t" 10956 "CALL d2l_wrapper\n" 10957 "fast:" %} 10958 ins_encode( X2L_encoding(src) ); 10959 ins_pipe( pipe_slow ); 10960%} 10961 10962instruct convI2D_reg(regD dst, stackSlotI src) %{ 10963 predicate( UseSSE<=1 ); 10964 match(Set dst (ConvI2D src)); 10965 format %{ "FILD $src\n\t" 10966 "FSTP $dst" %} 10967 opcode(0xDB, 0x0); /* DB /0 */ 10968 ins_encode(Push_Mem_I(src), Pop_Reg_D(dst)); 10969 ins_pipe( fpu_reg_mem ); 10970%} 10971 10972instruct convI2XD_reg(regXD dst, eRegI src) %{ 10973 predicate( UseSSE>=2 && !UseXmmI2D ); 10974 match(Set dst (ConvI2D src)); 10975 format %{ "CVTSI2SD $dst,$src" %} 10976 opcode(0xF2, 0x0F, 0x2A); 10977 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 10978 ins_pipe( pipe_slow ); 10979%} 10980 10981instruct convI2XD_mem(regXD dst, memory mem) %{ 10982 predicate( UseSSE>=2 ); 10983 match(Set dst (ConvI2D (LoadI mem))); 10984 format %{ "CVTSI2SD $dst,$mem" %} 10985 opcode(0xF2, 0x0F, 0x2A); 10986 ins_encode( OpcP, OpcS, Opcode(tertiary), RegMem(dst, mem)); 10987 ins_pipe( pipe_slow ); 10988%} 10989 10990instruct convXI2XD_reg(regXD dst, eRegI src) 10991%{ 10992 predicate( UseSSE>=2 && UseXmmI2D ); 10993 match(Set dst (ConvI2D src)); 10994 10995 format %{ "MOVD $dst,$src\n\t" 10996 "CVTDQ2PD $dst,$dst\t# i2d" %} 10997 ins_encode %{ 10998 __ movd($dst$$XMMRegister, $src$$Register); 10999 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister); 11000 %} 11001 ins_pipe(pipe_slow); // XXX 11002%} 11003 11004instruct convI2D_mem(regD dst, memory mem) %{ 11005 predicate( UseSSE<=1 && !Compile::current()->select_24_bit_instr()); 11006 match(Set dst (ConvI2D (LoadI mem))); 11007 format %{ "FILD $mem\n\t" 11008 "FSTP $dst" %} 11009 opcode(0xDB); /* DB /0 */ 11010 ins_encode( OpcP, RMopc_Mem(0x00,mem), 11011 Pop_Reg_D(dst)); 11012 ins_pipe( fpu_reg_mem ); 11013%} 11014 11015// Convert a byte to a float; no rounding step needed. 11016instruct conv24I2F_reg(regF dst, stackSlotI src) %{ 11017 predicate( UseSSE==0 && n->in(1)->Opcode() == Op_AndI && n->in(1)->in(2)->is_Con() && n->in(1)->in(2)->get_int() == 255 ); 11018 match(Set dst (ConvI2F src)); 11019 format %{ "FILD $src\n\t" 11020 "FSTP $dst" %} 11021 11022 opcode(0xDB, 0x0); /* DB /0 */ 11023 ins_encode(Push_Mem_I(src), Pop_Reg_F(dst)); 11024 ins_pipe( fpu_reg_mem ); 11025%} 11026 11027// In 24-bit mode, force exponent rounding by storing back out 11028instruct convI2F_SSF(stackSlotF dst, stackSlotI src) %{ 11029 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 11030 match(Set dst (ConvI2F src)); 11031 ins_cost(200); 11032 format %{ "FILD $src\n\t" 11033 "FSTP_S $dst" %} 11034 opcode(0xDB, 0x0); /* DB /0 */ 11035 ins_encode( Push_Mem_I(src), 11036 Pop_Mem_F(dst)); 11037 ins_pipe( fpu_mem_mem ); 11038%} 11039 11040// In 24-bit mode, force exponent rounding by storing back out 11041instruct convI2F_SSF_mem(stackSlotF dst, memory mem) %{ 11042 predicate( UseSSE==0 && Compile::current()->select_24_bit_instr()); 11043 match(Set dst (ConvI2F (LoadI mem))); 11044 ins_cost(200); 11045 format %{ "FILD $mem\n\t" 11046 "FSTP_S $dst" %} 11047 opcode(0xDB); /* DB /0 */ 11048 ins_encode( OpcP, RMopc_Mem(0x00,mem), 11049 Pop_Mem_F(dst)); 11050 ins_pipe( fpu_mem_mem ); 11051%} 11052 11053// This instruction does not round to 24-bits 11054instruct convI2F_reg(regF dst, stackSlotI src) %{ 11055 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11056 match(Set dst (ConvI2F src)); 11057 format %{ "FILD $src\n\t" 11058 "FSTP $dst" %} 11059 opcode(0xDB, 0x0); /* DB /0 */ 11060 ins_encode( Push_Mem_I(src), 11061 Pop_Reg_F(dst)); 11062 ins_pipe( fpu_reg_mem ); 11063%} 11064 11065// This instruction does not round to 24-bits 11066instruct convI2F_mem(regF dst, memory mem) %{ 11067 predicate( UseSSE==0 && !Compile::current()->select_24_bit_instr()); 11068 match(Set dst (ConvI2F (LoadI mem))); 11069 format %{ "FILD $mem\n\t" 11070 "FSTP $dst" %} 11071 opcode(0xDB); /* DB /0 */ 11072 ins_encode( OpcP, RMopc_Mem(0x00,mem), 11073 Pop_Reg_F(dst)); 11074 ins_pipe( fpu_reg_mem ); 11075%} 11076 11077// Convert an int to a float in xmm; no rounding step needed. 11078instruct convI2X_reg(regX dst, eRegI src) %{ 11079 predicate( UseSSE==1 || UseSSE>=2 && !UseXmmI2F ); 11080 match(Set dst (ConvI2F src)); 11081 format %{ "CVTSI2SS $dst, $src" %} 11082 11083 opcode(0xF3, 0x0F, 0x2A); /* F3 0F 2A /r */ 11084 ins_encode( OpcP, OpcS, Opcode(tertiary), RegReg(dst, src)); 11085 ins_pipe( pipe_slow ); 11086%} 11087 11088 instruct convXI2X_reg(regX dst, eRegI src) 11089%{ 11090 predicate( UseSSE>=2 && UseXmmI2F ); 11091 match(Set dst (ConvI2F src)); 11092 11093 format %{ "MOVD $dst,$src\n\t" 11094 "CVTDQ2PS $dst,$dst\t# i2f" %} 11095 ins_encode %{ 11096 __ movd($dst$$XMMRegister, $src$$Register); 11097 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister); 11098 %} 11099 ins_pipe(pipe_slow); // XXX 11100%} 11101 11102instruct convI2L_reg( eRegL dst, eRegI src, eFlagsReg cr) %{ 11103 match(Set dst (ConvI2L src)); 11104 effect(KILL cr); 11105 format %{ "MOV $dst.lo,$src\n\t" 11106 "MOV $dst.hi,$src\n\t" 11107 "SAR $dst.hi,31" %} 11108 ins_encode(convert_int_long(dst,src)); 11109 ins_pipe( ialu_reg_reg_long ); 11110%} 11111 11112// Zero-extend convert int to long 11113instruct convI2L_reg_zex(eRegL dst, eRegI src, immL_32bits mask, eFlagsReg flags ) %{ 11114 match(Set dst (AndL (ConvI2L src) mask) ); 11115 effect( KILL flags ); 11116 format %{ "MOV $dst.lo,$src\n\t" 11117 "XOR $dst.hi,$dst.hi" %} 11118 opcode(0x33); // XOR 11119 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); 11120 ins_pipe( ialu_reg_reg_long ); 11121%} 11122 11123// Zero-extend long 11124instruct zerox_long(eRegL dst, eRegL src, immL_32bits mask, eFlagsReg flags ) %{ 11125 match(Set dst (AndL src mask) ); 11126 effect( KILL flags ); 11127 format %{ "MOV $dst.lo,$src.lo\n\t" 11128 "XOR $dst.hi,$dst.hi\n\t" %} 11129 opcode(0x33); // XOR 11130 ins_encode(enc_Copy(dst,src), OpcP, RegReg_Hi2(dst,dst) ); 11131 ins_pipe( ialu_reg_reg_long ); 11132%} 11133 11134instruct convL2D_reg( stackSlotD dst, eRegL src, eFlagsReg cr) %{ 11135 predicate (UseSSE<=1); 11136 match(Set dst (ConvL2D src)); 11137 effect( KILL cr ); 11138 format %{ "PUSH $src.hi\t# Convert long to double\n\t" 11139 "PUSH $src.lo\n\t" 11140 "FILD ST,[ESP + #0]\n\t" 11141 "ADD ESP,8\n\t" 11142 "FSTP_D $dst\t# D-round" %} 11143 opcode(0xDF, 0x5); /* DF /5 */ 11144 ins_encode(convert_long_double(src), Pop_Mem_D(dst)); 11145 ins_pipe( pipe_slow ); 11146%} 11147 11148instruct convL2XD_reg( regXD dst, eRegL src, eFlagsReg cr) %{ 11149 predicate (UseSSE>=2); 11150 match(Set dst (ConvL2D src)); 11151 effect( KILL cr ); 11152 format %{ "PUSH $src.hi\t# Convert long to double\n\t" 11153 "PUSH $src.lo\n\t" 11154 "FILD_D [ESP]\n\t" 11155 "FSTP_D [ESP]\n\t" 11156 "MOVSD $dst,[ESP]\n\t" 11157 "ADD ESP,8" %} 11158 opcode(0xDF, 0x5); /* DF /5 */ 11159 ins_encode(convert_long_double2(src), Push_ResultXD(dst)); 11160 ins_pipe( pipe_slow ); 11161%} 11162 11163instruct convL2X_reg( regX dst, eRegL src, eFlagsReg cr) %{ 11164 predicate (UseSSE>=1); 11165 match(Set dst (ConvL2F src)); 11166 effect( KILL cr ); 11167 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" 11168 "PUSH $src.lo\n\t" 11169 "FILD_D [ESP]\n\t" 11170 "FSTP_S [ESP]\n\t" 11171 "MOVSS $dst,[ESP]\n\t" 11172 "ADD ESP,8" %} 11173 opcode(0xDF, 0x5); /* DF /5 */ 11174 ins_encode(convert_long_double2(src), Push_ResultX(dst,0x8)); 11175 ins_pipe( pipe_slow ); 11176%} 11177 11178instruct convL2F_reg( stackSlotF dst, eRegL src, eFlagsReg cr) %{ 11179 match(Set dst (ConvL2F src)); 11180 effect( KILL cr ); 11181 format %{ "PUSH $src.hi\t# Convert long to single float\n\t" 11182 "PUSH $src.lo\n\t" 11183 "FILD ST,[ESP + #0]\n\t" 11184 "ADD ESP,8\n\t" 11185 "FSTP_S $dst\t# F-round" %} 11186 opcode(0xDF, 0x5); /* DF /5 */ 11187 ins_encode(convert_long_double(src), Pop_Mem_F(dst)); 11188 ins_pipe( pipe_slow ); 11189%} 11190 11191instruct convL2I_reg( eRegI dst, eRegL src ) %{ 11192 match(Set dst (ConvL2I src)); 11193 effect( DEF dst, USE src ); 11194 format %{ "MOV $dst,$src.lo" %} 11195 ins_encode(enc_CopyL_Lo(dst,src)); 11196 ins_pipe( ialu_reg_reg ); 11197%} 11198 11199 11200instruct MoveF2I_stack_reg(eRegI dst, stackSlotF src) %{ 11201 match(Set dst (MoveF2I src)); 11202 effect( DEF dst, USE src ); 11203 ins_cost(100); 11204 format %{ "MOV $dst,$src\t# MoveF2I_stack_reg" %} 11205 opcode(0x8B); 11206 ins_encode( OpcP, RegMem(dst,src)); 11207 ins_pipe( ialu_reg_mem ); 11208%} 11209 11210instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 11211 predicate(UseSSE==0); 11212 match(Set dst (MoveF2I src)); 11213 effect( DEF dst, USE src ); 11214 11215 ins_cost(125); 11216 format %{ "FST_S $dst,$src\t# MoveF2I_reg_stack" %} 11217 ins_encode( Pop_Mem_Reg_F(dst, src) ); 11218 ins_pipe( fpu_mem_reg ); 11219%} 11220 11221instruct MoveF2I_reg_stack_sse(stackSlotI dst, regX src) %{ 11222 predicate(UseSSE>=1); 11223 match(Set dst (MoveF2I src)); 11224 effect( DEF dst, USE src ); 11225 11226 ins_cost(95); 11227 format %{ "MOVSS $dst,$src\t# MoveF2I_reg_stack_sse" %} 11228 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x11), RegMem(src, dst)); 11229 ins_pipe( pipe_slow ); 11230%} 11231 11232instruct MoveF2I_reg_reg_sse(eRegI dst, regX src) %{ 11233 predicate(UseSSE>=2); 11234 match(Set dst (MoveF2I src)); 11235 effect( DEF dst, USE src ); 11236 ins_cost(85); 11237 format %{ "MOVD $dst,$src\t# MoveF2I_reg_reg_sse" %} 11238 ins_encode( MovX2I_reg(dst, src)); 11239 ins_pipe( pipe_slow ); 11240%} 11241 11242instruct MoveI2F_reg_stack(stackSlotF dst, eRegI src) %{ 11243 match(Set dst (MoveI2F src)); 11244 effect( DEF dst, USE src ); 11245 11246 ins_cost(100); 11247 format %{ "MOV $dst,$src\t# MoveI2F_reg_stack" %} 11248 opcode(0x89); 11249 ins_encode( OpcPRegSS( dst, src ) ); 11250 ins_pipe( ialu_mem_reg ); 11251%} 11252 11253 11254instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 11255 predicate(UseSSE==0); 11256 match(Set dst (MoveI2F src)); 11257 effect(DEF dst, USE src); 11258 11259 ins_cost(125); 11260 format %{ "FLD_S $src\n\t" 11261 "FSTP $dst\t# MoveI2F_stack_reg" %} 11262 opcode(0xD9); /* D9 /0, FLD m32real */ 11263 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 11264 Pop_Reg_F(dst) ); 11265 ins_pipe( fpu_reg_mem ); 11266%} 11267 11268instruct MoveI2F_stack_reg_sse(regX dst, stackSlotI src) %{ 11269 predicate(UseSSE>=1); 11270 match(Set dst (MoveI2F src)); 11271 effect( DEF dst, USE src ); 11272 11273 ins_cost(95); 11274 format %{ "MOVSS $dst,$src\t# MoveI2F_stack_reg_sse" %} 11275 ins_encode( Opcode(0xF3), Opcode(0x0F), Opcode(0x10), RegMem(dst,src)); 11276 ins_pipe( pipe_slow ); 11277%} 11278 11279instruct MoveI2F_reg_reg_sse(regX dst, eRegI src) %{ 11280 predicate(UseSSE>=2); 11281 match(Set dst (MoveI2F src)); 11282 effect( DEF dst, USE src ); 11283 11284 ins_cost(85); 11285 format %{ "MOVD $dst,$src\t# MoveI2F_reg_reg_sse" %} 11286 ins_encode( MovI2X_reg(dst, src) ); 11287 ins_pipe( pipe_slow ); 11288%} 11289 11290instruct MoveD2L_stack_reg(eRegL dst, stackSlotD src) %{ 11291 match(Set dst (MoveD2L src)); 11292 effect(DEF dst, USE src); 11293 11294 ins_cost(250); 11295 format %{ "MOV $dst.lo,$src\n\t" 11296 "MOV $dst.hi,$src+4\t# MoveD2L_stack_reg" %} 11297 opcode(0x8B, 0x8B); 11298 ins_encode( OpcP, RegMem(dst,src), OpcS, RegMem_Hi(dst,src)); 11299 ins_pipe( ialu_mem_long_reg ); 11300%} 11301 11302instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 11303 predicate(UseSSE<=1); 11304 match(Set dst (MoveD2L src)); 11305 effect(DEF dst, USE src); 11306 11307 ins_cost(125); 11308 format %{ "FST_D $dst,$src\t# MoveD2L_reg_stack" %} 11309 ins_encode( Pop_Mem_Reg_D(dst, src) ); 11310 ins_pipe( fpu_mem_reg ); 11311%} 11312 11313instruct MoveD2L_reg_stack_sse(stackSlotL dst, regXD src) %{ 11314 predicate(UseSSE>=2); 11315 match(Set dst (MoveD2L src)); 11316 effect(DEF dst, USE src); 11317 ins_cost(95); 11318 11319 format %{ "MOVSD $dst,$src\t# MoveD2L_reg_stack_sse" %} 11320 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x11), RegMem(src,dst)); 11321 ins_pipe( pipe_slow ); 11322%} 11323 11324instruct MoveD2L_reg_reg_sse(eRegL dst, regXD src, regXD tmp) %{ 11325 predicate(UseSSE>=2); 11326 match(Set dst (MoveD2L src)); 11327 effect(DEF dst, USE src, TEMP tmp); 11328 ins_cost(85); 11329 format %{ "MOVD $dst.lo,$src\n\t" 11330 "PSHUFLW $tmp,$src,0x4E\n\t" 11331 "MOVD $dst.hi,$tmp\t# MoveD2L_reg_reg_sse" %} 11332 ins_encode( MovXD2L_reg(dst, src, tmp) ); 11333 ins_pipe( pipe_slow ); 11334%} 11335 11336instruct MoveL2D_reg_stack(stackSlotD dst, eRegL src) %{ 11337 match(Set dst (MoveL2D src)); 11338 effect(DEF dst, USE src); 11339 11340 ins_cost(200); 11341 format %{ "MOV $dst,$src.lo\n\t" 11342 "MOV $dst+4,$src.hi\t# MoveL2D_reg_stack" %} 11343 opcode(0x89, 0x89); 11344 ins_encode( OpcP, RegMem( src, dst ), OpcS, RegMem_Hi( src, dst ) ); 11345 ins_pipe( ialu_mem_long_reg ); 11346%} 11347 11348 11349instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 11350 predicate(UseSSE<=1); 11351 match(Set dst (MoveL2D src)); 11352 effect(DEF dst, USE src); 11353 ins_cost(125); 11354 11355 format %{ "FLD_D $src\n\t" 11356 "FSTP $dst\t# MoveL2D_stack_reg" %} 11357 opcode(0xDD); /* DD /0, FLD m64real */ 11358 ins_encode( OpcP, RMopc_Mem_no_oop(0x00,src), 11359 Pop_Reg_D(dst) ); 11360 ins_pipe( fpu_reg_mem ); 11361%} 11362 11363 11364instruct MoveL2D_stack_reg_sse(regXD dst, stackSlotL src) %{ 11365 predicate(UseSSE>=2 && UseXmmLoadAndClearUpper); 11366 match(Set dst (MoveL2D src)); 11367 effect(DEF dst, USE src); 11368 11369 ins_cost(95); 11370 format %{ "MOVSD $dst,$src\t# MoveL2D_stack_reg_sse" %} 11371 ins_encode( Opcode(0xF2), Opcode(0x0F), Opcode(0x10), RegMem(dst,src)); 11372 ins_pipe( pipe_slow ); 11373%} 11374 11375instruct MoveL2D_stack_reg_sse_partial(regXD dst, stackSlotL src) %{ 11376 predicate(UseSSE>=2 && !UseXmmLoadAndClearUpper); 11377 match(Set dst (MoveL2D src)); 11378 effect(DEF dst, USE src); 11379 11380 ins_cost(95); 11381 format %{ "MOVLPD $dst,$src\t# MoveL2D_stack_reg_sse" %} 11382 ins_encode( Opcode(0x66), Opcode(0x0F), Opcode(0x12), RegMem(dst,src)); 11383 ins_pipe( pipe_slow ); 11384%} 11385 11386instruct MoveL2D_reg_reg_sse(regXD dst, eRegL src, regXD tmp) %{ 11387 predicate(UseSSE>=2); 11388 match(Set dst (MoveL2D src)); 11389 effect(TEMP dst, USE src, TEMP tmp); 11390 ins_cost(85); 11391 format %{ "MOVD $dst,$src.lo\n\t" 11392 "MOVD $tmp,$src.hi\n\t" 11393 "PUNPCKLDQ $dst,$tmp\t# MoveL2D_reg_reg_sse" %} 11394 ins_encode( MovL2XD_reg(dst, src, tmp) ); 11395 ins_pipe( pipe_slow ); 11396%} 11397 11398// Replicate scalar to packed byte (1 byte) values in xmm 11399instruct Repl8B_reg(regXD dst, regXD src) %{ 11400 predicate(UseSSE>=2); 11401 match(Set dst (Replicate8B src)); 11402 format %{ "MOVDQA $dst,$src\n\t" 11403 "PUNPCKLBW $dst,$dst\n\t" 11404 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} 11405 ins_encode( pshufd_8x8(dst, src)); 11406 ins_pipe( pipe_slow ); 11407%} 11408 11409// Replicate scalar to packed byte (1 byte) values in xmm 11410instruct Repl8B_eRegI(regXD dst, eRegI src) %{ 11411 predicate(UseSSE>=2); 11412 match(Set dst (Replicate8B src)); 11413 format %{ "MOVD $dst,$src\n\t" 11414 "PUNPCKLBW $dst,$dst\n\t" 11415 "PSHUFLW $dst,$dst,0x00\t! replicate8B" %} 11416 ins_encode( mov_i2x(dst, src), pshufd_8x8(dst, dst)); 11417 ins_pipe( pipe_slow ); 11418%} 11419 11420// Replicate scalar zero to packed byte (1 byte) values in xmm 11421instruct Repl8B_immI0(regXD dst, immI0 zero) %{ 11422 predicate(UseSSE>=2); 11423 match(Set dst (Replicate8B zero)); 11424 format %{ "PXOR $dst,$dst\t! replicate8B" %} 11425 ins_encode( pxor(dst, dst)); 11426 ins_pipe( fpu_reg_reg ); 11427%} 11428 11429// Replicate scalar to packed shore (2 byte) values in xmm 11430instruct Repl4S_reg(regXD dst, regXD src) %{ 11431 predicate(UseSSE>=2); 11432 match(Set dst (Replicate4S src)); 11433 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4S" %} 11434 ins_encode( pshufd_4x16(dst, src)); 11435 ins_pipe( fpu_reg_reg ); 11436%} 11437 11438// Replicate scalar to packed shore (2 byte) values in xmm 11439instruct Repl4S_eRegI(regXD dst, eRegI src) %{ 11440 predicate(UseSSE>=2); 11441 match(Set dst (Replicate4S src)); 11442 format %{ "MOVD $dst,$src\n\t" 11443 "PSHUFLW $dst,$dst,0x00\t! replicate4S" %} 11444 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); 11445 ins_pipe( fpu_reg_reg ); 11446%} 11447 11448// Replicate scalar zero to packed short (2 byte) values in xmm 11449instruct Repl4S_immI0(regXD dst, immI0 zero) %{ 11450 predicate(UseSSE>=2); 11451 match(Set dst (Replicate4S zero)); 11452 format %{ "PXOR $dst,$dst\t! replicate4S" %} 11453 ins_encode( pxor(dst, dst)); 11454 ins_pipe( fpu_reg_reg ); 11455%} 11456 11457// Replicate scalar to packed char (2 byte) values in xmm 11458instruct Repl4C_reg(regXD dst, regXD src) %{ 11459 predicate(UseSSE>=2); 11460 match(Set dst (Replicate4C src)); 11461 format %{ "PSHUFLW $dst,$src,0x00\t! replicate4C" %} 11462 ins_encode( pshufd_4x16(dst, src)); 11463 ins_pipe( fpu_reg_reg ); 11464%} 11465 11466// Replicate scalar to packed char (2 byte) values in xmm 11467instruct Repl4C_eRegI(regXD dst, eRegI src) %{ 11468 predicate(UseSSE>=2); 11469 match(Set dst (Replicate4C src)); 11470 format %{ "MOVD $dst,$src\n\t" 11471 "PSHUFLW $dst,$dst,0x00\t! replicate4C" %} 11472 ins_encode( mov_i2x(dst, src), pshufd_4x16(dst, dst)); 11473 ins_pipe( fpu_reg_reg ); 11474%} 11475 11476// Replicate scalar zero to packed char (2 byte) values in xmm 11477instruct Repl4C_immI0(regXD dst, immI0 zero) %{ 11478 predicate(UseSSE>=2); 11479 match(Set dst (Replicate4C zero)); 11480 format %{ "PXOR $dst,$dst\t! replicate4C" %} 11481 ins_encode( pxor(dst, dst)); 11482 ins_pipe( fpu_reg_reg ); 11483%} 11484 11485// Replicate scalar to packed integer (4 byte) values in xmm 11486instruct Repl2I_reg(regXD dst, regXD src) %{ 11487 predicate(UseSSE>=2); 11488 match(Set dst (Replicate2I src)); 11489 format %{ "PSHUFD $dst,$src,0x00\t! replicate2I" %} 11490 ins_encode( pshufd(dst, src, 0x00)); 11491 ins_pipe( fpu_reg_reg ); 11492%} 11493 11494// Replicate scalar to packed integer (4 byte) values in xmm 11495instruct Repl2I_eRegI(regXD dst, eRegI src) %{ 11496 predicate(UseSSE>=2); 11497 match(Set dst (Replicate2I src)); 11498 format %{ "MOVD $dst,$src\n\t" 11499 "PSHUFD $dst,$dst,0x00\t! replicate2I" %} 11500 ins_encode( mov_i2x(dst, src), pshufd(dst, dst, 0x00)); 11501 ins_pipe( fpu_reg_reg ); 11502%} 11503 11504// Replicate scalar zero to packed integer (2 byte) values in xmm 11505instruct Repl2I_immI0(regXD dst, immI0 zero) %{ 11506 predicate(UseSSE>=2); 11507 match(Set dst (Replicate2I zero)); 11508 format %{ "PXOR $dst,$dst\t! replicate2I" %} 11509 ins_encode( pxor(dst, dst)); 11510 ins_pipe( fpu_reg_reg ); 11511%} 11512 11513// Replicate scalar to packed single precision floating point values in xmm 11514instruct Repl2F_reg(regXD dst, regXD src) %{ 11515 predicate(UseSSE>=2); 11516 match(Set dst (Replicate2F src)); 11517 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} 11518 ins_encode( pshufd(dst, src, 0xe0)); 11519 ins_pipe( fpu_reg_reg ); 11520%} 11521 11522// Replicate scalar to packed single precision floating point values in xmm 11523instruct Repl2F_regX(regXD dst, regX src) %{ 11524 predicate(UseSSE>=2); 11525 match(Set dst (Replicate2F src)); 11526 format %{ "PSHUFD $dst,$src,0xe0\t! replicate2F" %} 11527 ins_encode( pshufd(dst, src, 0xe0)); 11528 ins_pipe( fpu_reg_reg ); 11529%} 11530 11531// Replicate scalar to packed single precision floating point values in xmm 11532instruct Repl2F_immXF0(regXD dst, immXF0 zero) %{ 11533 predicate(UseSSE>=2); 11534 match(Set dst (Replicate2F zero)); 11535 format %{ "PXOR $dst,$dst\t! replicate2F" %} 11536 ins_encode( pxor(dst, dst)); 11537 ins_pipe( fpu_reg_reg ); 11538%} 11539 11540 11541 11542// ======================================================================= 11543// fast clearing of an array 11544 11545instruct rep_stos(eCXRegI cnt, eDIRegP base, eAXRegI zero, Universe dummy, eFlagsReg cr) %{ 11546 match(Set dummy (ClearArray cnt base)); 11547 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr); 11548 format %{ "SHL ECX,1\t# Convert doublewords to words\n\t" 11549 "XOR EAX,EAX\n\t" 11550 "REP STOS\t# store EAX into [EDI++] while ECX--" %} 11551 opcode(0,0x4); 11552 ins_encode( Opcode(0xD1), RegOpc(ECX), 11553 OpcRegReg(0x33,EAX,EAX), 11554 Opcode(0xF3), Opcode(0xAB) ); 11555 ins_pipe( pipe_slow ); 11556%} 11557 11558instruct string_compare(eDIRegP str1, eSIRegP str2, eAXRegI tmp1, eBXRegI tmp2, eCXRegI result, eFlagsReg cr) %{ 11559 match(Set result (StrComp str1 str2)); 11560 effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL cr); 11561 //ins_cost(300); 11562 11563 format %{ "String Compare $str1,$str2 -> $result // KILL EAX, EBX" %} 11564 ins_encode( enc_String_Compare() ); 11565 ins_pipe( pipe_slow ); 11566%} 11567 11568//----------Control Flow Instructions------------------------------------------ 11569// Signed compare Instructions 11570instruct compI_eReg(eFlagsReg cr, eRegI op1, eRegI op2) %{ 11571 match(Set cr (CmpI op1 op2)); 11572 effect( DEF cr, USE op1, USE op2 ); 11573 format %{ "CMP $op1,$op2" %} 11574 opcode(0x3B); /* Opcode 3B /r */ 11575 ins_encode( OpcP, RegReg( op1, op2) ); 11576 ins_pipe( ialu_cr_reg_reg ); 11577%} 11578 11579instruct compI_eReg_imm(eFlagsReg cr, eRegI op1, immI op2) %{ 11580 match(Set cr (CmpI op1 op2)); 11581 effect( DEF cr, USE op1 ); 11582 format %{ "CMP $op1,$op2" %} 11583 opcode(0x81,0x07); /* Opcode 81 /7 */ 11584 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */ 11585 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 11586 ins_pipe( ialu_cr_reg_imm ); 11587%} 11588 11589// Cisc-spilled version of cmpI_eReg 11590instruct compI_eReg_mem(eFlagsReg cr, eRegI op1, memory op2) %{ 11591 match(Set cr (CmpI op1 (LoadI op2))); 11592 11593 format %{ "CMP $op1,$op2" %} 11594 ins_cost(500); 11595 opcode(0x3B); /* Opcode 3B /r */ 11596 ins_encode( OpcP, RegMem( op1, op2) ); 11597 ins_pipe( ialu_cr_reg_mem ); 11598%} 11599 11600instruct testI_reg( eFlagsReg cr, eRegI src, immI0 zero ) %{ 11601 match(Set cr (CmpI src zero)); 11602 effect( DEF cr, USE src ); 11603 11604 format %{ "TEST $src,$src" %} 11605 opcode(0x85); 11606 ins_encode( OpcP, RegReg( src, src ) ); 11607 ins_pipe( ialu_cr_reg_imm ); 11608%} 11609 11610instruct testI_reg_imm( eFlagsReg cr, eRegI src, immI con, immI0 zero ) %{ 11611 match(Set cr (CmpI (AndI src con) zero)); 11612 11613 format %{ "TEST $src,$con" %} 11614 opcode(0xF7,0x00); 11615 ins_encode( OpcP, RegOpc(src), Con32(con) ); 11616 ins_pipe( ialu_cr_reg_imm ); 11617%} 11618 11619instruct testI_reg_mem( eFlagsReg cr, eRegI src, memory mem, immI0 zero ) %{ 11620 match(Set cr (CmpI (AndI src mem) zero)); 11621 11622 format %{ "TEST $src,$mem" %} 11623 opcode(0x85); 11624 ins_encode( OpcP, RegMem( src, mem ) ); 11625 ins_pipe( ialu_cr_reg_mem ); 11626%} 11627 11628// Unsigned compare Instructions; really, same as signed except they 11629// produce an eFlagsRegU instead of eFlagsReg. 11630instruct compU_eReg(eFlagsRegU cr, eRegI op1, eRegI op2) %{ 11631 match(Set cr (CmpU op1 op2)); 11632 11633 format %{ "CMPu $op1,$op2" %} 11634 opcode(0x3B); /* Opcode 3B /r */ 11635 ins_encode( OpcP, RegReg( op1, op2) ); 11636 ins_pipe( ialu_cr_reg_reg ); 11637%} 11638 11639instruct compU_eReg_imm(eFlagsRegU cr, eRegI op1, immI op2) %{ 11640 match(Set cr (CmpU op1 op2)); 11641 11642 format %{ "CMPu $op1,$op2" %} 11643 opcode(0x81,0x07); /* Opcode 81 /7 */ 11644 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 11645 ins_pipe( ialu_cr_reg_imm ); 11646%} 11647 11648// // Cisc-spilled version of cmpU_eReg 11649instruct compU_eReg_mem(eFlagsRegU cr, eRegI op1, memory op2) %{ 11650 match(Set cr (CmpU op1 (LoadI op2))); 11651 11652 format %{ "CMPu $op1,$op2" %} 11653 ins_cost(500); 11654 opcode(0x3B); /* Opcode 3B /r */ 11655 ins_encode( OpcP, RegMem( op1, op2) ); 11656 ins_pipe( ialu_cr_reg_mem ); 11657%} 11658 11659// // Cisc-spilled version of cmpU_eReg 11660//instruct compU_mem_eReg(eFlagsRegU cr, memory op1, eRegI op2) %{ 11661// match(Set cr (CmpU (LoadI op1) op2)); 11662// 11663// format %{ "CMPu $op1,$op2" %} 11664// ins_cost(500); 11665// opcode(0x39); /* Opcode 39 /r */ 11666// ins_encode( OpcP, RegMem( op1, op2) ); 11667//%} 11668 11669instruct testU_reg( eFlagsRegU cr, eRegI src, immI0 zero ) %{ 11670 match(Set cr (CmpU src zero)); 11671 11672 format %{ "TESTu $src,$src" %} 11673 opcode(0x85); 11674 ins_encode( OpcP, RegReg( src, src ) ); 11675 ins_pipe( ialu_cr_reg_imm ); 11676%} 11677 11678// Unsigned pointer compare Instructions 11679instruct compP_eReg(eFlagsRegU cr, eRegP op1, eRegP op2) %{ 11680 match(Set cr (CmpP op1 op2)); 11681 11682 format %{ "CMPu $op1,$op2" %} 11683 opcode(0x3B); /* Opcode 3B /r */ 11684 ins_encode( OpcP, RegReg( op1, op2) ); 11685 ins_pipe( ialu_cr_reg_reg ); 11686%} 11687 11688instruct compP_eReg_imm(eFlagsRegU cr, eRegP op1, immP op2) %{ 11689 match(Set cr (CmpP op1 op2)); 11690 11691 format %{ "CMPu $op1,$op2" %} 11692 opcode(0x81,0x07); /* Opcode 81 /7 */ 11693 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) ); 11694 ins_pipe( ialu_cr_reg_imm ); 11695%} 11696 11697// // Cisc-spilled version of cmpP_eReg 11698instruct compP_eReg_mem(eFlagsRegU cr, eRegP op1, memory op2) %{ 11699 match(Set cr (CmpP op1 (LoadP op2))); 11700 11701 format %{ "CMPu $op1,$op2" %} 11702 ins_cost(500); 11703 opcode(0x3B); /* Opcode 3B /r */ 11704 ins_encode( OpcP, RegMem( op1, op2) ); 11705 ins_pipe( ialu_cr_reg_mem ); 11706%} 11707 11708// // Cisc-spilled version of cmpP_eReg 11709//instruct compP_mem_eReg(eFlagsRegU cr, memory op1, eRegP op2) %{ 11710// match(Set cr (CmpP (LoadP op1) op2)); 11711// 11712// format %{ "CMPu $op1,$op2" %} 11713// ins_cost(500); 11714// opcode(0x39); /* Opcode 39 /r */ 11715// ins_encode( OpcP, RegMem( op1, op2) ); 11716//%} 11717 11718// Compare raw pointer (used in out-of-heap check). 11719// Only works because non-oop pointers must be raw pointers 11720// and raw pointers have no anti-dependencies. 11721instruct compP_mem_eReg( eFlagsRegU cr, eRegP op1, memory op2 ) %{ 11722 predicate( !n->in(2)->in(2)->bottom_type()->isa_oop_ptr() ); 11723 match(Set cr (CmpP op1 (LoadP op2))); 11724 11725 format %{ "CMPu $op1,$op2" %} 11726 opcode(0x3B); /* Opcode 3B /r */ 11727 ins_encode( OpcP, RegMem( op1, op2) ); 11728 ins_pipe( ialu_cr_reg_mem ); 11729%} 11730 11731// 11732// This will generate a signed flags result. This should be ok 11733// since any compare to a zero should be eq/neq. 11734instruct testP_reg( eFlagsReg cr, eRegP src, immP0 zero ) %{ 11735 match(Set cr (CmpP src zero)); 11736 11737 format %{ "TEST $src,$src" %} 11738 opcode(0x85); 11739 ins_encode( OpcP, RegReg( src, src ) ); 11740 ins_pipe( ialu_cr_reg_imm ); 11741%} 11742 11743// Cisc-spilled version of testP_reg 11744// This will generate a signed flags result. This should be ok 11745// since any compare to a zero should be eq/neq. 11746instruct testP_Reg_mem( eFlagsReg cr, memory op, immI0 zero ) %{ 11747 match(Set cr (CmpP (LoadP op) zero)); 11748 11749 format %{ "TEST $op,0xFFFFFFFF" %} 11750 ins_cost(500); 11751 opcode(0xF7); /* Opcode F7 /0 */ 11752 ins_encode( OpcP, RMopc_Mem(0x00,op), Con_d32(0xFFFFFFFF) ); 11753 ins_pipe( ialu_cr_reg_imm ); 11754%} 11755 11756// Yanked all unsigned pointer compare operations. 11757// Pointer compares are done with CmpP which is already unsigned. 11758 11759//----------Max and Min-------------------------------------------------------- 11760// Min Instructions 11761//// 11762// *** Min and Max using the conditional move are slower than the 11763// *** branch version on a Pentium III. 11764// // Conditional move for min 11765//instruct cmovI_reg_lt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ 11766// effect( USE_DEF op2, USE op1, USE cr ); 11767// format %{ "CMOVlt $op2,$op1\t! min" %} 11768// opcode(0x4C,0x0F); 11769// ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); 11770// ins_pipe( pipe_cmov_reg ); 11771//%} 11772// 11773//// Min Register with Register (P6 version) 11774//instruct minI_eReg_p6( eRegI op1, eRegI op2 ) %{ 11775// predicate(VM_Version::supports_cmov() ); 11776// match(Set op2 (MinI op1 op2)); 11777// ins_cost(200); 11778// expand %{ 11779// eFlagsReg cr; 11780// compI_eReg(cr,op1,op2); 11781// cmovI_reg_lt(op2,op1,cr); 11782// %} 11783//%} 11784 11785// Min Register with Register (generic version) 11786instruct minI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ 11787 match(Set dst (MinI dst src)); 11788 effect(KILL flags); 11789 ins_cost(300); 11790 11791 format %{ "MIN $dst,$src" %} 11792 opcode(0xCC); 11793 ins_encode( min_enc(dst,src) ); 11794 ins_pipe( pipe_slow ); 11795%} 11796 11797// Max Register with Register 11798// *** Min and Max using the conditional move are slower than the 11799// *** branch version on a Pentium III. 11800// // Conditional move for max 11801//instruct cmovI_reg_gt( eRegI op2, eRegI op1, eFlagsReg cr ) %{ 11802// effect( USE_DEF op2, USE op1, USE cr ); 11803// format %{ "CMOVgt $op2,$op1\t! max" %} 11804// opcode(0x4F,0x0F); 11805// ins_encode( OpcS, OpcP, RegReg( op2, op1 ) ); 11806// ins_pipe( pipe_cmov_reg ); 11807//%} 11808// 11809// // Max Register with Register (P6 version) 11810//instruct maxI_eReg_p6( eRegI op1, eRegI op2 ) %{ 11811// predicate(VM_Version::supports_cmov() ); 11812// match(Set op2 (MaxI op1 op2)); 11813// ins_cost(200); 11814// expand %{ 11815// eFlagsReg cr; 11816// compI_eReg(cr,op1,op2); 11817// cmovI_reg_gt(op2,op1,cr); 11818// %} 11819//%} 11820 11821// Max Register with Register (generic version) 11822instruct maxI_eReg(eRegI dst, eRegI src, eFlagsReg flags) %{ 11823 match(Set dst (MaxI dst src)); 11824 effect(KILL flags); 11825 ins_cost(300); 11826 11827 format %{ "MAX $dst,$src" %} 11828 opcode(0xCC); 11829 ins_encode( max_enc(dst,src) ); 11830 ins_pipe( pipe_slow ); 11831%} 11832 11833// ============================================================================ 11834// Branch Instructions 11835// Jump Table 11836instruct jumpXtnd(eRegI switch_val) %{ 11837 match(Jump switch_val); 11838 ins_cost(350); 11839 11840 format %{ "JMP [table_base](,$switch_val,1)\n\t" %} 11841 11842 ins_encode %{ 11843 address table_base = __ address_table_constant(_index2label); 11844 11845 // Jump to Address(table_base + switch_reg) 11846 InternalAddress table(table_base); 11847 Address index(noreg, $switch_val$$Register, Address::times_1); 11848 __ jump(ArrayAddress(table, index)); 11849 %} 11850 ins_pc_relative(1); 11851 ins_pipe(pipe_jmp); 11852%} 11853 11854// Jump Direct - Label defines a relative address from JMP+1 11855instruct jmpDir(label labl) %{ 11856 match(Goto); 11857 effect(USE labl); 11858 11859 ins_cost(300); 11860 format %{ "JMP $labl" %} 11861 size(5); 11862 opcode(0xE9); 11863 ins_encode( OpcP, Lbl( labl ) ); 11864 ins_pipe( pipe_jmp ); 11865 ins_pc_relative(1); 11866%} 11867 11868// Jump Direct Conditional - Label defines a relative address from Jcc+1 11869instruct jmpCon(cmpOp cop, eFlagsReg cr, label labl) %{ 11870 match(If cop cr); 11871 effect(USE labl); 11872 11873 ins_cost(300); 11874 format %{ "J$cop $labl" %} 11875 size(6); 11876 opcode(0x0F, 0x80); 11877 ins_encode( Jcc( cop, labl) ); 11878 ins_pipe( pipe_jcc ); 11879 ins_pc_relative(1); 11880%} 11881 11882// Jump Direct Conditional - Label defines a relative address from Jcc+1 11883instruct jmpLoopEnd(cmpOp cop, eFlagsReg cr, label labl) %{ 11884 match(CountedLoopEnd cop cr); 11885 effect(USE labl); 11886 11887 ins_cost(300); 11888 format %{ "J$cop $labl\t# Loop end" %} 11889 size(6); 11890 opcode(0x0F, 0x80); 11891 ins_encode( Jcc( cop, labl) ); 11892 ins_pipe( pipe_jcc ); 11893 ins_pc_relative(1); 11894%} 11895 11896// Jump Direct Conditional - Label defines a relative address from Jcc+1 11897instruct jmpLoopEndU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 11898 match(CountedLoopEnd cop cmp); 11899 effect(USE labl); 11900 11901 ins_cost(300); 11902 format %{ "J$cop,u $labl\t# Loop end" %} 11903 size(6); 11904 opcode(0x0F, 0x80); 11905 ins_encode( Jcc( cop, labl) ); 11906 ins_pipe( pipe_jcc ); 11907 ins_pc_relative(1); 11908%} 11909 11910// Jump Direct Conditional - using unsigned comparison 11911instruct jmpConU(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 11912 match(If cop cmp); 11913 effect(USE labl); 11914 11915 ins_cost(300); 11916 format %{ "J$cop,u $labl" %} 11917 size(6); 11918 opcode(0x0F, 0x80); 11919 ins_encode( Jcc( cop, labl) ); 11920 ins_pipe( pipe_jcc ); 11921 ins_pc_relative(1); 11922%} 11923 11924// ============================================================================ 11925// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 11926// array for an instance of the superklass. Set a hidden internal cache on a 11927// hit (cache is checked with exposed code in gen_subtype_check()). Return 11928// NZ for a miss or zero for a hit. The encoding ALSO sets flags. 11929instruct partialSubtypeCheck( eDIRegP result, eSIRegP sub, eAXRegP super, eCXRegI rcx, eFlagsReg cr ) %{ 11930 match(Set result (PartialSubtypeCheck sub super)); 11931 effect( KILL rcx, KILL cr ); 11932 11933 ins_cost(1100); // slightly larger than the next version 11934 format %{ "CMPL EAX,ESI\n\t" 11935 "JEQ,s hit\n\t" 11936 "MOV EDI,[$sub+Klass::secondary_supers]\n\t" 11937 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" 11938 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" 11939 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" 11940 "JNE,s miss\t\t# Missed: EDI not-zero\n\t" 11941 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache\n\t" 11942 "hit:\n\t" 11943 "XOR $result,$result\t\t Hit: EDI zero\n\t" 11944 "miss:\t" %} 11945 11946 opcode(0x1); // Force a XOR of EDI 11947 ins_encode( enc_PartialSubtypeCheck() ); 11948 ins_pipe( pipe_slow ); 11949%} 11950 11951instruct partialSubtypeCheck_vs_Zero( eFlagsReg cr, eSIRegP sub, eAXRegP super, eCXRegI rcx, eDIRegP result, immP0 zero ) %{ 11952 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero)); 11953 effect( KILL rcx, KILL result ); 11954 11955 ins_cost(1000); 11956 format %{ "CMPL EAX,ESI\n\t" 11957 "JEQ,s miss\t# Actually a hit; we are done.\n\t" 11958 "MOV EDI,[$sub+Klass::secondary_supers]\n\t" 11959 "MOV ECX,[EDI+arrayKlass::length]\t# length to scan\n\t" 11960 "ADD EDI,arrayKlass::base_offset\t# Skip to start of data; set NZ in case count is zero\n\t" 11961 "REPNE SCASD\t# Scan *EDI++ for a match with EAX while CX-- != 0\n\t" 11962 "JNE,s miss\t\t# Missed: flags NZ\n\t" 11963 "MOV [$sub+Klass::secondary_super_cache],$super\t# Hit: update cache, flags Z\n\t" 11964 "miss:\t" %} 11965 11966 opcode(0x0); // No need to XOR EDI 11967 ins_encode( enc_PartialSubtypeCheck() ); 11968 ins_pipe( pipe_slow ); 11969%} 11970 11971// ============================================================================ 11972// Branch Instructions -- short offset versions 11973// 11974// These instructions are used to replace jumps of a long offset (the default 11975// match) with jumps of a shorter offset. These instructions are all tagged 11976// with the ins_short_branch attribute, which causes the ADLC to suppress the 11977// match rules in general matching. Instead, the ADLC generates a conversion 11978// method in the MachNode which can be used to do in-place replacement of the 11979// long variant with the shorter variant. The compiler will determine if a 11980// branch can be taken by the is_short_branch_offset() predicate in the machine 11981// specific code section of the file. 11982 11983// Jump Direct - Label defines a relative address from JMP+1 11984instruct jmpDir_short(label labl) %{ 11985 match(Goto); 11986 effect(USE labl); 11987 11988 ins_cost(300); 11989 format %{ "JMP,s $labl" %} 11990 size(2); 11991 opcode(0xEB); 11992 ins_encode( OpcP, LblShort( labl ) ); 11993 ins_pipe( pipe_jmp ); 11994 ins_pc_relative(1); 11995 ins_short_branch(1); 11996%} 11997 11998// Jump Direct Conditional - Label defines a relative address from Jcc+1 11999instruct jmpCon_short(cmpOp cop, eFlagsReg cr, label labl) %{ 12000 match(If cop cr); 12001 effect(USE labl); 12002 12003 ins_cost(300); 12004 format %{ "J$cop,s $labl" %} 12005 size(2); 12006 opcode(0x70); 12007 ins_encode( JccShort( cop, labl) ); 12008 ins_pipe( pipe_jcc ); 12009 ins_pc_relative(1); 12010 ins_short_branch(1); 12011%} 12012 12013// Jump Direct Conditional - Label defines a relative address from Jcc+1 12014instruct jmpLoopEnd_short(cmpOp cop, eFlagsReg cr, label labl) %{ 12015 match(CountedLoopEnd cop cr); 12016 effect(USE labl); 12017 12018 ins_cost(300); 12019 format %{ "J$cop,s $labl" %} 12020 size(2); 12021 opcode(0x70); 12022 ins_encode( JccShort( cop, labl) ); 12023 ins_pipe( pipe_jcc ); 12024 ins_pc_relative(1); 12025 ins_short_branch(1); 12026%} 12027 12028// Jump Direct Conditional - Label defines a relative address from Jcc+1 12029instruct jmpLoopEndU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12030 match(CountedLoopEnd cop cmp); 12031 effect(USE labl); 12032 12033 ins_cost(300); 12034 format %{ "J$cop,us $labl" %} 12035 size(2); 12036 opcode(0x70); 12037 ins_encode( JccShort( cop, labl) ); 12038 ins_pipe( pipe_jcc ); 12039 ins_pc_relative(1); 12040 ins_short_branch(1); 12041%} 12042 12043// Jump Direct Conditional - using unsigned comparison 12044instruct jmpConU_short(cmpOpU cop, eFlagsRegU cmp, label labl) %{ 12045 match(If cop cmp); 12046 effect(USE labl); 12047 12048 ins_cost(300); 12049 format %{ "J$cop,us $labl" %} 12050 size(2); 12051 opcode(0x70); 12052 ins_encode( JccShort( cop, labl) ); 12053 ins_pipe( pipe_jcc ); 12054 ins_pc_relative(1); 12055 ins_short_branch(1); 12056%} 12057 12058// ============================================================================ 12059// Long Compare 12060// 12061// Currently we hold longs in 2 registers. Comparing such values efficiently 12062// is tricky. The flavor of compare used depends on whether we are testing 12063// for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 12064// The GE test is the negated LT test. The LE test can be had by commuting 12065// the operands (yielding a GE test) and then negating; negate again for the 12066// GT test. The EQ test is done by ORcc'ing the high and low halves, and the 12067// NE test is negated from that. 12068 12069// Due to a shortcoming in the ADLC, it mixes up expressions like: 12070// (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 12071// difference between 'Y' and '0L'. The tree-matches for the CmpI sections 12072// are collapsed internally in the ADLC's dfa-gen code. The match for 12073// (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 12074// foo match ends up with the wrong leaf. One fix is to not match both 12075// reg-reg and reg-zero forms of long-compare. This is unfortunate because 12076// both forms beat the trinary form of long-compare and both are very useful 12077// on Intel which has so few registers. 12078 12079// Manifest a CmpL result in an integer register. Very painful. 12080// This is the test to avoid. 12081instruct cmpL3_reg_reg(eSIRegI dst, eRegL src1, eRegL src2, eFlagsReg flags ) %{ 12082 match(Set dst (CmpL3 src1 src2)); 12083 effect( KILL flags ); 12084 ins_cost(1000); 12085 format %{ "XOR $dst,$dst\n\t" 12086 "CMP $src1.hi,$src2.hi\n\t" 12087 "JLT,s m_one\n\t" 12088 "JGT,s p_one\n\t" 12089 "CMP $src1.lo,$src2.lo\n\t" 12090 "JB,s m_one\n\t" 12091 "JEQ,s done\n" 12092 "p_one:\tINC $dst\n\t" 12093 "JMP,s done\n" 12094 "m_one:\tDEC $dst\n" 12095 "done:" %} 12096 ins_encode %{ 12097 Label p_one, m_one, done; 12098 __ xorl($dst$$Register, $dst$$Register); 12099 __ cmpl(HIGH_FROM_LOW($src1$$Register), HIGH_FROM_LOW($src2$$Register)); 12100 __ jccb(Assembler::less, m_one); 12101 __ jccb(Assembler::greater, p_one); 12102 __ cmpl($src1$$Register, $src2$$Register); 12103 __ jccb(Assembler::below, m_one); 12104 __ jccb(Assembler::equal, done); 12105 __ bind(p_one); 12106 __ increment($dst$$Register); 12107 __ jmpb(done); 12108 __ bind(m_one); 12109 __ decrement($dst$$Register); 12110 __ bind(done); 12111 %} 12112 ins_pipe( pipe_slow ); 12113%} 12114 12115//====== 12116// Manifest a CmpL result in the normal flags. Only good for LT or GE 12117// compares. Can be used for LE or GT compares by reversing arguments. 12118// NOT GOOD FOR EQ/NE tests. 12119instruct cmpL_zero_flags_LTGE( flagsReg_long_LTGE flags, eRegL src, immL0 zero ) %{ 12120 match( Set flags (CmpL src zero )); 12121 ins_cost(100); 12122 format %{ "TEST $src.hi,$src.hi" %} 12123 opcode(0x85); 12124 ins_encode( OpcP, RegReg_Hi2( src, src ) ); 12125 ins_pipe( ialu_cr_reg_reg ); 12126%} 12127 12128// Manifest a CmpL result in the normal flags. Only good for LT or GE 12129// compares. Can be used for LE or GT compares by reversing arguments. 12130// NOT GOOD FOR EQ/NE tests. 12131instruct cmpL_reg_flags_LTGE( flagsReg_long_LTGE flags, eRegL src1, eRegL src2, eRegI tmp ) %{ 12132 match( Set flags (CmpL src1 src2 )); 12133 effect( TEMP tmp ); 12134 ins_cost(300); 12135 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" 12136 "MOV $tmp,$src1.hi\n\t" 12137 "SBB $tmp,$src2.hi\t! Compute flags for long compare" %} 12138 ins_encode( long_cmp_flags2( src1, src2, tmp ) ); 12139 ins_pipe( ialu_cr_reg_reg ); 12140%} 12141 12142// Long compares reg < zero/req OR reg >= zero/req. 12143// Just a wrapper for a normal branch, plus the predicate test. 12144instruct cmpL_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, label labl) %{ 12145 match(If cmp flags); 12146 effect(USE labl); 12147 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12148 expand %{ 12149 jmpCon(cmp,flags,labl); // JLT or JGE... 12150 %} 12151%} 12152 12153// Compare 2 longs and CMOVE longs. 12154instruct cmovLL_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, eRegL src) %{ 12155 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 12156 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12157 ins_cost(400); 12158 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12159 "CMOV$cmp $dst.hi,$src.hi" %} 12160 opcode(0x0F,0x40); 12161 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 12162 ins_pipe( pipe_cmov_reg_long ); 12163%} 12164 12165instruct cmovLL_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegL dst, load_long_memory src) %{ 12166 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 12167 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12168 ins_cost(500); 12169 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12170 "CMOV$cmp $dst.hi,$src.hi" %} 12171 opcode(0x0F,0x40); 12172 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 12173 ins_pipe( pipe_cmov_reg_long ); 12174%} 12175 12176// Compare 2 longs and CMOVE ints. 12177instruct cmovII_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, eRegI src) %{ 12178 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12179 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 12180 ins_cost(200); 12181 format %{ "CMOV$cmp $dst,$src" %} 12182 opcode(0x0F,0x40); 12183 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12184 ins_pipe( pipe_cmov_reg ); 12185%} 12186 12187instruct cmovII_mem_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegI dst, memory src) %{ 12188 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12189 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 12190 ins_cost(250); 12191 format %{ "CMOV$cmp $dst,$src" %} 12192 opcode(0x0F,0x40); 12193 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 12194 ins_pipe( pipe_cmov_mem ); 12195%} 12196 12197// Compare 2 longs and CMOVE ints. 12198instruct cmovPP_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, eRegP dst, eRegP src) %{ 12199 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge )); 12200 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 12201 ins_cost(200); 12202 format %{ "CMOV$cmp $dst,$src" %} 12203 opcode(0x0F,0x40); 12204 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12205 ins_pipe( pipe_cmov_reg ); 12206%} 12207 12208// Compare 2 longs and CMOVE doubles 12209instruct cmovDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regD dst, regD src) %{ 12210 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12211 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12212 ins_cost(200); 12213 expand %{ 12214 fcmovD_regS(cmp,flags,dst,src); 12215 %} 12216%} 12217 12218// Compare 2 longs and CMOVE doubles 12219instruct cmovXDD_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regXD dst, regXD src) %{ 12220 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12221 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12222 ins_cost(200); 12223 expand %{ 12224 fcmovXD_regS(cmp,flags,dst,src); 12225 %} 12226%} 12227 12228instruct cmovFF_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regF dst, regF src) %{ 12229 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12230 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12231 ins_cost(200); 12232 expand %{ 12233 fcmovF_regS(cmp,flags,dst,src); 12234 %} 12235%} 12236 12237instruct cmovXX_reg_LTGE(cmpOp cmp, flagsReg_long_LTGE flags, regX dst, regX src) %{ 12238 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ge ); 12239 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12240 ins_cost(200); 12241 expand %{ 12242 fcmovX_regS(cmp,flags,dst,src); 12243 %} 12244%} 12245 12246//====== 12247// Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. 12248instruct cmpL_zero_flags_EQNE( flagsReg_long_EQNE flags, eRegL src, immL0 zero, eRegI tmp ) %{ 12249 match( Set flags (CmpL src zero )); 12250 effect(TEMP tmp); 12251 ins_cost(200); 12252 format %{ "MOV $tmp,$src.lo\n\t" 12253 "OR $tmp,$src.hi\t! Long is EQ/NE 0?" %} 12254 ins_encode( long_cmp_flags0( src, tmp ) ); 12255 ins_pipe( ialu_reg_reg_long ); 12256%} 12257 12258// Manifest a CmpL result in the normal flags. Only good for EQ/NE compares. 12259instruct cmpL_reg_flags_EQNE( flagsReg_long_EQNE flags, eRegL src1, eRegL src2 ) %{ 12260 match( Set flags (CmpL src1 src2 )); 12261 ins_cost(200+300); 12262 format %{ "CMP $src1.lo,$src2.lo\t! Long compare; set flags for low bits\n\t" 12263 "JNE,s skip\n\t" 12264 "CMP $src1.hi,$src2.hi\n\t" 12265 "skip:\t" %} 12266 ins_encode( long_cmp_flags1( src1, src2 ) ); 12267 ins_pipe( ialu_cr_reg_reg ); 12268%} 12269 12270// Long compare reg == zero/reg OR reg != zero/reg 12271// Just a wrapper for a normal branch, plus the predicate test. 12272instruct cmpL_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, label labl) %{ 12273 match(If cmp flags); 12274 effect(USE labl); 12275 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12276 expand %{ 12277 jmpCon(cmp,flags,labl); // JEQ or JNE... 12278 %} 12279%} 12280 12281// Compare 2 longs and CMOVE longs. 12282instruct cmovLL_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, eRegL src) %{ 12283 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 12284 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12285 ins_cost(400); 12286 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12287 "CMOV$cmp $dst.hi,$src.hi" %} 12288 opcode(0x0F,0x40); 12289 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 12290 ins_pipe( pipe_cmov_reg_long ); 12291%} 12292 12293instruct cmovLL_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegL dst, load_long_memory src) %{ 12294 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 12295 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12296 ins_cost(500); 12297 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12298 "CMOV$cmp $dst.hi,$src.hi" %} 12299 opcode(0x0F,0x40); 12300 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 12301 ins_pipe( pipe_cmov_reg_long ); 12302%} 12303 12304// Compare 2 longs and CMOVE ints. 12305instruct cmovII_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, eRegI src) %{ 12306 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12307 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 12308 ins_cost(200); 12309 format %{ "CMOV$cmp $dst,$src" %} 12310 opcode(0x0F,0x40); 12311 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12312 ins_pipe( pipe_cmov_reg ); 12313%} 12314 12315instruct cmovII_mem_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegI dst, memory src) %{ 12316 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12317 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 12318 ins_cost(250); 12319 format %{ "CMOV$cmp $dst,$src" %} 12320 opcode(0x0F,0x40); 12321 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 12322 ins_pipe( pipe_cmov_mem ); 12323%} 12324 12325// Compare 2 longs and CMOVE ints. 12326instruct cmovPP_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, eRegP dst, eRegP src) %{ 12327 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne )); 12328 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 12329 ins_cost(200); 12330 format %{ "CMOV$cmp $dst,$src" %} 12331 opcode(0x0F,0x40); 12332 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12333 ins_pipe( pipe_cmov_reg ); 12334%} 12335 12336// Compare 2 longs and CMOVE doubles 12337instruct cmovDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regD dst, regD src) %{ 12338 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12339 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12340 ins_cost(200); 12341 expand %{ 12342 fcmovD_regS(cmp,flags,dst,src); 12343 %} 12344%} 12345 12346// Compare 2 longs and CMOVE doubles 12347instruct cmovXDD_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regXD dst, regXD src) %{ 12348 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12349 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12350 ins_cost(200); 12351 expand %{ 12352 fcmovXD_regS(cmp,flags,dst,src); 12353 %} 12354%} 12355 12356instruct cmovFF_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regF dst, regF src) %{ 12357 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12358 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12359 ins_cost(200); 12360 expand %{ 12361 fcmovF_regS(cmp,flags,dst,src); 12362 %} 12363%} 12364 12365instruct cmovXX_reg_EQNE(cmpOp cmp, flagsReg_long_EQNE flags, regX dst, regX src) %{ 12366 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::eq || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne ); 12367 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12368 ins_cost(200); 12369 expand %{ 12370 fcmovX_regS(cmp,flags,dst,src); 12371 %} 12372%} 12373 12374//====== 12375// Manifest a CmpL result in the normal flags. Only good for LE or GT compares. 12376// Same as cmpL_reg_flags_LEGT except must negate src 12377instruct cmpL_zero_flags_LEGT( flagsReg_long_LEGT flags, eRegL src, immL0 zero, eRegI tmp ) %{ 12378 match( Set flags (CmpL src zero )); 12379 effect( TEMP tmp ); 12380 ins_cost(300); 12381 format %{ "XOR $tmp,$tmp\t# Long compare for -$src < 0, use commuted test\n\t" 12382 "CMP $tmp,$src.lo\n\t" 12383 "SBB $tmp,$src.hi\n\t" %} 12384 ins_encode( long_cmp_flags3(src, tmp) ); 12385 ins_pipe( ialu_reg_reg_long ); 12386%} 12387 12388// Manifest a CmpL result in the normal flags. Only good for LE or GT compares. 12389// Same as cmpL_reg_flags_LTGE except operands swapped. Swapping operands 12390// requires a commuted test to get the same result. 12391instruct cmpL_reg_flags_LEGT( flagsReg_long_LEGT flags, eRegL src1, eRegL src2, eRegI tmp ) %{ 12392 match( Set flags (CmpL src1 src2 )); 12393 effect( TEMP tmp ); 12394 ins_cost(300); 12395 format %{ "CMP $src2.lo,$src1.lo\t! Long compare, swapped operands, use with commuted test\n\t" 12396 "MOV $tmp,$src2.hi\n\t" 12397 "SBB $tmp,$src1.hi\t! Compute flags for long compare" %} 12398 ins_encode( long_cmp_flags2( src2, src1, tmp ) ); 12399 ins_pipe( ialu_cr_reg_reg ); 12400%} 12401 12402// Long compares reg < zero/req OR reg >= zero/req. 12403// Just a wrapper for a normal branch, plus the predicate test 12404instruct cmpL_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, label labl) %{ 12405 match(If cmp flags); 12406 effect(USE labl); 12407 predicate( _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt || _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le ); 12408 ins_cost(300); 12409 expand %{ 12410 jmpCon(cmp,flags,labl); // JGT or JLE... 12411 %} 12412%} 12413 12414// Compare 2 longs and CMOVE longs. 12415instruct cmovLL_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, eRegL src) %{ 12416 match(Set dst (CMoveL (Binary cmp flags) (Binary dst src))); 12417 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12418 ins_cost(400); 12419 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12420 "CMOV$cmp $dst.hi,$src.hi" %} 12421 opcode(0x0F,0x40); 12422 ins_encode( enc_cmov(cmp), RegReg_Lo2( dst, src ), enc_cmov(cmp), RegReg_Hi2( dst, src ) ); 12423 ins_pipe( pipe_cmov_reg_long ); 12424%} 12425 12426instruct cmovLL_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegL dst, load_long_memory src) %{ 12427 match(Set dst (CMoveL (Binary cmp flags) (Binary dst (LoadL src)))); 12428 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12429 ins_cost(500); 12430 format %{ "CMOV$cmp $dst.lo,$src.lo\n\t" 12431 "CMOV$cmp $dst.hi,$src.hi+4" %} 12432 opcode(0x0F,0x40); 12433 ins_encode( enc_cmov(cmp), RegMem(dst, src), enc_cmov(cmp), RegMem_Hi(dst, src) ); 12434 ins_pipe( pipe_cmov_reg_long ); 12435%} 12436 12437// Compare 2 longs and CMOVE ints. 12438instruct cmovII_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, eRegI src) %{ 12439 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12440 match(Set dst (CMoveI (Binary cmp flags) (Binary dst src))); 12441 ins_cost(200); 12442 format %{ "CMOV$cmp $dst,$src" %} 12443 opcode(0x0F,0x40); 12444 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12445 ins_pipe( pipe_cmov_reg ); 12446%} 12447 12448instruct cmovII_mem_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegI dst, memory src) %{ 12449 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12450 match(Set dst (CMoveI (Binary cmp flags) (Binary dst (LoadI src)))); 12451 ins_cost(250); 12452 format %{ "CMOV$cmp $dst,$src" %} 12453 opcode(0x0F,0x40); 12454 ins_encode( enc_cmov(cmp), RegMem( dst, src ) ); 12455 ins_pipe( pipe_cmov_mem ); 12456%} 12457 12458// Compare 2 longs and CMOVE ptrs. 12459instruct cmovPP_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, eRegP dst, eRegP src) %{ 12460 predicate(VM_Version::supports_cmov() && ( _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt )); 12461 match(Set dst (CMoveP (Binary cmp flags) (Binary dst src))); 12462 ins_cost(200); 12463 format %{ "CMOV$cmp $dst,$src" %} 12464 opcode(0x0F,0x40); 12465 ins_encode( enc_cmov(cmp), RegReg( dst, src ) ); 12466 ins_pipe( pipe_cmov_reg ); 12467%} 12468 12469// Compare 2 longs and CMOVE doubles 12470instruct cmovDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regD dst, regD src) %{ 12471 predicate( UseSSE<=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 12472 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12473 ins_cost(200); 12474 expand %{ 12475 fcmovD_regS(cmp,flags,dst,src); 12476 %} 12477%} 12478 12479// Compare 2 longs and CMOVE doubles 12480instruct cmovXDD_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regXD dst, regXD src) %{ 12481 predicate( UseSSE>=2 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 12482 match(Set dst (CMoveD (Binary cmp flags) (Binary dst src))); 12483 ins_cost(200); 12484 expand %{ 12485 fcmovXD_regS(cmp,flags,dst,src); 12486 %} 12487%} 12488 12489instruct cmovFF_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regF dst, regF src) %{ 12490 predicate( UseSSE==0 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 12491 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12492 ins_cost(200); 12493 expand %{ 12494 fcmovF_regS(cmp,flags,dst,src); 12495 %} 12496%} 12497 12498 12499instruct cmovXX_reg_LEGT(cmpOp_commute cmp, flagsReg_long_LEGT flags, regX dst, regX src) %{ 12500 predicate( UseSSE>=1 && _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le || _kids[0]->_kids[0]->_leaf->as_Bool()->_test._test == BoolTest::gt ); 12501 match(Set dst (CMoveF (Binary cmp flags) (Binary dst src))); 12502 ins_cost(200); 12503 expand %{ 12504 fcmovX_regS(cmp,flags,dst,src); 12505 %} 12506%} 12507 12508 12509// ============================================================================ 12510// Procedure Call/Return Instructions 12511// Call Java Static Instruction 12512// Note: If this code changes, the corresponding ret_addr_offset() and 12513// compute_padding() functions will have to be adjusted. 12514instruct CallStaticJavaDirect(method meth) %{ 12515 match(CallStaticJava); 12516 effect(USE meth); 12517 12518 ins_cost(300); 12519 format %{ "CALL,static " %} 12520 opcode(0xE8); /* E8 cd */ 12521 ins_encode( pre_call_FPU, 12522 Java_Static_Call( meth ), 12523 call_epilog, 12524 post_call_FPU ); 12525 ins_pipe( pipe_slow ); 12526 ins_pc_relative(1); 12527 ins_alignment(4); 12528%} 12529 12530// Call Java Dynamic Instruction 12531// Note: If this code changes, the corresponding ret_addr_offset() and 12532// compute_padding() functions will have to be adjusted. 12533instruct CallDynamicJavaDirect(method meth) %{ 12534 match(CallDynamicJava); 12535 effect(USE meth); 12536 12537 ins_cost(300); 12538 format %{ "MOV EAX,(oop)-1\n\t" 12539 "CALL,dynamic" %} 12540 opcode(0xE8); /* E8 cd */ 12541 ins_encode( pre_call_FPU, 12542 Java_Dynamic_Call( meth ), 12543 call_epilog, 12544 post_call_FPU ); 12545 ins_pipe( pipe_slow ); 12546 ins_pc_relative(1); 12547 ins_alignment(4); 12548%} 12549 12550// Call Runtime Instruction 12551instruct CallRuntimeDirect(method meth) %{ 12552 match(CallRuntime ); 12553 effect(USE meth); 12554 12555 ins_cost(300); 12556 format %{ "CALL,runtime " %} 12557 opcode(0xE8); /* E8 cd */ 12558 // Use FFREEs to clear entries in float stack 12559 ins_encode( pre_call_FPU, 12560 FFree_Float_Stack_All, 12561 Java_To_Runtime( meth ), 12562 post_call_FPU ); 12563 ins_pipe( pipe_slow ); 12564 ins_pc_relative(1); 12565%} 12566 12567// Call runtime without safepoint 12568instruct CallLeafDirect(method meth) %{ 12569 match(CallLeaf); 12570 effect(USE meth); 12571 12572 ins_cost(300); 12573 format %{ "CALL_LEAF,runtime " %} 12574 opcode(0xE8); /* E8 cd */ 12575 ins_encode( pre_call_FPU, 12576 FFree_Float_Stack_All, 12577 Java_To_Runtime( meth ), 12578 Verify_FPU_For_Leaf, post_call_FPU ); 12579 ins_pipe( pipe_slow ); 12580 ins_pc_relative(1); 12581%} 12582 12583instruct CallLeafNoFPDirect(method meth) %{ 12584 match(CallLeafNoFP); 12585 effect(USE meth); 12586 12587 ins_cost(300); 12588 format %{ "CALL_LEAF_NOFP,runtime " %} 12589 opcode(0xE8); /* E8 cd */ 12590 ins_encode(Java_To_Runtime(meth)); 12591 ins_pipe( pipe_slow ); 12592 ins_pc_relative(1); 12593%} 12594 12595 12596// Return Instruction 12597// Remove the return address & jump to it. 12598instruct Ret() %{ 12599 match(Return); 12600 format %{ "RET" %} 12601 opcode(0xC3); 12602 ins_encode(OpcP); 12603 ins_pipe( pipe_jmp ); 12604%} 12605 12606// Tail Call; Jump from runtime stub to Java code. 12607// Also known as an 'interprocedural jump'. 12608// Target of jump will eventually return to caller. 12609// TailJump below removes the return address. 12610instruct TailCalljmpInd(eRegP_no_EBP jump_target, eBXRegP method_oop) %{ 12611 match(TailCall jump_target method_oop ); 12612 ins_cost(300); 12613 format %{ "JMP $jump_target \t# EBX holds method oop" %} 12614 opcode(0xFF, 0x4); /* Opcode FF /4 */ 12615 ins_encode( OpcP, RegOpc(jump_target) ); 12616 ins_pipe( pipe_jmp ); 12617%} 12618 12619 12620// Tail Jump; remove the return address; jump to target. 12621// TailCall above leaves the return address around. 12622instruct tailjmpInd(eRegP_no_EBP jump_target, eAXRegP ex_oop) %{ 12623 match( TailJump jump_target ex_oop ); 12624 ins_cost(300); 12625 format %{ "POP EDX\t# pop return address into dummy\n\t" 12626 "JMP $jump_target " %} 12627 opcode(0xFF, 0x4); /* Opcode FF /4 */ 12628 ins_encode( enc_pop_rdx, 12629 OpcP, RegOpc(jump_target) ); 12630 ins_pipe( pipe_jmp ); 12631%} 12632 12633// Create exception oop: created by stack-crawling runtime code. 12634// Created exception is now available to this handler, and is setup 12635// just prior to jumping to this handler. No code emitted. 12636instruct CreateException( eAXRegP ex_oop ) 12637%{ 12638 match(Set ex_oop (CreateEx)); 12639 12640 size(0); 12641 // use the following format syntax 12642 format %{ "# exception oop is in EAX; no code emitted" %} 12643 ins_encode(); 12644 ins_pipe( empty ); 12645%} 12646 12647 12648// Rethrow exception: 12649// The exception oop will come in the first argument position. 12650// Then JUMP (not call) to the rethrow stub code. 12651instruct RethrowException() 12652%{ 12653 match(Rethrow); 12654 12655 // use the following format syntax 12656 format %{ "JMP rethrow_stub" %} 12657 ins_encode(enc_rethrow); 12658 ins_pipe( pipe_jmp ); 12659%} 12660 12661// inlined locking and unlocking 12662 12663 12664instruct cmpFastLock( eFlagsReg cr, eRegP object, eRegP box, eAXRegI tmp, eRegP scr) %{ 12665 match( Set cr (FastLock object box) ); 12666 effect( TEMP tmp, TEMP scr ); 12667 ins_cost(300); 12668 format %{ "FASTLOCK $object, $box KILLS $tmp,$scr" %} 12669 ins_encode( Fast_Lock(object,box,tmp,scr) ); 12670 ins_pipe( pipe_slow ); 12671 ins_pc_relative(1); 12672%} 12673 12674instruct cmpFastUnlock( eFlagsReg cr, eRegP object, eAXRegP box, eRegP tmp ) %{ 12675 match( Set cr (FastUnlock object box) ); 12676 effect( TEMP tmp ); 12677 ins_cost(300); 12678 format %{ "FASTUNLOCK $object, $box, $tmp" %} 12679 ins_encode( Fast_Unlock(object,box,tmp) ); 12680 ins_pipe( pipe_slow ); 12681 ins_pc_relative(1); 12682%} 12683 12684 12685 12686// ============================================================================ 12687// Safepoint Instruction 12688instruct safePoint_poll(eFlagsReg cr) %{ 12689 match(SafePoint); 12690 effect(KILL cr); 12691 12692 // TODO-FIXME: we currently poll at offset 0 of the safepoint polling page. 12693 // On SPARC that might be acceptable as we can generate the address with 12694 // just a sethi, saving an or. By polling at offset 0 we can end up 12695 // putting additional pressure on the index-0 in the D$. Because of 12696 // alignment (just like the situation at hand) the lower indices tend 12697 // to see more traffic. It'd be better to change the polling address 12698 // to offset 0 of the last $line in the polling page. 12699 12700 format %{ "TSTL #polladdr,EAX\t! Safepoint: poll for GC" %} 12701 ins_cost(125); 12702 size(6) ; 12703 ins_encode( Safepoint_Poll() ); 12704 ins_pipe( ialu_reg_mem ); 12705%} 12706 12707//----------PEEPHOLE RULES----------------------------------------------------- 12708// These must follow all instruction definitions as they use the names 12709// defined in the instructions definitions. 12710// 12711// peepmatch ( root_instr_name [preceeding_instruction]* ); 12712// 12713// peepconstraint %{ 12714// (instruction_number.operand_name relational_op instruction_number.operand_name 12715// [, ...] ); 12716// // instruction numbers are zero-based using left to right order in peepmatch 12717// 12718// peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 12719// // provide an instruction_number.operand_name for each operand that appears 12720// // in the replacement instruction's match rule 12721// 12722// ---------VM FLAGS--------------------------------------------------------- 12723// 12724// All peephole optimizations can be turned off using -XX:-OptoPeephole 12725// 12726// Each peephole rule is given an identifying number starting with zero and 12727// increasing by one in the order seen by the parser. An individual peephole 12728// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 12729// on the command-line. 12730// 12731// ---------CURRENT LIMITATIONS---------------------------------------------- 12732// 12733// Only match adjacent instructions in same basic block 12734// Only equality constraints 12735// Only constraints between operands, not (0.dest_reg == EAX_enc) 12736// Only one replacement instruction 12737// 12738// ---------EXAMPLE---------------------------------------------------------- 12739// 12740// // pertinent parts of existing instructions in architecture description 12741// instruct movI(eRegI dst, eRegI src) %{ 12742// match(Set dst (CopyI src)); 12743// %} 12744// 12745// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 12746// match(Set dst (AddI dst src)); 12747// effect(KILL cr); 12748// %} 12749// 12750// // Change (inc mov) to lea 12751// peephole %{ 12752// // increment preceeded by register-register move 12753// peepmatch ( incI_eReg movI ); 12754// // require that the destination register of the increment 12755// // match the destination register of the move 12756// peepconstraint ( 0.dst == 1.dst ); 12757// // construct a replacement instruction that sets 12758// // the destination to ( move's source register + one ) 12759// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12760// %} 12761// 12762// Implementation no longer uses movX instructions since 12763// machine-independent system no longer uses CopyX nodes. 12764// 12765// peephole %{ 12766// peepmatch ( incI_eReg movI ); 12767// peepconstraint ( 0.dst == 1.dst ); 12768// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12769// %} 12770// 12771// peephole %{ 12772// peepmatch ( decI_eReg movI ); 12773// peepconstraint ( 0.dst == 1.dst ); 12774// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12775// %} 12776// 12777// peephole %{ 12778// peepmatch ( addI_eReg_imm movI ); 12779// peepconstraint ( 0.dst == 1.dst ); 12780// peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12781// %} 12782// 12783// peephole %{ 12784// peepmatch ( addP_eReg_imm movP ); 12785// peepconstraint ( 0.dst == 1.dst ); 12786// peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); 12787// %} 12788 12789// // Change load of spilled value to only a spill 12790// instruct storeI(memory mem, eRegI src) %{ 12791// match(Set mem (StoreI mem src)); 12792// %} 12793// 12794// instruct loadI(eRegI dst, memory mem) %{ 12795// match(Set dst (LoadI mem)); 12796// %} 12797// 12798peephole %{ 12799 peepmatch ( loadI storeI ); 12800 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12801 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 12802%} 12803 12804//----------SMARTSPILL RULES--------------------------------------------------- 12805// These must follow all instruction definitions as they use the names 12806// defined in the instructions definitions. 12807