register_x86.hpp revision 9149:a8a8604f890f 
1/*
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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5 * This code is free software; you can redistribute it and/or modify it
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7 * published by the Free Software Foundation.
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
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23 */
24
25#ifndef CPU_X86_VM_REGISTER_X86_HPP
26#define CPU_X86_VM_REGISTER_X86_HPP
27
28#include "asm/register.hpp"
29
30class VMRegImpl;
31typedef VMRegImpl* VMReg;
32
33// Use Register as shortcut
34class RegisterImpl;
35typedef RegisterImpl* Register;
36
37
38// The implementation of integer registers for the ia32 architecture
39inline Register as_Register(int encoding) {
40  return (Register)(intptr_t) encoding;
41}
42
43class RegisterImpl: public AbstractRegisterImpl {
44 public:
45  enum {
46#ifndef AMD64
47    number_of_registers      = 8,
48    number_of_byte_registers = 4,
49    max_slots_per_register   = 1
50#else
51    number_of_registers      = 16,
52    number_of_byte_registers = 16,
53    max_slots_per_register   = 1
54#endif // AMD64
55  };
56
57  // derived registers, offsets, and addresses
58  Register successor() const                          { return as_Register(encoding() + 1); }
59
60  // construction
61  inline friend Register as_Register(int encoding);
62
63  inline VMReg as_VMReg();
64
65  // accessors
66  int   encoding() const                         { assert(is_valid(), "invalid register"); return (intptr_t)this; }
67  bool  is_valid() const                         { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
68  bool  has_byte_register() const                { return 0 <= (intptr_t)this && (intptr_t)this < number_of_byte_registers; }
69  const char* name() const;
70};
71
72// The integer registers of the ia32/amd64 architecture
73
74CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1));
75
76
77CONSTANT_REGISTER_DECLARATION(Register, rax,    (0));
78CONSTANT_REGISTER_DECLARATION(Register, rcx,    (1));
79CONSTANT_REGISTER_DECLARATION(Register, rdx,    (2));
80CONSTANT_REGISTER_DECLARATION(Register, rbx,    (3));
81CONSTANT_REGISTER_DECLARATION(Register, rsp,    (4));
82CONSTANT_REGISTER_DECLARATION(Register, rbp,    (5));
83CONSTANT_REGISTER_DECLARATION(Register, rsi,    (6));
84CONSTANT_REGISTER_DECLARATION(Register, rdi,    (7));
85#ifdef AMD64
86CONSTANT_REGISTER_DECLARATION(Register, r8,     (8));
87CONSTANT_REGISTER_DECLARATION(Register, r9,     (9));
88CONSTANT_REGISTER_DECLARATION(Register, r10,   (10));
89CONSTANT_REGISTER_DECLARATION(Register, r11,   (11));
90CONSTANT_REGISTER_DECLARATION(Register, r12,   (12));
91CONSTANT_REGISTER_DECLARATION(Register, r13,   (13));
92CONSTANT_REGISTER_DECLARATION(Register, r14,   (14));
93CONSTANT_REGISTER_DECLARATION(Register, r15,   (15));
94#endif // AMD64
95
96// Use FloatRegister as shortcut
97class FloatRegisterImpl;
98typedef FloatRegisterImpl* FloatRegister;
99
100inline FloatRegister as_FloatRegister(int encoding) {
101  return (FloatRegister)(intptr_t) encoding;
102}
103
104// The implementation of floating point registers for the ia32 architecture
105class FloatRegisterImpl: public AbstractRegisterImpl {
106 public:
107  enum {
108    number_of_registers = 8
109  };
110
111  // construction
112  inline friend FloatRegister as_FloatRegister(int encoding);
113
114  inline VMReg as_VMReg();
115
116  // derived registers, offsets, and addresses
117
118  FloatRegister successor() const                          { return as_FloatRegister(encoding() + 1); }
119
120  // accessors
121  int   encoding() const                          { assert(is_valid(), "invalid register"); return (intptr_t)this; }
122  bool  is_valid() const                          { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
123  const char* name() const;
124
125};
126
127// Use XMMRegister as shortcut
128class XMMRegisterImpl;
129typedef XMMRegisterImpl* XMMRegister;
130
131// Use MMXRegister as shortcut
132class MMXRegisterImpl;
133typedef MMXRegisterImpl* MMXRegister;
134
135inline XMMRegister as_XMMRegister(int encoding) {
136  return (XMMRegister)(intptr_t)encoding;
137}
138
139inline MMXRegister as_MMXRegister(int encoding) {
140  return (MMXRegister)(intptr_t)encoding;
141}
142
143// The implementation of XMM registers for the IA32 architecture
144class XMMRegisterImpl: public AbstractRegisterImpl {
145 public:
146  enum {
147#ifndef AMD64
148    number_of_registers = 8,
149    max_slots_per_register = 16   // 512-bit
150#else
151    number_of_registers = 32,
152    max_slots_per_register = 16   // 512-bit
153#endif // AMD64
154  };
155
156  // construction
157  friend XMMRegister as_XMMRegister(int encoding);
158
159  inline VMReg as_VMReg();
160
161  // derived registers, offsets, and addresses
162  XMMRegister successor() const                          { return as_XMMRegister(encoding() + 1); }
163
164  // accessors
165  int   encoding() const                          { assert(is_valid(), "invalid register (%d)", (int)(intptr_t)this ); return (intptr_t)this; }
166  bool  is_valid() const                          { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
167  const char* name() const;
168  const char* sub_word_name(int offset) const;
169};
170
171
172// The XMM registers, for P3 and up chips
173CONSTANT_REGISTER_DECLARATION(XMMRegister, xnoreg , (-1));
174CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm0 , ( 0));
175CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm1 , ( 1));
176CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm2 , ( 2));
177CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm3 , ( 3));
178CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm4 , ( 4));
179CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm5 , ( 5));
180CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm6 , ( 6));
181CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm7 , ( 7));
182#ifdef AMD64
183CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm8,      (8));
184CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm9,      (9));
185CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm10,    (10));
186CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm11,    (11));
187CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm12,    (12));
188CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm13,    (13));
189CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm14,    (14));
190CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm15,    (15));
191CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm16,    (16));
192CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm17,    (17));
193CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm18,    (18));
194CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm19,    (19));
195CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm20,    (20));
196CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm21,    (21));
197CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm22,    (22));
198CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm23,    (23));
199CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm24,    (24));
200CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm25,    (25));
201CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm26,    (26));
202CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm27,    (27));
203CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm28,    (28));
204CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm29,    (29));
205CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm30,    (30));
206CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm31,    (31));
207#endif // AMD64
208
209// Only used by the 32bit stubGenerator. These can't be described by vmreg and hence
210// can't be described in oopMaps and therefore can't be used by the compilers (at least
211// were deopt might wan't to see them).
212
213// The MMX registers, for P3 and up chips
214CONSTANT_REGISTER_DECLARATION(MMXRegister, mnoreg , (-1));
215CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx0 , ( 0));
216CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx1 , ( 1));
217CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx2 , ( 2));
218CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx3 , ( 3));
219CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx4 , ( 4));
220CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx5 , ( 5));
221CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx6 , ( 6));
222CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx7 , ( 7));
223
224// Use XMMRegister as shortcut
225class KRegisterImpl;
226typedef KRegisterImpl* KRegister;
227
228inline KRegister as_KRegister(int encoding) {
229  return (KRegister)(intptr_t)encoding;
230}
231
232// The implementation of XMM registers for the IA32 architecture
233class KRegisterImpl : public AbstractRegisterImpl {
234public:
235  enum {
236    number_of_registers = 8,
237    max_slots_per_register = 1
238  };
239
240  // construction
241  friend KRegister as_KRegister(int encoding);
242
243  inline VMReg as_VMReg();
244
245  // derived registers, offsets, and addresses
246  KRegister successor() const                          { return as_KRegister(encoding() + 1); }
247
248  // accessors
249  int   encoding() const                          { assert(is_valid(), "invalid register (%d)", (int)(intptr_t)this); return (intptr_t)this; }
250  bool  is_valid() const                          { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
251  const char* name() const;
252};
253
254// The Mask registers, for AVX3 enabled and up chips
255CONSTANT_REGISTER_DECLARATION(KRegister, knoreg, (-1));
256CONSTANT_REGISTER_DECLARATION(KRegister, k0, (0));
257CONSTANT_REGISTER_DECLARATION(KRegister, k1, (1));
258CONSTANT_REGISTER_DECLARATION(KRegister, k2, (2));
259CONSTANT_REGISTER_DECLARATION(KRegister, k3, (3));
260CONSTANT_REGISTER_DECLARATION(KRegister, k4, (4));
261CONSTANT_REGISTER_DECLARATION(KRegister, k5, (5));
262CONSTANT_REGISTER_DECLARATION(KRegister, k6, (6));
263CONSTANT_REGISTER_DECLARATION(KRegister, k7, (7));
264
265// Need to know the total number of registers of all sorts for SharedInfo.
266// Define a class that exports it.
267class ConcreteRegisterImpl : public AbstractRegisterImpl {
268 public:
269  enum {
270  // A big enough number for C2: all the registers plus flags
271  // This number must be large enough to cover REG_COUNT (defined by c2) registers.
272  // There is no requirement that any ordering here matches any ordering c2 gives
273  // it's optoregs.
274
275    number_of_registers = RegisterImpl::number_of_registers +
276#ifdef AMD64
277      RegisterImpl::number_of_registers +  // "H" half of a 64bit register
278#endif // AMD64
279      2 * FloatRegisterImpl::number_of_registers +
280      XMMRegisterImpl::max_slots_per_register * XMMRegisterImpl::number_of_registers +
281      KRegisterImpl::number_of_registers + // mask registers
282      1 // eflags
283  };
284
285  static const int max_gpr;
286  static const int max_fpr;
287  static const int max_xmm;
288  static const int max_kpr;
289
290};
291
292#endif // CPU_X86_VM_REGISTER_X86_HPP
293