register_x86.hpp revision 9111:a41fe5ffa839
1169695Skan/* 2169695Skan * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved. 3169695Skan * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4169695Skan * 5169695Skan * This code is free software; you can redistribute it and/or modify it 6169695Skan * under the terms of the GNU General Public License version 2 only, as 7169695Skan * published by the Free Software Foundation. 8169695Skan * 9169695Skan * This code is distributed in the hope that it will be useful, but WITHOUT 10169695Skan * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11169695Skan * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12169695Skan * version 2 for more details (a copy is included in the LICENSE file that 13169695Skan * accompanied this code). 14169695Skan * 15169695Skan * You should have received a copy of the GNU General Public License version 16169695Skan * 2 along with this work; if not, write to the Free Software Foundation, 17169695Skan * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18169695Skan * 19169695Skan * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20169695Skan * or visit www.oracle.com if you need additional information or have any 21169695Skan * questions. 22169695Skan * 23169695Skan */ 24169695Skan 25169695Skan#ifndef CPU_X86_VM_REGISTER_X86_HPP 26169695Skan#define CPU_X86_VM_REGISTER_X86_HPP 27169695Skan 28169695Skan#include "asm/register.hpp" 29169695Skan 30169695Skanclass VMRegImpl; 31169695Skantypedef VMRegImpl* VMReg; 32169695Skan 33169695Skan// Use Register as shortcut 34169695Skanclass RegisterImpl; 35169695Skantypedef RegisterImpl* Register; 36169695Skan 37169695Skan 38169695Skan// The implementation of integer registers for the ia32 architecture 39169695Skaninline Register as_Register(int encoding) { 40169695Skan return (Register)(intptr_t) encoding; 41169695Skan} 42169695Skan 43169695Skanclass RegisterImpl: public AbstractRegisterImpl { 44169695Skan public: 45169695Skan enum { 46169695Skan#ifndef AMD64 47169695Skan number_of_registers = 8, 48169695Skan number_of_byte_registers = 4, 49169695Skan max_slots_per_register = 1 50169695Skan#else 51169695Skan number_of_registers = 16, 52169695Skan number_of_byte_registers = 16, 53169695Skan max_slots_per_register = 1 54169695Skan#endif // AMD64 55169695Skan }; 56169695Skan 57169695Skan // derived registers, offsets, and addresses 58169695Skan Register successor() const { return as_Register(encoding() + 1); } 59169695Skan 60169695Skan // construction 61282152Spfg inline friend Register as_Register(int encoding); 62169695Skan 63169695Skan inline VMReg as_VMReg(); 64169695Skan 65282152Spfg // accessors 66169695Skan int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } 67169695Skan bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } 68169695Skan bool has_byte_register() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_byte_registers; } 69169695Skan const char* name() const; 70169695Skan}; 71169695Skan 72169695Skan// The integer registers of the ia32/amd64 architecture 73169695Skan 74169695SkanCONSTANT_REGISTER_DECLARATION(Register, noreg, (-1)); 75169695Skan 76169695Skan 77169695SkanCONSTANT_REGISTER_DECLARATION(Register, rax, (0)); 78169695SkanCONSTANT_REGISTER_DECLARATION(Register, rcx, (1)); 79169695SkanCONSTANT_REGISTER_DECLARATION(Register, rdx, (2)); 80169695SkanCONSTANT_REGISTER_DECLARATION(Register, rbx, (3)); 81169695SkanCONSTANT_REGISTER_DECLARATION(Register, rsp, (4)); 82169695SkanCONSTANT_REGISTER_DECLARATION(Register, rbp, (5)); 83169695SkanCONSTANT_REGISTER_DECLARATION(Register, rsi, (6)); 84169695SkanCONSTANT_REGISTER_DECLARATION(Register, rdi, (7)); 85169695Skan#ifdef AMD64 86169695SkanCONSTANT_REGISTER_DECLARATION(Register, r8, (8)); 87169695SkanCONSTANT_REGISTER_DECLARATION(Register, r9, (9)); 88169695SkanCONSTANT_REGISTER_DECLARATION(Register, r10, (10)); 89169695SkanCONSTANT_REGISTER_DECLARATION(Register, r11, (11)); 90169695SkanCONSTANT_REGISTER_DECLARATION(Register, r12, (12)); 91169695SkanCONSTANT_REGISTER_DECLARATION(Register, r13, (13)); 92169695SkanCONSTANT_REGISTER_DECLARATION(Register, r14, (14)); 93169695SkanCONSTANT_REGISTER_DECLARATION(Register, r15, (15)); 94169695Skan#endif // AMD64 95169695Skan 96169695Skan// Use FloatRegister as shortcut 97169695Skanclass FloatRegisterImpl; 98169695Skantypedef FloatRegisterImpl* FloatRegister; 99169695Skan 100169695Skaninline FloatRegister as_FloatRegister(int encoding) { 101169695Skan return (FloatRegister)(intptr_t) encoding; 102169695Skan} 103169695Skan 104169695Skan// The implementation of floating point registers for the ia32 architecture 105169695Skanclass FloatRegisterImpl: public AbstractRegisterImpl { 106169695Skan public: 107169695Skan enum { 108169695Skan number_of_registers = 8 109169695Skan }; 110169695Skan 111169695Skan // construction 112169695Skan inline friend FloatRegister as_FloatRegister(int encoding); 113169695Skan 114169695Skan inline VMReg as_VMReg(); 115169695Skan 116169695Skan // derived registers, offsets, and addresses 117169695Skan 118169695Skan FloatRegister successor() const { return as_FloatRegister(encoding() + 1); } 119169695Skan 120169695Skan // accessors 121169695Skan int encoding() const { assert(is_valid(), "invalid register"); return (intptr_t)this; } 122169695Skan bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } 123169695Skan const char* name() const; 124169695Skan 125169695Skan}; 126169695Skan 127169695Skan// Use XMMRegister as shortcut 128169695Skanclass XMMRegisterImpl; 129169695Skantypedef XMMRegisterImpl* XMMRegister; 130169695Skan 131169695Skan// Use MMXRegister as shortcut 132282152Spfgclass MMXRegisterImpl; 133169695Skantypedef MMXRegisterImpl* MMXRegister; 134169695Skan 135169695Skaninline XMMRegister as_XMMRegister(int encoding) { 136169695Skan return (XMMRegister)(intptr_t)encoding; 137169695Skan} 138169695Skan 139169695Skaninline MMXRegister as_MMXRegister(int encoding) { 140169695Skan return (MMXRegister)(intptr_t)encoding; 141169695Skan} 142169695Skan 143169695Skan// The implementation of XMM registers for the IA32 architecture 144169695Skanclass XMMRegisterImpl: public AbstractRegisterImpl { 145169695Skan public: 146169695Skan enum { 147169695Skan#ifndef AMD64 148169695Skan number_of_registers = 8, 149169695Skan max_slots_per_register = 16 // 512-bit 150169695Skan#else 151169695Skan number_of_registers = 32, 152169695Skan max_slots_per_register = 16 // 512-bit 153169695Skan#endif // AMD64 154169695Skan }; 155169695Skan 156169695Skan // construction 157282201Spfg friend XMMRegister as_XMMRegister(int encoding); 158169695Skan 159169695Skan inline VMReg as_VMReg(); 160169695Skan 161169695Skan // derived registers, offsets, and addresses 162169695Skan XMMRegister successor() const { return as_XMMRegister(encoding() + 1); } 163169695Skan 164169695Skan // accessors 165169695Skan int encoding() const { assert(is_valid(), err_msg("invalid register (%d)", (int)(intptr_t)this )); return (intptr_t)this; } 166169695Skan bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } 167169695Skan const char* name() const; 168169695Skan const char* sub_word_name(int offset) const; 169169695Skan}; 170169695Skan 171169695Skan 172169695Skan// The XMM registers, for P3 and up chips 173169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xnoreg , (-1)); 174169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm0 , ( 0)); 175169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm1 , ( 1)); 176169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm2 , ( 2)); 177169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm3 , ( 3)); 178169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm4 , ( 4)); 179169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm5 , ( 5)); 180169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm6 , ( 6)); 181169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm7 , ( 7)); 182169695Skan#ifdef AMD64 183169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm8, (8)); 184169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm9, (9)); 185169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm10, (10)); 186169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm11, (11)); 187169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm12, (12)); 188169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm13, (13)); 189169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm14, (14)); 190169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm15, (15)); 191169695SkanCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm16, (16)); 192282152SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm17, (17)); 193282152SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm18, (18)); 194282115SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm19, (19)); 195282115SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm20, (20)); 196282115SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm21, (21)); 197282115SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm22, (22)); 198282115SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm23, (23)); 199282115SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm24, (24)); 200282115SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm25, (25)); 201282115SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm26, (26)); 202282115SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm27, (27)); 203282115SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm28, (28)); 204282115SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm29, (29)); 205282115SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm30, (30)); 206282115SpfgCONSTANT_REGISTER_DECLARATION(XMMRegister, xmm31, (31)); 207282115Spfg#endif // AMD64 208282115Spfg 209282115Spfg// Only used by the 32bit stubGenerator. These can't be described by vmreg and hence 210282115Spfg// can't be described in oopMaps and therefore can't be used by the compilers (at least 211282115Spfg// were deopt might wan't to see them). 212282115Spfg 213169695Skan// The MMX registers, for P3 and up chips 214169695SkanCONSTANT_REGISTER_DECLARATION(MMXRegister, mnoreg , (-1)); 215169695SkanCONSTANT_REGISTER_DECLARATION(MMXRegister, mmx0 , ( 0)); 216169695SkanCONSTANT_REGISTER_DECLARATION(MMXRegister, mmx1 , ( 1)); 217169695SkanCONSTANT_REGISTER_DECLARATION(MMXRegister, mmx2 , ( 2)); 218169695SkanCONSTANT_REGISTER_DECLARATION(MMXRegister, mmx3 , ( 3)); 219169695SkanCONSTANT_REGISTER_DECLARATION(MMXRegister, mmx4 , ( 4)); 220169695SkanCONSTANT_REGISTER_DECLARATION(MMXRegister, mmx5 , ( 5)); 221169695SkanCONSTANT_REGISTER_DECLARATION(MMXRegister, mmx6 , ( 6)); 222169695SkanCONSTANT_REGISTER_DECLARATION(MMXRegister, mmx7 , ( 7)); 223169695Skan 224169695Skan// Use XMMRegister as shortcut 225169695Skanclass KRegisterImpl; 226169695Skantypedef KRegisterImpl* KRegister; 227169695Skan 228169695Skaninline KRegister as_KRegister(int encoding) { 229169695Skan return (KRegister)(intptr_t)encoding; 230169695Skan} 231169695Skan 232169695Skan// The implementation of XMM registers for the IA32 architecture 233169695Skanclass KRegisterImpl : public AbstractRegisterImpl { 234169695Skanpublic: 235169695Skan enum { 236169695Skan number_of_registers = 8, 237169695Skan max_slots_per_register = 1 238169695Skan }; 239169695Skan 240169695Skan // construction 241169695Skan friend KRegister as_KRegister(int encoding); 242169695Skan 243169695Skan inline VMReg as_VMReg(); 244169695Skan 245169695Skan // derived registers, offsets, and addresses 246169695Skan KRegister successor() const { return as_KRegister(encoding() + 1); } 247169695Skan 248169695Skan // accessors 249169695Skan int encoding() const { assert(is_valid(), err_msg("invalid register (%d)", (int)(intptr_t)this)); return (intptr_t)this; } 250169695Skan bool is_valid() const { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; } 251169695Skan const char* name() const; 252169695Skan}; 253169695Skan 254169695Skan// The Mask registers, for AVX3 enabled and up chips 255169695SkanCONSTANT_REGISTER_DECLARATION(KRegister, knoreg, (-1)); 256169695SkanCONSTANT_REGISTER_DECLARATION(KRegister, k0, (0)); 257169695SkanCONSTANT_REGISTER_DECLARATION(KRegister, k1, (1)); 258169695SkanCONSTANT_REGISTER_DECLARATION(KRegister, k2, (2)); 259169695SkanCONSTANT_REGISTER_DECLARATION(KRegister, k3, (3)); 260169695SkanCONSTANT_REGISTER_DECLARATION(KRegister, k4, (4)); 261169695SkanCONSTANT_REGISTER_DECLARATION(KRegister, k5, (5)); 262169695SkanCONSTANT_REGISTER_DECLARATION(KRegister, k6, (6)); 263169695SkanCONSTANT_REGISTER_DECLARATION(KRegister, k7, (7)); 264169695Skan 265169695Skan// Need to know the total number of registers of all sorts for SharedInfo. 266169695Skan// Define a class that exports it. 267169695Skanclass ConcreteRegisterImpl : public AbstractRegisterImpl { 268169695Skan public: 269169695Skan enum { 270169695Skan // A big enough number for C2: all the registers plus flags 271169695Skan // This number must be large enough to cover REG_COUNT (defined by c2) registers. 272169695Skan // There is no requirement that any ordering here matches any ordering c2 gives 273169695Skan // it's optoregs. 274169695Skan 275169695Skan number_of_registers = RegisterImpl::number_of_registers + 276169695Skan#ifdef AMD64 277169695Skan RegisterImpl::number_of_registers + // "H" half of a 64bit register 278169695Skan#endif // AMD64 279169695Skan 2 * FloatRegisterImpl::number_of_registers + 280169695Skan XMMRegisterImpl::max_slots_per_register * XMMRegisterImpl::number_of_registers + 281169695Skan KRegisterImpl::number_of_registers + // mask registers 282169695Skan 1 // eflags 283169695Skan }; 284169695Skan 285169695Skan static const int max_gpr; 286169695Skan static const int max_fpr; 287169695Skan static const int max_xmm; 288169695Skan static const int max_kpr; 289169695Skan 290169695Skan}; 291169695Skan 292169695Skan#endif // CPU_X86_VM_REGISTER_X86_HPP 293169695Skan