register_x86.hpp revision 6760:22b98ab2a69f 
1/*
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24
25#ifndef CPU_X86_VM_REGISTER_X86_HPP
26#define CPU_X86_VM_REGISTER_X86_HPP
27
28#include "asm/register.hpp"
29
30class VMRegImpl;
31typedef VMRegImpl* VMReg;
32
33// Use Register as shortcut
34class RegisterImpl;
35typedef RegisterImpl* Register;
36
37
38// The implementation of integer registers for the ia32 architecture
39inline Register as_Register(int encoding) {
40  return (Register)(intptr_t) encoding;
41}
42
43class RegisterImpl: public AbstractRegisterImpl {
44 public:
45  enum {
46#ifndef AMD64
47    number_of_registers      = 8,
48    number_of_byte_registers = 4
49#else
50    number_of_registers      = 16,
51    number_of_byte_registers = 16
52#endif // AMD64
53  };
54
55  // derived registers, offsets, and addresses
56  Register successor() const                          { return as_Register(encoding() + 1); }
57
58  // construction
59  inline friend Register as_Register(int encoding);
60
61  inline VMReg as_VMReg();
62
63  // accessors
64  int   encoding() const                         { assert(is_valid(), "invalid register"); return (intptr_t)this; }
65  bool  is_valid() const                         { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
66  bool  has_byte_register() const                { return 0 <= (intptr_t)this && (intptr_t)this < number_of_byte_registers; }
67  const char* name() const;
68};
69
70// The integer registers of the ia32/amd64 architecture
71
72CONSTANT_REGISTER_DECLARATION(Register, noreg, (-1));
73
74
75CONSTANT_REGISTER_DECLARATION(Register, rax,    (0));
76CONSTANT_REGISTER_DECLARATION(Register, rcx,    (1));
77CONSTANT_REGISTER_DECLARATION(Register, rdx,    (2));
78CONSTANT_REGISTER_DECLARATION(Register, rbx,    (3));
79CONSTANT_REGISTER_DECLARATION(Register, rsp,    (4));
80CONSTANT_REGISTER_DECLARATION(Register, rbp,    (5));
81CONSTANT_REGISTER_DECLARATION(Register, rsi,    (6));
82CONSTANT_REGISTER_DECLARATION(Register, rdi,    (7));
83#ifdef AMD64
84CONSTANT_REGISTER_DECLARATION(Register, r8,     (8));
85CONSTANT_REGISTER_DECLARATION(Register, r9,     (9));
86CONSTANT_REGISTER_DECLARATION(Register, r10,   (10));
87CONSTANT_REGISTER_DECLARATION(Register, r11,   (11));
88CONSTANT_REGISTER_DECLARATION(Register, r12,   (12));
89CONSTANT_REGISTER_DECLARATION(Register, r13,   (13));
90CONSTANT_REGISTER_DECLARATION(Register, r14,   (14));
91CONSTANT_REGISTER_DECLARATION(Register, r15,   (15));
92#endif // AMD64
93
94// Use FloatRegister as shortcut
95class FloatRegisterImpl;
96typedef FloatRegisterImpl* FloatRegister;
97
98inline FloatRegister as_FloatRegister(int encoding) {
99  return (FloatRegister)(intptr_t) encoding;
100}
101
102// The implementation of floating point registers for the ia32 architecture
103class FloatRegisterImpl: public AbstractRegisterImpl {
104 public:
105  enum {
106    number_of_registers = 8
107  };
108
109  // construction
110  inline friend FloatRegister as_FloatRegister(int encoding);
111
112  inline VMReg as_VMReg();
113
114  // derived registers, offsets, and addresses
115
116  FloatRegister successor() const                          { return as_FloatRegister(encoding() + 1); }
117
118  // accessors
119  int   encoding() const                          { assert(is_valid(), "invalid register"); return (intptr_t)this; }
120  bool  is_valid() const                          { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
121  const char* name() const;
122
123};
124
125// Use XMMRegister as shortcut
126class XMMRegisterImpl;
127typedef XMMRegisterImpl* XMMRegister;
128
129// Use MMXRegister as shortcut
130class MMXRegisterImpl;
131typedef MMXRegisterImpl* MMXRegister;
132
133inline XMMRegister as_XMMRegister(int encoding) {
134  return (XMMRegister)(intptr_t)encoding;
135}
136
137inline MMXRegister as_MMXRegister(int encoding) {
138  return (MMXRegister)(intptr_t)encoding;
139}
140
141// The implementation of XMM registers for the IA32 architecture
142class XMMRegisterImpl: public AbstractRegisterImpl {
143 public:
144  enum {
145#ifndef AMD64
146    number_of_registers = 8
147#else
148    number_of_registers = 16
149#endif // AMD64
150  };
151
152  // construction
153  friend XMMRegister as_XMMRegister(int encoding);
154
155  inline VMReg as_VMReg();
156
157  // derived registers, offsets, and addresses
158  XMMRegister successor() const                          { return as_XMMRegister(encoding() + 1); }
159
160  // accessors
161  int   encoding() const                          { assert(is_valid(), err_msg("invalid register (%d)", (int)(intptr_t)this )); return (intptr_t)this; }
162  bool  is_valid() const                          { return 0 <= (intptr_t)this && (intptr_t)this < number_of_registers; }
163  const char* name() const;
164};
165
166
167// The XMM registers, for P3 and up chips
168CONSTANT_REGISTER_DECLARATION(XMMRegister, xnoreg , (-1));
169CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm0 , ( 0));
170CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm1 , ( 1));
171CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm2 , ( 2));
172CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm3 , ( 3));
173CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm4 , ( 4));
174CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm5 , ( 5));
175CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm6 , ( 6));
176CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm7 , ( 7));
177#ifdef AMD64
178CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm8,      (8));
179CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm9,      (9));
180CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm10,    (10));
181CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm11,    (11));
182CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm12,    (12));
183CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm13,    (13));
184CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm14,    (14));
185CONSTANT_REGISTER_DECLARATION(XMMRegister, xmm15,    (15));
186#endif // AMD64
187
188// Only used by the 32bit stubGenerator. These can't be described by vmreg and hence
189// can't be described in oopMaps and therefore can't be used by the compilers (at least
190// were deopt might wan't to see them).
191
192// The MMX registers, for P3 and up chips
193CONSTANT_REGISTER_DECLARATION(MMXRegister, mnoreg , (-1));
194CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx0 , ( 0));
195CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx1 , ( 1));
196CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx2 , ( 2));
197CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx3 , ( 3));
198CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx4 , ( 4));
199CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx5 , ( 5));
200CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx6 , ( 6));
201CONSTANT_REGISTER_DECLARATION(MMXRegister, mmx7 , ( 7));
202
203
204// Need to know the total number of registers of all sorts for SharedInfo.
205// Define a class that exports it.
206class ConcreteRegisterImpl : public AbstractRegisterImpl {
207 public:
208  enum {
209  // A big enough number for C2: all the registers plus flags
210  // This number must be large enough to cover REG_COUNT (defined by c2) registers.
211  // There is no requirement that any ordering here matches any ordering c2 gives
212  // it's optoregs.
213
214    number_of_registers =      RegisterImpl::number_of_registers +
215#ifdef AMD64
216                               RegisterImpl::number_of_registers +  // "H" half of a 64bit register
217#endif // AMD64
218                           2 * FloatRegisterImpl::number_of_registers +
219                           8 * XMMRegisterImpl::number_of_registers +
220                           1 // eflags
221  };
222
223  static const int max_gpr;
224  static const int max_fpr;
225  static const int max_xmm;
226
227};
228
229#endif // CPU_X86_VM_REGISTER_X86_HPP
230