macroAssembler_x86.hpp revision 4438:e961c11b85fe
1/* 2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25#ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP 26#define CPU_X86_VM_MACROASSEMBLER_X86_HPP 27 28#include "asm/assembler.hpp" 29#include "utilities/macros.hpp" 30 31 32// MacroAssembler extends Assembler by frequently used macros. 33// 34// Instructions for which a 'better' code sequence exists depending 35// on arguments should also go in here. 36 37class MacroAssembler: public Assembler { 38 friend class LIR_Assembler; 39 friend class Runtime1; // as_Address() 40 41 protected: 42 43 Address as_Address(AddressLiteral adr); 44 Address as_Address(ArrayAddress adr); 45 46 // Support for VM calls 47 // 48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 49 // may customize this version by overriding it for its purposes (e.g., to save/restore 50 // additional registers when doing a VM call). 51#ifdef CC_INTERP 52 // c++ interpreter never wants to use interp_masm version of call_VM 53 #define VIRTUAL 54#else 55 #define VIRTUAL virtual 56#endif 57 58 VIRTUAL void call_VM_leaf_base( 59 address entry_point, // the entry point 60 int number_of_arguments // the number of arguments to pop after the call 61 ); 62 63 // This is the base routine called by the different versions of call_VM. The interpreter 64 // may customize this version by overriding it for its purposes (e.g., to save/restore 65 // additional registers when doing a VM call). 66 // 67 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base 68 // returns the register which contains the thread upon return. If a thread register has been 69 // specified, the return value will correspond to that register. If no last_java_sp is specified 70 // (noreg) than rsp will be used instead. 71 VIRTUAL void call_VM_base( // returns the register containing the thread upon return 72 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 73 Register java_thread, // the thread if computed before ; use noreg otherwise 74 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 75 address entry_point, // the entry point 76 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 77 bool check_exceptions // whether to check for pending exceptions after return 78 ); 79 80 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 81 // The implementation is only non-empty for the InterpreterMacroAssembler, 82 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 83 virtual void check_and_handle_popframe(Register java_thread); 84 virtual void check_and_handle_earlyret(Register java_thread); 85 86 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 87 88 // helpers for FPU flag access 89 // tmp is a temporary register, if none is available use noreg 90 void save_rax (Register tmp); 91 void restore_rax(Register tmp); 92 93 public: 94 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 95 96 // Support for NULL-checks 97 // 98 // Generates code that causes a NULL OS exception if the content of reg is NULL. 99 // If the accessed location is M[reg + offset] and the offset is known, provide the 100 // offset. No explicit code generation is needed if the offset is within a certain 101 // range (0 <= offset <= page_size). 102 103 void null_check(Register reg, int offset = -1); 104 static bool needs_explicit_null_check(intptr_t offset); 105 106 // Required platform-specific helpers for Label::patch_instructions. 107 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 108 void pd_patch_instruction(address branch, address target) { 109 unsigned char op = branch[0]; 110 assert(op == 0xE8 /* call */ || 111 op == 0xE9 /* jmp */ || 112 op == 0xEB /* short jmp */ || 113 (op & 0xF0) == 0x70 /* short jcc */ || 114 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */, 115 "Invalid opcode at patch point"); 116 117 if (op == 0xEB || (op & 0xF0) == 0x70) { 118 // short offset operators (jmp and jcc) 119 char* disp = (char*) &branch[1]; 120 int imm8 = target - (address) &disp[1]; 121 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset"); 122 *disp = imm8; 123 } else { 124 int* disp = (int*) &branch[(op == 0x0F)? 2: 1]; 125 int imm32 = target - (address) &disp[1]; 126 *disp = imm32; 127 } 128 } 129 130 // The following 4 methods return the offset of the appropriate move instruction 131 132 // Support for fast byte/short loading with zero extension (depending on particular CPU) 133 int load_unsigned_byte(Register dst, Address src); 134 int load_unsigned_short(Register dst, Address src); 135 136 // Support for fast byte/short loading with sign extension (depending on particular CPU) 137 int load_signed_byte(Register dst, Address src); 138 int load_signed_short(Register dst, Address src); 139 140 // Support for sign-extension (hi:lo = extend_sign(lo)) 141 void extend_sign(Register hi, Register lo); 142 143 // Load and store values by size and signed-ness 144 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); 145 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); 146 147 // Support for inc/dec with optimal instruction selection depending on value 148 149 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } 150 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } 151 152 void decrementl(Address dst, int value = 1); 153 void decrementl(Register reg, int value = 1); 154 155 void decrementq(Register reg, int value = 1); 156 void decrementq(Address dst, int value = 1); 157 158 void incrementl(Address dst, int value = 1); 159 void incrementl(Register reg, int value = 1); 160 161 void incrementq(Register reg, int value = 1); 162 void incrementq(Address dst, int value = 1); 163 164 165 // Support optimal SSE move instructions. 166 void movflt(XMMRegister dst, XMMRegister src) { 167 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } 168 else { movss (dst, src); return; } 169 } 170 void movflt(XMMRegister dst, Address src) { movss(dst, src); } 171 void movflt(XMMRegister dst, AddressLiteral src); 172 void movflt(Address dst, XMMRegister src) { movss(dst, src); } 173 174 void movdbl(XMMRegister dst, XMMRegister src) { 175 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } 176 else { movsd (dst, src); return; } 177 } 178 179 void movdbl(XMMRegister dst, AddressLiteral src); 180 181 void movdbl(XMMRegister dst, Address src) { 182 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } 183 else { movlpd(dst, src); return; } 184 } 185 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } 186 187 void incrementl(AddressLiteral dst); 188 void incrementl(ArrayAddress dst); 189 190 // Alignment 191 void align(int modulus); 192 193 // A 5 byte nop that is safe for patching (see patch_verified_entry) 194 void fat_nop(); 195 196 // Stack frame creation/removal 197 void enter(); 198 void leave(); 199 200 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 201 // The pointer will be loaded into the thread register. 202 void get_thread(Register thread); 203 204 205 // Support for VM calls 206 // 207 // It is imperative that all calls into the VM are handled via the call_VM macros. 208 // They make sure that the stack linkage is setup correctly. call_VM's correspond 209 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 210 211 212 void call_VM(Register oop_result, 213 address entry_point, 214 bool check_exceptions = true); 215 void call_VM(Register oop_result, 216 address entry_point, 217 Register arg_1, 218 bool check_exceptions = true); 219 void call_VM(Register oop_result, 220 address entry_point, 221 Register arg_1, Register arg_2, 222 bool check_exceptions = true); 223 void call_VM(Register oop_result, 224 address entry_point, 225 Register arg_1, Register arg_2, Register arg_3, 226 bool check_exceptions = true); 227 228 // Overloadings with last_Java_sp 229 void call_VM(Register oop_result, 230 Register last_java_sp, 231 address entry_point, 232 int number_of_arguments = 0, 233 bool check_exceptions = true); 234 void call_VM(Register oop_result, 235 Register last_java_sp, 236 address entry_point, 237 Register arg_1, bool 238 check_exceptions = true); 239 void call_VM(Register oop_result, 240 Register last_java_sp, 241 address entry_point, 242 Register arg_1, Register arg_2, 243 bool check_exceptions = true); 244 void call_VM(Register oop_result, 245 Register last_java_sp, 246 address entry_point, 247 Register arg_1, Register arg_2, Register arg_3, 248 bool check_exceptions = true); 249 250 void get_vm_result (Register oop_result, Register thread); 251 void get_vm_result_2(Register metadata_result, Register thread); 252 253 // These always tightly bind to MacroAssembler::call_VM_base 254 // bypassing the virtual implementation 255 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); 260 261 void call_VM_leaf(address entry_point, 262 int number_of_arguments = 0); 263 void call_VM_leaf(address entry_point, 264 Register arg_1); 265 void call_VM_leaf(address entry_point, 266 Register arg_1, Register arg_2); 267 void call_VM_leaf(address entry_point, 268 Register arg_1, Register arg_2, Register arg_3); 269 270 // These always tightly bind to MacroAssembler::call_VM_leaf_base 271 // bypassing the virtual implementation 272 void super_call_VM_leaf(address entry_point); 273 void super_call_VM_leaf(address entry_point, Register arg_1); 274 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 275 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 276 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); 277 278 // last Java Frame (fills frame anchor) 279 void set_last_Java_frame(Register thread, 280 Register last_java_sp, 281 Register last_java_fp, 282 address last_java_pc); 283 284 // thread in the default location (r15_thread on 64bit) 285 void set_last_Java_frame(Register last_java_sp, 286 Register last_java_fp, 287 address last_java_pc); 288 289 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); 290 291 // thread in the default location (r15_thread on 64bit) 292 void reset_last_Java_frame(bool clear_fp, bool clear_pc); 293 294 // Stores 295 void store_check(Register obj); // store check for obj - register is destroyed afterwards 296 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 297 298#if INCLUDE_ALL_GCS 299 300 void g1_write_barrier_pre(Register obj, 301 Register pre_val, 302 Register thread, 303 Register tmp, 304 bool tosca_live, 305 bool expand_call); 306 307 void g1_write_barrier_post(Register store_addr, 308 Register new_val, 309 Register thread, 310 Register tmp, 311 Register tmp2); 312 313#endif // INCLUDE_ALL_GCS 314 315 // split store_check(Register obj) to enhance instruction interleaving 316 void store_check_part_1(Register obj); 317 void store_check_part_2(Register obj); 318 319 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 320 void c2bool(Register x); 321 322 // C++ bool manipulation 323 324 void movbool(Register dst, Address src); 325 void movbool(Address dst, bool boolconst); 326 void movbool(Address dst, Register src); 327 void testbool(Register dst); 328 329 // oop manipulations 330 void load_klass(Register dst, Register src); 331 void store_klass(Register dst, Register src); 332 333 void load_heap_oop(Register dst, Address src); 334 void load_heap_oop_not_null(Register dst, Address src); 335 void store_heap_oop(Address dst, Register src); 336 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg); 337 338 // Used for storing NULL. All other oop constants should be 339 // stored using routines that take a jobject. 340 void store_heap_oop_null(Address dst); 341 342 void load_prototype_header(Register dst, Register src); 343 344#ifdef _LP64 345 void store_klass_gap(Register dst, Register src); 346 347 // This dummy is to prevent a call to store_heap_oop from 348 // converting a zero (like NULL) into a Register by giving 349 // the compiler two choices it can't resolve 350 351 void store_heap_oop(Address dst, void* dummy); 352 353 void encode_heap_oop(Register r); 354 void decode_heap_oop(Register r); 355 void encode_heap_oop_not_null(Register r); 356 void decode_heap_oop_not_null(Register r); 357 void encode_heap_oop_not_null(Register dst, Register src); 358 void decode_heap_oop_not_null(Register dst, Register src); 359 360 void set_narrow_oop(Register dst, jobject obj); 361 void set_narrow_oop(Address dst, jobject obj); 362 void cmp_narrow_oop(Register dst, jobject obj); 363 void cmp_narrow_oop(Address dst, jobject obj); 364 365 void encode_klass_not_null(Register r); 366 void decode_klass_not_null(Register r); 367 void encode_klass_not_null(Register dst, Register src); 368 void decode_klass_not_null(Register dst, Register src); 369 void set_narrow_klass(Register dst, Klass* k); 370 void set_narrow_klass(Address dst, Klass* k); 371 void cmp_narrow_klass(Register dst, Klass* k); 372 void cmp_narrow_klass(Address dst, Klass* k); 373 374 // if heap base register is used - reinit it with the correct value 375 void reinit_heapbase(); 376 377 DEBUG_ONLY(void verify_heapbase(const char* msg);) 378 379#endif // _LP64 380 381 // Int division/remainder for Java 382 // (as idivl, but checks for special case as described in JVM spec.) 383 // returns idivl instruction offset for implicit exception handling 384 int corrected_idivl(Register reg); 385 386 // Long division/remainder for Java 387 // (as idivq, but checks for special case as described in JVM spec.) 388 // returns idivq instruction offset for implicit exception handling 389 int corrected_idivq(Register reg); 390 391 void int3(); 392 393 // Long operation macros for a 32bit cpu 394 // Long negation for Java 395 void lneg(Register hi, Register lo); 396 397 // Long multiplication for Java 398 // (destroys contents of eax, ebx, ecx and edx) 399 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y 400 401 // Long shifts for Java 402 // (semantics as described in JVM spec.) 403 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) 404 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) 405 406 // Long compare for Java 407 // (semantics as described in JVM spec.) 408 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) 409 410 411 // misc 412 413 // Sign extension 414 void sign_extend_short(Register reg); 415 void sign_extend_byte(Register reg); 416 417 // Division by power of 2, rounding towards 0 418 void division_with_shift(Register reg, int shift_value); 419 420 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: 421 // 422 // CF (corresponds to C0) if x < y 423 // PF (corresponds to C2) if unordered 424 // ZF (corresponds to C3) if x = y 425 // 426 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 427 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) 428 void fcmp(Register tmp); 429 // Variant of the above which allows y to be further down the stack 430 // and which only pops x and y if specified. If pop_right is 431 // specified then pop_left must also be specified. 432 void fcmp(Register tmp, int index, bool pop_left, bool pop_right); 433 434 // Floating-point comparison for Java 435 // Compares the top-most stack entries on the FPU stack and stores the result in dst. 436 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 437 // (semantics as described in JVM spec.) 438 void fcmp2int(Register dst, bool unordered_is_less); 439 // Variant of the above which allows y to be further down the stack 440 // and which only pops x and y if specified. If pop_right is 441 // specified then pop_left must also be specified. 442 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); 443 444 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) 445 // tmp is a temporary register, if none is available use noreg 446 void fremr(Register tmp); 447 448 449 // same as fcmp2int, but using SSE2 450 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 451 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 452 453 // Inlined sin/cos generator for Java; must not use CPU instruction 454 // directly on Intel as it does not have high enough precision 455 // outside of the range [-pi/4, pi/4]. Extra argument indicate the 456 // number of FPU stack slots in use; all but the topmost will 457 // require saving if a slow case is necessary. Assumes argument is 458 // on FP TOS; result is on FP TOS. No cpu registers are changed by 459 // this code. 460 void trigfunc(char trig, int num_fpu_regs_in_use = 1); 461 462 // branch to L if FPU flag C2 is set/not set 463 // tmp is a temporary register, if none is available use noreg 464 void jC2 (Register tmp, Label& L); 465 void jnC2(Register tmp, Label& L); 466 467 // Pop ST (ffree & fincstp combined) 468 void fpop(); 469 470 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack 471 void push_fTOS(); 472 473 // pops double TOS element from CPU stack and pushes on FPU stack 474 void pop_fTOS(); 475 476 void empty_FPU_stack(); 477 478 void push_IU_state(); 479 void pop_IU_state(); 480 481 void push_FPU_state(); 482 void pop_FPU_state(); 483 484 void push_CPU_state(); 485 void pop_CPU_state(); 486 487 // Round up to a power of two 488 void round_to(Register reg, int modulus); 489 490 // Callee saved registers handling 491 void push_callee_saved_registers(); 492 void pop_callee_saved_registers(); 493 494 // allocation 495 void eden_allocate( 496 Register obj, // result: pointer to object after successful allocation 497 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 498 int con_size_in_bytes, // object size in bytes if known at compile time 499 Register t1, // temp register 500 Label& slow_case // continuation point if fast allocation fails 501 ); 502 void tlab_allocate( 503 Register obj, // result: pointer to object after successful allocation 504 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 505 int con_size_in_bytes, // object size in bytes if known at compile time 506 Register t1, // temp register 507 Register t2, // temp register 508 Label& slow_case // continuation point if fast allocation fails 509 ); 510 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address 511 void incr_allocated_bytes(Register thread, 512 Register var_size_in_bytes, int con_size_in_bytes, 513 Register t1 = noreg); 514 515 // interface method calling 516 void lookup_interface_method(Register recv_klass, 517 Register intf_klass, 518 RegisterOrConstant itable_index, 519 Register method_result, 520 Register scan_temp, 521 Label& no_such_interface); 522 523 // virtual method calling 524 void lookup_virtual_method(Register recv_klass, 525 RegisterOrConstant vtable_index, 526 Register method_result); 527 528 // Test sub_klass against super_klass, with fast and slow paths. 529 530 // The fast path produces a tri-state answer: yes / no / maybe-slow. 531 // One of the three labels can be NULL, meaning take the fall-through. 532 // If super_check_offset is -1, the value is loaded up from super_klass. 533 // No registers are killed, except temp_reg. 534 void check_klass_subtype_fast_path(Register sub_klass, 535 Register super_klass, 536 Register temp_reg, 537 Label* L_success, 538 Label* L_failure, 539 Label* L_slow_path, 540 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 541 542 // The rest of the type check; must be wired to a corresponding fast path. 543 // It does not repeat the fast path logic, so don't use it standalone. 544 // The temp_reg and temp2_reg can be noreg, if no temps are available. 545 // Updates the sub's secondary super cache as necessary. 546 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 547 void check_klass_subtype_slow_path(Register sub_klass, 548 Register super_klass, 549 Register temp_reg, 550 Register temp2_reg, 551 Label* L_success, 552 Label* L_failure, 553 bool set_cond_codes = false); 554 555 // Simplified, combined version, good for typical uses. 556 // Falls through on failure. 557 void check_klass_subtype(Register sub_klass, 558 Register super_klass, 559 Register temp_reg, 560 Label& L_success); 561 562 // method handles (JSR 292) 563 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 564 565 //---- 566 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 567 568 // Debugging 569 570 // only if +VerifyOops 571 // TODO: Make these macros with file and line like sparc version! 572 void verify_oop(Register reg, const char* s = "broken oop"); 573 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); 574 575 // TODO: verify method and klass metadata (compare against vptr?) 576 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 577 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 578 579#define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 580#define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 581 582 // only if +VerifyFPU 583 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 584 585 // Verify or restore cpu control state after JNI call 586 void restore_cpu_control_state_after_jni(); 587 588 // prints msg, dumps registers and stops execution 589 void stop(const char* msg); 590 591 // prints msg and continues 592 void warn(const char* msg); 593 594 // dumps registers and other state 595 void print_state(); 596 597 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); 598 static void debug64(char* msg, int64_t pc, int64_t regs[]); 599 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip); 600 static void print_state64(int64_t pc, int64_t regs[]); 601 602 void os_breakpoint(); 603 604 void untested() { stop("untested"); } 605 606 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, 1024, "unimplemented: %s", what); stop(b); } 607 608 void should_not_reach_here() { stop("should not reach here"); } 609 610 void print_CPU_state(); 611 612 // Stack overflow checking 613 void bang_stack_with_offset(int offset) { 614 // stack grows down, caller passes positive offset 615 assert(offset > 0, "must bang with negative offset"); 616 movl(Address(rsp, (-offset)), rax); 617 } 618 619 // Writes to stack successive pages until offset reached to check for 620 // stack overflow + shadow pages. Also, clobbers tmp 621 void bang_stack_size(Register size, Register tmp); 622 623 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 624 Register tmp, 625 int offset); 626 627 // Support for serializing memory accesses between threads 628 void serialize_memory(Register thread, Register tmp); 629 630 void verify_tlab(); 631 632 // Biased locking support 633 // lock_reg and obj_reg must be loaded up with the appropriate values. 634 // swap_reg must be rax, and is killed. 635 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will 636 // be killed; if not supplied, push/pop will be used internally to 637 // allocate a temporary (inefficient, avoid if possible). 638 // Optional slow case is for implementations (interpreter and C1) which branch to 639 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. 640 // Returns offset of first potentially-faulting instruction for null 641 // check info (currently consumed only by C1). If 642 // swap_reg_contains_mark is true then returns -1 as it is assumed 643 // the calling code has already passed any potential faults. 644 int biased_locking_enter(Register lock_reg, Register obj_reg, 645 Register swap_reg, Register tmp_reg, 646 bool swap_reg_contains_mark, 647 Label& done, Label* slow_case = NULL, 648 BiasedLockingCounters* counters = NULL); 649 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); 650 651 652 Condition negate_condition(Condition cond); 653 654 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit 655 // operands. In general the names are modified to avoid hiding the instruction in Assembler 656 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers 657 // here in MacroAssembler. The major exception to this rule is call 658 659 // Arithmetics 660 661 662 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } 663 void addptr(Address dst, Register src); 664 665 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } 666 void addptr(Register dst, int32_t src); 667 void addptr(Register dst, Register src); 668 void addptr(Register dst, RegisterOrConstant src) { 669 if (src.is_constant()) addptr(dst, (int) src.as_constant()); 670 else addptr(dst, src.as_register()); 671 } 672 673 void andptr(Register dst, int32_t src); 674 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } 675 676 void cmp8(AddressLiteral src1, int imm); 677 678 // renamed to drag out the casting of address to int32_t/intptr_t 679 void cmp32(Register src1, int32_t imm); 680 681 void cmp32(AddressLiteral src1, int32_t imm); 682 // compare reg - mem, or reg - &mem 683 void cmp32(Register src1, AddressLiteral src2); 684 685 void cmp32(Register src1, Address src2); 686 687#ifndef _LP64 688 void cmpklass(Address dst, Metadata* obj); 689 void cmpklass(Register dst, Metadata* obj); 690 void cmpoop(Address dst, jobject obj); 691 void cmpoop(Register dst, jobject obj); 692#endif // _LP64 693 694 // NOTE src2 must be the lval. This is NOT an mem-mem compare 695 void cmpptr(Address src1, AddressLiteral src2); 696 697 void cmpptr(Register src1, AddressLiteral src2); 698 699 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 700 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 701 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 702 703 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 704 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 705 706 // cmp64 to avoild hiding cmpq 707 void cmp64(Register src1, AddressLiteral src); 708 709 void cmpxchgptr(Register reg, Address adr); 710 711 void locked_cmpxchgptr(Register reg, AddressLiteral adr); 712 713 714 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } 715 716 717 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } 718 719 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } 720 721 void shlptr(Register dst, int32_t shift); 722 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } 723 724 void shrptr(Register dst, int32_t shift); 725 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } 726 727 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } 728 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } 729 730 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 731 732 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 733 void subptr(Register dst, int32_t src); 734 // Force generation of a 4 byte immediate value even if it fits into 8bit 735 void subptr_imm32(Register dst, int32_t src); 736 void subptr(Register dst, Register src); 737 void subptr(Register dst, RegisterOrConstant src) { 738 if (src.is_constant()) subptr(dst, (int) src.as_constant()); 739 else subptr(dst, src.as_register()); 740 } 741 742 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 743 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 744 745 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 746 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 747 748 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } 749 750 751 752 // Helper functions for statistics gathering. 753 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. 754 void cond_inc32(Condition cond, AddressLiteral counter_addr); 755 // Unconditional atomic increment. 756 void atomic_incl(AddressLiteral counter_addr); 757 758 void lea(Register dst, AddressLiteral adr); 759 void lea(Address dst, AddressLiteral adr); 760 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } 761 762 void leal32(Register dst, Address src) { leal(dst, src); } 763 764 // Import other testl() methods from the parent class or else 765 // they will be hidden by the following overriding declaration. 766 using Assembler::testl; 767 void testl(Register dst, AddressLiteral src); 768 769 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 770 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 771 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 772 773 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } 774 void testptr(Register src1, Register src2); 775 776 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 777 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 778 779 // Calls 780 781 void call(Label& L, relocInfo::relocType rtype); 782 void call(Register entry); 783 784 // NOTE: this call tranfers to the effective address of entry NOT 785 // the address contained by entry. This is because this is more natural 786 // for jumps/calls. 787 void call(AddressLiteral entry); 788 789 // Emit the CompiledIC call idiom 790 void ic_call(address entry); 791 792 // Jumps 793 794 // NOTE: these jumps tranfer to the effective address of dst NOT 795 // the address contained by dst. This is because this is more natural 796 // for jumps/calls. 797 void jump(AddressLiteral dst); 798 void jump_cc(Condition cc, AddressLiteral dst); 799 800 // 32bit can do a case table jump in one instruction but we no longer allow the base 801 // to be installed in the Address class. This jump will tranfers to the address 802 // contained in the location described by entry (not the address of entry) 803 void jump(ArrayAddress entry); 804 805 // Floating 806 807 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } 808 void andpd(XMMRegister dst, AddressLiteral src); 809 810 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); } 811 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); } 812 void andps(XMMRegister dst, AddressLiteral src); 813 814 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); } 815 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } 816 void comiss(XMMRegister dst, AddressLiteral src); 817 818 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); } 819 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } 820 void comisd(XMMRegister dst, AddressLiteral src); 821 822 void fadd_s(Address src) { Assembler::fadd_s(src); } 823 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); } 824 825 void fldcw(Address src) { Assembler::fldcw(src); } 826 void fldcw(AddressLiteral src); 827 828 void fld_s(int index) { Assembler::fld_s(index); } 829 void fld_s(Address src) { Assembler::fld_s(src); } 830 void fld_s(AddressLiteral src); 831 832 void fld_d(Address src) { Assembler::fld_d(src); } 833 void fld_d(AddressLiteral src); 834 835 void fld_x(Address src) { Assembler::fld_x(src); } 836 void fld_x(AddressLiteral src); 837 838 void fmul_s(Address src) { Assembler::fmul_s(src); } 839 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); } 840 841 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } 842 void ldmxcsr(AddressLiteral src); 843 844 // compute pow(x,y) and exp(x) with x86 instructions. Don't cover 845 // all corner cases and may result in NaN and require fallback to a 846 // runtime call. 847 void fast_pow(); 848 void fast_exp(); 849 void increase_precision(); 850 void restore_precision(); 851 852 // computes exp(x). Fallback to runtime call included. 853 void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); } 854 // computes pow(x,y). Fallback to runtime call included. 855 void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); } 856 857private: 858 859 // call runtime as a fallback for trig functions and pow/exp. 860 void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use); 861 862 // computes 2^(Ylog2X); Ylog2X in ST(0) 863 void pow_exp_core_encoding(); 864 865 // computes pow(x,y) or exp(x). Fallback to runtime call included. 866 void pow_or_exp(bool is_exp, int num_fpu_regs_in_use); 867 868 // these are private because users should be doing movflt/movdbl 869 870 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } 871 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } 872 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } 873 void movss(XMMRegister dst, AddressLiteral src); 874 875 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } 876 void movlpd(XMMRegister dst, AddressLiteral src); 877 878public: 879 880 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); } 881 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); } 882 void addsd(XMMRegister dst, AddressLiteral src); 883 884 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); } 885 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); } 886 void addss(XMMRegister dst, AddressLiteral src); 887 888 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); } 889 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); } 890 void divsd(XMMRegister dst, AddressLiteral src); 891 892 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); } 893 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); } 894 void divss(XMMRegister dst, AddressLiteral src); 895 896 // Move Unaligned Double Quadword 897 void movdqu(Address dst, XMMRegister src) { Assembler::movdqu(dst, src); } 898 void movdqu(XMMRegister dst, Address src) { Assembler::movdqu(dst, src); } 899 void movdqu(XMMRegister dst, XMMRegister src) { Assembler::movdqu(dst, src); } 900 void movdqu(XMMRegister dst, AddressLiteral src); 901 902 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } 903 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } 904 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } 905 void movsd(XMMRegister dst, AddressLiteral src); 906 907 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); } 908 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); } 909 void mulsd(XMMRegister dst, AddressLiteral src); 910 911 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); } 912 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); } 913 void mulss(XMMRegister dst, AddressLiteral src); 914 915 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); } 916 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } 917 void sqrtsd(XMMRegister dst, AddressLiteral src); 918 919 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } 920 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } 921 void sqrtss(XMMRegister dst, AddressLiteral src); 922 923 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); } 924 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); } 925 void subsd(XMMRegister dst, AddressLiteral src); 926 927 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); } 928 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); } 929 void subss(XMMRegister dst, AddressLiteral src); 930 931 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } 932 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } 933 void ucomiss(XMMRegister dst, AddressLiteral src); 934 935 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } 936 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } 937 void ucomisd(XMMRegister dst, AddressLiteral src); 938 939 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values 940 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } 941 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } 942 void xorpd(XMMRegister dst, AddressLiteral src); 943 944 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values 945 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } 946 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } 947 void xorps(XMMRegister dst, AddressLiteral src); 948 949 // Shuffle Bytes 950 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); } 951 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); } 952 void pshufb(XMMRegister dst, AddressLiteral src); 953 // AVX 3-operands instructions 954 955 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); } 956 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); } 957 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 958 959 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); } 960 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); } 961 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 962 963 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); } 964 void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); } 965 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); 966 967 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); } 968 void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); } 969 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); 970 971 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); } 972 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); } 973 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 974 975 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); } 976 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); } 977 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 978 979 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); } 980 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); } 981 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 982 983 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); } 984 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); } 985 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 986 987 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); } 988 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); } 989 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 990 991 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); } 992 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); } 993 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 994 995 // AVX Vector instructions 996 997 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); } 998 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); } 999 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); 1000 1001 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); } 1002 void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); } 1003 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256); 1004 1005 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { 1006 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2 1007 Assembler::vpxor(dst, nds, src, vector256); 1008 else 1009 Assembler::vxorpd(dst, nds, src, vector256); 1010 } 1011 void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { 1012 if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2 1013 Assembler::vpxor(dst, nds, src, vector256); 1014 else 1015 Assembler::vxorpd(dst, nds, src, vector256); 1016 } 1017 1018 // Simple version for AVX2 256bit vectors 1019 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); } 1020 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); } 1021 1022 // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector. 1023 void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) { 1024 if (UseAVX > 1) // vinserti128h is available only in AVX2 1025 Assembler::vinserti128h(dst, nds, src); 1026 else 1027 Assembler::vinsertf128h(dst, nds, src); 1028 } 1029 1030 // Data 1031 1032 void cmov32( Condition cc, Register dst, Address src); 1033 void cmov32( Condition cc, Register dst, Register src); 1034 1035 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); } 1036 1037 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } 1038 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } 1039 1040 void movoop(Register dst, jobject obj); 1041 void movoop(Address dst, jobject obj); 1042 1043 void mov_metadata(Register dst, Metadata* obj); 1044 void mov_metadata(Address dst, Metadata* obj); 1045 1046 void movptr(ArrayAddress dst, Register src); 1047 // can this do an lea? 1048 void movptr(Register dst, ArrayAddress src); 1049 1050 void movptr(Register dst, Address src); 1051 1052 void movptr(Register dst, AddressLiteral src); 1053 1054 void movptr(Register dst, intptr_t src); 1055 void movptr(Register dst, Register src); 1056 void movptr(Address dst, intptr_t src); 1057 1058 void movptr(Address dst, Register src); 1059 1060 void movptr(Register dst, RegisterOrConstant src) { 1061 if (src.is_constant()) movptr(dst, src.as_constant()); 1062 else movptr(dst, src.as_register()); 1063 } 1064 1065#ifdef _LP64 1066 // Generally the next two are only used for moving NULL 1067 // Although there are situations in initializing the mark word where 1068 // they could be used. They are dangerous. 1069 1070 // They only exist on LP64 so that int32_t and intptr_t are not the same 1071 // and we have ambiguous declarations. 1072 1073 void movptr(Address dst, int32_t imm32); 1074 void movptr(Register dst, int32_t imm32); 1075#endif // _LP64 1076 1077 // to avoid hiding movl 1078 void mov32(AddressLiteral dst, Register src); 1079 void mov32(Register dst, AddressLiteral src); 1080 1081 // to avoid hiding movb 1082 void movbyte(ArrayAddress dst, int src); 1083 1084 // Import other mov() methods from the parent class or else 1085 // they will be hidden by the following overriding declaration. 1086 using Assembler::movdl; 1087 using Assembler::movq; 1088 void movdl(XMMRegister dst, AddressLiteral src); 1089 void movq(XMMRegister dst, AddressLiteral src); 1090 1091 // Can push value or effective address 1092 void pushptr(AddressLiteral src); 1093 1094 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } 1095 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } 1096 1097 void pushoop(jobject obj); 1098 void pushklass(Metadata* obj); 1099 1100 // sign extend as need a l to ptr sized element 1101 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } 1102 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } 1103 1104 // C2 compiled method's prolog code. 1105 void verified_entry(int framesize, bool stack_bang, bool fp_mode_24b); 1106 1107 // clear memory of size 'cnt' qwords, starting at 'base'. 1108 void clear_mem(Register base, Register cnt, Register rtmp); 1109 1110 // IndexOf strings. 1111 // Small strings are loaded through stack if they cross page boundary. 1112 void string_indexof(Register str1, Register str2, 1113 Register cnt1, Register cnt2, 1114 int int_cnt2, Register result, 1115 XMMRegister vec, Register tmp); 1116 1117 // IndexOf for constant substrings with size >= 8 elements 1118 // which don't need to be loaded through stack. 1119 void string_indexofC8(Register str1, Register str2, 1120 Register cnt1, Register cnt2, 1121 int int_cnt2, Register result, 1122 XMMRegister vec, Register tmp); 1123 1124 // Smallest code: we don't need to load through stack, 1125 // check string tail. 1126 1127 // Compare strings. 1128 void string_compare(Register str1, Register str2, 1129 Register cnt1, Register cnt2, Register result, 1130 XMMRegister vec1); 1131 1132 // Compare char[] arrays. 1133 void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2, 1134 Register limit, Register result, Register chr, 1135 XMMRegister vec1, XMMRegister vec2); 1136 1137 // Fill primitive arrays 1138 void generate_fill(BasicType t, bool aligned, 1139 Register to, Register value, Register count, 1140 Register rtmp, XMMRegister xtmp); 1141 1142 void encode_iso_array(Register src, Register dst, Register len, 1143 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3, 1144 XMMRegister tmp4, Register tmp5, Register result); 1145 1146#undef VIRTUAL 1147 1148}; 1149 1150/** 1151 * class SkipIfEqual: 1152 * 1153 * Instantiating this class will result in assembly code being output that will 1154 * jump around any code emitted between the creation of the instance and it's 1155 * automatic destruction at the end of a scope block, depending on the value of 1156 * the flag passed to the constructor, which will be checked at run-time. 1157 */ 1158class SkipIfEqual { 1159 private: 1160 MacroAssembler* _masm; 1161 Label _label; 1162 1163 public: 1164 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 1165 ~SkipIfEqual(); 1166}; 1167 1168#endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP 1169