macroAssembler_x86.hpp revision 13184:7903df1b0c4f
1/* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25#ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP 26#define CPU_X86_VM_MACROASSEMBLER_X86_HPP 27 28#include "asm/assembler.hpp" 29#include "utilities/macros.hpp" 30#include "runtime/rtmLocking.hpp" 31 32// MacroAssembler extends Assembler by frequently used macros. 33// 34// Instructions for which a 'better' code sequence exists depending 35// on arguments should also go in here. 36 37class MacroAssembler: public Assembler { 38 friend class LIR_Assembler; 39 friend class Runtime1; // as_Address() 40 41 protected: 42 43 Address as_Address(AddressLiteral adr); 44 Address as_Address(ArrayAddress adr); 45 46 // Support for VM calls 47 // 48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 49 // may customize this version by overriding it for its purposes (e.g., to save/restore 50 // additional registers when doing a VM call). 51 52 virtual void call_VM_leaf_base( 53 address entry_point, // the entry point 54 int number_of_arguments // the number of arguments to pop after the call 55 ); 56 57 // This is the base routine called by the different versions of call_VM. The interpreter 58 // may customize this version by overriding it for its purposes (e.g., to save/restore 59 // additional registers when doing a VM call). 60 // 61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base 62 // returns the register which contains the thread upon return. If a thread register has been 63 // specified, the return value will correspond to that register. If no last_java_sp is specified 64 // (noreg) than rsp will be used instead. 65 virtual void call_VM_base( // returns the register containing the thread upon return 66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 67 Register java_thread, // the thread if computed before ; use noreg otherwise 68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 69 address entry_point, // the entry point 70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 71 bool check_exceptions // whether to check for pending exceptions after return 72 ); 73 74 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 75 76 // helpers for FPU flag access 77 // tmp is a temporary register, if none is available use noreg 78 void save_rax (Register tmp); 79 void restore_rax(Register tmp); 80 81 public: 82 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 83 84 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 85 // The implementation is only non-empty for the InterpreterMacroAssembler, 86 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 87 virtual void check_and_handle_popframe(Register java_thread); 88 virtual void check_and_handle_earlyret(Register java_thread); 89 90 // Support for NULL-checks 91 // 92 // Generates code that causes a NULL OS exception if the content of reg is NULL. 93 // If the accessed location is M[reg + offset] and the offset is known, provide the 94 // offset. No explicit code generation is needed if the offset is within a certain 95 // range (0 <= offset <= page_size). 96 97 void null_check(Register reg, int offset = -1); 98 static bool needs_explicit_null_check(intptr_t offset); 99 100 // Required platform-specific helpers for Label::patch_instructions. 101 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 102 void pd_patch_instruction(address branch, address target) { 103 unsigned char op = branch[0]; 104 assert(op == 0xE8 /* call */ || 105 op == 0xE9 /* jmp */ || 106 op == 0xEB /* short jmp */ || 107 (op & 0xF0) == 0x70 /* short jcc */ || 108 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ || 109 op == 0xC7 && branch[1] == 0xF8 /* xbegin */, 110 "Invalid opcode at patch point"); 111 112 if (op == 0xEB || (op & 0xF0) == 0x70) { 113 // short offset operators (jmp and jcc) 114 char* disp = (char*) &branch[1]; 115 int imm8 = target - (address) &disp[1]; 116 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset"); 117 *disp = imm8; 118 } else { 119 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1]; 120 int imm32 = target - (address) &disp[1]; 121 *disp = imm32; 122 } 123 } 124 125 // The following 4 methods return the offset of the appropriate move instruction 126 127 // Support for fast byte/short loading with zero extension (depending on particular CPU) 128 int load_unsigned_byte(Register dst, Address src); 129 int load_unsigned_short(Register dst, Address src); 130 131 // Support for fast byte/short loading with sign extension (depending on particular CPU) 132 int load_signed_byte(Register dst, Address src); 133 int load_signed_short(Register dst, Address src); 134 135 // Support for sign-extension (hi:lo = extend_sign(lo)) 136 void extend_sign(Register hi, Register lo); 137 138 // Load and store values by size and signed-ness 139 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg); 140 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg); 141 142 // Support for inc/dec with optimal instruction selection depending on value 143 144 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } 145 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } 146 147 void decrementl(Address dst, int value = 1); 148 void decrementl(Register reg, int value = 1); 149 150 void decrementq(Register reg, int value = 1); 151 void decrementq(Address dst, int value = 1); 152 153 void incrementl(Address dst, int value = 1); 154 void incrementl(Register reg, int value = 1); 155 156 void incrementq(Register reg, int value = 1); 157 void incrementq(Address dst, int value = 1); 158 159 // special instructions for EVEX 160 void setvectmask(Register dst, Register src); 161 void restorevectmask(); 162 163 // Support optimal SSE move instructions. 164 void movflt(XMMRegister dst, XMMRegister src) { 165 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } 166 else { movss (dst, src); return; } 167 } 168 void movflt(XMMRegister dst, Address src) { movss(dst, src); } 169 void movflt(XMMRegister dst, AddressLiteral src); 170 void movflt(Address dst, XMMRegister src) { movss(dst, src); } 171 172 void movdbl(XMMRegister dst, XMMRegister src) { 173 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } 174 else { movsd (dst, src); return; } 175 } 176 177 void movdbl(XMMRegister dst, AddressLiteral src); 178 179 void movdbl(XMMRegister dst, Address src) { 180 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } 181 else { movlpd(dst, src); return; } 182 } 183 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } 184 185 void incrementl(AddressLiteral dst); 186 void incrementl(ArrayAddress dst); 187 188 void incrementq(AddressLiteral dst); 189 190 // Alignment 191 void align(int modulus); 192 void align(int modulus, int target); 193 194 // A 5 byte nop that is safe for patching (see patch_verified_entry) 195 void fat_nop(); 196 197 // Stack frame creation/removal 198 void enter(); 199 void leave(); 200 201 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 202 // The pointer will be loaded into the thread register. 203 void get_thread(Register thread); 204 205 206 // Support for VM calls 207 // 208 // It is imperative that all calls into the VM are handled via the call_VM macros. 209 // They make sure that the stack linkage is setup correctly. call_VM's correspond 210 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 211 212 213 void call_VM(Register oop_result, 214 address entry_point, 215 bool check_exceptions = true); 216 void call_VM(Register oop_result, 217 address entry_point, 218 Register arg_1, 219 bool check_exceptions = true); 220 void call_VM(Register oop_result, 221 address entry_point, 222 Register arg_1, Register arg_2, 223 bool check_exceptions = true); 224 void call_VM(Register oop_result, 225 address entry_point, 226 Register arg_1, Register arg_2, Register arg_3, 227 bool check_exceptions = true); 228 229 // Overloadings with last_Java_sp 230 void call_VM(Register oop_result, 231 Register last_java_sp, 232 address entry_point, 233 int number_of_arguments = 0, 234 bool check_exceptions = true); 235 void call_VM(Register oop_result, 236 Register last_java_sp, 237 address entry_point, 238 Register arg_1, bool 239 check_exceptions = true); 240 void call_VM(Register oop_result, 241 Register last_java_sp, 242 address entry_point, 243 Register arg_1, Register arg_2, 244 bool check_exceptions = true); 245 void call_VM(Register oop_result, 246 Register last_java_sp, 247 address entry_point, 248 Register arg_1, Register arg_2, Register arg_3, 249 bool check_exceptions = true); 250 251 void get_vm_result (Register oop_result, Register thread); 252 void get_vm_result_2(Register metadata_result, Register thread); 253 254 // These always tightly bind to MacroAssembler::call_VM_base 255 // bypassing the virtual implementation 256 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true); 257 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true); 258 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 259 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 260 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true); 261 262 void call_VM_leaf0(address entry_point); 263 void call_VM_leaf(address entry_point, 264 int number_of_arguments = 0); 265 void call_VM_leaf(address entry_point, 266 Register arg_1); 267 void call_VM_leaf(address entry_point, 268 Register arg_1, Register arg_2); 269 void call_VM_leaf(address entry_point, 270 Register arg_1, Register arg_2, Register arg_3); 271 272 // These always tightly bind to MacroAssembler::call_VM_leaf_base 273 // bypassing the virtual implementation 274 void super_call_VM_leaf(address entry_point); 275 void super_call_VM_leaf(address entry_point, Register arg_1); 276 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 277 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 278 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4); 279 280 // last Java Frame (fills frame anchor) 281 void set_last_Java_frame(Register thread, 282 Register last_java_sp, 283 Register last_java_fp, 284 address last_java_pc); 285 286 // thread in the default location (r15_thread on 64bit) 287 void set_last_Java_frame(Register last_java_sp, 288 Register last_java_fp, 289 address last_java_pc); 290 291 void reset_last_Java_frame(Register thread, bool clear_fp); 292 293 // thread in the default location (r15_thread on 64bit) 294 void reset_last_Java_frame(bool clear_fp); 295 296 // Stores 297 void store_check(Register obj); // store check for obj - register is destroyed afterwards 298 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 299 300 void resolve_jobject(Register value, Register thread, Register tmp); 301 void clear_jweak_tag(Register possibly_jweak); 302 303#if INCLUDE_ALL_GCS 304 305 void g1_write_barrier_pre(Register obj, 306 Register pre_val, 307 Register thread, 308 Register tmp, 309 bool tosca_live, 310 bool expand_call); 311 312 void g1_write_barrier_post(Register store_addr, 313 Register new_val, 314 Register thread, 315 Register tmp, 316 Register tmp2); 317 318#endif // INCLUDE_ALL_GCS 319 320 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 321 void c2bool(Register x); 322 323 // C++ bool manipulation 324 325 void movbool(Register dst, Address src); 326 void movbool(Address dst, bool boolconst); 327 void movbool(Address dst, Register src); 328 void testbool(Register dst); 329 330 void load_mirror(Register mirror, Register method); 331 332 // oop manipulations 333 void load_klass(Register dst, Register src); 334 void store_klass(Register dst, Register src); 335 336 void load_heap_oop(Register dst, Address src); 337 void load_heap_oop_not_null(Register dst, Address src); 338 void store_heap_oop(Address dst, Register src); 339 void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg); 340 341 // Used for storing NULL. All other oop constants should be 342 // stored using routines that take a jobject. 343 void store_heap_oop_null(Address dst); 344 345 void load_prototype_header(Register dst, Register src); 346 347#ifdef _LP64 348 void store_klass_gap(Register dst, Register src); 349 350 // This dummy is to prevent a call to store_heap_oop from 351 // converting a zero (like NULL) into a Register by giving 352 // the compiler two choices it can't resolve 353 354 void store_heap_oop(Address dst, void* dummy); 355 356 void encode_heap_oop(Register r); 357 void decode_heap_oop(Register r); 358 void encode_heap_oop_not_null(Register r); 359 void decode_heap_oop_not_null(Register r); 360 void encode_heap_oop_not_null(Register dst, Register src); 361 void decode_heap_oop_not_null(Register dst, Register src); 362 363 void set_narrow_oop(Register dst, jobject obj); 364 void set_narrow_oop(Address dst, jobject obj); 365 void cmp_narrow_oop(Register dst, jobject obj); 366 void cmp_narrow_oop(Address dst, jobject obj); 367 368 void encode_klass_not_null(Register r); 369 void decode_klass_not_null(Register r); 370 void encode_klass_not_null(Register dst, Register src); 371 void decode_klass_not_null(Register dst, Register src); 372 void set_narrow_klass(Register dst, Klass* k); 373 void set_narrow_klass(Address dst, Klass* k); 374 void cmp_narrow_klass(Register dst, Klass* k); 375 void cmp_narrow_klass(Address dst, Klass* k); 376 377 // Returns the byte size of the instructions generated by decode_klass_not_null() 378 // when compressed klass pointers are being used. 379 static int instr_size_for_decode_klass_not_null(); 380 381 // if heap base register is used - reinit it with the correct value 382 void reinit_heapbase(); 383 384 DEBUG_ONLY(void verify_heapbase(const char* msg);) 385 386#endif // _LP64 387 388 // Int division/remainder for Java 389 // (as idivl, but checks for special case as described in JVM spec.) 390 // returns idivl instruction offset for implicit exception handling 391 int corrected_idivl(Register reg); 392 393 // Long division/remainder for Java 394 // (as idivq, but checks for special case as described in JVM spec.) 395 // returns idivq instruction offset for implicit exception handling 396 int corrected_idivq(Register reg); 397 398 void int3(); 399 400 // Long operation macros for a 32bit cpu 401 // Long negation for Java 402 void lneg(Register hi, Register lo); 403 404 // Long multiplication for Java 405 // (destroys contents of eax, ebx, ecx and edx) 406 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y 407 408 // Long shifts for Java 409 // (semantics as described in JVM spec.) 410 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) 411 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) 412 413 // Long compare for Java 414 // (semantics as described in JVM spec.) 415 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) 416 417 418 // misc 419 420 // Sign extension 421 void sign_extend_short(Register reg); 422 void sign_extend_byte(Register reg); 423 424 // Division by power of 2, rounding towards 0 425 void division_with_shift(Register reg, int shift_value); 426 427 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: 428 // 429 // CF (corresponds to C0) if x < y 430 // PF (corresponds to C2) if unordered 431 // ZF (corresponds to C3) if x = y 432 // 433 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 434 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) 435 void fcmp(Register tmp); 436 // Variant of the above which allows y to be further down the stack 437 // and which only pops x and y if specified. If pop_right is 438 // specified then pop_left must also be specified. 439 void fcmp(Register tmp, int index, bool pop_left, bool pop_right); 440 441 // Floating-point comparison for Java 442 // Compares the top-most stack entries on the FPU stack and stores the result in dst. 443 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 444 // (semantics as described in JVM spec.) 445 void fcmp2int(Register dst, bool unordered_is_less); 446 // Variant of the above which allows y to be further down the stack 447 // and which only pops x and y if specified. If pop_right is 448 // specified then pop_left must also be specified. 449 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); 450 451 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) 452 // tmp is a temporary register, if none is available use noreg 453 void fremr(Register tmp); 454 455 // dst = c = a * b + c 456 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c); 457 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c); 458 459 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len); 460 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len); 461 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len); 462 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len); 463 464 465 // same as fcmp2int, but using SSE2 466 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 467 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 468 469 // branch to L if FPU flag C2 is set/not set 470 // tmp is a temporary register, if none is available use noreg 471 void jC2 (Register tmp, Label& L); 472 void jnC2(Register tmp, Label& L); 473 474 // Pop ST (ffree & fincstp combined) 475 void fpop(); 476 477 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into 478 // register xmm0. Otherwise, the value is loaded onto the FPU stack. 479 void load_float(Address src); 480 481 // Store float value to 'address'. If UseSSE >= 1, the value is stored 482 // from register xmm0. Otherwise, the value is stored from the FPU stack. 483 void store_float(Address dst); 484 485 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into 486 // register xmm0. Otherwise, the value is loaded onto the FPU stack. 487 void load_double(Address src); 488 489 // Store double value to 'address'. If UseSSE >= 2, the value is stored 490 // from register xmm0. Otherwise, the value is stored from the FPU stack. 491 void store_double(Address dst); 492 493 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack 494 void push_fTOS(); 495 496 // pops double TOS element from CPU stack and pushes on FPU stack 497 void pop_fTOS(); 498 499 void empty_FPU_stack(); 500 501 void push_IU_state(); 502 void pop_IU_state(); 503 504 void push_FPU_state(); 505 void pop_FPU_state(); 506 507 void push_CPU_state(); 508 void pop_CPU_state(); 509 510 // Round up to a power of two 511 void round_to(Register reg, int modulus); 512 513 // Callee saved registers handling 514 void push_callee_saved_registers(); 515 void pop_callee_saved_registers(); 516 517 // allocation 518 void eden_allocate( 519 Register obj, // result: pointer to object after successful allocation 520 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 521 int con_size_in_bytes, // object size in bytes if known at compile time 522 Register t1, // temp register 523 Label& slow_case // continuation point if fast allocation fails 524 ); 525 void tlab_allocate( 526 Register obj, // result: pointer to object after successful allocation 527 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 528 int con_size_in_bytes, // object size in bytes if known at compile time 529 Register t1, // temp register 530 Register t2, // temp register 531 Label& slow_case // continuation point if fast allocation fails 532 ); 533 Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address 534 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp); 535 536 void incr_allocated_bytes(Register thread, 537 Register var_size_in_bytes, int con_size_in_bytes, 538 Register t1 = noreg); 539 540 // interface method calling 541 void lookup_interface_method(Register recv_klass, 542 Register intf_klass, 543 RegisterOrConstant itable_index, 544 Register method_result, 545 Register scan_temp, 546 Label& no_such_interface); 547 548 // virtual method calling 549 void lookup_virtual_method(Register recv_klass, 550 RegisterOrConstant vtable_index, 551 Register method_result); 552 553 // Test sub_klass against super_klass, with fast and slow paths. 554 555 // The fast path produces a tri-state answer: yes / no / maybe-slow. 556 // One of the three labels can be NULL, meaning take the fall-through. 557 // If super_check_offset is -1, the value is loaded up from super_klass. 558 // No registers are killed, except temp_reg. 559 void check_klass_subtype_fast_path(Register sub_klass, 560 Register super_klass, 561 Register temp_reg, 562 Label* L_success, 563 Label* L_failure, 564 Label* L_slow_path, 565 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 566 567 // The rest of the type check; must be wired to a corresponding fast path. 568 // It does not repeat the fast path logic, so don't use it standalone. 569 // The temp_reg and temp2_reg can be noreg, if no temps are available. 570 // Updates the sub's secondary super cache as necessary. 571 // If set_cond_codes, condition codes will be Z on success, NZ on failure. 572 void check_klass_subtype_slow_path(Register sub_klass, 573 Register super_klass, 574 Register temp_reg, 575 Register temp2_reg, 576 Label* L_success, 577 Label* L_failure, 578 bool set_cond_codes = false); 579 580 // Simplified, combined version, good for typical uses. 581 // Falls through on failure. 582 void check_klass_subtype(Register sub_klass, 583 Register super_klass, 584 Register temp_reg, 585 Label& L_success); 586 587 // method handles (JSR 292) 588 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0); 589 590 //---- 591 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 592 593 // Debugging 594 595 // only if +VerifyOops 596 // TODO: Make these macros with file and line like sparc version! 597 void verify_oop(Register reg, const char* s = "broken oop"); 598 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); 599 600 // TODO: verify method and klass metadata (compare against vptr?) 601 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 602 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){} 603 604#define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 605#define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 606 607 // only if +VerifyFPU 608 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 609 610 // Verify or restore cpu control state after JNI call 611 void restore_cpu_control_state_after_jni(); 612 613 // prints msg, dumps registers and stops execution 614 void stop(const char* msg); 615 616 // prints msg and continues 617 void warn(const char* msg); 618 619 // dumps registers and other state 620 void print_state(); 621 622 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); 623 static void debug64(char* msg, int64_t pc, int64_t regs[]); 624 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip); 625 static void print_state64(int64_t pc, int64_t regs[]); 626 627 void os_breakpoint(); 628 629 void untested() { stop("untested"); } 630 631 void unimplemented(const char* what = ""); 632 633 void should_not_reach_here() { stop("should not reach here"); } 634 635 void print_CPU_state(); 636 637 // Stack overflow checking 638 void bang_stack_with_offset(int offset) { 639 // stack grows down, caller passes positive offset 640 assert(offset > 0, "must bang with negative offset"); 641 movl(Address(rsp, (-offset)), rax); 642 } 643 644 // Writes to stack successive pages until offset reached to check for 645 // stack overflow + shadow pages. Also, clobbers tmp 646 void bang_stack_size(Register size, Register tmp); 647 648 // Check for reserved stack access in method being exited (for JIT) 649 void reserved_stack_check(); 650 651 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 652 Register tmp, 653 int offset); 654 655 // Support for serializing memory accesses between threads 656 void serialize_memory(Register thread, Register tmp); 657 658 void verify_tlab(); 659 660 // Biased locking support 661 // lock_reg and obj_reg must be loaded up with the appropriate values. 662 // swap_reg must be rax, and is killed. 663 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will 664 // be killed; if not supplied, push/pop will be used internally to 665 // allocate a temporary (inefficient, avoid if possible). 666 // Optional slow case is for implementations (interpreter and C1) which branch to 667 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. 668 // Returns offset of first potentially-faulting instruction for null 669 // check info (currently consumed only by C1). If 670 // swap_reg_contains_mark is true then returns -1 as it is assumed 671 // the calling code has already passed any potential faults. 672 int biased_locking_enter(Register lock_reg, Register obj_reg, 673 Register swap_reg, Register tmp_reg, 674 bool swap_reg_contains_mark, 675 Label& done, Label* slow_case = NULL, 676 BiasedLockingCounters* counters = NULL); 677 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); 678#ifdef COMPILER2 679 // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file. 680 // See full desription in macroAssembler_x86.cpp. 681 void fast_lock(Register obj, Register box, Register tmp, 682 Register scr, Register cx1, Register cx2, 683 BiasedLockingCounters* counters, 684 RTMLockingCounters* rtm_counters, 685 RTMLockingCounters* stack_rtm_counters, 686 Metadata* method_data, 687 bool use_rtm, bool profile_rtm); 688 void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm); 689#if INCLUDE_RTM_OPT 690 void rtm_counters_update(Register abort_status, Register rtm_counters); 691 void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel); 692 void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg, 693 RTMLockingCounters* rtm_counters, 694 Metadata* method_data); 695 void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg, 696 RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm); 697 void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel); 698 void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel); 699 void rtm_stack_locking(Register obj, Register tmp, Register scr, 700 Register retry_on_abort_count, 701 RTMLockingCounters* stack_rtm_counters, 702 Metadata* method_data, bool profile_rtm, 703 Label& DONE_LABEL, Label& IsInflated); 704 void rtm_inflated_locking(Register obj, Register box, Register tmp, 705 Register scr, Register retry_on_busy_count, 706 Register retry_on_abort_count, 707 RTMLockingCounters* rtm_counters, 708 Metadata* method_data, bool profile_rtm, 709 Label& DONE_LABEL); 710#endif 711#endif 712 713 Condition negate_condition(Condition cond); 714 715 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit 716 // operands. In general the names are modified to avoid hiding the instruction in Assembler 717 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers 718 // here in MacroAssembler. The major exception to this rule is call 719 720 // Arithmetics 721 722 723 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } 724 void addptr(Address dst, Register src); 725 726 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } 727 void addptr(Register dst, int32_t src); 728 void addptr(Register dst, Register src); 729 void addptr(Register dst, RegisterOrConstant src) { 730 if (src.is_constant()) addptr(dst, (int) src.as_constant()); 731 else addptr(dst, src.as_register()); 732 } 733 734 void andptr(Register dst, int32_t src); 735 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } 736 737 void cmp8(AddressLiteral src1, int imm); 738 739 // renamed to drag out the casting of address to int32_t/intptr_t 740 void cmp32(Register src1, int32_t imm); 741 742 void cmp32(AddressLiteral src1, int32_t imm); 743 // compare reg - mem, or reg - &mem 744 void cmp32(Register src1, AddressLiteral src2); 745 746 void cmp32(Register src1, Address src2); 747 748#ifndef _LP64 749 void cmpklass(Address dst, Metadata* obj); 750 void cmpklass(Register dst, Metadata* obj); 751 void cmpoop(Address dst, jobject obj); 752 void cmpoop(Register dst, jobject obj); 753#endif // _LP64 754 755 // NOTE src2 must be the lval. This is NOT an mem-mem compare 756 void cmpptr(Address src1, AddressLiteral src2); 757 758 void cmpptr(Register src1, AddressLiteral src2); 759 760 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 761 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 762 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 763 764 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 765 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 766 767 // cmp64 to avoild hiding cmpq 768 void cmp64(Register src1, AddressLiteral src); 769 770 void cmpxchgptr(Register reg, Address adr); 771 772 void locked_cmpxchgptr(Register reg, AddressLiteral adr); 773 774 775 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } 776 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); } 777 778 779 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } 780 781 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } 782 783 void shlptr(Register dst, int32_t shift); 784 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } 785 786 void shrptr(Register dst, int32_t shift); 787 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } 788 789 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } 790 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } 791 792 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 793 794 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 795 void subptr(Register dst, int32_t src); 796 // Force generation of a 4 byte immediate value even if it fits into 8bit 797 void subptr_imm32(Register dst, int32_t src); 798 void subptr(Register dst, Register src); 799 void subptr(Register dst, RegisterOrConstant src) { 800 if (src.is_constant()) subptr(dst, (int) src.as_constant()); 801 else subptr(dst, src.as_register()); 802 } 803 804 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 805 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 806 807 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 808 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 809 810 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } 811 812 813 814 // Helper functions for statistics gathering. 815 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. 816 void cond_inc32(Condition cond, AddressLiteral counter_addr); 817 // Unconditional atomic increment. 818 void atomic_incl(Address counter_addr); 819 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1); 820#ifdef _LP64 821 void atomic_incq(Address counter_addr); 822 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1); 823#endif 824 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; } 825 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; } 826 827 void lea(Register dst, AddressLiteral adr); 828 void lea(Address dst, AddressLiteral adr); 829 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } 830 831 void leal32(Register dst, Address src) { leal(dst, src); } 832 833 // Import other testl() methods from the parent class or else 834 // they will be hidden by the following overriding declaration. 835 using Assembler::testl; 836 void testl(Register dst, AddressLiteral src); 837 838 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 839 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 840 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 841 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); } 842 843 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } 844 void testptr(Register src1, Register src2); 845 846 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 847 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 848 849 // Calls 850 851 void call(Label& L, relocInfo::relocType rtype); 852 void call(Register entry); 853 854 // NOTE: this call transfers to the effective address of entry NOT 855 // the address contained by entry. This is because this is more natural 856 // for jumps/calls. 857 void call(AddressLiteral entry); 858 859 // Emit the CompiledIC call idiom 860 void ic_call(address entry, jint method_index = 0); 861 862 // Jumps 863 864 // NOTE: these jumps tranfer to the effective address of dst NOT 865 // the address contained by dst. This is because this is more natural 866 // for jumps/calls. 867 void jump(AddressLiteral dst); 868 void jump_cc(Condition cc, AddressLiteral dst); 869 870 // 32bit can do a case table jump in one instruction but we no longer allow the base 871 // to be installed in the Address class. This jump will tranfers to the address 872 // contained in the location described by entry (not the address of entry) 873 void jump(ArrayAddress entry); 874 875 // Floating 876 877 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } 878 void andpd(XMMRegister dst, AddressLiteral src); 879 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); } 880 881 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); } 882 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); } 883 void andps(XMMRegister dst, AddressLiteral src); 884 885 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); } 886 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } 887 void comiss(XMMRegister dst, AddressLiteral src); 888 889 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); } 890 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } 891 void comisd(XMMRegister dst, AddressLiteral src); 892 893 void fadd_s(Address src) { Assembler::fadd_s(src); } 894 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); } 895 896 void fldcw(Address src) { Assembler::fldcw(src); } 897 void fldcw(AddressLiteral src); 898 899 void fld_s(int index) { Assembler::fld_s(index); } 900 void fld_s(Address src) { Assembler::fld_s(src); } 901 void fld_s(AddressLiteral src); 902 903 void fld_d(Address src) { Assembler::fld_d(src); } 904 void fld_d(AddressLiteral src); 905 906 void fld_x(Address src) { Assembler::fld_x(src); } 907 void fld_x(AddressLiteral src); 908 909 void fmul_s(Address src) { Assembler::fmul_s(src); } 910 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); } 911 912 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } 913 void ldmxcsr(AddressLiteral src); 914 915#ifdef _LP64 916 private: 917 void sha256_AVX2_one_round_compute( 918 Register reg_old_h, 919 Register reg_a, 920 Register reg_b, 921 Register reg_c, 922 Register reg_d, 923 Register reg_e, 924 Register reg_f, 925 Register reg_g, 926 Register reg_h, 927 int iter); 928 void sha256_AVX2_four_rounds_compute_first(int start); 929 void sha256_AVX2_four_rounds_compute_last(int start); 930 void sha256_AVX2_one_round_and_sched( 931 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */ 932 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */ 933 XMMRegister xmm_2, /* ymm6 */ 934 XMMRegister xmm_3, /* ymm7 */ 935 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */ 936 Register reg_b, /* ebx */ /* full cycle is 8 iterations */ 937 Register reg_c, /* edi */ 938 Register reg_d, /* esi */ 939 Register reg_e, /* r8d */ 940 Register reg_f, /* r9d */ 941 Register reg_g, /* r10d */ 942 Register reg_h, /* r11d */ 943 int iter); 944 945 void addm(int disp, Register r1, Register r2); 946 947 public: 948 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0, 949 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4, 950 Register buf, Register state, Register ofs, Register limit, Register rsp, 951 bool multi_block, XMMRegister shuf_mask); 952#endif 953 954#ifdef _LP64 955 private: 956 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d, 957 Register e, Register f, Register g, Register h, int iteration); 958 959 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 960 Register a, Register b, Register c, Register d, Register e, Register f, 961 Register g, Register h, int iteration); 962 963 void addmq(int disp, Register r1, Register r2); 964 public: 965 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0, 966 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4, 967 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block, 968 XMMRegister shuf_mask); 969#endif 970 971 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0, 972 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask, 973 Register buf, Register state, Register ofs, Register limit, Register rsp, 974 bool multi_block); 975 976#ifdef _LP64 977 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0, 978 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4, 979 Register buf, Register state, Register ofs, Register limit, Register rsp, 980 bool multi_block, XMMRegister shuf_mask); 981#else 982 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0, 983 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4, 984 Register buf, Register state, Register ofs, Register limit, Register rsp, 985 bool multi_block); 986#endif 987 988 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 989 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 990 Register rax, Register rcx, Register rdx, Register tmp); 991 992#ifdef _LP64 993 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 994 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 995 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2); 996 997 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 998 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 999 Register rax, Register rcx, Register rdx, Register r11); 1000 1001 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4, 1002 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx, 1003 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4); 1004 1005 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1006 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1007 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2, 1008 Register tmp3, Register tmp4); 1009 1010 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1011 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1012 Register rax, Register rcx, Register rdx, Register tmp1, 1013 Register tmp2, Register tmp3, Register tmp4); 1014 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1015 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1016 Register rax, Register rcx, Register rdx, Register tmp1, 1017 Register tmp2, Register tmp3, Register tmp4); 1018#else 1019 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1020 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1021 Register rax, Register rcx, Register rdx, Register tmp1); 1022 1023 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1024 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1025 Register rax, Register rcx, Register rdx, Register tmp); 1026 1027 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4, 1028 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx, 1029 Register rdx, Register tmp); 1030 1031 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1032 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1033 Register rax, Register rbx, Register rdx); 1034 1035 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1036 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1037 Register rax, Register rcx, Register rdx, Register tmp); 1038 1039 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx, 1040 Register edx, Register ebx, Register esi, Register edi, 1041 Register ebp, Register esp); 1042 1043 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx, 1044 Register esi, Register edi, Register ebp, Register esp); 1045 1046 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx, 1047 Register edx, Register ebx, Register esi, Register edi, 1048 Register ebp, Register esp); 1049 1050 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, 1051 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, 1052 Register rax, Register rcx, Register rdx, Register tmp); 1053#endif 1054 1055 void increase_precision(); 1056 void restore_precision(); 1057 1058private: 1059 1060 // these are private because users should be doing movflt/movdbl 1061 1062 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } 1063 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } 1064 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } 1065 void movss(XMMRegister dst, AddressLiteral src); 1066 1067 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } 1068 void movlpd(XMMRegister dst, AddressLiteral src); 1069 1070public: 1071 1072 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); } 1073 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); } 1074 void addsd(XMMRegister dst, AddressLiteral src); 1075 1076 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); } 1077 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); } 1078 void addss(XMMRegister dst, AddressLiteral src); 1079 1080 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); } 1081 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); } 1082 void addpd(XMMRegister dst, AddressLiteral src); 1083 1084 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); } 1085 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); } 1086 void divsd(XMMRegister dst, AddressLiteral src); 1087 1088 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); } 1089 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); } 1090 void divss(XMMRegister dst, AddressLiteral src); 1091 1092 // Move Unaligned Double Quadword 1093 void movdqu(Address dst, XMMRegister src); 1094 void movdqu(XMMRegister dst, Address src); 1095 void movdqu(XMMRegister dst, XMMRegister src); 1096 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1); 1097 // AVX Unaligned forms 1098 void vmovdqu(Address dst, XMMRegister src); 1099 void vmovdqu(XMMRegister dst, Address src); 1100 void vmovdqu(XMMRegister dst, XMMRegister src); 1101 void vmovdqu(XMMRegister dst, AddressLiteral src); 1102 1103 // Move Aligned Double Quadword 1104 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); } 1105 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); } 1106 void movdqa(XMMRegister dst, AddressLiteral src); 1107 1108 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } 1109 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } 1110 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } 1111 void movsd(XMMRegister dst, AddressLiteral src); 1112 1113 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); } 1114 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); } 1115 void mulpd(XMMRegister dst, AddressLiteral src); 1116 1117 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); } 1118 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); } 1119 void mulsd(XMMRegister dst, AddressLiteral src); 1120 1121 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); } 1122 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); } 1123 void mulss(XMMRegister dst, AddressLiteral src); 1124 1125 // Carry-Less Multiplication Quadword 1126 void pclmulldq(XMMRegister dst, XMMRegister src) { 1127 // 0x00 - multiply lower 64 bits [0:63] 1128 Assembler::pclmulqdq(dst, src, 0x00); 1129 } 1130 void pclmulhdq(XMMRegister dst, XMMRegister src) { 1131 // 0x11 - multiply upper 64 bits [64:127] 1132 Assembler::pclmulqdq(dst, src, 0x11); 1133 } 1134 1135 void pcmpeqb(XMMRegister dst, XMMRegister src); 1136 void pcmpeqw(XMMRegister dst, XMMRegister src); 1137 1138 void pcmpestri(XMMRegister dst, Address src, int imm8); 1139 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8); 1140 1141 void pmovzxbw(XMMRegister dst, XMMRegister src); 1142 void pmovzxbw(XMMRegister dst, Address src); 1143 1144 void pmovmskb(Register dst, XMMRegister src); 1145 1146 void ptest(XMMRegister dst, XMMRegister src); 1147 1148 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); } 1149 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); } 1150 void sqrtsd(XMMRegister dst, AddressLiteral src); 1151 1152 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); } 1153 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); } 1154 void sqrtss(XMMRegister dst, AddressLiteral src); 1155 1156 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); } 1157 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); } 1158 void subsd(XMMRegister dst, AddressLiteral src); 1159 1160 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); } 1161 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); } 1162 void subss(XMMRegister dst, AddressLiteral src); 1163 1164 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } 1165 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } 1166 void ucomiss(XMMRegister dst, AddressLiteral src); 1167 1168 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } 1169 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } 1170 void ucomisd(XMMRegister dst, AddressLiteral src); 1171 1172 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values 1173 void xorpd(XMMRegister dst, XMMRegister src); 1174 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } 1175 void xorpd(XMMRegister dst, AddressLiteral src); 1176 1177 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values 1178 void xorps(XMMRegister dst, XMMRegister src); 1179 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } 1180 void xorps(XMMRegister dst, AddressLiteral src); 1181 1182 // Shuffle Bytes 1183 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); } 1184 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); } 1185 void pshufb(XMMRegister dst, AddressLiteral src); 1186 // AVX 3-operands instructions 1187 1188 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); } 1189 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); } 1190 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1191 1192 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); } 1193 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); } 1194 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1195 1196 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len); 1197 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len); 1198 1199 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1200 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 1201 1202 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1203 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 1204 1205 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); } 1206 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); } 1207 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); 1208 1209 void vpbroadcastw(XMMRegister dst, XMMRegister src); 1210 1211 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1212 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1213 1214 void vpmovzxbw(XMMRegister dst, Address src, int vector_len); 1215 void vpmovmskb(Register dst, XMMRegister src); 1216 1217 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1218 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 1219 1220 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1221 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 1222 1223 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1224 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 1225 1226 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len); 1227 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len); 1228 1229 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len); 1230 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len); 1231 1232 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len); 1233 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len); 1234 1235 void vptest(XMMRegister dst, XMMRegister src); 1236 1237 void punpcklbw(XMMRegister dst, XMMRegister src); 1238 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); } 1239 1240 void pshufd(XMMRegister dst, Address src, int mode); 1241 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); } 1242 1243 void pshuflw(XMMRegister dst, XMMRegister src, int mode); 1244 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); } 1245 1246 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); } 1247 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); } 1248 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); 1249 1250 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); } 1251 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); } 1252 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); 1253 1254 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); } 1255 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); } 1256 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1257 1258 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); } 1259 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); } 1260 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1261 1262 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); } 1263 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); } 1264 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1265 1266 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); } 1267 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); } 1268 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1269 1270 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); } 1271 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); } 1272 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1273 1274 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); } 1275 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); } 1276 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1277 1278 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1279 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src); 1280 1281 // AVX Vector instructions 1282 1283 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); } 1284 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); } 1285 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); 1286 1287 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); } 1288 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); } 1289 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len); 1290 1291 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 1292 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2 1293 Assembler::vpxor(dst, nds, src, vector_len); 1294 else 1295 Assembler::vxorpd(dst, nds, src, vector_len); 1296 } 1297 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 1298 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2 1299 Assembler::vpxor(dst, nds, src, vector_len); 1300 else 1301 Assembler::vxorpd(dst, nds, src, vector_len); 1302 } 1303 1304 // Simple version for AVX2 256bit vectors 1305 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); } 1306 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); } 1307 1308 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 1309 if (UseAVX > 2) { 1310 Assembler::vinserti32x4(dst, dst, src, imm8); 1311 } else if (UseAVX > 1) { 1312 // vinserti128 is available only in AVX2 1313 Assembler::vinserti128(dst, nds, src, imm8); 1314 } else { 1315 Assembler::vinsertf128(dst, nds, src, imm8); 1316 } 1317 } 1318 1319 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 1320 if (UseAVX > 2) { 1321 Assembler::vinserti32x4(dst, dst, src, imm8); 1322 } else if (UseAVX > 1) { 1323 // vinserti128 is available only in AVX2 1324 Assembler::vinserti128(dst, nds, src, imm8); 1325 } else { 1326 Assembler::vinsertf128(dst, nds, src, imm8); 1327 } 1328 } 1329 1330 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) { 1331 if (UseAVX > 2) { 1332 Assembler::vextracti32x4(dst, src, imm8); 1333 } else if (UseAVX > 1) { 1334 // vextracti128 is available only in AVX2 1335 Assembler::vextracti128(dst, src, imm8); 1336 } else { 1337 Assembler::vextractf128(dst, src, imm8); 1338 } 1339 } 1340 1341 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) { 1342 if (UseAVX > 2) { 1343 Assembler::vextracti32x4(dst, src, imm8); 1344 } else if (UseAVX > 1) { 1345 // vextracti128 is available only in AVX2 1346 Assembler::vextracti128(dst, src, imm8); 1347 } else { 1348 Assembler::vextractf128(dst, src, imm8); 1349 } 1350 } 1351 1352 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers 1353 void vinserti128_high(XMMRegister dst, XMMRegister src) { 1354 vinserti128(dst, dst, src, 1); 1355 } 1356 void vinserti128_high(XMMRegister dst, Address src) { 1357 vinserti128(dst, dst, src, 1); 1358 } 1359 void vextracti128_high(XMMRegister dst, XMMRegister src) { 1360 vextracti128(dst, src, 1); 1361 } 1362 void vextracti128_high(Address dst, XMMRegister src) { 1363 vextracti128(dst, src, 1); 1364 } 1365 1366 void vinsertf128_high(XMMRegister dst, XMMRegister src) { 1367 if (UseAVX > 2) { 1368 Assembler::vinsertf32x4(dst, dst, src, 1); 1369 } else { 1370 Assembler::vinsertf128(dst, dst, src, 1); 1371 } 1372 } 1373 1374 void vinsertf128_high(XMMRegister dst, Address src) { 1375 if (UseAVX > 2) { 1376 Assembler::vinsertf32x4(dst, dst, src, 1); 1377 } else { 1378 Assembler::vinsertf128(dst, dst, src, 1); 1379 } 1380 } 1381 1382 void vextractf128_high(XMMRegister dst, XMMRegister src) { 1383 if (UseAVX > 2) { 1384 Assembler::vextractf32x4(dst, src, 1); 1385 } else { 1386 Assembler::vextractf128(dst, src, 1); 1387 } 1388 } 1389 1390 void vextractf128_high(Address dst, XMMRegister src) { 1391 if (UseAVX > 2) { 1392 Assembler::vextractf32x4(dst, src, 1); 1393 } else { 1394 Assembler::vextractf128(dst, src, 1); 1395 } 1396 } 1397 1398 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers 1399 void vinserti64x4_high(XMMRegister dst, XMMRegister src) { 1400 Assembler::vinserti64x4(dst, dst, src, 1); 1401 } 1402 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) { 1403 Assembler::vinsertf64x4(dst, dst, src, 1); 1404 } 1405 void vextracti64x4_high(XMMRegister dst, XMMRegister src) { 1406 Assembler::vextracti64x4(dst, src, 1); 1407 } 1408 void vextractf64x4_high(XMMRegister dst, XMMRegister src) { 1409 Assembler::vextractf64x4(dst, src, 1); 1410 } 1411 void vextractf64x4_high(Address dst, XMMRegister src) { 1412 Assembler::vextractf64x4(dst, src, 1); 1413 } 1414 void vinsertf64x4_high(XMMRegister dst, Address src) { 1415 Assembler::vinsertf64x4(dst, dst, src, 1); 1416 } 1417 1418 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers 1419 void vinserti128_low(XMMRegister dst, XMMRegister src) { 1420 vinserti128(dst, dst, src, 0); 1421 } 1422 void vinserti128_low(XMMRegister dst, Address src) { 1423 vinserti128(dst, dst, src, 0); 1424 } 1425 void vextracti128_low(XMMRegister dst, XMMRegister src) { 1426 vextracti128(dst, src, 0); 1427 } 1428 void vextracti128_low(Address dst, XMMRegister src) { 1429 vextracti128(dst, src, 0); 1430 } 1431 1432 void vinsertf128_low(XMMRegister dst, XMMRegister src) { 1433 if (UseAVX > 2) { 1434 Assembler::vinsertf32x4(dst, dst, src, 0); 1435 } else { 1436 Assembler::vinsertf128(dst, dst, src, 0); 1437 } 1438 } 1439 1440 void vinsertf128_low(XMMRegister dst, Address src) { 1441 if (UseAVX > 2) { 1442 Assembler::vinsertf32x4(dst, dst, src, 0); 1443 } else { 1444 Assembler::vinsertf128(dst, dst, src, 0); 1445 } 1446 } 1447 1448 void vextractf128_low(XMMRegister dst, XMMRegister src) { 1449 if (UseAVX > 2) { 1450 Assembler::vextractf32x4(dst, src, 0); 1451 } else { 1452 Assembler::vextractf128(dst, src, 0); 1453 } 1454 } 1455 1456 void vextractf128_low(Address dst, XMMRegister src) { 1457 if (UseAVX > 2) { 1458 Assembler::vextractf32x4(dst, src, 0); 1459 } else { 1460 Assembler::vextractf128(dst, src, 0); 1461 } 1462 } 1463 1464 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers 1465 void vinserti64x4_low(XMMRegister dst, XMMRegister src) { 1466 Assembler::vinserti64x4(dst, dst, src, 0); 1467 } 1468 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) { 1469 Assembler::vinsertf64x4(dst, dst, src, 0); 1470 } 1471 void vextracti64x4_low(XMMRegister dst, XMMRegister src) { 1472 Assembler::vextracti64x4(dst, src, 0); 1473 } 1474 void vextractf64x4_low(XMMRegister dst, XMMRegister src) { 1475 Assembler::vextractf64x4(dst, src, 0); 1476 } 1477 void vextractf64x4_low(Address dst, XMMRegister src) { 1478 Assembler::vextractf64x4(dst, src, 0); 1479 } 1480 void vinsertf64x4_low(XMMRegister dst, Address src) { 1481 Assembler::vinsertf64x4(dst, dst, src, 0); 1482 } 1483 1484 // Carry-Less Multiplication Quadword 1485 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) { 1486 // 0x00 - multiply lower 64 bits [0:63] 1487 Assembler::vpclmulqdq(dst, nds, src, 0x00); 1488 } 1489 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) { 1490 // 0x11 - multiply upper 64 bits [64:127] 1491 Assembler::vpclmulqdq(dst, nds, src, 0x11); 1492 } 1493 1494 // Data 1495 1496 void cmov32( Condition cc, Register dst, Address src); 1497 void cmov32( Condition cc, Register dst, Register src); 1498 1499 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); } 1500 1501 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } 1502 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); } 1503 1504 void movoop(Register dst, jobject obj); 1505 void movoop(Address dst, jobject obj); 1506 1507 void mov_metadata(Register dst, Metadata* obj); 1508 void mov_metadata(Address dst, Metadata* obj); 1509 1510 void movptr(ArrayAddress dst, Register src); 1511 // can this do an lea? 1512 void movptr(Register dst, ArrayAddress src); 1513 1514 void movptr(Register dst, Address src); 1515 1516#ifdef _LP64 1517 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1); 1518#else 1519 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit 1520#endif 1521 1522 void movptr(Register dst, intptr_t src); 1523 void movptr(Register dst, Register src); 1524 void movptr(Address dst, intptr_t src); 1525 1526 void movptr(Address dst, Register src); 1527 1528 void movptr(Register dst, RegisterOrConstant src) { 1529 if (src.is_constant()) movptr(dst, src.as_constant()); 1530 else movptr(dst, src.as_register()); 1531 } 1532 1533#ifdef _LP64 1534 // Generally the next two are only used for moving NULL 1535 // Although there are situations in initializing the mark word where 1536 // they could be used. They are dangerous. 1537 1538 // They only exist on LP64 so that int32_t and intptr_t are not the same 1539 // and we have ambiguous declarations. 1540 1541 void movptr(Address dst, int32_t imm32); 1542 void movptr(Register dst, int32_t imm32); 1543#endif // _LP64 1544 1545 // to avoid hiding movl 1546 void mov32(AddressLiteral dst, Register src); 1547 void mov32(Register dst, AddressLiteral src); 1548 1549 // to avoid hiding movb 1550 void movbyte(ArrayAddress dst, int src); 1551 1552 // Import other mov() methods from the parent class or else 1553 // they will be hidden by the following overriding declaration. 1554 using Assembler::movdl; 1555 using Assembler::movq; 1556 void movdl(XMMRegister dst, AddressLiteral src); 1557 void movq(XMMRegister dst, AddressLiteral src); 1558 1559 // Can push value or effective address 1560 void pushptr(AddressLiteral src); 1561 1562 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } 1563 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } 1564 1565 void pushoop(jobject obj); 1566 void pushklass(Metadata* obj); 1567 1568 // sign extend as need a l to ptr sized element 1569 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } 1570 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } 1571 1572 // C2 compiled method's prolog code. 1573 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b); 1574 1575 // clear memory of size 'cnt' qwords, starting at 'base'; 1576 // if 'is_large' is set, do not try to produce short loop 1577 void clear_mem(Register base, Register cnt, Register rtmp, bool is_large); 1578 1579#ifdef COMPILER2 1580 void string_indexof_char(Register str1, Register cnt1, Register ch, Register result, 1581 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp); 1582 1583 // IndexOf strings. 1584 // Small strings are loaded through stack if they cross page boundary. 1585 void string_indexof(Register str1, Register str2, 1586 Register cnt1, Register cnt2, 1587 int int_cnt2, Register result, 1588 XMMRegister vec, Register tmp, 1589 int ae); 1590 1591 // IndexOf for constant substrings with size >= 8 elements 1592 // which don't need to be loaded through stack. 1593 void string_indexofC8(Register str1, Register str2, 1594 Register cnt1, Register cnt2, 1595 int int_cnt2, Register result, 1596 XMMRegister vec, Register tmp, 1597 int ae); 1598 1599 // Smallest code: we don't need to load through stack, 1600 // check string tail. 1601 1602 // helper function for string_compare 1603 void load_next_elements(Register elem1, Register elem2, Register str1, Register str2, 1604 Address::ScaleFactor scale, Address::ScaleFactor scale1, 1605 Address::ScaleFactor scale2, Register index, int ae); 1606 // Compare strings. 1607 void string_compare(Register str1, Register str2, 1608 Register cnt1, Register cnt2, Register result, 1609 XMMRegister vec1, int ae); 1610 1611 // Search for Non-ASCII character (Negative byte value) in a byte array, 1612 // return true if it has any and false otherwise. 1613 void has_negatives(Register ary1, Register len, 1614 Register result, Register tmp1, 1615 XMMRegister vec1, XMMRegister vec2); 1616 1617 // Compare char[] or byte[] arrays. 1618 void arrays_equals(bool is_array_equ, Register ary1, Register ary2, 1619 Register limit, Register result, Register chr, 1620 XMMRegister vec1, XMMRegister vec2, bool is_char); 1621 1622#endif 1623 1624 // Fill primitive arrays 1625 void generate_fill(BasicType t, bool aligned, 1626 Register to, Register value, Register count, 1627 Register rtmp, XMMRegister xtmp); 1628 1629 void encode_iso_array(Register src, Register dst, Register len, 1630 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3, 1631 XMMRegister tmp4, Register tmp5, Register result); 1632 1633#ifdef _LP64 1634 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2); 1635 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 1636 Register y, Register y_idx, Register z, 1637 Register carry, Register product, 1638 Register idx, Register kdx); 1639 void multiply_add_128_x_128(Register x_xstart, Register y, Register z, 1640 Register yz_idx, Register idx, 1641 Register carry, Register product, int offset); 1642 void multiply_128_x_128_bmi2_loop(Register y, Register z, 1643 Register carry, Register carry2, 1644 Register idx, Register jdx, 1645 Register yz_idx1, Register yz_idx2, 1646 Register tmp, Register tmp3, Register tmp4); 1647 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 1648 Register yz_idx, Register idx, Register jdx, 1649 Register carry, Register product, 1650 Register carry2); 1651 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 1652 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5); 1653 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3, 1654 Register tmp4, Register tmp5, Register rdxReg, Register raxReg); 1655 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, 1656 Register tmp2); 1657 void multiply_add_64(Register sum, Register op1, Register op2, Register carry, 1658 Register rdxReg, Register raxReg); 1659 void add_one_64(Register z, Register zlen, Register carry, Register tmp1); 1660 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, 1661 Register tmp3, Register tmp4); 1662 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, 1663 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg); 1664 1665 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1, 1666 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, 1667 Register raxReg); 1668 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1, 1669 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, 1670 Register raxReg); 1671 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale, 1672 Register result, Register tmp1, Register tmp2, 1673 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3); 1674#endif 1675 1676 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic. 1677 void update_byte_crc32(Register crc, Register val, Register table); 1678 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp); 1679 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic 1680 // Note on a naming convention: 1681 // Prefix w = register only used on a Westmere+ architecture 1682 // Prefix n = register only used on a Nehalem architecture 1683#ifdef _LP64 1684 void crc32c_ipl_alg4(Register in_out, uint32_t n, 1685 Register tmp1, Register tmp2, Register tmp3); 1686#else 1687 void crc32c_ipl_alg4(Register in_out, uint32_t n, 1688 Register tmp1, Register tmp2, Register tmp3, 1689 XMMRegister xtmp1, XMMRegister xtmp2); 1690#endif 1691 void crc32c_pclmulqdq(XMMRegister w_xtmp1, 1692 Register in_out, 1693 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 1694 XMMRegister w_xtmp2, 1695 Register tmp1, 1696 Register n_tmp2, Register n_tmp3); 1697 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 1698 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 1699 Register tmp1, Register tmp2, 1700 Register n_tmp3); 1701 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 1702 Register in_out1, Register in_out2, Register in_out3, 1703 Register tmp1, Register tmp2, Register tmp3, 1704 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 1705 Register tmp4, Register tmp5, 1706 Register n_tmp6); 1707 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 1708 Register tmp1, Register tmp2, Register tmp3, 1709 Register tmp4, Register tmp5, Register tmp6, 1710 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 1711 bool is_pclmulqdq_supported); 1712 // Fold 128-bit data chunk 1713 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset); 1714 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf); 1715 // Fold 8-bit data 1716 void fold_8bit_crc32(Register crc, Register table, Register tmp); 1717 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp); 1718 1719 // Compress char[] array to byte[]. 1720 void char_array_compress(Register src, Register dst, Register len, 1721 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3, 1722 XMMRegister tmp4, Register tmp5, Register result); 1723 1724 // Inflate byte[] array to char[]. 1725 void byte_array_inflate(Register src, Register dst, Register len, 1726 XMMRegister tmp1, Register tmp2); 1727 1728}; 1729 1730/** 1731 * class SkipIfEqual: 1732 * 1733 * Instantiating this class will result in assembly code being output that will 1734 * jump around any code emitted between the creation of the instance and it's 1735 * automatic destruction at the end of a scope block, depending on the value of 1736 * the flag passed to the constructor, which will be checked at run-time. 1737 */ 1738class SkipIfEqual { 1739 private: 1740 MacroAssembler* _masm; 1741 Label _label; 1742 1743 public: 1744 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 1745 ~SkipIfEqual(); 1746}; 1747 1748#endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP 1749