c1_LIRAssembler_x86.cpp revision 304:dc7f315e41f7
1/* 2 * Copyright 2000-2008 Sun Microsystems, Inc. All Rights Reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 * CA 95054 USA or visit www.sun.com if you need additional information or 21 * have any questions. 22 * 23 */ 24 25# include "incls/_precompiled.incl" 26# include "incls/_c1_LIRAssembler_x86.cpp.incl" 27 28 29// These masks are used to provide 128-bit aligned bitmasks to the XMM 30// instructions, to allow sign-masking or sign-bit flipping. They allow 31// fast versions of NegF/NegD and AbsF/AbsD. 32 33// Note: 'double' and 'long long' have 32-bits alignment on x86. 34static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 35 // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 36 // of 128-bits operands for SSE instructions. 37 jlong *operand = (jlong*)(((long)adr)&((long)(~0xF))); 38 // Store the value to a 128-bits operand. 39 operand[0] = lo; 40 operand[1] = hi; 41 return operand; 42} 43 44// Buffer for 128-bits masks used by SSE instructions. 45static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 46 47// Static initialization during VM startup. 48static jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 49static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 50static jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); 51static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); 52 53 54 55NEEDS_CLEANUP // remove this definitions ? 56const Register IC_Klass = rax; // where the IC klass is cached 57const Register SYNC_header = rax; // synchronization header 58const Register SHIFT_count = rcx; // where count for shift operations must be 59 60#define __ _masm-> 61 62 63static void select_different_registers(Register preserve, 64 Register extra, 65 Register &tmp1, 66 Register &tmp2) { 67 if (tmp1 == preserve) { 68 assert_different_registers(tmp1, tmp2, extra); 69 tmp1 = extra; 70 } else if (tmp2 == preserve) { 71 assert_different_registers(tmp1, tmp2, extra); 72 tmp2 = extra; 73 } 74 assert_different_registers(preserve, tmp1, tmp2); 75} 76 77 78 79static void select_different_registers(Register preserve, 80 Register extra, 81 Register &tmp1, 82 Register &tmp2, 83 Register &tmp3) { 84 if (tmp1 == preserve) { 85 assert_different_registers(tmp1, tmp2, tmp3, extra); 86 tmp1 = extra; 87 } else if (tmp2 == preserve) { 88 assert_different_registers(tmp1, tmp2, tmp3, extra); 89 tmp2 = extra; 90 } else if (tmp3 == preserve) { 91 assert_different_registers(tmp1, tmp2, tmp3, extra); 92 tmp3 = extra; 93 } 94 assert_different_registers(preserve, tmp1, tmp2, tmp3); 95} 96 97 98 99bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 100 if (opr->is_constant()) { 101 LIR_Const* constant = opr->as_constant_ptr(); 102 switch (constant->type()) { 103 case T_INT: { 104 return true; 105 } 106 107 default: 108 return false; 109 } 110 } 111 return false; 112} 113 114 115LIR_Opr LIR_Assembler::receiverOpr() { 116 return FrameMap::receiver_opr; 117} 118 119LIR_Opr LIR_Assembler::incomingReceiverOpr() { 120 return receiverOpr(); 121} 122 123LIR_Opr LIR_Assembler::osrBufferPointer() { 124 return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 125} 126 127//--------------fpu register translations----------------------- 128 129 130address LIR_Assembler::float_constant(float f) { 131 address const_addr = __ float_constant(f); 132 if (const_addr == NULL) { 133 bailout("const section overflow"); 134 return __ code()->consts()->start(); 135 } else { 136 return const_addr; 137 } 138} 139 140 141address LIR_Assembler::double_constant(double d) { 142 address const_addr = __ double_constant(d); 143 if (const_addr == NULL) { 144 bailout("const section overflow"); 145 return __ code()->consts()->start(); 146 } else { 147 return const_addr; 148 } 149} 150 151 152void LIR_Assembler::set_24bit_FPU() { 153 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 154} 155 156void LIR_Assembler::reset_FPU() { 157 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 158} 159 160void LIR_Assembler::fpop() { 161 __ fpop(); 162} 163 164void LIR_Assembler::fxch(int i) { 165 __ fxch(i); 166} 167 168void LIR_Assembler::fld(int i) { 169 __ fld_s(i); 170} 171 172void LIR_Assembler::ffree(int i) { 173 __ ffree(i); 174} 175 176void LIR_Assembler::breakpoint() { 177 __ int3(); 178} 179 180void LIR_Assembler::push(LIR_Opr opr) { 181 if (opr->is_single_cpu()) { 182 __ push_reg(opr->as_register()); 183 } else if (opr->is_double_cpu()) { 184 NOT_LP64(__ push_reg(opr->as_register_hi())); 185 __ push_reg(opr->as_register_lo()); 186 } else if (opr->is_stack()) { 187 __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 188 } else if (opr->is_constant()) { 189 LIR_Const* const_opr = opr->as_constant_ptr(); 190 if (const_opr->type() == T_OBJECT) { 191 __ push_oop(const_opr->as_jobject()); 192 } else if (const_opr->type() == T_INT) { 193 __ push_jint(const_opr->as_jint()); 194 } else { 195 ShouldNotReachHere(); 196 } 197 198 } else { 199 ShouldNotReachHere(); 200 } 201} 202 203void LIR_Assembler::pop(LIR_Opr opr) { 204 if (opr->is_single_cpu()) { 205 __ pop_reg(opr->as_register()); 206 } else { 207 ShouldNotReachHere(); 208 } 209} 210 211bool LIR_Assembler::is_literal_address(LIR_Address* addr) { 212 return addr->base()->is_illegal() && addr->index()->is_illegal(); 213} 214 215//------------------------------------------- 216 217Address LIR_Assembler::as_Address(LIR_Address* addr) { 218 return as_Address(addr, rscratch1); 219} 220 221Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 222 if (addr->base()->is_illegal()) { 223 assert(addr->index()->is_illegal(), "must be illegal too"); 224 AddressLiteral laddr((address)addr->disp(), relocInfo::none); 225 if (! __ reachable(laddr)) { 226 __ movptr(tmp, laddr.addr()); 227 Address res(tmp, 0); 228 return res; 229 } else { 230 return __ as_Address(laddr); 231 } 232 } 233 234 Register base = addr->base()->as_pointer_register(); 235 236 if (addr->index()->is_illegal()) { 237 return Address( base, addr->disp()); 238 } else if (addr->index()->is_cpu_register()) { 239 Register index = addr->index()->as_pointer_register(); 240 return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 241 } else if (addr->index()->is_constant()) { 242 intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 243 assert(Assembler::is_simm32(addr_offset), "must be"); 244 245 return Address(base, addr_offset); 246 } else { 247 Unimplemented(); 248 return Address(); 249 } 250} 251 252 253Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 254 Address base = as_Address(addr); 255 return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 256} 257 258 259Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 260 return as_Address(addr); 261} 262 263 264void LIR_Assembler::osr_entry() { 265 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 266 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 267 ValueStack* entry_state = osr_entry->state(); 268 int number_of_locks = entry_state->locks_size(); 269 270 // we jump here if osr happens with the interpreter 271 // state set up to continue at the beginning of the 272 // loop that triggered osr - in particular, we have 273 // the following registers setup: 274 // 275 // rcx: osr buffer 276 // 277 278 // build frame 279 ciMethod* m = compilation()->method(); 280 __ build_frame(initial_frame_size_in_bytes()); 281 282 // OSR buffer is 283 // 284 // locals[nlocals-1..0] 285 // monitors[0..number_of_locks] 286 // 287 // locals is a direct copy of the interpreter frame so in the osr buffer 288 // so first slot in the local array is the last local from the interpreter 289 // and last slot is local[0] (receiver) from the interpreter 290 // 291 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 292 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 293 // in the interpreter frame (the method lock if a sync method) 294 295 // Initialize monitors in the compiled activation. 296 // rcx: pointer to osr buffer 297 // 298 // All other registers are dead at this point and the locals will be 299 // copied into place by code emitted in the IR. 300 301 Register OSR_buf = osrBufferPointer()->as_pointer_register(); 302 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 303 int monitor_offset = BytesPerWord * method()->max_locals() + 304 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); 305 for (int i = 0; i < number_of_locks; i++) { 306 int slot_offset = monitor_offset - ((i * BasicObjectLock::size()) * BytesPerWord); 307#ifdef ASSERT 308 // verify the interpreter's monitor has a non-null object 309 { 310 Label L; 311 __ cmpptr(Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes()), (int32_t)NULL_WORD); 312 __ jcc(Assembler::notZero, L); 313 __ stop("locked object is NULL"); 314 __ bind(L); 315 } 316#endif 317 __ movptr(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::lock_offset_in_bytes())); 318 __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 319 __ movptr(rbx, Address(OSR_buf, slot_offset + BasicObjectLock::obj_offset_in_bytes())); 320 __ movptr(frame_map()->address_for_monitor_object(i), rbx); 321 } 322 } 323} 324 325 326// inline cache check; done before the frame is built. 327int LIR_Assembler::check_icache() { 328 Register receiver = FrameMap::receiver_opr->as_register(); 329 Register ic_klass = IC_Klass; 330 const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 331 332 if (!VerifyOops) { 333 // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 334 while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { 335 __ nop(); 336 } 337 } 338 int offset = __ offset(); 339 __ inline_cache_check(receiver, IC_Klass); 340 assert(__ offset() % CodeEntryAlignment == 0 || VerifyOops, "alignment must be correct"); 341 if (VerifyOops) { 342 // force alignment after the cache check. 343 // It's been verified to be aligned if !VerifyOops 344 __ align(CodeEntryAlignment); 345 } 346 return offset; 347} 348 349 350void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 351 jobject o = NULL; 352 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 353 __ movoop(reg, o); 354 patching_epilog(patch, lir_patch_normal, reg, info); 355} 356 357 358void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register new_hdr, int monitor_no, Register exception) { 359 if (exception->is_valid()) { 360 // preserve exception 361 // note: the monitor_exit runtime call is a leaf routine 362 // and cannot block => no GC can happen 363 // The slow case (MonitorAccessStub) uses the first two stack slots 364 // ([esp+0] and [esp+4]), therefore we store the exception at [esp+8] 365 __ movptr (Address(rsp, 2*wordSize), exception); 366 } 367 368 Register obj_reg = obj_opr->as_register(); 369 Register lock_reg = lock_opr->as_register(); 370 371 // setup registers (lock_reg must be rax, for lock_object) 372 assert(obj_reg != SYNC_header && lock_reg != SYNC_header, "rax, must be available here"); 373 Register hdr = lock_reg; 374 assert(new_hdr == SYNC_header, "wrong register"); 375 lock_reg = new_hdr; 376 // compute pointer to BasicLock 377 Address lock_addr = frame_map()->address_for_monitor_lock(monitor_no); 378 __ lea(lock_reg, lock_addr); 379 // unlock object 380 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, true, monitor_no); 381 // _slow_case_stubs->append(slow_case); 382 // temporary fix: must be created after exceptionhandler, therefore as call stub 383 _slow_case_stubs->append(slow_case); 384 if (UseFastLocking) { 385 // try inlined fast unlocking first, revert to slow locking if it fails 386 // note: lock_reg points to the displaced header since the displaced header offset is 0! 387 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 388 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); 389 } else { 390 // always do slow unlocking 391 // note: the slow unlocking code could be inlined here, however if we use 392 // slow unlocking, speed doesn't matter anyway and this solution is 393 // simpler and requires less duplicated code - additionally, the 394 // slow unlocking code is the same in either case which simplifies 395 // debugging 396 __ jmp(*slow_case->entry()); 397 } 398 // done 399 __ bind(*slow_case->continuation()); 400 401 if (exception->is_valid()) { 402 // restore exception 403 __ movptr (exception, Address(rsp, 2 * wordSize)); 404 } 405} 406 407// This specifies the rsp decrement needed to build the frame 408int LIR_Assembler::initial_frame_size_in_bytes() { 409 // if rounding, must let FrameMap know! 410 411 // The frame_map records size in slots (32bit word) 412 413 // subtract two words to account for return address and link 414 return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 415} 416 417 418void LIR_Assembler::emit_exception_handler() { 419 // if the last instruction is a call (typically to do a throw which 420 // is coming at the end after block reordering) the return address 421 // must still point into the code area in order to avoid assertion 422 // failures when searching for the corresponding bci => add a nop 423 // (was bug 5/14/1999 - gri) 424 425 __ nop(); 426 427 // generate code for exception handler 428 address handler_base = __ start_a_stub(exception_handler_size); 429 if (handler_base == NULL) { 430 // not enough space left for the handler 431 bailout("exception handler overflow"); 432 return; 433 } 434#ifdef ASSERT 435 int offset = code_offset(); 436#endif // ASSERT 437 438 compilation()->offsets()->set_value(CodeOffsets::Exceptions, code_offset()); 439 440 // if the method does not have an exception handler, then there is 441 // no reason to search for one 442 if (compilation()->has_exception_handlers() || JvmtiExport::can_post_exceptions()) { 443 // the exception oop and pc are in rax, and rdx 444 // no other registers need to be preserved, so invalidate them 445 __ invalidate_registers(false, true, true, false, true, true); 446 447 // check that there is really an exception 448 __ verify_not_null_oop(rax); 449 450 // search an exception handler (rax: exception oop, rdx: throwing pc) 451 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_nofpu_id))); 452 453 // if the call returns here, then the exception handler for particular 454 // exception doesn't exist -> unwind activation and forward exception to caller 455 } 456 457 // the exception oop is in rax, 458 // no other registers need to be preserved, so invalidate them 459 __ invalidate_registers(false, true, true, true, true, true); 460 461 // check that there is really an exception 462 __ verify_not_null_oop(rax); 463 464 // unlock the receiver/klass if necessary 465 // rax,: exception 466 ciMethod* method = compilation()->method(); 467 if (method->is_synchronized() && GenerateSynchronizationCode) { 468 monitorexit(FrameMap::rbx_oop_opr, FrameMap::rcx_opr, SYNC_header, 0, rax); 469 } 470 471 // unwind activation and forward exception to caller 472 // rax,: exception 473 __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 474 475 assert(code_offset() - offset <= exception_handler_size, "overflow"); 476 477 __ end_a_stub(); 478} 479 480void LIR_Assembler::emit_deopt_handler() { 481 // if the last instruction is a call (typically to do a throw which 482 // is coming at the end after block reordering) the return address 483 // must still point into the code area in order to avoid assertion 484 // failures when searching for the corresponding bci => add a nop 485 // (was bug 5/14/1999 - gri) 486 487 __ nop(); 488 489 // generate code for exception handler 490 address handler_base = __ start_a_stub(deopt_handler_size); 491 if (handler_base == NULL) { 492 // not enough space left for the handler 493 bailout("deopt handler overflow"); 494 return; 495 } 496#ifdef ASSERT 497 int offset = code_offset(); 498#endif // ASSERT 499 500 compilation()->offsets()->set_value(CodeOffsets::Deopt, code_offset()); 501 502 InternalAddress here(__ pc()); 503 __ pushptr(here.addr()); 504 505 __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 506 507 assert(code_offset() - offset <= deopt_handler_size, "overflow"); 508 509 __ end_a_stub(); 510 511} 512 513 514// This is the fast version of java.lang.String.compare; it has not 515// OSR-entry and therefore, we generate a slow version for OSR's 516void LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { 517 __ movptr (rbx, rcx); // receiver is in rcx 518 __ movptr (rax, arg1->as_register()); 519 520 // Get addresses of first characters from both Strings 521 __ movptr (rsi, Address(rax, java_lang_String::value_offset_in_bytes())); 522 __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); 523 __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 524 525 526 // rbx, may be NULL 527 add_debug_info_for_null_check_here(info); 528 __ movptr (rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); 529 __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); 530 __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 531 532 // compute minimum length (in rax) and difference of lengths (on top of stack) 533 if (VM_Version::supports_cmov()) { 534 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); 535 __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); 536 __ mov (rcx, rbx); 537 __ subptr (rbx, rax); // subtract lengths 538 __ push (rbx); // result 539 __ cmov (Assembler::lessEqual, rax, rcx); 540 } else { 541 Label L; 542 __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); 543 __ movl (rcx, Address(rax, java_lang_String::count_offset_in_bytes())); 544 __ mov (rax, rbx); 545 __ subptr (rbx, rcx); 546 __ push (rbx); 547 __ jcc (Assembler::lessEqual, L); 548 __ mov (rax, rcx); 549 __ bind (L); 550 } 551 // is minimum length 0? 552 Label noLoop, haveResult; 553 __ testptr (rax, rax); 554 __ jcc (Assembler::zero, noLoop); 555 556 // compare first characters 557 __ load_unsigned_word(rcx, Address(rdi, 0)); 558 __ load_unsigned_word(rbx, Address(rsi, 0)); 559 __ subl(rcx, rbx); 560 __ jcc(Assembler::notZero, haveResult); 561 // starting loop 562 __ decrement(rax); // we already tested index: skip one 563 __ jcc(Assembler::zero, noLoop); 564 565 // set rsi.edi to the end of the arrays (arrays have same length) 566 // negate the index 567 568 __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); 569 __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); 570 __ negptr(rax); 571 572 // compare the strings in a loop 573 574 Label loop; 575 __ align(wordSize); 576 __ bind(loop); 577 __ load_unsigned_word(rcx, Address(rdi, rax, Address::times_2, 0)); 578 __ load_unsigned_word(rbx, Address(rsi, rax, Address::times_2, 0)); 579 __ subl(rcx, rbx); 580 __ jcc(Assembler::notZero, haveResult); 581 __ increment(rax); 582 __ jcc(Assembler::notZero, loop); 583 584 // strings are equal up to min length 585 586 __ bind(noLoop); 587 __ pop(rax); 588 return_op(LIR_OprFact::illegalOpr); 589 590 __ bind(haveResult); 591 // leave instruction is going to discard the TOS value 592 __ mov (rax, rcx); // result of call is in rax, 593} 594 595 596void LIR_Assembler::return_op(LIR_Opr result) { 597 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 598 if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 599 assert(result->fpu() == 0, "result must already be on TOS"); 600 } 601 602 // Pop the stack before the safepoint code 603 __ leave(); 604 605 bool result_is_oop = result->is_valid() ? result->is_oop() : false; 606 607 // Note: we do not need to round double result; float result has the right precision 608 // the poll sets the condition code, but no data registers 609 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), 610 relocInfo::poll_return_type); 611 612 // NOTE: the requires that the polling page be reachable else the reloc 613 // goes to the movq that loads the address and not the faulting instruction 614 // which breaks the signal handler code 615 616 __ test32(rax, polling_page); 617 618 __ ret(0); 619} 620 621 622int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 623 AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), 624 relocInfo::poll_type); 625 626 if (info != NULL) { 627 add_debug_info_for_branch(info); 628 } else { 629 ShouldNotReachHere(); 630 } 631 632 int offset = __ offset(); 633 634 // NOTE: the requires that the polling page be reachable else the reloc 635 // goes to the movq that loads the address and not the faulting instruction 636 // which breaks the signal handler code 637 638 __ test32(rax, polling_page); 639 return offset; 640} 641 642 643void LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 644 if (from_reg != to_reg) __ mov(to_reg, from_reg); 645} 646 647void LIR_Assembler::swap_reg(Register a, Register b) { 648 __ xchgptr(a, b); 649} 650 651 652void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 653 assert(src->is_constant(), "should not call otherwise"); 654 assert(dest->is_register(), "should not call otherwise"); 655 LIR_Const* c = src->as_constant_ptr(); 656 657 switch (c->type()) { 658 case T_INT: { 659 assert(patch_code == lir_patch_none, "no patching handled here"); 660 __ movl(dest->as_register(), c->as_jint()); 661 break; 662 } 663 664 case T_LONG: { 665 assert(patch_code == lir_patch_none, "no patching handled here"); 666#ifdef _LP64 667 __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 668#else 669 __ movptr(dest->as_register_lo(), c->as_jint_lo()); 670 __ movptr(dest->as_register_hi(), c->as_jint_hi()); 671#endif // _LP64 672 break; 673 } 674 675 case T_OBJECT: { 676 if (patch_code != lir_patch_none) { 677 jobject2reg_with_patching(dest->as_register(), info); 678 } else { 679 __ movoop(dest->as_register(), c->as_jobject()); 680 } 681 break; 682 } 683 684 case T_FLOAT: { 685 if (dest->is_single_xmm()) { 686 if (c->is_zero_float()) { 687 __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 688 } else { 689 __ movflt(dest->as_xmm_float_reg(), 690 InternalAddress(float_constant(c->as_jfloat()))); 691 } 692 } else { 693 assert(dest->is_single_fpu(), "must be"); 694 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 695 if (c->is_zero_float()) { 696 __ fldz(); 697 } else if (c->is_one_float()) { 698 __ fld1(); 699 } else { 700 __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 701 } 702 } 703 break; 704 } 705 706 case T_DOUBLE: { 707 if (dest->is_double_xmm()) { 708 if (c->is_zero_double()) { 709 __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 710 } else { 711 __ movdbl(dest->as_xmm_double_reg(), 712 InternalAddress(double_constant(c->as_jdouble()))); 713 } 714 } else { 715 assert(dest->is_double_fpu(), "must be"); 716 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 717 if (c->is_zero_double()) { 718 __ fldz(); 719 } else if (c->is_one_double()) { 720 __ fld1(); 721 } else { 722 __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 723 } 724 } 725 break; 726 } 727 728 default: 729 ShouldNotReachHere(); 730 } 731} 732 733void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 734 assert(src->is_constant(), "should not call otherwise"); 735 assert(dest->is_stack(), "should not call otherwise"); 736 LIR_Const* c = src->as_constant_ptr(); 737 738 switch (c->type()) { 739 case T_INT: // fall through 740 case T_FLOAT: 741 __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 742 break; 743 744 case T_OBJECT: 745 __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 746 break; 747 748 case T_LONG: // fall through 749 case T_DOUBLE: 750#ifdef _LP64 751 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 752 lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 753#else 754 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 755 lo_word_offset_in_bytes), c->as_jint_lo_bits()); 756 __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 757 hi_word_offset_in_bytes), c->as_jint_hi_bits()); 758#endif // _LP64 759 break; 760 761 default: 762 ShouldNotReachHere(); 763 } 764} 765 766void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { 767 assert(src->is_constant(), "should not call otherwise"); 768 assert(dest->is_address(), "should not call otherwise"); 769 LIR_Const* c = src->as_constant_ptr(); 770 LIR_Address* addr = dest->as_address_ptr(); 771 772 int null_check_here = code_offset(); 773 switch (type) { 774 case T_INT: // fall through 775 case T_FLOAT: 776 __ movl(as_Address(addr), c->as_jint_bits()); 777 break; 778 779 case T_OBJECT: // fall through 780 case T_ARRAY: 781 if (c->as_jobject() == NULL) { 782 __ movptr(as_Address(addr), (int32_t)NULL_WORD); 783 } else { 784 if (is_literal_address(addr)) { 785 ShouldNotReachHere(); 786 __ movoop(as_Address(addr, noreg), c->as_jobject()); 787 } else { 788 __ movoop(as_Address(addr), c->as_jobject()); 789 } 790 } 791 break; 792 793 case T_LONG: // fall through 794 case T_DOUBLE: 795#ifdef _LP64 796 if (is_literal_address(addr)) { 797 ShouldNotReachHere(); 798 __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 799 } else { 800 __ movptr(r10, (intptr_t)c->as_jlong_bits()); 801 null_check_here = code_offset(); 802 __ movptr(as_Address_lo(addr), r10); 803 } 804#else 805 // Always reachable in 32bit so this doesn't produce useless move literal 806 __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 807 __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 808#endif // _LP64 809 break; 810 811 case T_BOOLEAN: // fall through 812 case T_BYTE: 813 __ movb(as_Address(addr), c->as_jint() & 0xFF); 814 break; 815 816 case T_CHAR: // fall through 817 case T_SHORT: 818 __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 819 break; 820 821 default: 822 ShouldNotReachHere(); 823 }; 824 825 if (info != NULL) { 826 add_debug_info_for_null_check(null_check_here, info); 827 } 828} 829 830 831void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 832 assert(src->is_register(), "should not call otherwise"); 833 assert(dest->is_register(), "should not call otherwise"); 834 835 // move between cpu-registers 836 if (dest->is_single_cpu()) { 837#ifdef _LP64 838 if (src->type() == T_LONG) { 839 // Can do LONG -> OBJECT 840 move_regs(src->as_register_lo(), dest->as_register()); 841 return; 842 } 843#endif 844 assert(src->is_single_cpu(), "must match"); 845 if (src->type() == T_OBJECT) { 846 __ verify_oop(src->as_register()); 847 } 848 move_regs(src->as_register(), dest->as_register()); 849 850 } else if (dest->is_double_cpu()) { 851#ifdef _LP64 852 if (src->type() == T_OBJECT || src->type() == T_ARRAY) { 853 // Surprising to me but we can see move of a long to t_object 854 __ verify_oop(src->as_register()); 855 move_regs(src->as_register(), dest->as_register_lo()); 856 return; 857 } 858#endif 859 assert(src->is_double_cpu(), "must match"); 860 Register f_lo = src->as_register_lo(); 861 Register f_hi = src->as_register_hi(); 862 Register t_lo = dest->as_register_lo(); 863 Register t_hi = dest->as_register_hi(); 864#ifdef _LP64 865 assert(f_hi == f_lo, "must be same"); 866 assert(t_hi == t_lo, "must be same"); 867 move_regs(f_lo, t_lo); 868#else 869 assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 870 871 872 if (f_lo == t_hi && f_hi == t_lo) { 873 swap_reg(f_lo, f_hi); 874 } else if (f_hi == t_lo) { 875 assert(f_lo != t_hi, "overwriting register"); 876 move_regs(f_hi, t_hi); 877 move_regs(f_lo, t_lo); 878 } else { 879 assert(f_hi != t_lo, "overwriting register"); 880 move_regs(f_lo, t_lo); 881 move_regs(f_hi, t_hi); 882 } 883#endif // LP64 884 885 // special moves from fpu-register to xmm-register 886 // necessary for method results 887 } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 888 __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 889 __ fld_s(Address(rsp, 0)); 890 } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 891 __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 892 __ fld_d(Address(rsp, 0)); 893 } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 894 __ fstp_s(Address(rsp, 0)); 895 __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 896 } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 897 __ fstp_d(Address(rsp, 0)); 898 __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 899 900 // move between xmm-registers 901 } else if (dest->is_single_xmm()) { 902 assert(src->is_single_xmm(), "must match"); 903 __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 904 } else if (dest->is_double_xmm()) { 905 assert(src->is_double_xmm(), "must match"); 906 __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 907 908 // move between fpu-registers (no instruction necessary because of fpu-stack) 909 } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 910 assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 911 assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 912 } else { 913 ShouldNotReachHere(); 914 } 915} 916 917void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 918 assert(src->is_register(), "should not call otherwise"); 919 assert(dest->is_stack(), "should not call otherwise"); 920 921 if (src->is_single_cpu()) { 922 Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 923 if (type == T_OBJECT || type == T_ARRAY) { 924 __ verify_oop(src->as_register()); 925 __ movptr (dst, src->as_register()); 926 } else { 927 __ movl (dst, src->as_register()); 928 } 929 930 } else if (src->is_double_cpu()) { 931 Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 932 Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 933 __ movptr (dstLO, src->as_register_lo()); 934 NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 935 936 } else if (src->is_single_xmm()) { 937 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 938 __ movflt(dst_addr, src->as_xmm_float_reg()); 939 940 } else if (src->is_double_xmm()) { 941 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 942 __ movdbl(dst_addr, src->as_xmm_double_reg()); 943 944 } else if (src->is_single_fpu()) { 945 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 946 Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 947 if (pop_fpu_stack) __ fstp_s (dst_addr); 948 else __ fst_s (dst_addr); 949 950 } else if (src->is_double_fpu()) { 951 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 952 Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 953 if (pop_fpu_stack) __ fstp_d (dst_addr); 954 else __ fst_d (dst_addr); 955 956 } else { 957 ShouldNotReachHere(); 958 } 959} 960 961 962void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool /* unaligned */) { 963 LIR_Address* to_addr = dest->as_address_ptr(); 964 PatchingStub* patch = NULL; 965 966 if (type == T_ARRAY || type == T_OBJECT) { 967 __ verify_oop(src->as_register()); 968 } 969 if (patch_code != lir_patch_none) { 970 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 971 Address toa = as_Address(to_addr); 972 assert(toa.disp() != 0, "must have"); 973 } 974 if (info != NULL) { 975 add_debug_info_for_null_check_here(info); 976 } 977 978 switch (type) { 979 case T_FLOAT: { 980 if (src->is_single_xmm()) { 981 __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 982 } else { 983 assert(src->is_single_fpu(), "must be"); 984 assert(src->fpu_regnr() == 0, "argument must be on TOS"); 985 if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 986 else __ fst_s (as_Address(to_addr)); 987 } 988 break; 989 } 990 991 case T_DOUBLE: { 992 if (src->is_double_xmm()) { 993 __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 994 } else { 995 assert(src->is_double_fpu(), "must be"); 996 assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 997 if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 998 else __ fst_d (as_Address(to_addr)); 999 } 1000 break; 1001 } 1002 1003 case T_ADDRESS: // fall through 1004 case T_ARRAY: // fall through 1005 case T_OBJECT: // fall through 1006#ifdef _LP64 1007 __ movptr(as_Address(to_addr), src->as_register()); 1008 break; 1009#endif // _LP64 1010 case T_INT: 1011 __ movl(as_Address(to_addr), src->as_register()); 1012 break; 1013 1014 case T_LONG: { 1015 Register from_lo = src->as_register_lo(); 1016 Register from_hi = src->as_register_hi(); 1017#ifdef _LP64 1018 __ movptr(as_Address_lo(to_addr), from_lo); 1019#else 1020 Register base = to_addr->base()->as_register(); 1021 Register index = noreg; 1022 if (to_addr->index()->is_register()) { 1023 index = to_addr->index()->as_register(); 1024 } 1025 if (base == from_lo || index == from_lo) { 1026 assert(base != from_hi, "can't be"); 1027 assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1028 __ movl(as_Address_hi(to_addr), from_hi); 1029 if (patch != NULL) { 1030 patching_epilog(patch, lir_patch_high, base, info); 1031 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1032 patch_code = lir_patch_low; 1033 } 1034 __ movl(as_Address_lo(to_addr), from_lo); 1035 } else { 1036 assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1037 __ movl(as_Address_lo(to_addr), from_lo); 1038 if (patch != NULL) { 1039 patching_epilog(patch, lir_patch_low, base, info); 1040 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1041 patch_code = lir_patch_high; 1042 } 1043 __ movl(as_Address_hi(to_addr), from_hi); 1044 } 1045#endif // _LP64 1046 break; 1047 } 1048 1049 case T_BYTE: // fall through 1050 case T_BOOLEAN: { 1051 Register src_reg = src->as_register(); 1052 Address dst_addr = as_Address(to_addr); 1053 assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1054 __ movb(dst_addr, src_reg); 1055 break; 1056 } 1057 1058 case T_CHAR: // fall through 1059 case T_SHORT: 1060 __ movw(as_Address(to_addr), src->as_register()); 1061 break; 1062 1063 default: 1064 ShouldNotReachHere(); 1065 } 1066 1067 if (patch_code != lir_patch_none) { 1068 patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 1069 } 1070} 1071 1072 1073void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1074 assert(src->is_stack(), "should not call otherwise"); 1075 assert(dest->is_register(), "should not call otherwise"); 1076 1077 if (dest->is_single_cpu()) { 1078 if (type == T_ARRAY || type == T_OBJECT) { 1079 __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1080 __ verify_oop(dest->as_register()); 1081 } else { 1082 __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 1083 } 1084 1085 } else if (dest->is_double_cpu()) { 1086 Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 1087 Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 1088 __ movptr(dest->as_register_lo(), src_addr_LO); 1089 NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 1090 1091 } else if (dest->is_single_xmm()) { 1092 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1093 __ movflt(dest->as_xmm_float_reg(), src_addr); 1094 1095 } else if (dest->is_double_xmm()) { 1096 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1097 __ movdbl(dest->as_xmm_double_reg(), src_addr); 1098 1099 } else if (dest->is_single_fpu()) { 1100 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1101 Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 1102 __ fld_s(src_addr); 1103 1104 } else if (dest->is_double_fpu()) { 1105 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1106 Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 1107 __ fld_d(src_addr); 1108 1109 } else { 1110 ShouldNotReachHere(); 1111 } 1112} 1113 1114 1115void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1116 if (src->is_single_stack()) { 1117 if (type == T_OBJECT || type == T_ARRAY) { 1118 __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1119 __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1120 } else { 1121 __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1122 __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1123 } 1124 1125 } else if (src->is_double_stack()) { 1126#ifdef _LP64 1127 __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1128 __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1129#else 1130 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1131 // push and pop the part at src + wordSize, adding wordSize for the previous push 1132 __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), wordSize)); 1133 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), wordSize)); 1134 __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1135#endif // _LP64 1136 1137 } else { 1138 ShouldNotReachHere(); 1139 } 1140} 1141 1142 1143void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool /* unaligned */) { 1144 assert(src->is_address(), "should not call otherwise"); 1145 assert(dest->is_register(), "should not call otherwise"); 1146 1147 LIR_Address* addr = src->as_address_ptr(); 1148 Address from_addr = as_Address(addr); 1149 1150 switch (type) { 1151 case T_BOOLEAN: // fall through 1152 case T_BYTE: // fall through 1153 case T_CHAR: // fall through 1154 case T_SHORT: 1155 if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 1156 // on pre P6 processors we may get partial register stalls 1157 // so blow away the value of to_rinfo before loading a 1158 // partial word into it. Do it here so that it precedes 1159 // the potential patch point below. 1160 __ xorptr(dest->as_register(), dest->as_register()); 1161 } 1162 break; 1163 } 1164 1165 PatchingStub* patch = NULL; 1166 if (patch_code != lir_patch_none) { 1167 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1168 assert(from_addr.disp() != 0, "must have"); 1169 } 1170 if (info != NULL) { 1171 add_debug_info_for_null_check_here(info); 1172 } 1173 1174 switch (type) { 1175 case T_FLOAT: { 1176 if (dest->is_single_xmm()) { 1177 __ movflt(dest->as_xmm_float_reg(), from_addr); 1178 } else { 1179 assert(dest->is_single_fpu(), "must be"); 1180 assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1181 __ fld_s(from_addr); 1182 } 1183 break; 1184 } 1185 1186 case T_DOUBLE: { 1187 if (dest->is_double_xmm()) { 1188 __ movdbl(dest->as_xmm_double_reg(), from_addr); 1189 } else { 1190 assert(dest->is_double_fpu(), "must be"); 1191 assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1192 __ fld_d(from_addr); 1193 } 1194 break; 1195 } 1196 1197 case T_ADDRESS: // fall through 1198 case T_OBJECT: // fall through 1199 case T_ARRAY: // fall through 1200#ifdef _LP64 1201 __ movptr(dest->as_register(), from_addr); 1202 break; 1203#endif // _L64 1204 case T_INT: 1205 // %%% could this be a movl? this is safer but longer instruction 1206 __ movl2ptr(dest->as_register(), from_addr); 1207 break; 1208 1209 case T_LONG: { 1210 Register to_lo = dest->as_register_lo(); 1211 Register to_hi = dest->as_register_hi(); 1212#ifdef _LP64 1213 __ movptr(to_lo, as_Address_lo(addr)); 1214#else 1215 Register base = addr->base()->as_register(); 1216 Register index = noreg; 1217 if (addr->index()->is_register()) { 1218 index = addr->index()->as_register(); 1219 } 1220 if ((base == to_lo && index == to_hi) || 1221 (base == to_hi && index == to_lo)) { 1222 // addresses with 2 registers are only formed as a result of 1223 // array access so this code will never have to deal with 1224 // patches or null checks. 1225 assert(info == NULL && patch == NULL, "must be"); 1226 __ lea(to_hi, as_Address(addr)); 1227 __ movl(to_lo, Address(to_hi, 0)); 1228 __ movl(to_hi, Address(to_hi, BytesPerWord)); 1229 } else if (base == to_lo || index == to_lo) { 1230 assert(base != to_hi, "can't be"); 1231 assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1232 __ movl(to_hi, as_Address_hi(addr)); 1233 if (patch != NULL) { 1234 patching_epilog(patch, lir_patch_high, base, info); 1235 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1236 patch_code = lir_patch_low; 1237 } 1238 __ movl(to_lo, as_Address_lo(addr)); 1239 } else { 1240 assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1241 __ movl(to_lo, as_Address_lo(addr)); 1242 if (patch != NULL) { 1243 patching_epilog(patch, lir_patch_low, base, info); 1244 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1245 patch_code = lir_patch_high; 1246 } 1247 __ movl(to_hi, as_Address_hi(addr)); 1248 } 1249#endif // _LP64 1250 break; 1251 } 1252 1253 case T_BOOLEAN: // fall through 1254 case T_BYTE: { 1255 Register dest_reg = dest->as_register(); 1256 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1257 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1258 __ movsbl(dest_reg, from_addr); 1259 } else { 1260 __ movb(dest_reg, from_addr); 1261 __ shll(dest_reg, 24); 1262 __ sarl(dest_reg, 24); 1263 } 1264 // These are unsigned so the zero extension on 64bit is just what we need 1265 break; 1266 } 1267 1268 case T_CHAR: { 1269 Register dest_reg = dest->as_register(); 1270 assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1271 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1272 __ movzwl(dest_reg, from_addr); 1273 } else { 1274 __ movw(dest_reg, from_addr); 1275 } 1276 // This is unsigned so the zero extension on 64bit is just what we need 1277 // __ movl2ptr(dest_reg, dest_reg); 1278 break; 1279 } 1280 1281 case T_SHORT: { 1282 Register dest_reg = dest->as_register(); 1283 if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 1284 __ movswl(dest_reg, from_addr); 1285 } else { 1286 __ movw(dest_reg, from_addr); 1287 __ shll(dest_reg, 16); 1288 __ sarl(dest_reg, 16); 1289 } 1290 // Might not be needed in 64bit but certainly doesn't hurt (except for code size) 1291 __ movl2ptr(dest_reg, dest_reg); 1292 break; 1293 } 1294 1295 default: 1296 ShouldNotReachHere(); 1297 } 1298 1299 if (patch != NULL) { 1300 patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1301 } 1302 1303 if (type == T_ARRAY || type == T_OBJECT) { 1304 __ verify_oop(dest->as_register()); 1305 } 1306} 1307 1308 1309void LIR_Assembler::prefetchr(LIR_Opr src) { 1310 LIR_Address* addr = src->as_address_ptr(); 1311 Address from_addr = as_Address(addr); 1312 1313 if (VM_Version::supports_sse()) { 1314 switch (ReadPrefetchInstr) { 1315 case 0: 1316 __ prefetchnta(from_addr); break; 1317 case 1: 1318 __ prefetcht0(from_addr); break; 1319 case 2: 1320 __ prefetcht2(from_addr); break; 1321 default: 1322 ShouldNotReachHere(); break; 1323 } 1324 } else if (VM_Version::supports_3dnow()) { 1325 __ prefetchr(from_addr); 1326 } 1327} 1328 1329 1330void LIR_Assembler::prefetchw(LIR_Opr src) { 1331 LIR_Address* addr = src->as_address_ptr(); 1332 Address from_addr = as_Address(addr); 1333 1334 if (VM_Version::supports_sse()) { 1335 switch (AllocatePrefetchInstr) { 1336 case 0: 1337 __ prefetchnta(from_addr); break; 1338 case 1: 1339 __ prefetcht0(from_addr); break; 1340 case 2: 1341 __ prefetcht2(from_addr); break; 1342 case 3: 1343 __ prefetchw(from_addr); break; 1344 default: 1345 ShouldNotReachHere(); break; 1346 } 1347 } else if (VM_Version::supports_3dnow()) { 1348 __ prefetchw(from_addr); 1349 } 1350} 1351 1352 1353NEEDS_CLEANUP; // This could be static? 1354Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 1355 int elem_size = type2aelembytes(type); 1356 switch (elem_size) { 1357 case 1: return Address::times_1; 1358 case 2: return Address::times_2; 1359 case 4: return Address::times_4; 1360 case 8: return Address::times_8; 1361 } 1362 ShouldNotReachHere(); 1363 return Address::no_scale; 1364} 1365 1366 1367void LIR_Assembler::emit_op3(LIR_Op3* op) { 1368 switch (op->code()) { 1369 case lir_idiv: 1370 case lir_irem: 1371 arithmetic_idiv(op->code(), 1372 op->in_opr1(), 1373 op->in_opr2(), 1374 op->in_opr3(), 1375 op->result_opr(), 1376 op->info()); 1377 break; 1378 default: ShouldNotReachHere(); break; 1379 } 1380} 1381 1382void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1383#ifdef ASSERT 1384 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1385 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1386 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1387#endif 1388 1389 if (op->cond() == lir_cond_always) { 1390 if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1391 __ jmp (*(op->label())); 1392 } else { 1393 Assembler::Condition acond = Assembler::zero; 1394 if (op->code() == lir_cond_float_branch) { 1395 assert(op->ublock() != NULL, "must have unordered successor"); 1396 __ jcc(Assembler::parity, *(op->ublock()->label())); 1397 switch(op->cond()) { 1398 case lir_cond_equal: acond = Assembler::equal; break; 1399 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1400 case lir_cond_less: acond = Assembler::below; break; 1401 case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 1402 case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 1403 case lir_cond_greater: acond = Assembler::above; break; 1404 default: ShouldNotReachHere(); 1405 } 1406 } else { 1407 switch (op->cond()) { 1408 case lir_cond_equal: acond = Assembler::equal; break; 1409 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1410 case lir_cond_less: acond = Assembler::less; break; 1411 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1412 case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 1413 case lir_cond_greater: acond = Assembler::greater; break; 1414 case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 1415 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 1416 default: ShouldNotReachHere(); 1417 } 1418 } 1419 __ jcc(acond,*(op->label())); 1420 } 1421} 1422 1423void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 1424 LIR_Opr src = op->in_opr(); 1425 LIR_Opr dest = op->result_opr(); 1426 1427 switch (op->bytecode()) { 1428 case Bytecodes::_i2l: 1429#ifdef _LP64 1430 __ movl2ptr(dest->as_register_lo(), src->as_register()); 1431#else 1432 move_regs(src->as_register(), dest->as_register_lo()); 1433 move_regs(src->as_register(), dest->as_register_hi()); 1434 __ sarl(dest->as_register_hi(), 31); 1435#endif // LP64 1436 break; 1437 1438 case Bytecodes::_l2i: 1439 move_regs(src->as_register_lo(), dest->as_register()); 1440 break; 1441 1442 case Bytecodes::_i2b: 1443 move_regs(src->as_register(), dest->as_register()); 1444 __ sign_extend_byte(dest->as_register()); 1445 break; 1446 1447 case Bytecodes::_i2c: 1448 move_regs(src->as_register(), dest->as_register()); 1449 __ andl(dest->as_register(), 0xFFFF); 1450 break; 1451 1452 case Bytecodes::_i2s: 1453 move_regs(src->as_register(), dest->as_register()); 1454 __ sign_extend_short(dest->as_register()); 1455 break; 1456 1457 1458 case Bytecodes::_f2d: 1459 case Bytecodes::_d2f: 1460 if (dest->is_single_xmm()) { 1461 __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 1462 } else if (dest->is_double_xmm()) { 1463 __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1464 } else { 1465 assert(src->fpu() == dest->fpu(), "register must be equal"); 1466 // do nothing (float result is rounded later through spilling) 1467 } 1468 break; 1469 1470 case Bytecodes::_i2f: 1471 case Bytecodes::_i2d: 1472 if (dest->is_single_xmm()) { 1473 __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 1474 } else if (dest->is_double_xmm()) { 1475 __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 1476 } else { 1477 assert(dest->fpu() == 0, "result must be on TOS"); 1478 __ movl(Address(rsp, 0), src->as_register()); 1479 __ fild_s(Address(rsp, 0)); 1480 } 1481 break; 1482 1483 case Bytecodes::_f2i: 1484 case Bytecodes::_d2i: 1485 if (src->is_single_xmm()) { 1486 __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 1487 } else if (src->is_double_xmm()) { 1488 __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 1489 } else { 1490 assert(src->fpu() == 0, "input must be on TOS"); 1491 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 1492 __ fist_s(Address(rsp, 0)); 1493 __ movl(dest->as_register(), Address(rsp, 0)); 1494 __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 1495 } 1496 1497 // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 1498 assert(op->stub() != NULL, "stub required"); 1499 __ cmpl(dest->as_register(), 0x80000000); 1500 __ jcc(Assembler::equal, *op->stub()->entry()); 1501 __ bind(*op->stub()->continuation()); 1502 break; 1503 1504 case Bytecodes::_l2f: 1505 case Bytecodes::_l2d: 1506 assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 1507 assert(dest->fpu() == 0, "result must be on TOS"); 1508 1509 __ movptr(Address(rsp, 0), src->as_register_lo()); 1510 NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 1511 __ fild_d(Address(rsp, 0)); 1512 // float result is rounded later through spilling 1513 break; 1514 1515 case Bytecodes::_f2l: 1516 case Bytecodes::_d2l: 1517 assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 1518 assert(src->fpu() == 0, "input must be on TOS"); 1519 assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 1520 1521 // instruction sequence too long to inline it here 1522 { 1523 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 1524 } 1525 break; 1526 1527 default: ShouldNotReachHere(); 1528 } 1529} 1530 1531void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 1532 if (op->init_check()) { 1533 __ cmpl(Address(op->klass()->as_register(), 1534 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc)), 1535 instanceKlass::fully_initialized); 1536 add_debug_info_for_null_check_here(op->stub()->info()); 1537 __ jcc(Assembler::notEqual, *op->stub()->entry()); 1538 } 1539 __ allocate_object(op->obj()->as_register(), 1540 op->tmp1()->as_register(), 1541 op->tmp2()->as_register(), 1542 op->header_size(), 1543 op->object_size(), 1544 op->klass()->as_register(), 1545 *op->stub()->entry()); 1546 __ bind(*op->stub()->continuation()); 1547} 1548 1549void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1550 if (UseSlowPath || 1551 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1552 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 1553 __ jmp(*op->stub()->entry()); 1554 } else { 1555 Register len = op->len()->as_register(); 1556 Register tmp1 = op->tmp1()->as_register(); 1557 Register tmp2 = op->tmp2()->as_register(); 1558 Register tmp3 = op->tmp3()->as_register(); 1559 if (len == tmp1) { 1560 tmp1 = tmp3; 1561 } else if (len == tmp2) { 1562 tmp2 = tmp3; 1563 } else if (len == tmp3) { 1564 // everything is ok 1565 } else { 1566 __ mov(tmp3, len); 1567 } 1568 __ allocate_array(op->obj()->as_register(), 1569 len, 1570 tmp1, 1571 tmp2, 1572 arrayOopDesc::header_size(op->type()), 1573 array_element_size(op->type()), 1574 op->klass()->as_register(), 1575 *op->stub()->entry()); 1576 } 1577 __ bind(*op->stub()->continuation()); 1578} 1579 1580 1581 1582void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1583 LIR_Code code = op->code(); 1584 if (code == lir_store_check) { 1585 Register value = op->object()->as_register(); 1586 Register array = op->array()->as_register(); 1587 Register k_RInfo = op->tmp1()->as_register(); 1588 Register klass_RInfo = op->tmp2()->as_register(); 1589 Register Rtmp1 = op->tmp3()->as_register(); 1590 1591 CodeStub* stub = op->stub(); 1592 Label done; 1593 __ cmpptr(value, (int32_t)NULL_WORD); 1594 __ jcc(Assembler::equal, done); 1595 add_debug_info_for_null_check_here(op->info_for_exception()); 1596 __ movptr(k_RInfo, Address(array, oopDesc::klass_offset_in_bytes())); 1597 __ movptr(klass_RInfo, Address(value, oopDesc::klass_offset_in_bytes())); 1598 1599 // get instance klass 1600 __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc))); 1601 // get super_check_offset 1602 __ movl(Rtmp1, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes())); 1603 // See if we get an immediate positive hit 1604 __ cmpptr(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1)); 1605 __ jcc(Assembler::equal, done); 1606 // check for immediate negative hit 1607 __ cmpl(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()); 1608 __ jcc(Assembler::notEqual, *stub->entry()); 1609 // check for self 1610 __ cmpptr(klass_RInfo, k_RInfo); 1611 __ jcc(Assembler::equal, done); 1612 1613 __ push(klass_RInfo); 1614 __ push(k_RInfo); 1615 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1616 __ pop(klass_RInfo); 1617 __ pop(k_RInfo); 1618 // result is a boolean 1619 __ cmpl(k_RInfo, 0); 1620 __ jcc(Assembler::equal, *stub->entry()); 1621 __ bind(done); 1622 } else if (op->code() == lir_checkcast) { 1623 // we always need a stub for the failure case. 1624 CodeStub* stub = op->stub(); 1625 Register obj = op->object()->as_register(); 1626 Register k_RInfo = op->tmp1()->as_register(); 1627 Register klass_RInfo = op->tmp2()->as_register(); 1628 Register dst = op->result_opr()->as_register(); 1629 ciKlass* k = op->klass(); 1630 Register Rtmp1 = noreg; 1631 1632 Label done; 1633 if (obj == k_RInfo) { 1634 k_RInfo = dst; 1635 } else if (obj == klass_RInfo) { 1636 klass_RInfo = dst; 1637 } 1638 if (k->is_loaded()) { 1639 select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1640 } else { 1641 Rtmp1 = op->tmp3()->as_register(); 1642 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1643 } 1644 1645 assert_different_registers(obj, k_RInfo, klass_RInfo); 1646 if (!k->is_loaded()) { 1647 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); 1648 } else { 1649#ifdef _LP64 1650 __ movoop(k_RInfo, k->encoding()); 1651#else 1652 k_RInfo = noreg; 1653#endif // _LP64 1654 } 1655 assert(obj != k_RInfo, "must be different"); 1656 __ cmpptr(obj, (int32_t)NULL_WORD); 1657 if (op->profiled_method() != NULL) { 1658 ciMethod* method = op->profiled_method(); 1659 int bci = op->profiled_bci(); 1660 1661 Label profile_done; 1662 __ jcc(Assembler::notEqual, profile_done); 1663 // Object is null; update methodDataOop 1664 ciMethodData* md = method->method_data(); 1665 if (md == NULL) { 1666 bailout("out of memory building methodDataOop"); 1667 return; 1668 } 1669 ciProfileData* data = md->bci_to_data(bci); 1670 assert(data != NULL, "need data for checkcast"); 1671 assert(data->is_BitData(), "need BitData for checkcast"); 1672 Register mdo = klass_RInfo; 1673 __ movoop(mdo, md->encoding()); 1674 Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1675 int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1676 __ orl(data_addr, header_bits); 1677 __ jmp(done); 1678 __ bind(profile_done); 1679 } else { 1680 __ jcc(Assembler::equal, done); 1681 } 1682 __ verify_oop(obj); 1683 1684 if (op->fast_check()) { 1685 // get object classo 1686 // not a safepoint as obj null check happens earlier 1687 if (k->is_loaded()) { 1688#ifdef _LP64 1689 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1690#else 1691 __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->encoding()); 1692#endif // _LP64 1693 } else { 1694 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1695 1696 } 1697 __ jcc(Assembler::notEqual, *stub->entry()); 1698 __ bind(done); 1699 } else { 1700 // get object class 1701 // not a safepoint as obj null check happens earlier 1702 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1703 if (k->is_loaded()) { 1704 // See if we get an immediate positive hit 1705#ifdef _LP64 1706 __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 1707#else 1708 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->encoding()); 1709#endif // _LP64 1710 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { 1711 __ jcc(Assembler::notEqual, *stub->entry()); 1712 } else { 1713 // See if we get an immediate positive hit 1714 __ jcc(Assembler::equal, done); 1715 // check for self 1716#ifdef _LP64 1717 __ cmpptr(klass_RInfo, k_RInfo); 1718#else 1719 __ cmpoop(klass_RInfo, k->encoding()); 1720#endif // _LP64 1721 __ jcc(Assembler::equal, done); 1722 1723 __ push(klass_RInfo); 1724#ifdef _LP64 1725 __ push(k_RInfo); 1726#else 1727 __ pushoop(k->encoding()); 1728#endif // _LP64 1729 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1730 __ pop(klass_RInfo); 1731 __ pop(klass_RInfo); 1732 // result is a boolean 1733 __ cmpl(klass_RInfo, 0); 1734 __ jcc(Assembler::equal, *stub->entry()); 1735 } 1736 __ bind(done); 1737 } else { 1738 __ movl(Rtmp1, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes())); 1739 // See if we get an immediate positive hit 1740 __ cmpptr(k_RInfo, Address(klass_RInfo, Rtmp1, Address::times_1)); 1741 __ jcc(Assembler::equal, done); 1742 // check for immediate negative hit 1743 __ cmpl(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()); 1744 __ jcc(Assembler::notEqual, *stub->entry()); 1745 // check for self 1746 __ cmpptr(klass_RInfo, k_RInfo); 1747 __ jcc(Assembler::equal, done); 1748 1749 __ push(klass_RInfo); 1750 __ push(k_RInfo); 1751 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1752 __ pop(klass_RInfo); 1753 __ pop(k_RInfo); 1754 // result is a boolean 1755 __ cmpl(k_RInfo, 0); 1756 __ jcc(Assembler::equal, *stub->entry()); 1757 __ bind(done); 1758 } 1759 1760 } 1761 if (dst != obj) { 1762 __ mov(dst, obj); 1763 } 1764 } else if (code == lir_instanceof) { 1765 Register obj = op->object()->as_register(); 1766 Register k_RInfo = op->tmp1()->as_register(); 1767 Register klass_RInfo = op->tmp2()->as_register(); 1768 Register dst = op->result_opr()->as_register(); 1769 ciKlass* k = op->klass(); 1770 1771 Label done; 1772 Label zero; 1773 Label one; 1774 if (obj == k_RInfo) { 1775 k_RInfo = klass_RInfo; 1776 klass_RInfo = obj; 1777 } 1778 // patching may screw with our temporaries on sparc, 1779 // so let's do it before loading the class 1780 if (!k->is_loaded()) { 1781 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); 1782 } else { 1783 LP64_ONLY(__ movoop(k_RInfo, k->encoding())); 1784 } 1785 assert(obj != k_RInfo, "must be different"); 1786 1787 __ verify_oop(obj); 1788 if (op->fast_check()) { 1789 __ cmpptr(obj, (int32_t)NULL_WORD); 1790 __ jcc(Assembler::equal, zero); 1791 // get object class 1792 // not a safepoint as obj null check happens earlier 1793 if (LP64_ONLY(false &&) k->is_loaded()) { 1794 NOT_LP64(__ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->encoding())); 1795 k_RInfo = noreg; 1796 } else { 1797 __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1798 1799 } 1800 __ jcc(Assembler::equal, one); 1801 } else { 1802 // get object class 1803 // not a safepoint as obj null check happens earlier 1804 __ cmpptr(obj, (int32_t)NULL_WORD); 1805 __ jcc(Assembler::equal, zero); 1806 __ movptr(klass_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1807 1808#ifndef _LP64 1809 if (k->is_loaded()) { 1810 // See if we get an immediate positive hit 1811 __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->encoding()); 1812 __ jcc(Assembler::equal, one); 1813 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() == k->super_check_offset()) { 1814 // check for self 1815 __ cmpoop(klass_RInfo, k->encoding()); 1816 __ jcc(Assembler::equal, one); 1817 __ push(klass_RInfo); 1818 __ pushoop(k->encoding()); 1819 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1820 __ pop(klass_RInfo); 1821 __ pop(dst); 1822 __ jmp(done); 1823 } 1824 } else { 1825#else 1826 { // YUCK 1827#endif // LP64 1828 assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers"); 1829 1830 __ movl(dst, Address(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes())); 1831 // See if we get an immediate positive hit 1832 __ cmpptr(k_RInfo, Address(klass_RInfo, dst, Address::times_1)); 1833 __ jcc(Assembler::equal, one); 1834 // check for immediate negative hit 1835 __ cmpl(dst, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()); 1836 __ jcc(Assembler::notEqual, zero); 1837 // check for self 1838 __ cmpptr(klass_RInfo, k_RInfo); 1839 __ jcc(Assembler::equal, one); 1840 1841 __ push(klass_RInfo); 1842 __ push(k_RInfo); 1843 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1844 __ pop(klass_RInfo); 1845 __ pop(dst); 1846 __ jmp(done); 1847 } 1848 } 1849 __ bind(zero); 1850 __ xorptr(dst, dst); 1851 __ jmp(done); 1852 __ bind(one); 1853 __ movptr(dst, 1); 1854 __ bind(done); 1855 } else { 1856 ShouldNotReachHere(); 1857 } 1858 1859} 1860 1861 1862void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1863 if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1864 assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1865 assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1866 assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1867 assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1868 Register addr = op->addr()->as_register(); 1869 if (os::is_MP()) { 1870 __ lock(); 1871 } 1872 NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1873 1874 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1875 NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1876 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1877 Register newval = op->new_value()->as_register(); 1878 Register cmpval = op->cmp_value()->as_register(); 1879 assert(cmpval == rax, "wrong register"); 1880 assert(newval != NULL, "new val must be register"); 1881 assert(cmpval != newval, "cmp and new values must be in different registers"); 1882 assert(cmpval != addr, "cmp and addr must be in different registers"); 1883 assert(newval != addr, "new value and addr must be in different registers"); 1884 if (os::is_MP()) { 1885 __ lock(); 1886 } 1887 if ( op->code() == lir_cas_obj) { 1888 __ cmpxchgptr(newval, Address(addr, 0)); 1889 } else if (op->code() == lir_cas_int) { 1890 __ cmpxchgl(newval, Address(addr, 0)); 1891 } else { 1892 LP64_ONLY(__ cmpxchgq(newval, Address(addr, 0))); 1893 } 1894#ifdef _LP64 1895 } else if (op->code() == lir_cas_long) { 1896 Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1897 Register newval = op->new_value()->as_register_lo(); 1898 Register cmpval = op->cmp_value()->as_register_lo(); 1899 assert(cmpval == rax, "wrong register"); 1900 assert(newval != NULL, "new val must be register"); 1901 assert(cmpval != newval, "cmp and new values must be in different registers"); 1902 assert(cmpval != addr, "cmp and addr must be in different registers"); 1903 assert(newval != addr, "new value and addr must be in different registers"); 1904 if (os::is_MP()) { 1905 __ lock(); 1906 } 1907 __ cmpxchgq(newval, Address(addr, 0)); 1908#endif // _LP64 1909 } else { 1910 Unimplemented(); 1911 } 1912} 1913 1914 1915void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { 1916 Assembler::Condition acond, ncond; 1917 switch (condition) { 1918 case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1919 case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1920 case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1921 case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 1922 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 1923 case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 1924 case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 1925 case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 1926 default: ShouldNotReachHere(); 1927 } 1928 1929 if (opr1->is_cpu_register()) { 1930 reg2reg(opr1, result); 1931 } else if (opr1->is_stack()) { 1932 stack2reg(opr1, result, result->type()); 1933 } else if (opr1->is_constant()) { 1934 const2reg(opr1, result, lir_patch_none, NULL); 1935 } else { 1936 ShouldNotReachHere(); 1937 } 1938 1939 if (VM_Version::supports_cmov() && !opr2->is_constant()) { 1940 // optimized version that does not require a branch 1941 if (opr2->is_single_cpu()) { 1942 assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 1943 __ cmov(ncond, result->as_register(), opr2->as_register()); 1944 } else if (opr2->is_double_cpu()) { 1945 assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1946 assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 1947 __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 1948 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 1949 } else if (opr2->is_single_stack()) { 1950 __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 1951 } else if (opr2->is_double_stack()) { 1952 __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 1953 NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 1954 } else { 1955 ShouldNotReachHere(); 1956 } 1957 1958 } else { 1959 Label skip; 1960 __ jcc (acond, skip); 1961 if (opr2->is_cpu_register()) { 1962 reg2reg(opr2, result); 1963 } else if (opr2->is_stack()) { 1964 stack2reg(opr2, result, result->type()); 1965 } else if (opr2->is_constant()) { 1966 const2reg(opr2, result, lir_patch_none, NULL); 1967 } else { 1968 ShouldNotReachHere(); 1969 } 1970 __ bind(skip); 1971 } 1972} 1973 1974 1975void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 1976 assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 1977 1978 if (left->is_single_cpu()) { 1979 assert(left == dest, "left and dest must be equal"); 1980 Register lreg = left->as_register(); 1981 1982 if (right->is_single_cpu()) { 1983 // cpu register - cpu register 1984 Register rreg = right->as_register(); 1985 switch (code) { 1986 case lir_add: __ addl (lreg, rreg); break; 1987 case lir_sub: __ subl (lreg, rreg); break; 1988 case lir_mul: __ imull(lreg, rreg); break; 1989 default: ShouldNotReachHere(); 1990 } 1991 1992 } else if (right->is_stack()) { 1993 // cpu register - stack 1994 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 1995 switch (code) { 1996 case lir_add: __ addl(lreg, raddr); break; 1997 case lir_sub: __ subl(lreg, raddr); break; 1998 default: ShouldNotReachHere(); 1999 } 2000 2001 } else if (right->is_constant()) { 2002 // cpu register - constant 2003 jint c = right->as_constant_ptr()->as_jint(); 2004 switch (code) { 2005 case lir_add: { 2006 __ increment(lreg, c); 2007 break; 2008 } 2009 case lir_sub: { 2010 __ decrement(lreg, c); 2011 break; 2012 } 2013 default: ShouldNotReachHere(); 2014 } 2015 2016 } else { 2017 ShouldNotReachHere(); 2018 } 2019 2020 } else if (left->is_double_cpu()) { 2021 assert(left == dest, "left and dest must be equal"); 2022 Register lreg_lo = left->as_register_lo(); 2023 Register lreg_hi = left->as_register_hi(); 2024 2025 if (right->is_double_cpu()) { 2026 // cpu register - cpu register 2027 Register rreg_lo = right->as_register_lo(); 2028 Register rreg_hi = right->as_register_hi(); 2029 NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2030 LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2031 switch (code) { 2032 case lir_add: 2033 __ addptr(lreg_lo, rreg_lo); 2034 NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2035 break; 2036 case lir_sub: 2037 __ subptr(lreg_lo, rreg_lo); 2038 NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2039 break; 2040 case lir_mul: 2041#ifdef _LP64 2042 __ imulq(lreg_lo, rreg_lo); 2043#else 2044 assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2045 __ imull(lreg_hi, rreg_lo); 2046 __ imull(rreg_hi, lreg_lo); 2047 __ addl (rreg_hi, lreg_hi); 2048 __ mull (rreg_lo); 2049 __ addl (lreg_hi, rreg_hi); 2050#endif // _LP64 2051 break; 2052 default: 2053 ShouldNotReachHere(); 2054 } 2055 2056 } else if (right->is_constant()) { 2057 // cpu register - constant 2058#ifdef _LP64 2059 jlong c = right->as_constant_ptr()->as_jlong_bits(); 2060 __ movptr(r10, (intptr_t) c); 2061 switch (code) { 2062 case lir_add: 2063 __ addptr(lreg_lo, r10); 2064 break; 2065 case lir_sub: 2066 __ subptr(lreg_lo, r10); 2067 break; 2068 default: 2069 ShouldNotReachHere(); 2070 } 2071#else 2072 jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2073 jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2074 switch (code) { 2075 case lir_add: 2076 __ addptr(lreg_lo, c_lo); 2077 __ adcl(lreg_hi, c_hi); 2078 break; 2079 case lir_sub: 2080 __ subptr(lreg_lo, c_lo); 2081 __ sbbl(lreg_hi, c_hi); 2082 break; 2083 default: 2084 ShouldNotReachHere(); 2085 } 2086#endif // _LP64 2087 2088 } else { 2089 ShouldNotReachHere(); 2090 } 2091 2092 } else if (left->is_single_xmm()) { 2093 assert(left == dest, "left and dest must be equal"); 2094 XMMRegister lreg = left->as_xmm_float_reg(); 2095 2096 if (right->is_single_xmm()) { 2097 XMMRegister rreg = right->as_xmm_float_reg(); 2098 switch (code) { 2099 case lir_add: __ addss(lreg, rreg); break; 2100 case lir_sub: __ subss(lreg, rreg); break; 2101 case lir_mul_strictfp: // fall through 2102 case lir_mul: __ mulss(lreg, rreg); break; 2103 case lir_div_strictfp: // fall through 2104 case lir_div: __ divss(lreg, rreg); break; 2105 default: ShouldNotReachHere(); 2106 } 2107 } else { 2108 Address raddr; 2109 if (right->is_single_stack()) { 2110 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2111 } else if (right->is_constant()) { 2112 // hack for now 2113 raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2114 } else { 2115 ShouldNotReachHere(); 2116 } 2117 switch (code) { 2118 case lir_add: __ addss(lreg, raddr); break; 2119 case lir_sub: __ subss(lreg, raddr); break; 2120 case lir_mul_strictfp: // fall through 2121 case lir_mul: __ mulss(lreg, raddr); break; 2122 case lir_div_strictfp: // fall through 2123 case lir_div: __ divss(lreg, raddr); break; 2124 default: ShouldNotReachHere(); 2125 } 2126 } 2127 2128 } else if (left->is_double_xmm()) { 2129 assert(left == dest, "left and dest must be equal"); 2130 2131 XMMRegister lreg = left->as_xmm_double_reg(); 2132 if (right->is_double_xmm()) { 2133 XMMRegister rreg = right->as_xmm_double_reg(); 2134 switch (code) { 2135 case lir_add: __ addsd(lreg, rreg); break; 2136 case lir_sub: __ subsd(lreg, rreg); break; 2137 case lir_mul_strictfp: // fall through 2138 case lir_mul: __ mulsd(lreg, rreg); break; 2139 case lir_div_strictfp: // fall through 2140 case lir_div: __ divsd(lreg, rreg); break; 2141 default: ShouldNotReachHere(); 2142 } 2143 } else { 2144 Address raddr; 2145 if (right->is_double_stack()) { 2146 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2147 } else if (right->is_constant()) { 2148 // hack for now 2149 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2150 } else { 2151 ShouldNotReachHere(); 2152 } 2153 switch (code) { 2154 case lir_add: __ addsd(lreg, raddr); break; 2155 case lir_sub: __ subsd(lreg, raddr); break; 2156 case lir_mul_strictfp: // fall through 2157 case lir_mul: __ mulsd(lreg, raddr); break; 2158 case lir_div_strictfp: // fall through 2159 case lir_div: __ divsd(lreg, raddr); break; 2160 default: ShouldNotReachHere(); 2161 } 2162 } 2163 2164 } else if (left->is_single_fpu()) { 2165 assert(dest->is_single_fpu(), "fpu stack allocation required"); 2166 2167 if (right->is_single_fpu()) { 2168 arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2169 2170 } else { 2171 assert(left->fpu_regnr() == 0, "left must be on TOS"); 2172 assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2173 2174 Address raddr; 2175 if (right->is_single_stack()) { 2176 raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2177 } else if (right->is_constant()) { 2178 address const_addr = float_constant(right->as_jfloat()); 2179 assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2180 // hack for now 2181 raddr = __ as_Address(InternalAddress(const_addr)); 2182 } else { 2183 ShouldNotReachHere(); 2184 } 2185 2186 switch (code) { 2187 case lir_add: __ fadd_s(raddr); break; 2188 case lir_sub: __ fsub_s(raddr); break; 2189 case lir_mul_strictfp: // fall through 2190 case lir_mul: __ fmul_s(raddr); break; 2191 case lir_div_strictfp: // fall through 2192 case lir_div: __ fdiv_s(raddr); break; 2193 default: ShouldNotReachHere(); 2194 } 2195 } 2196 2197 } else if (left->is_double_fpu()) { 2198 assert(dest->is_double_fpu(), "fpu stack allocation required"); 2199 2200 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2201 // Double values require special handling for strictfp mul/div on x86 2202 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2203 __ fmulp(left->fpu_regnrLo() + 1); 2204 } 2205 2206 if (right->is_double_fpu()) { 2207 arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2208 2209 } else { 2210 assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2211 assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2212 2213 Address raddr; 2214 if (right->is_double_stack()) { 2215 raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2216 } else if (right->is_constant()) { 2217 // hack for now 2218 raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2219 } else { 2220 ShouldNotReachHere(); 2221 } 2222 2223 switch (code) { 2224 case lir_add: __ fadd_d(raddr); break; 2225 case lir_sub: __ fsub_d(raddr); break; 2226 case lir_mul_strictfp: // fall through 2227 case lir_mul: __ fmul_d(raddr); break; 2228 case lir_div_strictfp: // fall through 2229 case lir_div: __ fdiv_d(raddr); break; 2230 default: ShouldNotReachHere(); 2231 } 2232 } 2233 2234 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2235 // Double values require special handling for strictfp mul/div on x86 2236 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2237 __ fmulp(dest->fpu_regnrLo() + 1); 2238 } 2239 2240 } else if (left->is_single_stack() || left->is_address()) { 2241 assert(left == dest, "left and dest must be equal"); 2242 2243 Address laddr; 2244 if (left->is_single_stack()) { 2245 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2246 } else if (left->is_address()) { 2247 laddr = as_Address(left->as_address_ptr()); 2248 } else { 2249 ShouldNotReachHere(); 2250 } 2251 2252 if (right->is_single_cpu()) { 2253 Register rreg = right->as_register(); 2254 switch (code) { 2255 case lir_add: __ addl(laddr, rreg); break; 2256 case lir_sub: __ subl(laddr, rreg); break; 2257 default: ShouldNotReachHere(); 2258 } 2259 } else if (right->is_constant()) { 2260 jint c = right->as_constant_ptr()->as_jint(); 2261 switch (code) { 2262 case lir_add: { 2263 __ incrementl(laddr, c); 2264 break; 2265 } 2266 case lir_sub: { 2267 __ decrementl(laddr, c); 2268 break; 2269 } 2270 default: ShouldNotReachHere(); 2271 } 2272 } else { 2273 ShouldNotReachHere(); 2274 } 2275 2276 } else { 2277 ShouldNotReachHere(); 2278 } 2279} 2280 2281void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2282 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2283 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2284 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2285 2286 bool left_is_tos = (left_index == 0); 2287 bool dest_is_tos = (dest_index == 0); 2288 int non_tos_index = (left_is_tos ? right_index : left_index); 2289 2290 switch (code) { 2291 case lir_add: 2292 if (pop_fpu_stack) __ faddp(non_tos_index); 2293 else if (dest_is_tos) __ fadd (non_tos_index); 2294 else __ fadda(non_tos_index); 2295 break; 2296 2297 case lir_sub: 2298 if (left_is_tos) { 2299 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2300 else if (dest_is_tos) __ fsub (non_tos_index); 2301 else __ fsubra(non_tos_index); 2302 } else { 2303 if (pop_fpu_stack) __ fsubp (non_tos_index); 2304 else if (dest_is_tos) __ fsubr (non_tos_index); 2305 else __ fsuba (non_tos_index); 2306 } 2307 break; 2308 2309 case lir_mul_strictfp: // fall through 2310 case lir_mul: 2311 if (pop_fpu_stack) __ fmulp(non_tos_index); 2312 else if (dest_is_tos) __ fmul (non_tos_index); 2313 else __ fmula(non_tos_index); 2314 break; 2315 2316 case lir_div_strictfp: // fall through 2317 case lir_div: 2318 if (left_is_tos) { 2319 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2320 else if (dest_is_tos) __ fdiv (non_tos_index); 2321 else __ fdivra(non_tos_index); 2322 } else { 2323 if (pop_fpu_stack) __ fdivp (non_tos_index); 2324 else if (dest_is_tos) __ fdivr (non_tos_index); 2325 else __ fdiva (non_tos_index); 2326 } 2327 break; 2328 2329 case lir_rem: 2330 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2331 __ fremr(noreg); 2332 break; 2333 2334 default: 2335 ShouldNotReachHere(); 2336 } 2337} 2338 2339 2340void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 2341 if (value->is_double_xmm()) { 2342 switch(code) { 2343 case lir_abs : 2344 { 2345 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2346 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2347 } 2348 __ andpd(dest->as_xmm_double_reg(), 2349 ExternalAddress((address)double_signmask_pool)); 2350 } 2351 break; 2352 2353 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2354 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2355 default : ShouldNotReachHere(); 2356 } 2357 2358 } else if (value->is_double_fpu()) { 2359 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2360 switch(code) { 2361 case lir_log : __ flog() ; break; 2362 case lir_log10 : __ flog10() ; break; 2363 case lir_abs : __ fabs() ; break; 2364 case lir_sqrt : __ fsqrt(); break; 2365 case lir_sin : 2366 // Should consider not saving rbx, if not necessary 2367 __ trigfunc('s', op->as_Op2()->fpu_stack_size()); 2368 break; 2369 case lir_cos : 2370 // Should consider not saving rbx, if not necessary 2371 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); 2372 __ trigfunc('c', op->as_Op2()->fpu_stack_size()); 2373 break; 2374 case lir_tan : 2375 // Should consider not saving rbx, if not necessary 2376 __ trigfunc('t', op->as_Op2()->fpu_stack_size()); 2377 break; 2378 default : ShouldNotReachHere(); 2379 } 2380 } else { 2381 Unimplemented(); 2382 } 2383} 2384 2385void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2386 // assert(left->destroys_register(), "check"); 2387 if (left->is_single_cpu()) { 2388 Register reg = left->as_register(); 2389 if (right->is_constant()) { 2390 int val = right->as_constant_ptr()->as_jint(); 2391 switch (code) { 2392 case lir_logic_and: __ andl (reg, val); break; 2393 case lir_logic_or: __ orl (reg, val); break; 2394 case lir_logic_xor: __ xorl (reg, val); break; 2395 default: ShouldNotReachHere(); 2396 } 2397 } else if (right->is_stack()) { 2398 // added support for stack operands 2399 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2400 switch (code) { 2401 case lir_logic_and: __ andl (reg, raddr); break; 2402 case lir_logic_or: __ orl (reg, raddr); break; 2403 case lir_logic_xor: __ xorl (reg, raddr); break; 2404 default: ShouldNotReachHere(); 2405 } 2406 } else { 2407 Register rright = right->as_register(); 2408 switch (code) { 2409 case lir_logic_and: __ andptr (reg, rright); break; 2410 case lir_logic_or : __ orptr (reg, rright); break; 2411 case lir_logic_xor: __ xorptr (reg, rright); break; 2412 default: ShouldNotReachHere(); 2413 } 2414 } 2415 move_regs(reg, dst->as_register()); 2416 } else { 2417 Register l_lo = left->as_register_lo(); 2418 Register l_hi = left->as_register_hi(); 2419 if (right->is_constant()) { 2420#ifdef _LP64 2421 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2422 switch (code) { 2423 case lir_logic_and: 2424 __ andq(l_lo, rscratch1); 2425 break; 2426 case lir_logic_or: 2427 __ orq(l_lo, rscratch1); 2428 break; 2429 case lir_logic_xor: 2430 __ xorq(l_lo, rscratch1); 2431 break; 2432 default: ShouldNotReachHere(); 2433 } 2434#else 2435 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2436 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2437 switch (code) { 2438 case lir_logic_and: 2439 __ andl(l_lo, r_lo); 2440 __ andl(l_hi, r_hi); 2441 break; 2442 case lir_logic_or: 2443 __ orl(l_lo, r_lo); 2444 __ orl(l_hi, r_hi); 2445 break; 2446 case lir_logic_xor: 2447 __ xorl(l_lo, r_lo); 2448 __ xorl(l_hi, r_hi); 2449 break; 2450 default: ShouldNotReachHere(); 2451 } 2452#endif // _LP64 2453 } else { 2454 Register r_lo = right->as_register_lo(); 2455 Register r_hi = right->as_register_hi(); 2456 assert(l_lo != r_hi, "overwriting registers"); 2457 switch (code) { 2458 case lir_logic_and: 2459 __ andptr(l_lo, r_lo); 2460 NOT_LP64(__ andptr(l_hi, r_hi);) 2461 break; 2462 case lir_logic_or: 2463 __ orptr(l_lo, r_lo); 2464 NOT_LP64(__ orptr(l_hi, r_hi);) 2465 break; 2466 case lir_logic_xor: 2467 __ xorptr(l_lo, r_lo); 2468 NOT_LP64(__ xorptr(l_hi, r_hi);) 2469 break; 2470 default: ShouldNotReachHere(); 2471 } 2472 } 2473 2474 Register dst_lo = dst->as_register_lo(); 2475 Register dst_hi = dst->as_register_hi(); 2476 2477#ifdef _LP64 2478 move_regs(l_lo, dst_lo); 2479#else 2480 if (dst_lo == l_hi) { 2481 assert(dst_hi != l_lo, "overwriting registers"); 2482 move_regs(l_hi, dst_hi); 2483 move_regs(l_lo, dst_lo); 2484 } else { 2485 assert(dst_lo != l_hi, "overwriting registers"); 2486 move_regs(l_lo, dst_lo); 2487 move_regs(l_hi, dst_hi); 2488 } 2489#endif // _LP64 2490 } 2491} 2492 2493 2494// we assume that rax, and rdx can be overwritten 2495void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2496 2497 assert(left->is_single_cpu(), "left must be register"); 2498 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2499 assert(result->is_single_cpu(), "result must be register"); 2500 2501 // assert(left->destroys_register(), "check"); 2502 // assert(right->destroys_register(), "check"); 2503 2504 Register lreg = left->as_register(); 2505 Register dreg = result->as_register(); 2506 2507 if (right->is_constant()) { 2508 int divisor = right->as_constant_ptr()->as_jint(); 2509 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2510 if (code == lir_idiv) { 2511 assert(lreg == rax, "must be rax,"); 2512 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2513 __ cdql(); // sign extend into rdx:rax 2514 if (divisor == 2) { 2515 __ subl(lreg, rdx); 2516 } else { 2517 __ andl(rdx, divisor - 1); 2518 __ addl(lreg, rdx); 2519 } 2520 __ sarl(lreg, log2_intptr(divisor)); 2521 move_regs(lreg, dreg); 2522 } else if (code == lir_irem) { 2523 Label done; 2524 __ mov(dreg, lreg); 2525 __ andl(dreg, 0x80000000 | (divisor - 1)); 2526 __ jcc(Assembler::positive, done); 2527 __ decrement(dreg); 2528 __ orl(dreg, ~(divisor - 1)); 2529 __ increment(dreg); 2530 __ bind(done); 2531 } else { 2532 ShouldNotReachHere(); 2533 } 2534 } else { 2535 Register rreg = right->as_register(); 2536 assert(lreg == rax, "left register must be rax,"); 2537 assert(rreg != rdx, "right register must not be rdx"); 2538 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2539 2540 move_regs(lreg, rax); 2541 2542 int idivl_offset = __ corrected_idivl(rreg); 2543 add_debug_info_for_div0(idivl_offset, info); 2544 if (code == lir_irem) { 2545 move_regs(rdx, dreg); // result is in rdx 2546 } else { 2547 move_regs(rax, dreg); 2548 } 2549 } 2550} 2551 2552 2553void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2554 if (opr1->is_single_cpu()) { 2555 Register reg1 = opr1->as_register(); 2556 if (opr2->is_single_cpu()) { 2557 // cpu register - cpu register 2558 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2559 __ cmpptr(reg1, opr2->as_register()); 2560 } else { 2561 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); 2562 __ cmpl(reg1, opr2->as_register()); 2563 } 2564 } else if (opr2->is_stack()) { 2565 // cpu register - stack 2566 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2567 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2568 } else { 2569 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2570 } 2571 } else if (opr2->is_constant()) { 2572 // cpu register - constant 2573 LIR_Const* c = opr2->as_constant_ptr(); 2574 if (c->type() == T_INT) { 2575 __ cmpl(reg1, c->as_jint()); 2576 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2577 // In 64bit oops are single register 2578 jobject o = c->as_jobject(); 2579 if (o == NULL) { 2580 __ cmpptr(reg1, (int32_t)NULL_WORD); 2581 } else { 2582#ifdef _LP64 2583 __ movoop(rscratch1, o); 2584 __ cmpptr(reg1, rscratch1); 2585#else 2586 __ cmpoop(reg1, c->as_jobject()); 2587#endif // _LP64 2588 } 2589 } else { 2590 ShouldNotReachHere(); 2591 } 2592 // cpu register - address 2593 } else if (opr2->is_address()) { 2594 if (op->info() != NULL) { 2595 add_debug_info_for_null_check_here(op->info()); 2596 } 2597 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2598 } else { 2599 ShouldNotReachHere(); 2600 } 2601 2602 } else if(opr1->is_double_cpu()) { 2603 Register xlo = opr1->as_register_lo(); 2604 Register xhi = opr1->as_register_hi(); 2605 if (opr2->is_double_cpu()) { 2606#ifdef _LP64 2607 __ cmpptr(xlo, opr2->as_register_lo()); 2608#else 2609 // cpu register - cpu register 2610 Register ylo = opr2->as_register_lo(); 2611 Register yhi = opr2->as_register_hi(); 2612 __ subl(xlo, ylo); 2613 __ sbbl(xhi, yhi); 2614 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2615 __ orl(xhi, xlo); 2616 } 2617#endif // _LP64 2618 } else if (opr2->is_constant()) { 2619 // cpu register - constant 0 2620 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2621#ifdef _LP64 2622 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2623#else 2624 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2625 __ orl(xhi, xlo); 2626#endif // _LP64 2627 } else { 2628 ShouldNotReachHere(); 2629 } 2630 2631 } else if (opr1->is_single_xmm()) { 2632 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2633 if (opr2->is_single_xmm()) { 2634 // xmm register - xmm register 2635 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2636 } else if (opr2->is_stack()) { 2637 // xmm register - stack 2638 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2639 } else if (opr2->is_constant()) { 2640 // xmm register - constant 2641 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2642 } else if (opr2->is_address()) { 2643 // xmm register - address 2644 if (op->info() != NULL) { 2645 add_debug_info_for_null_check_here(op->info()); 2646 } 2647 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2648 } else { 2649 ShouldNotReachHere(); 2650 } 2651 2652 } else if (opr1->is_double_xmm()) { 2653 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2654 if (opr2->is_double_xmm()) { 2655 // xmm register - xmm register 2656 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2657 } else if (opr2->is_stack()) { 2658 // xmm register - stack 2659 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2660 } else if (opr2->is_constant()) { 2661 // xmm register - constant 2662 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2663 } else if (opr2->is_address()) { 2664 // xmm register - address 2665 if (op->info() != NULL) { 2666 add_debug_info_for_null_check_here(op->info()); 2667 } 2668 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2669 } else { 2670 ShouldNotReachHere(); 2671 } 2672 2673 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2674 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2675 assert(opr2->is_fpu_register(), "both must be registers"); 2676 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2677 2678 } else if (opr1->is_address() && opr2->is_constant()) { 2679 LIR_Const* c = opr2->as_constant_ptr(); 2680#ifdef _LP64 2681 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2682 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2683 __ movoop(rscratch1, c->as_jobject()); 2684 } 2685#endif // LP64 2686 if (op->info() != NULL) { 2687 add_debug_info_for_null_check_here(op->info()); 2688 } 2689 // special case: address - constant 2690 LIR_Address* addr = opr1->as_address_ptr(); 2691 if (c->type() == T_INT) { 2692 __ cmpl(as_Address(addr), c->as_jint()); 2693 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2694#ifdef _LP64 2695 // %%% Make this explode if addr isn't reachable until we figure out a 2696 // better strategy by giving noreg as the temp for as_Address 2697 __ cmpptr(rscratch1, as_Address(addr, noreg)); 2698#else 2699 __ cmpoop(as_Address(addr), c->as_jobject()); 2700#endif // _LP64 2701 } else { 2702 ShouldNotReachHere(); 2703 } 2704 2705 } else { 2706 ShouldNotReachHere(); 2707 } 2708} 2709 2710void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2711 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2712 if (left->is_single_xmm()) { 2713 assert(right->is_single_xmm(), "must match"); 2714 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2715 } else if (left->is_double_xmm()) { 2716 assert(right->is_double_xmm(), "must match"); 2717 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2718 2719 } else { 2720 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2721 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2722 2723 assert(left->fpu() == 0, "left must be on TOS"); 2724 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2725 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2726 } 2727 } else { 2728 assert(code == lir_cmp_l2i, "check"); 2729#ifdef _LP64 2730 Register dest = dst->as_register(); 2731 __ xorptr(dest, dest); 2732 Label high, done; 2733 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2734 __ jcc(Assembler::equal, done); 2735 __ jcc(Assembler::greater, high); 2736 __ decrement(dest); 2737 __ jmp(done); 2738 __ bind(high); 2739 __ increment(dest); 2740 2741 __ bind(done); 2742 2743#else 2744 __ lcmp2int(left->as_register_hi(), 2745 left->as_register_lo(), 2746 right->as_register_hi(), 2747 right->as_register_lo()); 2748 move_regs(left->as_register_hi(), dst->as_register()); 2749#endif // _LP64 2750 } 2751} 2752 2753 2754void LIR_Assembler::align_call(LIR_Code code) { 2755 if (os::is_MP()) { 2756 // make sure that the displacement word of the call ends up word aligned 2757 int offset = __ offset(); 2758 switch (code) { 2759 case lir_static_call: 2760 case lir_optvirtual_call: 2761 offset += NativeCall::displacement_offset; 2762 break; 2763 case lir_icvirtual_call: 2764 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2765 break; 2766 case lir_virtual_call: // currently, sparc-specific for niagara 2767 default: ShouldNotReachHere(); 2768 } 2769 while (offset++ % BytesPerWord != 0) { 2770 __ nop(); 2771 } 2772 } 2773} 2774 2775 2776void LIR_Assembler::call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info) { 2777 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2778 "must be aligned"); 2779 __ call(AddressLiteral(entry, rtype)); 2780 add_call_info(code_offset(), info); 2781} 2782 2783 2784void LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) { 2785 RelocationHolder rh = virtual_call_Relocation::spec(pc()); 2786 __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); 2787 assert(!os::is_MP() || 2788 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2789 "must be aligned"); 2790 __ call(AddressLiteral(entry, rh)); 2791 add_call_info(code_offset(), info); 2792} 2793 2794 2795/* Currently, vtable-dispatch is only enabled for sparc platforms */ 2796void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) { 2797 ShouldNotReachHere(); 2798} 2799 2800void LIR_Assembler::emit_static_call_stub() { 2801 address call_pc = __ pc(); 2802 address stub = __ start_a_stub(call_stub_size); 2803 if (stub == NULL) { 2804 bailout("static call stub overflow"); 2805 return; 2806 } 2807 2808 int start = __ offset(); 2809 if (os::is_MP()) { 2810 // make sure that the displacement word of the call ends up word aligned 2811 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; 2812 while (offset++ % BytesPerWord != 0) { 2813 __ nop(); 2814 } 2815 } 2816 __ relocate(static_stub_Relocation::spec(call_pc)); 2817 __ movoop(rbx, (jobject)NULL); 2818 // must be set to -1 at code generation time 2819 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); 2820 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2821 __ jump(RuntimeAddress(__ pc())); 2822 2823 assert(__ offset() - start <= call_stub_size, "stub too big") 2824 __ end_a_stub(); 2825} 2826 2827 2828void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) { 2829 assert(exceptionOop->as_register() == rax, "must match"); 2830 assert(unwind || exceptionPC->as_register() == rdx, "must match"); 2831 2832 // exception object is not added to oop map by LinearScan 2833 // (LinearScan assumes that no oops are in fixed registers) 2834 info->add_register_oop(exceptionOop); 2835 Runtime1::StubID unwind_id; 2836 2837 if (!unwind) { 2838 // get current pc information 2839 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2840 int pc_for_athrow_offset = __ offset(); 2841 InternalAddress pc_for_athrow(__ pc()); 2842 __ lea(exceptionPC->as_register(), pc_for_athrow); 2843 add_call_info(pc_for_athrow_offset, info); // for exception handler 2844 2845 __ verify_not_null_oop(rax); 2846 // search an exception handler (rax: exception oop, rdx: throwing pc) 2847 if (compilation()->has_fpu_code()) { 2848 unwind_id = Runtime1::handle_exception_id; 2849 } else { 2850 unwind_id = Runtime1::handle_exception_nofpu_id; 2851 } 2852 } else { 2853 unwind_id = Runtime1::unwind_exception_id; 2854 } 2855 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2856 2857 // enough room for two byte trap 2858 __ nop(); 2859} 2860 2861 2862void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2863 2864 // optimized version for linear scan: 2865 // * count must be already in ECX (guaranteed by LinearScan) 2866 // * left and dest must be equal 2867 // * tmp must be unused 2868 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2869 assert(left == dest, "left and dest must be equal"); 2870 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2871 2872 if (left->is_single_cpu()) { 2873 Register value = left->as_register(); 2874 assert(value != SHIFT_count, "left cannot be ECX"); 2875 2876 switch (code) { 2877 case lir_shl: __ shll(value); break; 2878 case lir_shr: __ sarl(value); break; 2879 case lir_ushr: __ shrl(value); break; 2880 default: ShouldNotReachHere(); 2881 } 2882 } else if (left->is_double_cpu()) { 2883 Register lo = left->as_register_lo(); 2884 Register hi = left->as_register_hi(); 2885 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2886#ifdef _LP64 2887 switch (code) { 2888 case lir_shl: __ shlptr(lo); break; 2889 case lir_shr: __ sarptr(lo); break; 2890 case lir_ushr: __ shrptr(lo); break; 2891 default: ShouldNotReachHere(); 2892 } 2893#else 2894 2895 switch (code) { 2896 case lir_shl: __ lshl(hi, lo); break; 2897 case lir_shr: __ lshr(hi, lo, true); break; 2898 case lir_ushr: __ lshr(hi, lo, false); break; 2899 default: ShouldNotReachHere(); 2900 } 2901#endif // LP64 2902 } else { 2903 ShouldNotReachHere(); 2904 } 2905} 2906 2907 2908void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2909 if (dest->is_single_cpu()) { 2910 // first move left into dest so that left is not destroyed by the shift 2911 Register value = dest->as_register(); 2912 count = count & 0x1F; // Java spec 2913 2914 move_regs(left->as_register(), value); 2915 switch (code) { 2916 case lir_shl: __ shll(value, count); break; 2917 case lir_shr: __ sarl(value, count); break; 2918 case lir_ushr: __ shrl(value, count); break; 2919 default: ShouldNotReachHere(); 2920 } 2921 } else if (dest->is_double_cpu()) { 2922#ifndef _LP64 2923 Unimplemented(); 2924#else 2925 // first move left into dest so that left is not destroyed by the shift 2926 Register value = dest->as_register_lo(); 2927 count = count & 0x1F; // Java spec 2928 2929 move_regs(left->as_register_lo(), value); 2930 switch (code) { 2931 case lir_shl: __ shlptr(value, count); break; 2932 case lir_shr: __ sarptr(value, count); break; 2933 case lir_ushr: __ shrptr(value, count); break; 2934 default: ShouldNotReachHere(); 2935 } 2936#endif // _LP64 2937 } else { 2938 ShouldNotReachHere(); 2939 } 2940} 2941 2942 2943void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 2944 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2945 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2946 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2947 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 2948} 2949 2950 2951void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 2952 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2953 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2954 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2955 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 2956} 2957 2958 2959void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 2960 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 2961 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 2962 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 2963 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 2964} 2965 2966 2967// This code replaces a call to arraycopy; no exception may 2968// be thrown in this code, they must be thrown in the System.arraycopy 2969// activation frame; we could save some checks if this would not be the case 2970void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 2971 ciArrayKlass* default_type = op->expected_type(); 2972 Register src = op->src()->as_register(); 2973 Register dst = op->dst()->as_register(); 2974 Register src_pos = op->src_pos()->as_register(); 2975 Register dst_pos = op->dst_pos()->as_register(); 2976 Register length = op->length()->as_register(); 2977 Register tmp = op->tmp()->as_register(); 2978 2979 CodeStub* stub = op->stub(); 2980 int flags = op->flags(); 2981 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 2982 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 2983 2984 // if we don't know anything or it's an object array, just go through the generic arraycopy 2985 if (default_type == NULL) { 2986 Label done; 2987 // save outgoing arguments on stack in case call to System.arraycopy is needed 2988 // HACK ALERT. This code used to push the parameters in a hardwired fashion 2989 // for interpreter calling conventions. Now we have to do it in new style conventions. 2990 // For the moment until C1 gets the new register allocator I just force all the 2991 // args to the right place (except the register args) and then on the back side 2992 // reload the register args properly if we go slow path. Yuck 2993 2994 // These are proper for the calling convention 2995 2996 store_parameter(length, 2); 2997 store_parameter(dst_pos, 1); 2998 store_parameter(dst, 0); 2999 3000 // these are just temporary placements until we need to reload 3001 store_parameter(src_pos, 3); 3002 store_parameter(src, 4); 3003 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3004 3005 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); 3006 3007 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3008#ifdef _LP64 3009 // The arguments are in java calling convention so we can trivially shift them to C 3010 // convention 3011 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3012 __ mov(c_rarg0, j_rarg0); 3013 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3014 __ mov(c_rarg1, j_rarg1); 3015 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3016 __ mov(c_rarg2, j_rarg2); 3017 assert_different_registers(c_rarg3, j_rarg4); 3018 __ mov(c_rarg3, j_rarg3); 3019#ifdef _WIN64 3020 // Allocate abi space for args but be sure to keep stack aligned 3021 __ subptr(rsp, 6*wordSize); 3022 store_parameter(j_rarg4, 4); 3023 __ call(RuntimeAddress(entry)); 3024 __ addptr(rsp, 6*wordSize); 3025#else 3026 __ mov(c_rarg4, j_rarg4); 3027 __ call(RuntimeAddress(entry)); 3028#endif // _WIN64 3029#else 3030 __ push(length); 3031 __ push(dst_pos); 3032 __ push(dst); 3033 __ push(src_pos); 3034 __ push(src); 3035 __ call_VM_leaf(entry, 5); // removes pushed parameter from the stack 3036 3037#endif // _LP64 3038 3039 __ cmpl(rax, 0); 3040 __ jcc(Assembler::equal, *stub->continuation()); 3041 3042 // Reload values from the stack so they are where the stub 3043 // expects them. 3044 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3045 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3046 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3047 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3048 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3049 __ jmp(*stub->entry()); 3050 3051 __ bind(*stub->continuation()); 3052 return; 3053 } 3054 3055 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3056 3057 int elem_size = type2aelembytes(basic_type); 3058 int shift_amount; 3059 Address::ScaleFactor scale; 3060 3061 switch (elem_size) { 3062 case 1 : 3063 shift_amount = 0; 3064 scale = Address::times_1; 3065 break; 3066 case 2 : 3067 shift_amount = 1; 3068 scale = Address::times_2; 3069 break; 3070 case 4 : 3071 shift_amount = 2; 3072 scale = Address::times_4; 3073 break; 3074 case 8 : 3075 shift_amount = 3; 3076 scale = Address::times_8; 3077 break; 3078 default: 3079 ShouldNotReachHere(); 3080 } 3081 3082 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3083 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3084 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3085 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3086 3087 // length and pos's are all sign extended at this point on 64bit 3088 3089 // test for NULL 3090 if (flags & LIR_OpArrayCopy::src_null_check) { 3091 __ testptr(src, src); 3092 __ jcc(Assembler::zero, *stub->entry()); 3093 } 3094 if (flags & LIR_OpArrayCopy::dst_null_check) { 3095 __ testptr(dst, dst); 3096 __ jcc(Assembler::zero, *stub->entry()); 3097 } 3098 3099 // check if negative 3100 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3101 __ testl(src_pos, src_pos); 3102 __ jcc(Assembler::less, *stub->entry()); 3103 } 3104 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3105 __ testl(dst_pos, dst_pos); 3106 __ jcc(Assembler::less, *stub->entry()); 3107 } 3108 if (flags & LIR_OpArrayCopy::length_positive_check) { 3109 __ testl(length, length); 3110 __ jcc(Assembler::less, *stub->entry()); 3111 } 3112 3113 if (flags & LIR_OpArrayCopy::src_range_check) { 3114 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3115 __ cmpl(tmp, src_length_addr); 3116 __ jcc(Assembler::above, *stub->entry()); 3117 } 3118 if (flags & LIR_OpArrayCopy::dst_range_check) { 3119 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3120 __ cmpl(tmp, dst_length_addr); 3121 __ jcc(Assembler::above, *stub->entry()); 3122 } 3123 3124 if (flags & LIR_OpArrayCopy::type_check) { 3125 __ movptr(tmp, src_klass_addr); 3126 __ cmpptr(tmp, dst_klass_addr); 3127 __ jcc(Assembler::notEqual, *stub->entry()); 3128 } 3129 3130#ifdef ASSERT 3131 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3132 // Sanity check the known type with the incoming class. For the 3133 // primitive case the types must match exactly with src.klass and 3134 // dst.klass each exactly matching the default type. For the 3135 // object array case, if no type check is needed then either the 3136 // dst type is exactly the expected type and the src type is a 3137 // subtype which we can't check or src is the same array as dst 3138 // but not necessarily exactly of type default_type. 3139 Label known_ok, halt; 3140 __ movoop(tmp, default_type->encoding()); 3141 if (basic_type != T_OBJECT) { 3142 __ cmpptr(tmp, dst_klass_addr); 3143 __ jcc(Assembler::notEqual, halt); 3144 __ cmpptr(tmp, src_klass_addr); 3145 __ jcc(Assembler::equal, known_ok); 3146 } else { 3147 __ cmpptr(tmp, dst_klass_addr); 3148 __ jcc(Assembler::equal, known_ok); 3149 __ cmpptr(src, dst); 3150 __ jcc(Assembler::equal, known_ok); 3151 } 3152 __ bind(halt); 3153 __ stop("incorrect type information in arraycopy"); 3154 __ bind(known_ok); 3155 } 3156#endif 3157 3158 if (shift_amount > 0 && basic_type != T_OBJECT) { 3159 __ shlptr(length, shift_amount); 3160 } 3161 3162#ifdef _LP64 3163 assert_different_registers(c_rarg0, dst, dst_pos, length); 3164 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3165 assert_different_registers(c_rarg1, length); 3166 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3167 __ mov(c_rarg2, length); 3168 3169#else 3170 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3171 store_parameter(tmp, 0); 3172 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3173 store_parameter(tmp, 1); 3174 store_parameter(length, 2); 3175#endif // _LP64 3176 if (basic_type == T_OBJECT) { 3177 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy), 0); 3178 } else { 3179 __ call_VM_leaf(CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy), 0); 3180 } 3181 3182 __ bind(*stub->continuation()); 3183} 3184 3185 3186void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3187 Register obj = op->obj_opr()->as_register(); // may not be an oop 3188 Register hdr = op->hdr_opr()->as_register(); 3189 Register lock = op->lock_opr()->as_register(); 3190 if (!UseFastLocking) { 3191 __ jmp(*op->stub()->entry()); 3192 } else if (op->code() == lir_lock) { 3193 Register scratch = noreg; 3194 if (UseBiasedLocking) { 3195 scratch = op->scratch_opr()->as_register(); 3196 } 3197 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3198 // add debug info for NullPointerException only if one is possible 3199 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3200 if (op->info() != NULL) { 3201 add_debug_info_for_null_check(null_check_offset, op->info()); 3202 } 3203 // done 3204 } else if (op->code() == lir_unlock) { 3205 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3206 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3207 } else { 3208 Unimplemented(); 3209 } 3210 __ bind(*op->stub()->continuation()); 3211} 3212 3213 3214void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3215 ciMethod* method = op->profiled_method(); 3216 int bci = op->profiled_bci(); 3217 3218 // Update counter for all call types 3219 ciMethodData* md = method->method_data(); 3220 if (md == NULL) { 3221 bailout("out of memory building methodDataOop"); 3222 return; 3223 } 3224 ciProfileData* data = md->bci_to_data(bci); 3225 assert(data->is_CounterData(), "need CounterData for calls"); 3226 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3227 Register mdo = op->mdo()->as_register(); 3228 __ movoop(mdo, md->encoding()); 3229 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3230 __ addl(counter_addr, DataLayout::counter_increment); 3231 Bytecodes::Code bc = method->java_code_at_bci(bci); 3232 // Perform additional virtual call profiling for invokevirtual and 3233 // invokeinterface bytecodes 3234 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 3235 Tier1ProfileVirtualCalls) { 3236 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3237 Register recv = op->recv()->as_register(); 3238 assert_different_registers(mdo, recv); 3239 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3240 ciKlass* known_klass = op->known_holder(); 3241 if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) { 3242 // We know the type that will be seen at this call site; we can 3243 // statically update the methodDataOop rather than needing to do 3244 // dynamic tests on the receiver type 3245 3246 // NOTE: we should probably put a lock around this search to 3247 // avoid collisions by concurrent compilations 3248 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3249 uint i; 3250 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3251 ciKlass* receiver = vc_data->receiver(i); 3252 if (known_klass->equals(receiver)) { 3253 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3254 __ addl(data_addr, DataLayout::counter_increment); 3255 return; 3256 } 3257 } 3258 3259 // Receiver type not found in profile data; select an empty slot 3260 3261 // Note that this is less efficient than it should be because it 3262 // always does a write to the receiver part of the 3263 // VirtualCallData rather than just the first time 3264 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3265 ciKlass* receiver = vc_data->receiver(i); 3266 if (receiver == NULL) { 3267 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3268 __ movoop(recv_addr, known_klass->encoding()); 3269 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3270 __ addl(data_addr, DataLayout::counter_increment); 3271 return; 3272 } 3273 } 3274 } else { 3275 __ movptr(recv, Address(recv, oopDesc::klass_offset_in_bytes())); 3276 Label update_done; 3277 uint i; 3278 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3279 Label next_test; 3280 // See if the receiver is receiver[n]. 3281 __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)))); 3282 __ jcc(Assembler::notEqual, next_test); 3283 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3284 __ addl(data_addr, DataLayout::counter_increment); 3285 __ jmp(update_done); 3286 __ bind(next_test); 3287 } 3288 3289 // Didn't find receiver; find next empty slot and fill it in 3290 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3291 Label next_test; 3292 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3293 __ cmpptr(recv_addr, (int32_t)NULL_WORD); 3294 __ jcc(Assembler::notEqual, next_test); 3295 __ movptr(recv_addr, recv); 3296 __ movl(Address(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))), DataLayout::counter_increment); 3297 if (i < (VirtualCallData::row_limit() - 1)) { 3298 __ jmp(update_done); 3299 } 3300 __ bind(next_test); 3301 } 3302 3303 __ bind(update_done); 3304 } 3305 } 3306} 3307 3308 3309void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3310 Unimplemented(); 3311} 3312 3313 3314void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3315 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3316} 3317 3318 3319void LIR_Assembler::align_backward_branch_target() { 3320 __ align(BytesPerWord); 3321} 3322 3323 3324void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3325 if (left->is_single_cpu()) { 3326 __ negl(left->as_register()); 3327 move_regs(left->as_register(), dest->as_register()); 3328 3329 } else if (left->is_double_cpu()) { 3330 Register lo = left->as_register_lo(); 3331#ifdef _LP64 3332 Register dst = dest->as_register_lo(); 3333 __ movptr(dst, lo); 3334 __ negptr(dst); 3335#else 3336 Register hi = left->as_register_hi(); 3337 __ lneg(hi, lo); 3338 if (dest->as_register_lo() == hi) { 3339 assert(dest->as_register_hi() != lo, "destroying register"); 3340 move_regs(hi, dest->as_register_hi()); 3341 move_regs(lo, dest->as_register_lo()); 3342 } else { 3343 move_regs(lo, dest->as_register_lo()); 3344 move_regs(hi, dest->as_register_hi()); 3345 } 3346#endif // _LP64 3347 3348 } else if (dest->is_single_xmm()) { 3349 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3350 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3351 } 3352 __ xorps(dest->as_xmm_float_reg(), 3353 ExternalAddress((address)float_signflip_pool)); 3354 3355 } else if (dest->is_double_xmm()) { 3356 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3357 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3358 } 3359 __ xorpd(dest->as_xmm_double_reg(), 3360 ExternalAddress((address)double_signflip_pool)); 3361 3362 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3363 assert(left->fpu() == 0, "arg must be on TOS"); 3364 assert(dest->fpu() == 0, "dest must be TOS"); 3365 __ fchs(); 3366 3367 } else { 3368 ShouldNotReachHere(); 3369 } 3370} 3371 3372 3373void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { 3374 assert(addr->is_address() && dest->is_register(), "check"); 3375 Register reg; 3376 reg = dest->as_pointer_register(); 3377 __ lea(reg, as_Address(addr->as_address_ptr())); 3378} 3379 3380 3381 3382void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3383 assert(!tmp->is_valid(), "don't need temporary"); 3384 __ call(RuntimeAddress(dest)); 3385 if (info != NULL) { 3386 add_call_info_here(info); 3387 } 3388} 3389 3390 3391void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3392 assert(type == T_LONG, "only for volatile long fields"); 3393 3394 if (info != NULL) { 3395 add_debug_info_for_null_check_here(info); 3396 } 3397 3398 if (src->is_double_xmm()) { 3399 if (dest->is_double_cpu()) { 3400#ifdef _LP64 3401 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3402#else 3403 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3404 __ psrlq(src->as_xmm_double_reg(), 32); 3405 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3406#endif // _LP64 3407 } else if (dest->is_double_stack()) { 3408 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3409 } else if (dest->is_address()) { 3410 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3411 } else { 3412 ShouldNotReachHere(); 3413 } 3414 3415 } else if (dest->is_double_xmm()) { 3416 if (src->is_double_stack()) { 3417 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3418 } else if (src->is_address()) { 3419 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3420 } else { 3421 ShouldNotReachHere(); 3422 } 3423 3424 } else if (src->is_double_fpu()) { 3425 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3426 if (dest->is_double_stack()) { 3427 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3428 } else if (dest->is_address()) { 3429 __ fistp_d(as_Address(dest->as_address_ptr())); 3430 } else { 3431 ShouldNotReachHere(); 3432 } 3433 3434 } else if (dest->is_double_fpu()) { 3435 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3436 if (src->is_double_stack()) { 3437 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3438 } else if (src->is_address()) { 3439 __ fild_d(as_Address(src->as_address_ptr())); 3440 } else { 3441 ShouldNotReachHere(); 3442 } 3443 } else { 3444 ShouldNotReachHere(); 3445 } 3446} 3447 3448 3449void LIR_Assembler::membar() { 3450 // QQQ sparc TSO uses this, 3451 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3452} 3453 3454void LIR_Assembler::membar_acquire() { 3455 // No x86 machines currently require load fences 3456 // __ load_fence(); 3457} 3458 3459void LIR_Assembler::membar_release() { 3460 // No x86 machines currently require store fences 3461 // __ store_fence(); 3462} 3463 3464void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3465 assert(result_reg->is_register(), "check"); 3466#ifdef _LP64 3467 // __ get_thread(result_reg->as_register_lo()); 3468 __ mov(result_reg->as_register(), r15_thread); 3469#else 3470 __ get_thread(result_reg->as_register()); 3471#endif // _LP64 3472} 3473 3474 3475void LIR_Assembler::peephole(LIR_List*) { 3476 // do nothing for now 3477} 3478 3479 3480#undef __ 3481