c1_FrameMap_x86.hpp revision 0:a61af66fc99e 
1133063Sdfr/*
2133063Sdfr * Copyright 1999-2006 Sun Microsystems, Inc.  All Rights Reserved.
3133063Sdfr * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4133063Sdfr *
5133063Sdfr * This code is free software; you can redistribute it and/or modify it
6133063Sdfr * under the terms of the GNU General Public License version 2 only, as
7133063Sdfr * published by the Free Software Foundation.
8133063Sdfr *
9133063Sdfr * This code is distributed in the hope that it will be useful, but WITHOUT
10133063Sdfr * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11133063Sdfr * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12133063Sdfr * version 2 for more details (a copy is included in the LICENSE file that
13133063Sdfr * accompanied this code).
14133063Sdfr *
15133063Sdfr * You should have received a copy of the GNU General Public License version
16133063Sdfr * 2 along with this work; if not, write to the Free Software Foundation,
17133063Sdfr * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18133063Sdfr *
19133063Sdfr * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
20133063Sdfr * CA 95054 USA or visit www.sun.com if you need additional information or
21133063Sdfr * have any questions.
22133063Sdfr *
23133063Sdfr */
24133063Sdfr
25133063Sdfr//  On i486 the frame looks as follows:
26133063Sdfr//
27133063Sdfr//  +-----------------------------+---------+----------------------------------------+----------------+-----------
28133063Sdfr//  | size_arguments-nof_reg_args | 2 words | size_locals-size_arguments+numreg_args | _size_monitors | spilling .
29133063Sdfr//  +-----------------------------+---------+----------------------------------------+----------------+-----------
30133063Sdfr//
31133063Sdfr//  The FPU registers are mapped with their offset from TOS; therefore the
32133063Sdfr//  status of FPU stack must be updated during code emission.
33133063Sdfr
34133063Sdfr public:
35133063Sdfr  static const int pd_c_runtime_reserved_arg_size;
36133063Sdfr
37133063Sdfr  enum {
38133063Sdfr    nof_xmm_regs = pd_nof_xmm_regs_frame_map,
39133063Sdfr    nof_caller_save_xmm_regs = pd_nof_caller_save_xmm_regs_frame_map,
40133063Sdfr    first_available_sp_in_frame = 0,
41133063Sdfr    frame_pad_in_bytes = 8,
42133063Sdfr    nof_reg_args = 2
43133063Sdfr  };
44133063Sdfr
45133063Sdfr private:
46133063Sdfr  static LIR_Opr      _caller_save_xmm_regs [nof_caller_save_xmm_regs];
47133063Sdfr
48133063Sdfr  static XMMRegister _xmm_regs[nof_xmm_regs];
49133063Sdfr
50133063Sdfr public:
51133063Sdfr  static LIR_Opr receiver_opr;
52133063Sdfr
53133063Sdfr  static LIR_Opr rsi_opr;
54133063Sdfr  static LIR_Opr rdi_opr;
55133063Sdfr  static LIR_Opr rbx_opr;
56133063Sdfr  static LIR_Opr rax_opr;
57133063Sdfr  static LIR_Opr rdx_opr;
58133063Sdfr  static LIR_Opr rcx_opr;
59133063Sdfr  static LIR_Opr rsp_opr;
60281453Skib  static LIR_Opr rbp_opr;
61281453Skib
62133063Sdfr  static LIR_Opr rsi_oop_opr;
63133063Sdfr  static LIR_Opr rdi_oop_opr;
64133063Sdfr  static LIR_Opr rbx_oop_opr;
65133063Sdfr  static LIR_Opr rax_oop_opr;
66133063Sdfr  static LIR_Opr rdx_oop_opr;
67133063Sdfr  static LIR_Opr rcx_oop_opr;
68281453Skib
69133063Sdfr  static LIR_Opr rax_rdx_long_opr;
70133063Sdfr  static LIR_Opr rbx_rcx_long_opr;
71  static LIR_Opr fpu0_float_opr;
72  static LIR_Opr fpu0_double_opr;
73  static LIR_Opr xmm0_float_opr;
74  static LIR_Opr xmm0_double_opr;
75
76  static LIR_Opr as_long_opr(Register r, Register r2) {
77    return LIR_OprFact::double_cpu(cpu_reg2rnr(r), cpu_reg2rnr(r2));
78  }
79
80  // VMReg name for spilled physical FPU stack slot n
81  static VMReg fpu_regname (int n);
82
83  static XMMRegister nr2xmmreg(int rnr);
84
85  static bool is_caller_save_register (LIR_Opr opr) { return true; }
86  static bool is_caller_save_register (Register r) { return true; }
87
88  static LIR_Opr caller_save_xmm_reg_at(int i) {
89    assert(i >= 0 && i < nof_caller_save_xmm_regs, "out of bounds");
90    return _caller_save_xmm_regs[i];
91  }
92