vm_version_sparc.hpp revision 12160:43c36489d6fe 
1/*
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3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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5 * This code is free software; you can redistribute it and/or modify it
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7 * published by the Free Software Foundation.
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12 * version 2 for more details (a copy is included in the LICENSE file that
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23 */
24
25#ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
26#define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
27
28#include "runtime/globals_extension.hpp"
29#include "runtime/vm_version.hpp"
30
31class VM_Version: public Abstract_VM_Version {
32  friend class VMStructs;
33  friend class JVMCIVMStructs;
34
35protected:
36  enum Feature_Flag {
37    v8_instructions       = 0,
38    hardware_mul32        = 1,
39    hardware_div32        = 2,
40    hardware_fsmuld       = 3,
41    hardware_popc         = 4,
42    v9_instructions       = 5,
43    vis1_instructions     = 6,
44    vis2_instructions     = 7,
45    sun4v_instructions    = 8,
46    blk_init_instructions = 9,
47    fmaf_instructions     = 10,
48    vis3_instructions     = 11,
49    cbcond_instructions   = 12,
50    sparc64_family        = 13,
51    M_family              = 14,
52    T_family              = 15,
53    T1_model              = 16,
54    sparc5_instructions   = 17,
55    aes_instructions      = 18,
56    sha1_instruction      = 19,
57    sha256_instruction    = 20,
58    sha512_instruction    = 21,
59    crc32c_instruction    = 22
60  };
61
62  enum Feature_Flag_Set {
63    unknown_m           = 0,
64    all_features_m      = -1,
65
66    v8_instructions_m       = 1 << v8_instructions,
67    hardware_mul32_m        = 1 << hardware_mul32,
68    hardware_div32_m        = 1 << hardware_div32,
69    hardware_fsmuld_m       = 1 << hardware_fsmuld,
70    hardware_popc_m         = 1 << hardware_popc,
71    v9_instructions_m       = 1 << v9_instructions,
72    vis1_instructions_m     = 1 << vis1_instructions,
73    vis2_instructions_m     = 1 << vis2_instructions,
74    sun4v_m                 = 1 << sun4v_instructions,
75    blk_init_instructions_m = 1 << blk_init_instructions,
76    fmaf_instructions_m     = 1 << fmaf_instructions,
77    vis3_instructions_m     = 1 << vis3_instructions,
78    cbcond_instructions_m   = 1 << cbcond_instructions,
79    sparc64_family_m        = 1 << sparc64_family,
80    M_family_m              = 1 << M_family,
81    T_family_m              = 1 << T_family,
82    T1_model_m              = 1 << T1_model,
83    sparc5_instructions_m   = 1 << sparc5_instructions,
84    aes_instructions_m      = 1 << aes_instructions,
85    sha1_instruction_m      = 1 << sha1_instruction,
86    sha256_instruction_m    = 1 << sha256_instruction,
87    sha512_instruction_m    = 1 << sha512_instruction,
88    crc32c_instruction_m    = 1 << crc32c_instruction,
89
90    generic_v8_m        = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
91    generic_v9_m        = generic_v8_m | v9_instructions_m,
92    ultra3_m            = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
93
94    // Temporary until we have something more accurate
95    niagara1_unique_m   = sun4v_m,
96    niagara1_m          = generic_v9_m | niagara1_unique_m
97  };
98
99  static unsigned int _L2_data_cache_line_size;
100  static unsigned int L2_data_cache_line_size() { return _L2_data_cache_line_size; }
101
102  static void print_features();
103  static int  determine_features();
104  static int  platform_features(int features);
105
106  // Returns true if the platform is in the niagara line (T series)
107  static bool is_M_family(int features) { return (features & M_family_m) != 0; }
108  static bool is_T_family(int features) { return (features & T_family_m) != 0; }
109  static bool is_niagara() { return is_T_family(_features); }
110#ifdef ASSERT
111  static bool is_niagara(int features)  {
112    // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as
113    // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'.
114    return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0;
115  }
116#endif
117
118  // Returns true if it is niagara1 (T1).
119  static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }
120
121  static int maximum_niagara1_processor_count() { return 32; }
122  static int parse_features(const char* implementation);
123public:
124  // Initialization
125  static void initialize();
126
127  static void init_before_ergo()        { _features = determine_features(); }
128
129  // Instruction support
130  static bool has_v8()                  { return (_features & v8_instructions_m) != 0; }
131  static bool has_v9()                  { return (_features & v9_instructions_m) != 0; }
132  static bool has_hardware_mul32()      { return (_features & hardware_mul32_m) != 0; }
133  static bool has_hardware_div32()      { return (_features & hardware_div32_m) != 0; }
134  static bool has_hardware_fsmuld()     { return (_features & hardware_fsmuld_m) != 0; }
135  static bool has_hardware_popc()       { return (_features & hardware_popc_m) != 0; }
136  static bool has_vis1()                { return (_features & vis1_instructions_m) != 0; }
137  static bool has_vis2()                { return (_features & vis2_instructions_m) != 0; }
138  static bool has_vis3()                { return (_features & vis3_instructions_m) != 0; }
139  static bool has_blk_init()            { return (_features & blk_init_instructions_m) != 0; }
140  static bool has_cbcond()              { return (_features & cbcond_instructions_m) != 0; }
141  static bool has_sparc5_instr()        { return (_features & sparc5_instructions_m) != 0; }
142  static bool has_aes()                 { return (_features & aes_instructions_m) != 0; }
143  static bool has_sha1()                { return (_features & sha1_instruction_m) != 0; }
144  static bool has_sha256()              { return (_features & sha256_instruction_m) != 0; }
145  static bool has_sha512()              { return (_features & sha512_instruction_m) != 0; }
146  static bool has_crc32c()              { return (_features & crc32c_instruction_m) != 0; }
147
148  static bool supports_compare_and_exchange()
149                                        { return has_v9(); }
150
151  // Returns true if the platform is in the niagara line (T series)
152  // and newer than the niagara1.
153  static bool is_niagara_plus()         { return is_T_family(_features) && !is_T1_model(_features); }
154
155  static bool is_M_series()             { return is_M_family(_features); }
156  static bool is_T4()                   { return is_T_family(_features) && has_cbcond(); }
157  static bool is_T7()                   { return is_T_family(_features) && has_sparc5_instr(); }
158
159  // Fujitsu SPARC64
160  static bool is_sparc64()              { return (_features & sparc64_family_m) != 0; }
161
162  static bool is_sun4v()                { return (_features & sun4v_m) != 0; }
163  static bool is_ultra3()               { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }
164
165  static bool has_fast_fxtof()          { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
166  static bool has_fast_idiv()           { return is_niagara_plus() || is_sparc64(); }
167
168  // T4 and newer Sparc have fast RDPC instruction.
169  static bool has_fast_rdpc()           { return is_T4(); }
170
171  // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
172  static bool has_block_zeroing()       { return has_blk_init() && is_T4(); }
173
174  // default prefetch block size on sparc
175  static intx prefetch_data_size()      { return L2_data_cache_line_size();  }
176
177  // Prefetch
178  static intx prefetch_copy_interval_in_bytes() {
179    intx interval = PrefetchCopyIntervalInBytes;
180    return interval >= 0 ? interval : (has_v9() ? 512 : 0);
181  }
182  static intx prefetch_scan_interval_in_bytes() {
183    intx interval = PrefetchScanIntervalInBytes;
184    return interval >= 0 ? interval : (has_v9() ? 512 : 0);
185  }
186  static intx prefetch_fields_ahead() {
187    intx count = PrefetchFieldsAhead;
188    return count >= 0 ? count : (is_ultra3() ? 1 : 0);
189  }
190
191  static intx allocate_prefetch_distance() {
192    // This method should be called before allocate_prefetch_style().
193    intx count = AllocatePrefetchDistance;
194    if (count < 0) { // default is not defined ?
195      count = 512;
196    }
197    return count;
198  }
199  static intx allocate_prefetch_style() {
200    assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
201    // Return 0 if AllocatePrefetchDistance was not defined.
202    return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
203  }
204
205  // Assembler testing
206  static void allow_all();
207  static void revert();
208
209  // Override the Abstract_VM_Version implementation.
210  static uint page_size_count() { return is_sun4v() ? 4 : 2; }
211
212  // Calculates the number of parallel threads
213  static unsigned int calc_parallel_worker_threads();
214};
215
216#endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP
217