vm_version_sparc.cpp revision 6683:08a2164660fb
1/* 2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25#include "precompiled.hpp" 26#include "asm/macroAssembler.inline.hpp" 27#include "memory/resourceArea.hpp" 28#include "runtime/java.hpp" 29#include "runtime/stubCodeGenerator.hpp" 30#include "vm_version_sparc.hpp" 31 32int VM_Version::_features = VM_Version::unknown_m; 33const char* VM_Version::_features_str = ""; 34 35void VM_Version::initialize() { 36 _features = determine_features(); 37 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 38 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 39 PrefetchFieldsAhead = prefetch_fields_ahead(); 40 41 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value"); 42 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0; 43 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0; 44 45 // Allocation prefetch settings 46 intx cache_line_size = prefetch_data_size(); 47 if( cache_line_size > AllocatePrefetchStepSize ) 48 AllocatePrefetchStepSize = cache_line_size; 49 50 assert(AllocatePrefetchLines > 0, "invalid value"); 51 if( AllocatePrefetchLines < 1 ) // set valid value in product VM 52 AllocatePrefetchLines = 3; 53 assert(AllocateInstancePrefetchLines > 0, "invalid value"); 54 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM 55 AllocateInstancePrefetchLines = 1; 56 57 AllocatePrefetchDistance = allocate_prefetch_distance(); 58 AllocatePrefetchStyle = allocate_prefetch_style(); 59 60 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 && 61 (AllocatePrefetchDistance > 0), "invalid value"); 62 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 || 63 (AllocatePrefetchDistance <= 0)) { 64 AllocatePrefetchDistance = AllocatePrefetchStepSize; 65 } 66 67 if (AllocatePrefetchStyle == 3 && !has_blk_init()) { 68 warning("BIS instructions are not available on this CPU"); 69 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1); 70 } 71 72 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); 73 74 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value"); 75 if (ArraycopySrcPrefetchDistance >= 4096) 76 ArraycopySrcPrefetchDistance = 4064; 77 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value"); 78 if (ArraycopyDstPrefetchDistance >= 4096) 79 ArraycopyDstPrefetchDistance = 4064; 80 81 UseSSE = 0; // Only on x86 and x64 82 83 _supports_cx8 = has_v9(); 84 _supports_atomic_getset4 = true; // swap instruction 85 86 // There are Fujitsu Sparc64 CPUs which support blk_init as well so 87 // we have to take this check out of the 'is_niagara()' block below. 88 if (has_blk_init()) { 89 // When using CMS or G1, we cannot use memset() in BOT updates 90 // because the sun4v/CMT version in libc_psr uses BIS which 91 // exposes "phantom zeros" to concurrent readers. See 6948537. 92 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) { 93 FLAG_SET_DEFAULT(UseMemSetInBOT, false); 94 } 95 // Issue a stern warning if the user has explicitly set 96 // UseMemSetInBOT (it is known to cause issues), but allow 97 // use for experimentation and debugging. 98 if (UseConcMarkSweepGC || UseG1GC) { 99 if (UseMemSetInBOT) { 100 assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error"); 101 warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability" 102 " on sun4v; please understand that you are using at your own risk!"); 103 } 104 } 105 } 106 107 if (is_niagara()) { 108 // Indirect branch is the same cost as direct 109 if (FLAG_IS_DEFAULT(UseInlineCaches)) { 110 FLAG_SET_DEFAULT(UseInlineCaches, false); 111 } 112 // Align loops on a single instruction boundary. 113 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { 114 FLAG_SET_DEFAULT(OptoLoopAlignment, 4); 115 } 116#ifdef _LP64 117 // 32-bit oops don't make sense for the 64-bit VM on sparc 118 // since the 32-bit VM has the same registers and smaller objects. 119 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); 120 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); 121#endif // _LP64 122#ifdef COMPILER2 123 // Indirect branch is the same cost as direct 124 if (FLAG_IS_DEFAULT(UseJumpTables)) { 125 FLAG_SET_DEFAULT(UseJumpTables, true); 126 } 127 // Single-issue, so entry and loop tops are 128 // aligned on a single instruction boundary 129 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { 130 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4); 131 } 132 if (is_niagara_plus()) { 133 if (has_blk_init() && UseTLAB && 134 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { 135 // Use BIS instruction for TLAB allocation prefetch. 136 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); 137 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { 138 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); 139 } 140 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 141 // Use smaller prefetch distance with BIS 142 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); 143 } 144 } 145 if (is_T4()) { 146 // Double number of prefetched cache lines on T4 147 // since L2 cache line size is smaller (32 bytes). 148 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { 149 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2); 150 } 151 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { 152 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2); 153 } 154 } 155 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 156 // Use different prefetch distance without BIS 157 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); 158 } 159 if (AllocatePrefetchInstr == 1) { 160 // Need a space at the end of TLAB for BIS since it 161 // will fault when accessing memory outside of heap. 162 163 // +1 for rounding up to next cache line, +1 to be safe 164 int lines = AllocatePrefetchLines + 2; 165 int step_size = AllocatePrefetchStepSize; 166 int distance = AllocatePrefetchDistance; 167 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize; 168 } 169 } 170#endif 171 } 172 173 // Use hardware population count instruction if available. 174 if (has_hardware_popc()) { 175 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 176 FLAG_SET_DEFAULT(UsePopCountInstruction, true); 177 } 178 } else if (UsePopCountInstruction) { 179 warning("POPC instruction is not available on this CPU"); 180 FLAG_SET_DEFAULT(UsePopCountInstruction, false); 181 } 182 183 // T4 and newer Sparc cpus have new compare and branch instruction. 184 if (has_cbcond()) { 185 if (FLAG_IS_DEFAULT(UseCBCond)) { 186 FLAG_SET_DEFAULT(UseCBCond, true); 187 } 188 } else if (UseCBCond) { 189 warning("CBCOND instruction is not available on this CPU"); 190 FLAG_SET_DEFAULT(UseCBCond, false); 191 } 192 193 assert(BlockZeroingLowLimit > 0, "invalid value"); 194 if (has_block_zeroing()) { 195 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { 196 FLAG_SET_DEFAULT(UseBlockZeroing, true); 197 } 198 } else if (UseBlockZeroing) { 199 warning("BIS zeroing instructions are not available on this CPU"); 200 FLAG_SET_DEFAULT(UseBlockZeroing, false); 201 } 202 203 assert(BlockCopyLowLimit > 0, "invalid value"); 204 if (has_block_zeroing()) { // has_blk_init() && is_T4(): core's local L2 cache 205 if (FLAG_IS_DEFAULT(UseBlockCopy)) { 206 FLAG_SET_DEFAULT(UseBlockCopy, true); 207 } 208 } else if (UseBlockCopy) { 209 warning("BIS instructions are not available or expensive on this CPU"); 210 FLAG_SET_DEFAULT(UseBlockCopy, false); 211 } 212 213#ifdef COMPILER2 214 // T4 and newer Sparc cpus have fast RDPC. 215 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { 216 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); 217 } 218 219 // Currently not supported anywhere. 220 FLAG_SET_DEFAULT(UseFPUForSpilling, false); 221 222 MaxVectorSize = 8; 223 224 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 225#endif 226 227 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 228 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 229 230 char buf[512]; 231 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 232 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")), 233 (has_hardware_popc() ? ", popc" : ""), 234 (has_vis1() ? ", vis1" : ""), 235 (has_vis2() ? ", vis2" : ""), 236 (has_vis3() ? ", vis3" : ""), 237 (has_blk_init() ? ", blk_init" : ""), 238 (has_cbcond() ? ", cbcond" : ""), 239 (has_aes() ? ", aes" : ""), 240 (has_sha1() ? ", sha1" : ""), 241 (has_sha256() ? ", sha256" : ""), 242 (has_sha512() ? ", sha512" : ""), 243 (is_ultra3() ? ", ultra3" : ""), 244 (is_sun4v() ? ", sun4v" : ""), 245 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")), 246 (is_sparc64() ? ", sparc64" : ""), 247 (!has_hardware_mul32() ? ", no-mul32" : ""), 248 (!has_hardware_div32() ? ", no-div32" : ""), 249 (!has_hardware_fsmuld() ? ", no-fsmuld" : "")); 250 251 // buf is started with ", " or is empty 252 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf); 253 254 // UseVIS is set to the smallest of what hardware supports and what 255 // the command line requires. I.e., you cannot set UseVIS to 3 on 256 // older UltraSparc which do not support it. 257 if (UseVIS > 3) UseVIS=3; 258 if (UseVIS < 0) UseVIS=0; 259 if (!has_vis3()) // Drop to 2 if no VIS3 support 260 UseVIS = MIN2((intx)2,UseVIS); 261 if (!has_vis2()) // Drop to 1 if no VIS2 support 262 UseVIS = MIN2((intx)1,UseVIS); 263 if (!has_vis1()) // Drop to 0 if no VIS1 support 264 UseVIS = 0; 265 266 // SPARC T4 and above should have support for AES instructions 267 if (has_aes()) { 268 if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3 269 if (FLAG_IS_DEFAULT(UseAES)) { 270 FLAG_SET_DEFAULT(UseAES, true); 271 } 272 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 273 FLAG_SET_DEFAULT(UseAESIntrinsics, true); 274 } 275 // we disable both the AES flags if either of them is disabled on the command line 276 if (!UseAES || !UseAESIntrinsics) { 277 FLAG_SET_DEFAULT(UseAES, false); 278 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 279 } 280 } else { 281 if (UseAES || UseAESIntrinsics) { 282 warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled."); 283 if (UseAES) { 284 FLAG_SET_DEFAULT(UseAES, false); 285 } 286 if (UseAESIntrinsics) { 287 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 288 } 289 } 290 } 291 } else if (UseAES || UseAESIntrinsics) { 292 warning("AES instructions are not available on this CPU"); 293 if (UseAES) { 294 FLAG_SET_DEFAULT(UseAES, false); 295 } 296 if (UseAESIntrinsics) { 297 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 298 } 299 } 300 301 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times 302 if (has_sha1() || has_sha256() || has_sha512()) { 303 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions 304 if (FLAG_IS_DEFAULT(UseSHA)) { 305 FLAG_SET_DEFAULT(UseSHA, true); 306 } 307 } else { 308 if (UseSHA) { 309 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled."); 310 FLAG_SET_DEFAULT(UseSHA, false); 311 } 312 } 313 } else if (UseSHA) { 314 warning("SHA instructions are not available on this CPU"); 315 FLAG_SET_DEFAULT(UseSHA, false); 316 } 317 318 if (!UseSHA) { 319 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 320 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 321 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 322 } else { 323 if (has_sha1()) { 324 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { 325 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); 326 } 327 } else if (UseSHA1Intrinsics) { 328 warning("SHA1 instruction is not available on this CPU."); 329 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 330 } 331 if (has_sha256()) { 332 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { 333 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); 334 } 335 } else if (UseSHA256Intrinsics) { 336 warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU."); 337 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 338 } 339 340 if (has_sha512()) { 341 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { 342 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); 343 } 344 } else if (UseSHA512Intrinsics) { 345 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU."); 346 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 347 } 348 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { 349 FLAG_SET_DEFAULT(UseSHA, false); 350 } 351 } 352 353 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && 354 (cache_line_size > ContendedPaddingWidth)) 355 ContendedPaddingWidth = cache_line_size; 356 357#ifndef PRODUCT 358 if (PrintMiscellaneous && Verbose) { 359 tty->print("Allocation"); 360 if (AllocatePrefetchStyle <= 0) { 361 tty->print_cr(": no prefetching"); 362 } else { 363 tty->print(" prefetching: "); 364 if (AllocatePrefetchInstr == 0) { 365 tty->print("PREFETCH"); 366 } else if (AllocatePrefetchInstr == 1) { 367 tty->print("BIS"); 368 } 369 if (AllocatePrefetchLines > 1) { 370 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); 371 } else { 372 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); 373 } 374 } 375 if (PrefetchCopyIntervalInBytes > 0) { 376 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); 377 } 378 if (PrefetchScanIntervalInBytes > 0) { 379 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); 380 } 381 if (PrefetchFieldsAhead > 0) { 382 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); 383 } 384 if (ContendedPaddingWidth > 0) { 385 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); 386 } 387 } 388#endif // PRODUCT 389} 390 391void VM_Version::print_features() { 392 tty->print_cr("Version:%s", cpu_features()); 393} 394 395int VM_Version::determine_features() { 396 if (UseV8InstrsOnly) { 397 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");) 398 return generic_v8_m; 399 } 400 401 int features = platform_features(unknown_m); // platform_features() is os_arch specific 402 403 if (features == unknown_m) { 404 features = generic_v9_m; 405 warning("Cannot recognize SPARC version. Default to V9"); 406 } 407 408 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series"); 409 if (UseNiagaraInstrs) { // Force code generation for Niagara 410 if (is_T_family(features)) { 411 // Happy to accomodate... 412 } else { 413 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");) 414 features |= T_family_m; 415 } 416 } else { 417 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) { 418 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");) 419 features &= ~(T_family_m | T1_model_m); 420 } else { 421 // Happy to accomodate... 422 } 423 } 424 425 return features; 426} 427 428static int saved_features = 0; 429 430void VM_Version::allow_all() { 431 saved_features = _features; 432 _features = all_features_m; 433} 434 435void VM_Version::revert() { 436 _features = saved_features; 437} 438 439unsigned int VM_Version::calc_parallel_worker_threads() { 440 unsigned int result; 441 if (is_M_series()) { 442 // for now, use same gc thread calculation for M-series as for niagara-plus 443 // in future, we may want to tweak parameters for nof_parallel_worker_thread 444 result = nof_parallel_worker_threads(5, 16, 8); 445 } else if (is_niagara_plus()) { 446 result = nof_parallel_worker_threads(5, 16, 8); 447 } else { 448 result = nof_parallel_worker_threads(5, 8, 8); 449 } 450 return result; 451} 452