vm_version_sparc.cpp revision 13216:3a11d383f61e
1/* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25#include "precompiled.hpp" 26#include "asm/macroAssembler.inline.hpp" 27#include "logging/log.hpp" 28#include "memory/resourceArea.hpp" 29#include "prims/jvm.h" 30#include "runtime/java.hpp" 31#include "runtime/os.hpp" 32#include "runtime/stubCodeGenerator.hpp" 33#include "vm_version_sparc.hpp" 34 35#include <sys/mman.h> 36 37uint VM_Version::_L2_data_cache_line_size = 0; 38 39void VM_Version::initialize() { 40 assert(_features != 0, "System pre-initialization is not complete."); 41 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported"); 42 43 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 44 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 45 PrefetchFieldsAhead = prefetch_fields_ahead(); 46 47 // Allocation prefetch settings 48 49 AllocatePrefetchDistance = allocate_prefetch_distance(); 50 AllocatePrefetchStyle = allocate_prefetch_style(); 51 52 intx cache_line_size = prefetch_data_size(); 53 54 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize)) { 55 AllocatePrefetchStepSize = MAX2(AllocatePrefetchStepSize, cache_line_size); 56 } 57 58 if (AllocatePrefetchInstr == 1) { 59 if (!has_blk_init()) { 60 warning("BIS instructions required for AllocatePrefetchInstr 1 unavailable"); 61 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0); 62 } 63 if (cache_line_size <= 0) { 64 warning("Cache-line size must be known for AllocatePrefetchInstr 1 to work"); 65 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0); 66 } 67 } 68 69 UseSSE = false; // Only used on x86 and x64. 70 71 _supports_cx8 = true; // All SPARC V9 implementations. 72 _supports_atomic_getset4 = true; // Using the 'swap' instruction. 73 74 if (has_fast_ind_br() && FLAG_IS_DEFAULT(UseInlineCaches)) { 75 // Indirect and direct branches are cost equivalent. 76 FLAG_SET_DEFAULT(UseInlineCaches, false); 77 } 78 // Align loops on the proper instruction boundary to fill the instruction 79 // fetch buffer. 80 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) { 81 FLAG_SET_DEFAULT(OptoLoopAlignment, VM_Version::insn_fetch_alignment); 82 } 83 84 // 32-bit oops don't make sense for the 64-bit VM on SPARC since the 32-bit 85 // VM has the same registers and smaller objects. 86 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes); 87 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes); 88 89#ifdef COMPILER2 90 if (has_fast_ind_br() && FLAG_IS_DEFAULT(UseJumpTables)) { 91 // Indirect and direct branches are cost equivalent. 92 FLAG_SET_DEFAULT(UseJumpTables, true); 93 } 94 // Entry and loop tops are aligned to fill the instruction fetch buffer. 95 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) { 96 FLAG_SET_DEFAULT(InteriorEntryAlignment, VM_Version::insn_fetch_alignment); 97 } 98 if (UseTLAB && cache_line_size > 0 && 99 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { 100 if (has_fast_bis()) { 101 // Use BIS instruction for TLAB allocation prefetch. 102 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1); 103 } 104 else if (has_sparc5()) { 105 // Use prefetch instruction to avoid partial RAW issue on Core S4 processors, 106 // also use prefetch style 3. 107 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0); 108 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { 109 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3); 110 } 111 } 112 } 113 if (AllocatePrefetchInstr == 1) { 114 // Use allocation prefetch style 3 because BIS instructions require 115 // aligned memory addresses. 116 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3); 117 } 118 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { 119 if (AllocatePrefetchInstr == 0) { 120 // Use different prefetch distance without BIS 121 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); 122 } else { 123 // Use smaller prefetch distance with BIS 124 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64); 125 } 126 } 127 128 // We increase the number of prefetched cache lines, to use just a bit more 129 // aggressive approach, when the L2-cache line size is small (32 bytes), or 130 // when running on newer processor implementations, such as the Core S4. 131 bool inc_prefetch = cache_line_size > 0 && (cache_line_size < 64 || has_sparc5()); 132 133 if (inc_prefetch) { 134 // We use a factor two for small cache line sizes (as before) but a slightly 135 // more conservative increase when running on more recent hardware that will 136 // benefit from just a bit more aggressive prefetching. 137 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { 138 const int ap_lns = AllocatePrefetchLines; 139 const int ap_inc = cache_line_size < 64 ? ap_lns : (ap_lns + 1) / 2; 140 FLAG_SET_ERGO(intx, AllocatePrefetchLines, ap_lns + ap_inc); 141 } 142 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) { 143 const int ip_lns = AllocateInstancePrefetchLines; 144 const int ip_inc = cache_line_size < 64 ? ip_lns : (ip_lns + 1) / 2; 145 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, ip_lns + ip_inc); 146 } 147 } 148#endif /* COMPILER2 */ 149 150 // Use hardware population count instruction if available. 151 if (has_popc()) { 152 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 153 FLAG_SET_DEFAULT(UsePopCountInstruction, true); 154 } 155 } else if (UsePopCountInstruction) { 156 warning("POPC instruction is not available on this CPU"); 157 FLAG_SET_DEFAULT(UsePopCountInstruction, false); 158 } 159 160 // Use compare and branch instructions if available. 161 if (has_cbcond()) { 162 if (FLAG_IS_DEFAULT(UseCBCond)) { 163 FLAG_SET_DEFAULT(UseCBCond, true); 164 } 165 } else if (UseCBCond) { 166 warning("CBCOND instruction is not available on this CPU"); 167 FLAG_SET_DEFAULT(UseCBCond, false); 168 } 169 170 assert(BlockZeroingLowLimit > 0, "invalid value"); 171 172 if (has_blk_zeroing() && cache_line_size > 0) { 173 if (FLAG_IS_DEFAULT(UseBlockZeroing)) { 174 FLAG_SET_DEFAULT(UseBlockZeroing, true); 175 } 176 } else if (UseBlockZeroing) { 177 warning("BIS zeroing instructions are not available on this CPU"); 178 FLAG_SET_DEFAULT(UseBlockZeroing, false); 179 } 180 181 assert(BlockCopyLowLimit > 0, "invalid value"); 182 183 if (has_blk_zeroing() && cache_line_size > 0) { 184 if (FLAG_IS_DEFAULT(UseBlockCopy)) { 185 FLAG_SET_DEFAULT(UseBlockCopy, true); 186 } 187 } else if (UseBlockCopy) { 188 warning("BIS instructions are not available or expensive on this CPU"); 189 FLAG_SET_DEFAULT(UseBlockCopy, false); 190 } 191 192#ifdef COMPILER2 193 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) { 194 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true); 195 } 196 197 // Currently not supported anywhere. 198 FLAG_SET_DEFAULT(UseFPUForSpilling, false); 199 200 MaxVectorSize = 8; 201 202 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 203#endif 204 205 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 206 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size"); 207 208 char buf[512]; 209 jio_snprintf(buf, sizeof(buf), 210 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 211 (has_v9() ? "v9" : ""), 212 (has_popc() ? ", popc" : ""), 213 (has_vis1() ? ", vis1" : ""), 214 (has_vis2() ? ", vis2" : ""), 215 (has_blk_init() ? ", blk_init" : ""), 216 (has_fmaf() ? ", fmaf" : ""), 217 (has_hpc() ? ", hpc" : ""), 218 (has_ima() ? ", ima" : ""), 219 (has_aes() ? ", aes" : ""), 220 (has_des() ? ", des" : ""), 221 (has_kasumi() ? ", kas" : ""), 222 (has_camellia() ? ", cam" : ""), 223 (has_md5() ? ", md5" : ""), 224 (has_sha1() ? ", sha1" : ""), 225 (has_sha256() ? ", sha256" : ""), 226 (has_sha512() ? ", sha512" : ""), 227 (has_mpmul() ? ", mpmul" : ""), 228 (has_mont() ? ", mont" : ""), 229 (has_pause() ? ", pause" : ""), 230 (has_cbcond() ? ", cbcond" : ""), 231 (has_crc32c() ? ", crc32c" : ""), 232 233 (has_athena_plus() ? ", athena_plus" : ""), 234 (has_vis3b() ? ", vis3b" : ""), 235 (has_adi() ? ", adi" : ""), 236 (has_sparc5() ? ", sparc5" : ""), 237 (has_mwait() ? ", mwait" : ""), 238 (has_xmpmul() ? ", xmpmul" : ""), 239 (has_xmont() ? ", xmont" : ""), 240 (has_pause_nsec() ? ", pause_nsec" : ""), 241 (has_vamask() ? ", vamask" : ""), 242 243 (has_fast_idiv() ? ", *idiv" : ""), 244 (has_fast_rdpc() ? ", *rdpc" : ""), 245 (has_fast_bis() ? ", *bis" : ""), 246 (has_fast_ld() ? ", *ld" : ""), 247 (has_fast_cmove() ? ", *cmove" : ""), 248 (has_fast_fxtof() ? ", *fxtof" : ""), 249 (has_fast_ind_br() ? ", *ind_br" : ""), 250 (has_blk_zeroing() ? ", *blk_zeroing" : "")); 251 252 assert(strlen(buf) >= 2, "must be"); 253 254 _features_string = os::strdup(buf); 255 256 log_info(os, cpu)("SPARC features detected: %s", _features_string); 257 258 // UseVIS is set to the smallest of what hardware supports and what the command 259 // line requires, i.e. you cannot set UseVIS to 3 on older UltraSparc which do 260 // not support it. 261 262 if (UseVIS > 3) UseVIS = 3; 263 if (UseVIS < 0) UseVIS = 0; 264 if (!has_vis3()) // Drop to 2 if no VIS3 support 265 UseVIS = MIN2((intx)2, UseVIS); 266 if (!has_vis2()) // Drop to 1 if no VIS2 support 267 UseVIS = MIN2((intx)1, UseVIS); 268 if (!has_vis1()) // Drop to 0 if no VIS1 support 269 UseVIS = 0; 270 271 if (has_aes()) { 272 if (FLAG_IS_DEFAULT(UseAES)) { 273 FLAG_SET_DEFAULT(UseAES, true); 274 } 275 if (!UseAES) { 276 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 277 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled."); 278 } 279 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 280 } else { 281 // The AES intrinsic stubs require AES instruction support (of course) 282 // but also require VIS3 mode or higher for instructions it use. 283 if (UseVIS > 2) { 284 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 285 FLAG_SET_DEFAULT(UseAESIntrinsics, true); 286 } 287 } else { 288 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 289 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled."); 290 } 291 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 292 } 293 } 294 } else if (UseAES || UseAESIntrinsics) { 295 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) { 296 warning("AES instructions are not available on this CPU"); 297 FLAG_SET_DEFAULT(UseAES, false); 298 } 299 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 300 warning("AES intrinsics are not available on this CPU"); 301 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 302 } 303 } 304 305 if (UseAESCTRIntrinsics) { 306 warning("AES/CTR intrinsics are not available on this CPU"); 307 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 308 } 309 310 // GHASH/GCM intrinsics 311 if (has_vis3() && (UseVIS > 2)) { 312 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { 313 UseGHASHIntrinsics = true; 314 } 315 } else if (UseGHASHIntrinsics) { 316 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics)) 317 warning("GHASH intrinsics require VIS3 instruction support. Intrinsics will be disabled"); 318 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 319 } 320 321 if (UseFMA) { 322 warning("FMA instructions are not available on this CPU"); 323 FLAG_SET_DEFAULT(UseFMA, false); 324 } 325 326 // SHA1, SHA256, and SHA512 instructions were added to SPARC at different times 327 if (has_sha1() || has_sha256() || has_sha512()) { 328 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions 329 if (FLAG_IS_DEFAULT(UseSHA)) { 330 FLAG_SET_DEFAULT(UseSHA, true); 331 } 332 } else { 333 if (UseSHA) { 334 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled."); 335 FLAG_SET_DEFAULT(UseSHA, false); 336 } 337 } 338 } else if (UseSHA) { 339 warning("SHA instructions are not available on this CPU"); 340 FLAG_SET_DEFAULT(UseSHA, false); 341 } 342 343 if (UseSHA && has_sha1()) { 344 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { 345 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); 346 } 347 } else if (UseSHA1Intrinsics) { 348 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); 349 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 350 } 351 352 if (UseSHA && has_sha256()) { 353 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { 354 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); 355 } 356 } else if (UseSHA256Intrinsics) { 357 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); 358 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 359 } 360 361 if (UseSHA && has_sha512()) { 362 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { 363 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); 364 } 365 } else if (UseSHA512Intrinsics) { 366 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); 367 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 368 } 369 370 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { 371 FLAG_SET_DEFAULT(UseSHA, false); 372 } 373 374 if (has_crc32c()) { 375 if (UseVIS > 2) { // CRC32C intrinsics use VIS3 instructions 376 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 377 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true); 378 } 379 } else { 380 if (UseCRC32CIntrinsics) { 381 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled."); 382 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 383 } 384 } 385 } else if (UseCRC32CIntrinsics) { 386 warning("CRC32C instruction is not available on this CPU"); 387 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 388 } 389 390 if (UseVIS > 2) { 391 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) { 392 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true); 393 } 394 } else if (UseAdler32Intrinsics) { 395 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled."); 396 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); 397 } 398 399 if (UseVIS > 2) { 400 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 401 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true); 402 } 403 } else if (UseCRC32Intrinsics) { 404 warning("SPARC CRC32 intrinsics require VIS3 instructions support. Intrinsics will be disabled"); 405 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); 406 } 407 408 if (UseVectorizedMismatchIntrinsic) { 409 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); 410 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 411 } 412 413 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && 414 (cache_line_size > ContendedPaddingWidth)) 415 ContendedPaddingWidth = cache_line_size; 416 417 // This machine does not allow unaligned memory accesses 418 if (UseUnalignedAccesses) { 419 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses)) 420 warning("Unaligned memory access is not available on this CPU"); 421 FLAG_SET_DEFAULT(UseUnalignedAccesses, false); 422 } 423 424 if (log_is_enabled(Info, os, cpu)) { 425 ResourceMark rm; 426 outputStream* log = Log(os, cpu)::info_stream(); 427 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size()); 428 log->print_cr("L2 data cache line size: %u", L2_data_cache_line_size()); 429 log->print("Allocation"); 430 if (AllocatePrefetchStyle <= 0) { 431 log->print(": no prefetching"); 432 } else { 433 log->print(" prefetching: "); 434 if (AllocatePrefetchInstr == 0) { 435 log->print("PREFETCH"); 436 } else if (AllocatePrefetchInstr == 1) { 437 log->print("BIS"); 438 } 439 if (AllocatePrefetchLines > 1) { 440 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); 441 } else { 442 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); 443 } 444 } 445 if (PrefetchCopyIntervalInBytes > 0) { 446 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); 447 } 448 if (PrefetchScanIntervalInBytes > 0) { 449 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); 450 } 451 if (PrefetchFieldsAhead > 0) { 452 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); 453 } 454 if (ContendedPaddingWidth > 0) { 455 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); 456 } 457 } 458} 459 460void VM_Version::print_features() { 461 tty->print("ISA features [0x%0" PRIx64 "]:", _features); 462 if (_features_string != NULL) { 463 tty->print(" %s", _features_string); 464 } 465 tty->cr(); 466} 467 468void VM_Version::determine_features() { 469 if (UseV8InstrsOnly) { 470 log_info(os, cpu)("SPARC V8 not supported"); 471 } 472 473 platform_features(); // platform_features() is os_arch specific 474 475 assert(has_v9(), "must be"); 476 477 if (UseNiagaraInstrs) { // Limit code generation to Niagara. 478 _features &= niagara1_msk; 479 } 480} 481 482static uint64_t saved_features = 0; 483 484void VM_Version::allow_all() { 485 saved_features = _features; 486 _features = full_feature_msk; 487} 488 489void VM_Version::revert() { 490 _features = saved_features; 491} 492 493/* Determine a suitable number of threads on this particular machine. 494 * 495 * FIXME: Simply checking the processor family is insufficient. 496 */ 497unsigned int VM_Version::calc_parallel_worker_threads() { 498 const int num = 5; 499 const int den = is_post_niagara() ? 16 : 8; 500 const int threshold = 8; 501 502 return nof_parallel_worker_threads(num, den, threshold); 503} 504