register_sparc.hpp revision 6760:22b98ab2a69f
1222417Sjulian/* 2222417Sjulian * Copyright (c) 2000, 2014, Oracle and/or its affiliates. All rights reserved. 3222417Sjulian * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4222417Sjulian * 5222417Sjulian * This code is free software; you can redistribute it and/or modify it 6222417Sjulian * under the terms of the GNU General Public License version 2 only, as 7222417Sjulian * published by the Free Software Foundation. 8222417Sjulian * 9222417Sjulian * This code is distributed in the hope that it will be useful, but WITHOUT 10222417Sjulian * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11222417Sjulian * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12222417Sjulian * version 2 for more details (a copy is included in the LICENSE file that 13222417Sjulian * accompanied this code). 14222417Sjulian * 15222417Sjulian * You should have received a copy of the GNU General Public License version 16222417Sjulian * 2 along with this work; if not, write to the Free Software Foundation, 17222417Sjulian * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18222417Sjulian * 19222417Sjulian * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20222417Sjulian * or visit www.oracle.com if you need additional information or have any 21222417Sjulian * questions. 22222417Sjulian * 23222417Sjulian */ 24222417Sjulian 25222417Sjulian#ifndef CPU_SPARC_VM_REGISTER_SPARC_HPP 26222417Sjulian#define CPU_SPARC_VM_REGISTER_SPARC_HPP 27222417Sjulian 28222417Sjulian#include "asm/register.hpp" 29222417Sjulian 30222417Sjulian// forward declaration 31222417Sjulianclass Address; 32222417Sjulianclass VMRegImpl; 33222417Sjuliantypedef VMRegImpl* VMReg; 34222417Sjulian 35222417Sjulian 36222417Sjulian// Use Register as shortcut 37222417Sjulianclass RegisterImpl; 38222417Sjuliantypedef RegisterImpl* Register; 39222417Sjulian 40222417Sjulian 41222417Sjulianinline Register as_Register(int encoding) { 42222417Sjulian return (Register)(intptr_t) encoding; 43222417Sjulian} 44222417Sjulian 45222417Sjulian// The implementation of integer registers for the SPARC architecture 46222417Sjulianclass RegisterImpl: public AbstractRegisterImpl { 47222417Sjulian public: 48222417Sjulian enum { 49222417Sjulian log_set_size = 3, // the number of bits to encode the set register number 50222417Sjulian number_of_sets = 4, // the number of registers sets (in, local, out, global) 51222417Sjulian number_of_registers = number_of_sets << log_set_size, 52222417Sjulian 53222417Sjulian iset_no = 3, ibase = iset_no << log_set_size, // the in register set 54222417Sjulian lset_no = 2, lbase = lset_no << log_set_size, // the local register set 55222417Sjulian oset_no = 1, obase = oset_no << log_set_size, // the output register set 56222417Sjulian gset_no = 0, gbase = gset_no << log_set_size // the global register set 57222417Sjulian }; 58222417Sjulian 59222417Sjulian 60222417Sjulian friend Register as_Register(int encoding); 61222417Sjulian // set specific construction 62222417Sjulian friend Register as_iRegister(int number); 63222417Sjulian friend Register as_lRegister(int number); 64222417Sjulian friend Register as_oRegister(int number); 65233941Savg friend Register as_gRegister(int number); 66222417Sjulian 67222417Sjulian inline VMReg as_VMReg(); 68222417Sjulian 69222417Sjulian // accessors 70233941Savg int encoding() const { assert(is_valid(), "invalid register"); return value(); } 71233941Savg const char* name() const; 72222417Sjulian 73233941Savg // testers 74222417Sjulian bool is_valid() const { return (0 <= (value()&0x7F) && (value()&0x7F) < number_of_registers); } 75222417Sjulian bool is_even() const { return (encoding() & 1) == 0; } 76222417Sjulian bool is_in() const { return (encoding() >> log_set_size) == iset_no; } 77222417Sjulian bool is_local() const { return (encoding() >> log_set_size) == lset_no; } 78233941Savg bool is_out() const { return (encoding() >> log_set_size) == oset_no; } 79233941Savg bool is_global() const { return (encoding() >> log_set_size) == gset_no; } 80222417Sjulian 81222417Sjulian // derived registers, offsets, and addresses 82222417Sjulian Register successor() const { return as_Register(encoding() + 1); } 83222417Sjulian 84222417Sjulian int input_number() const { 85222417Sjulian assert(is_in(), "must be input register"); 86222417Sjulian return encoding() - ibase; 87222417Sjulian } 88222417Sjulian 89222417Sjulian Register after_save() const { 90222417Sjulian assert(is_out() || is_global(), "register not visible after save"); 91222417Sjulian return is_out() ? as_Register(encoding() + (ibase - obase)) : (const Register)this; 92222417Sjulian } 93222417Sjulian 94222417Sjulian Register after_restore() const { 95222417Sjulian assert(is_in() || is_global(), "register not visible after restore"); 96222417Sjulian return is_in() ? as_Register(encoding() + (obase - ibase)) : (const Register)this; 97222417Sjulian } 98222417Sjulian 99222417Sjulian int sp_offset_in_saved_window() const { 100222417Sjulian assert(is_in() || is_local(), "only i and l registers are saved in frame"); 101222417Sjulian return encoding() - lbase; 102222417Sjulian } 103222417Sjulian 104222417Sjulian inline Address address_in_saved_window() const; // implemented in assembler_sparc.hpp 105222417Sjulian}; 106222417Sjulian 107222417Sjulian 108222417Sjulian// set specific construction 109222417Sjulianinline Register as_iRegister(int number) { return as_Register(RegisterImpl::ibase + number); } 110222417Sjulianinline Register as_lRegister(int number) { return as_Register(RegisterImpl::lbase + number); } 111222417Sjulianinline Register as_oRegister(int number) { return as_Register(RegisterImpl::obase + number); } 112222417Sjulianinline Register as_gRegister(int number) { return as_Register(RegisterImpl::gbase + number); } 113222417Sjulian 114222417Sjulian// The integer registers of the SPARC architecture 115222417Sjulian 116222417SjulianCONSTANT_REGISTER_DECLARATION(Register, noreg , (-1)); 117222417Sjulian 118222417SjulianCONSTANT_REGISTER_DECLARATION(Register, G0 , (RegisterImpl::gbase + 0)); 119222417SjulianCONSTANT_REGISTER_DECLARATION(Register, G1 , (RegisterImpl::gbase + 1)); 120222417SjulianCONSTANT_REGISTER_DECLARATION(Register, G2 , (RegisterImpl::gbase + 2)); 121222417SjulianCONSTANT_REGISTER_DECLARATION(Register, G3 , (RegisterImpl::gbase + 3)); 122222417SjulianCONSTANT_REGISTER_DECLARATION(Register, G4 , (RegisterImpl::gbase + 4)); 123222417SjulianCONSTANT_REGISTER_DECLARATION(Register, G5 , (RegisterImpl::gbase + 5)); 124222417SjulianCONSTANT_REGISTER_DECLARATION(Register, G6 , (RegisterImpl::gbase + 6)); 125222417SjulianCONSTANT_REGISTER_DECLARATION(Register, G7 , (RegisterImpl::gbase + 7)); 126222417Sjulian 127222417SjulianCONSTANT_REGISTER_DECLARATION(Register, O0 , (RegisterImpl::obase + 0)); 128222417SjulianCONSTANT_REGISTER_DECLARATION(Register, O1 , (RegisterImpl::obase + 1)); 129222417SjulianCONSTANT_REGISTER_DECLARATION(Register, O2 , (RegisterImpl::obase + 2)); 130222417SjulianCONSTANT_REGISTER_DECLARATION(Register, O3 , (RegisterImpl::obase + 3)); 131222417SjulianCONSTANT_REGISTER_DECLARATION(Register, O4 , (RegisterImpl::obase + 4)); 132222417SjulianCONSTANT_REGISTER_DECLARATION(Register, O5 , (RegisterImpl::obase + 5)); 133222417SjulianCONSTANT_REGISTER_DECLARATION(Register, O6 , (RegisterImpl::obase + 6)); 134222417SjulianCONSTANT_REGISTER_DECLARATION(Register, O7 , (RegisterImpl::obase + 7)); 135222417Sjulian 136222417SjulianCONSTANT_REGISTER_DECLARATION(Register, L0 , (RegisterImpl::lbase + 0)); 137222417SjulianCONSTANT_REGISTER_DECLARATION(Register, L1 , (RegisterImpl::lbase + 1)); 138222417SjulianCONSTANT_REGISTER_DECLARATION(Register, L2 , (RegisterImpl::lbase + 2)); 139222417SjulianCONSTANT_REGISTER_DECLARATION(Register, L3 , (RegisterImpl::lbase + 3)); 140222417SjulianCONSTANT_REGISTER_DECLARATION(Register, L4 , (RegisterImpl::lbase + 4)); 141222417SjulianCONSTANT_REGISTER_DECLARATION(Register, L5 , (RegisterImpl::lbase + 5)); 142222417SjulianCONSTANT_REGISTER_DECLARATION(Register, L6 , (RegisterImpl::lbase + 6)); 143222417SjulianCONSTANT_REGISTER_DECLARATION(Register, L7 , (RegisterImpl::lbase + 7)); 144222417Sjulian 145222417SjulianCONSTANT_REGISTER_DECLARATION(Register, I0 , (RegisterImpl::ibase + 0)); 146222417SjulianCONSTANT_REGISTER_DECLARATION(Register, I1 , (RegisterImpl::ibase + 1)); 147222417SjulianCONSTANT_REGISTER_DECLARATION(Register, I2 , (RegisterImpl::ibase + 2)); 148222417SjulianCONSTANT_REGISTER_DECLARATION(Register, I3 , (RegisterImpl::ibase + 3)); 149222417SjulianCONSTANT_REGISTER_DECLARATION(Register, I4 , (RegisterImpl::ibase + 4)); 150222417SjulianCONSTANT_REGISTER_DECLARATION(Register, I5 , (RegisterImpl::ibase + 5)); 151222417SjulianCONSTANT_REGISTER_DECLARATION(Register, I6 , (RegisterImpl::ibase + 6)); 152222417SjulianCONSTANT_REGISTER_DECLARATION(Register, I7 , (RegisterImpl::ibase + 7)); 153222417Sjulian 154222417SjulianCONSTANT_REGISTER_DECLARATION(Register, FP , (RegisterImpl::ibase + 6)); 155222417SjulianCONSTANT_REGISTER_DECLARATION(Register, SP , (RegisterImpl::obase + 6)); 156222417Sjulian 157222417Sjulian// 158222417Sjulian// Because sparc has so many registers, #define'ing values for the is 159222417Sjulian// beneficial in code size and the cost of some of the dangers of 160222417Sjulian// defines. We don't use them on Intel because win32 uses asm 161222417Sjulian// directives which use the same names for registers as Hotspot does, 162222417Sjulian// so #defines would screw up the inline assembly. If a particular 163222417Sjulian// file has a problem with these defines then it's possible to turn 164222417Sjulian// them off in that file by defining DONT_USE_REGISTER_DEFINES. 165222417Sjulian// register_definition_sparc.cpp does that so that it's able to 166222417Sjulian// provide real definitions of these registers for use in debuggers 167222417Sjulian// and such. 168222417Sjulian// 169222417Sjulian 170222417Sjulian#ifndef DONT_USE_REGISTER_DEFINES 171222417Sjulian#define noreg ((Register)(noreg_RegisterEnumValue)) 172222417Sjulian 173222417Sjulian#define G0 ((Register)(G0_RegisterEnumValue)) 174222417Sjulian#define G1 ((Register)(G1_RegisterEnumValue)) 175222417Sjulian#define G2 ((Register)(G2_RegisterEnumValue)) 176222417Sjulian#define G3 ((Register)(G3_RegisterEnumValue)) 177222417Sjulian#define G4 ((Register)(G4_RegisterEnumValue)) 178222417Sjulian#define G5 ((Register)(G5_RegisterEnumValue)) 179222417Sjulian#define G6 ((Register)(G6_RegisterEnumValue)) 180222417Sjulian#define G7 ((Register)(G7_RegisterEnumValue)) 181222417Sjulian 182#define O0 ((Register)(O0_RegisterEnumValue)) 183#define O1 ((Register)(O1_RegisterEnumValue)) 184#define O2 ((Register)(O2_RegisterEnumValue)) 185#define O3 ((Register)(O3_RegisterEnumValue)) 186#define O4 ((Register)(O4_RegisterEnumValue)) 187#define O5 ((Register)(O5_RegisterEnumValue)) 188#define O6 ((Register)(O6_RegisterEnumValue)) 189#define O7 ((Register)(O7_RegisterEnumValue)) 190 191#define L0 ((Register)(L0_RegisterEnumValue)) 192#define L1 ((Register)(L1_RegisterEnumValue)) 193#define L2 ((Register)(L2_RegisterEnumValue)) 194#define L3 ((Register)(L3_RegisterEnumValue)) 195#define L4 ((Register)(L4_RegisterEnumValue)) 196#define L5 ((Register)(L5_RegisterEnumValue)) 197#define L6 ((Register)(L6_RegisterEnumValue)) 198#define L7 ((Register)(L7_RegisterEnumValue)) 199 200#define I0 ((Register)(I0_RegisterEnumValue)) 201#define I1 ((Register)(I1_RegisterEnumValue)) 202#define I2 ((Register)(I2_RegisterEnumValue)) 203#define I3 ((Register)(I3_RegisterEnumValue)) 204#define I4 ((Register)(I4_RegisterEnumValue)) 205#define I5 ((Register)(I5_RegisterEnumValue)) 206#define I6 ((Register)(I6_RegisterEnumValue)) 207#define I7 ((Register)(I7_RegisterEnumValue)) 208 209#define FP ((Register)(FP_RegisterEnumValue)) 210#define SP ((Register)(SP_RegisterEnumValue)) 211#endif // DONT_USE_REGISTER_DEFINES 212 213// Use FloatRegister as shortcut 214class FloatRegisterImpl; 215typedef FloatRegisterImpl* FloatRegister; 216 217 218// construction 219inline FloatRegister as_FloatRegister(int encoding) { 220 return (FloatRegister)(intptr_t)encoding; 221} 222 223// The implementation of float registers for the SPARC architecture 224 225class FloatRegisterImpl: public AbstractRegisterImpl { 226 public: 227 enum { 228 number_of_registers = 64 229 }; 230 231 enum Width { 232 S = 1, D = 2, Q = 3 233 }; 234 235 // construction 236 inline VMReg as_VMReg( ); 237 238 // accessors 239 int encoding() const { assert(is_valid(), "invalid register"); return value(); } 240 241 public: 242 int encoding(Width w) const { 243 const int c = encoding(); 244 switch (w) { 245 case S: 246 assert(c < 32, "bad single float register"); 247 return c; 248 249 case D: 250 assert(c < 64 && (c & 1) == 0, "bad double float register"); 251 return (c & 0x1e) | ((c & 0x20) >> 5); 252 253 case Q: 254 assert(c < 64 && (c & 3) == 0, "bad quad float register"); 255 return (c & 0x1c) | ((c & 0x20) >> 5); 256 } 257 ShouldNotReachHere(); 258 return -1; 259 } 260 261 bool is_valid() const { return 0 <= value() && value() < number_of_registers; } 262 const char* name() const; 263 264 FloatRegister successor() const { return as_FloatRegister(encoding() + 1); } 265}; 266 267 268// The float registers of the SPARC architecture 269 270CONSTANT_REGISTER_DECLARATION(FloatRegister, fnoreg , (-1)); 271 272CONSTANT_REGISTER_DECLARATION(FloatRegister, F0 , ( 0)); 273CONSTANT_REGISTER_DECLARATION(FloatRegister, F1 , ( 1)); 274CONSTANT_REGISTER_DECLARATION(FloatRegister, F2 , ( 2)); 275CONSTANT_REGISTER_DECLARATION(FloatRegister, F3 , ( 3)); 276CONSTANT_REGISTER_DECLARATION(FloatRegister, F4 , ( 4)); 277CONSTANT_REGISTER_DECLARATION(FloatRegister, F5 , ( 5)); 278CONSTANT_REGISTER_DECLARATION(FloatRegister, F6 , ( 6)); 279CONSTANT_REGISTER_DECLARATION(FloatRegister, F7 , ( 7)); 280CONSTANT_REGISTER_DECLARATION(FloatRegister, F8 , ( 8)); 281CONSTANT_REGISTER_DECLARATION(FloatRegister, F9 , ( 9)); 282CONSTANT_REGISTER_DECLARATION(FloatRegister, F10 , (10)); 283CONSTANT_REGISTER_DECLARATION(FloatRegister, F11 , (11)); 284CONSTANT_REGISTER_DECLARATION(FloatRegister, F12 , (12)); 285CONSTANT_REGISTER_DECLARATION(FloatRegister, F13 , (13)); 286CONSTANT_REGISTER_DECLARATION(FloatRegister, F14 , (14)); 287CONSTANT_REGISTER_DECLARATION(FloatRegister, F15 , (15)); 288CONSTANT_REGISTER_DECLARATION(FloatRegister, F16 , (16)); 289CONSTANT_REGISTER_DECLARATION(FloatRegister, F17 , (17)); 290CONSTANT_REGISTER_DECLARATION(FloatRegister, F18 , (18)); 291CONSTANT_REGISTER_DECLARATION(FloatRegister, F19 , (19)); 292CONSTANT_REGISTER_DECLARATION(FloatRegister, F20 , (20)); 293CONSTANT_REGISTER_DECLARATION(FloatRegister, F21 , (21)); 294CONSTANT_REGISTER_DECLARATION(FloatRegister, F22 , (22)); 295CONSTANT_REGISTER_DECLARATION(FloatRegister, F23 , (23)); 296CONSTANT_REGISTER_DECLARATION(FloatRegister, F24 , (24)); 297CONSTANT_REGISTER_DECLARATION(FloatRegister, F25 , (25)); 298CONSTANT_REGISTER_DECLARATION(FloatRegister, F26 , (26)); 299CONSTANT_REGISTER_DECLARATION(FloatRegister, F27 , (27)); 300CONSTANT_REGISTER_DECLARATION(FloatRegister, F28 , (28)); 301CONSTANT_REGISTER_DECLARATION(FloatRegister, F29 , (29)); 302CONSTANT_REGISTER_DECLARATION(FloatRegister, F30 , (30)); 303CONSTANT_REGISTER_DECLARATION(FloatRegister, F31 , (31)); 304 305CONSTANT_REGISTER_DECLARATION(FloatRegister, F32 , (32)); 306CONSTANT_REGISTER_DECLARATION(FloatRegister, F34 , (34)); 307CONSTANT_REGISTER_DECLARATION(FloatRegister, F36 , (36)); 308CONSTANT_REGISTER_DECLARATION(FloatRegister, F38 , (38)); 309CONSTANT_REGISTER_DECLARATION(FloatRegister, F40 , (40)); 310CONSTANT_REGISTER_DECLARATION(FloatRegister, F42 , (42)); 311CONSTANT_REGISTER_DECLARATION(FloatRegister, F44 , (44)); 312CONSTANT_REGISTER_DECLARATION(FloatRegister, F46 , (46)); 313CONSTANT_REGISTER_DECLARATION(FloatRegister, F48 , (48)); 314CONSTANT_REGISTER_DECLARATION(FloatRegister, F50 , (50)); 315CONSTANT_REGISTER_DECLARATION(FloatRegister, F52 , (52)); 316CONSTANT_REGISTER_DECLARATION(FloatRegister, F54 , (54)); 317CONSTANT_REGISTER_DECLARATION(FloatRegister, F56 , (56)); 318CONSTANT_REGISTER_DECLARATION(FloatRegister, F58 , (58)); 319CONSTANT_REGISTER_DECLARATION(FloatRegister, F60 , (60)); 320CONSTANT_REGISTER_DECLARATION(FloatRegister, F62 , (62)); 321 322 323#ifndef DONT_USE_REGISTER_DEFINES 324#define fnoreg ((FloatRegister)(fnoreg_FloatRegisterEnumValue)) 325#define F0 ((FloatRegister)( F0_FloatRegisterEnumValue)) 326#define F1 ((FloatRegister)( F1_FloatRegisterEnumValue)) 327#define F2 ((FloatRegister)( F2_FloatRegisterEnumValue)) 328#define F3 ((FloatRegister)( F3_FloatRegisterEnumValue)) 329#define F4 ((FloatRegister)( F4_FloatRegisterEnumValue)) 330#define F5 ((FloatRegister)( F5_FloatRegisterEnumValue)) 331#define F6 ((FloatRegister)( F6_FloatRegisterEnumValue)) 332#define F7 ((FloatRegister)( F7_FloatRegisterEnumValue)) 333#define F8 ((FloatRegister)( F8_FloatRegisterEnumValue)) 334#define F9 ((FloatRegister)( F9_FloatRegisterEnumValue)) 335#define F10 ((FloatRegister)( F10_FloatRegisterEnumValue)) 336#define F11 ((FloatRegister)( F11_FloatRegisterEnumValue)) 337#define F12 ((FloatRegister)( F12_FloatRegisterEnumValue)) 338#define F13 ((FloatRegister)( F13_FloatRegisterEnumValue)) 339#define F14 ((FloatRegister)( F14_FloatRegisterEnumValue)) 340#define F15 ((FloatRegister)( F15_FloatRegisterEnumValue)) 341#define F16 ((FloatRegister)( F16_FloatRegisterEnumValue)) 342#define F17 ((FloatRegister)( F17_FloatRegisterEnumValue)) 343#define F18 ((FloatRegister)( F18_FloatRegisterEnumValue)) 344#define F19 ((FloatRegister)( F19_FloatRegisterEnumValue)) 345#define F20 ((FloatRegister)( F20_FloatRegisterEnumValue)) 346#define F21 ((FloatRegister)( F21_FloatRegisterEnumValue)) 347#define F22 ((FloatRegister)( F22_FloatRegisterEnumValue)) 348#define F23 ((FloatRegister)( F23_FloatRegisterEnumValue)) 349#define F24 ((FloatRegister)( F24_FloatRegisterEnumValue)) 350#define F25 ((FloatRegister)( F25_FloatRegisterEnumValue)) 351#define F26 ((FloatRegister)( F26_FloatRegisterEnumValue)) 352#define F27 ((FloatRegister)( F27_FloatRegisterEnumValue)) 353#define F28 ((FloatRegister)( F28_FloatRegisterEnumValue)) 354#define F29 ((FloatRegister)( F29_FloatRegisterEnumValue)) 355#define F30 ((FloatRegister)( F30_FloatRegisterEnumValue)) 356#define F31 ((FloatRegister)( F31_FloatRegisterEnumValue)) 357#define F32 ((FloatRegister)( F32_FloatRegisterEnumValue)) 358#define F34 ((FloatRegister)( F34_FloatRegisterEnumValue)) 359#define F36 ((FloatRegister)( F36_FloatRegisterEnumValue)) 360#define F38 ((FloatRegister)( F38_FloatRegisterEnumValue)) 361#define F40 ((FloatRegister)( F40_FloatRegisterEnumValue)) 362#define F42 ((FloatRegister)( F42_FloatRegisterEnumValue)) 363#define F44 ((FloatRegister)( F44_FloatRegisterEnumValue)) 364#define F46 ((FloatRegister)( F46_FloatRegisterEnumValue)) 365#define F48 ((FloatRegister)( F48_FloatRegisterEnumValue)) 366#define F50 ((FloatRegister)( F50_FloatRegisterEnumValue)) 367#define F52 ((FloatRegister)( F52_FloatRegisterEnumValue)) 368#define F54 ((FloatRegister)( F54_FloatRegisterEnumValue)) 369#define F56 ((FloatRegister)( F56_FloatRegisterEnumValue)) 370#define F58 ((FloatRegister)( F58_FloatRegisterEnumValue)) 371#define F60 ((FloatRegister)( F60_FloatRegisterEnumValue)) 372#define F62 ((FloatRegister)( F62_FloatRegisterEnumValue)) 373#endif // DONT_USE_REGISTER_DEFINES 374 375// Maximum number of incoming arguments that can be passed in i registers. 376const int SPARC_ARGS_IN_REGS_NUM = 6; 377 378class ConcreteRegisterImpl : public AbstractRegisterImpl { 379 public: 380 enum { 381 // This number must be large enough to cover REG_COUNT (defined by c2) registers. 382 // There is no requirement that any ordering here matches any ordering c2 gives 383 // it's optoregs. 384 number_of_registers = 2*RegisterImpl::number_of_registers + 385 FloatRegisterImpl::number_of_registers + 386 1 + // ccr 387 4 // fcc 388 }; 389 static const int max_gpr; 390 static const int max_fpr; 391 392}; 393 394// Single, Double and Quad fp reg classes. These exist to map the ADLC 395// encoding for a floating point register, to the FloatRegister number 396// desired by the macroassembler. A FloatRegister is a number between 397// 0 and 63 passed around as a pointer. For ADLC, an fp register encoding 398// is the actual bit encoding used by the sparc hardware. When ADLC used 399// the macroassembler to generate an instruction that references, e.g., a 400// double fp reg, it passed the bit encoding to the macroassembler via 401// as_FloatRegister, which, for double regs > 30, returns an illegal 402// register number. 403// 404// Therefore we provide the following classes for use by ADLC. Their 405// sole purpose is to convert from sparc register encodings to FloatRegisters. 406// At some future time, we might replace FloatRegister with these classes, 407// hence the definitions of as_xxxFloatRegister as class methods rather 408// than as external inline routines. 409 410class SingleFloatRegisterImpl; 411typedef SingleFloatRegisterImpl *SingleFloatRegister; 412 413inline FloatRegister as_SingleFloatRegister(int encoding); 414class SingleFloatRegisterImpl { 415 public: 416 friend inline FloatRegister as_SingleFloatRegister(int encoding) { 417 assert(encoding < 32, "bad single float register encoding"); 418 return as_FloatRegister(encoding); 419 } 420}; 421 422 423class DoubleFloatRegisterImpl; 424typedef DoubleFloatRegisterImpl *DoubleFloatRegister; 425 426inline FloatRegister as_DoubleFloatRegister(int encoding); 427class DoubleFloatRegisterImpl { 428 public: 429 friend inline FloatRegister as_DoubleFloatRegister(int encoding) { 430 assert(encoding < 32, "bad double float register encoding"); 431 return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1e) ); 432 } 433}; 434 435 436class QuadFloatRegisterImpl; 437typedef QuadFloatRegisterImpl *QuadFloatRegister; 438 439class QuadFloatRegisterImpl { 440 public: 441 friend FloatRegister as_QuadFloatRegister(int encoding) { 442 assert(encoding < 32 && ((encoding & 2) == 0), "bad quad float register encoding"); 443 return as_FloatRegister( ((encoding & 1) << 5) | (encoding & 0x1c) ); 444 } 445}; 446 447#endif // CPU_SPARC_VM_REGISTER_SPARC_HPP 448