c1_FrameMap_sparc.cpp revision 1879:f95d63e2154a
1108930Speter/* 244743Smarkm * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. 344743Smarkm * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 444743Smarkm * 544743Smarkm * This code is free software; you can redistribute it and/or modify it 644743Smarkm * under the terms of the GNU General Public License version 2 only, as 744743Smarkm * published by the Free Software Foundation. 844743Smarkm * 944743Smarkm * This code is distributed in the hope that it will be useful, but WITHOUT 1044743Smarkm * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1144743Smarkm * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 1244743Smarkm * version 2 for more details (a copy is included in the LICENSE file that 1344743Smarkm * accompanied this code). 1444743Smarkm * 1544743Smarkm * You should have received a copy of the GNU General Public License version 1644743Smarkm * 2 along with this work; if not, write to the Free Software Foundation, 1744743Smarkm * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 1844743Smarkm * 1944743Smarkm * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 2044743Smarkm * or visit www.oracle.com if you need additional information or have any 21108930Speter * questions. 2244743Smarkm * 2344743Smarkm */ 2444743Smarkm 2544743Smarkm#include "precompiled.hpp" 2644743Smarkm#include "c1/c1_FrameMap.hpp" 2744743Smarkm#include "c1/c1_LIR.hpp" 2844743Smarkm#include "runtime/sharedRuntime.hpp" 2944743Smarkm#include "vmreg_sparc.inline.hpp" 3044743Smarkm 3144743Smarkm 3244743Smarkmconst int FrameMap::pd_c_runtime_reserved_arg_size = 7; 3344743Smarkm 3444743Smarkm 3544743SmarkmLIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) { 3644743Smarkm LIR_Opr opr = LIR_OprFact::illegalOpr; 3744743Smarkm VMReg r_1 = reg->first(); 3844743Smarkm VMReg r_2 = reg->second(); 3944743Smarkm if (r_1->is_stack()) { 4044743Smarkm // Convert stack slot to an SP offset 4144743Smarkm // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value 4244743Smarkm // so we must add it in here. 4344743Smarkm int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; 4444743Smarkm opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type)); 4544743Smarkm } else if (r_1->is_Register()) { 4644743Smarkm Register reg = r_1->as_Register(); 4744743Smarkm if (outgoing) { 4844743Smarkm assert(!reg->is_in(), "should be using I regs"); 4944743Smarkm } else { 5044743Smarkm assert(!reg->is_out(), "should be using O regs"); 5144743Smarkm } 5244743Smarkm if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) { 5344743Smarkm opr = as_long_opr(reg); 5444743Smarkm } else if (type == T_OBJECT || type == T_ARRAY) { 5544743Smarkm opr = as_oop_opr(reg); 5644743Smarkm } else { 5744743Smarkm opr = as_opr(reg); 5844743Smarkm } 5944743Smarkm } else if (r_1->is_FloatRegister()) { 6044743Smarkm assert(type == T_DOUBLE || type == T_FLOAT, "wrong type"); 6144743Smarkm FloatRegister f = r_1->as_FloatRegister(); 6244743Smarkm if (type == T_DOUBLE) { 6344743Smarkm opr = as_double_opr(f); 6444743Smarkm } else { 6544743Smarkm opr = as_float_opr(f); 6644743Smarkm } 6744743Smarkm } 6844743Smarkm return opr; 6944743Smarkm} 7044743Smarkm 7144743Smarkm// FrameMap 7244743Smarkm//-------------------------------------------------------- 7344743Smarkm 7444743SmarkmFloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs]; 7544743Smarkm 7644743Smarkm// some useful constant RInfo's: 7744743SmarkmLIR_Opr FrameMap::in_long_opr; 7844743SmarkmLIR_Opr FrameMap::out_long_opr; 7944743SmarkmLIR_Opr FrameMap::g1_long_single_opr; 8044743Smarkm 8144743SmarkmLIR_Opr FrameMap::F0_opr; 8244743SmarkmLIR_Opr FrameMap::F0_double_opr; 8344743Smarkm 8444743SmarkmLIR_Opr FrameMap::G0_opr; 8544743SmarkmLIR_Opr FrameMap::G1_opr; 8644743SmarkmLIR_Opr FrameMap::G2_opr; 8744743SmarkmLIR_Opr FrameMap::G3_opr; 8844743SmarkmLIR_Opr FrameMap::G4_opr; 8944743SmarkmLIR_Opr FrameMap::G5_opr; 9044743SmarkmLIR_Opr FrameMap::G6_opr; 9144743SmarkmLIR_Opr FrameMap::G7_opr; 9244743SmarkmLIR_Opr FrameMap::O0_opr; 9344743SmarkmLIR_Opr FrameMap::O1_opr; 9444743SmarkmLIR_Opr FrameMap::O2_opr; 9544743SmarkmLIR_Opr FrameMap::O3_opr; 9644743SmarkmLIR_Opr FrameMap::O4_opr; 9744743SmarkmLIR_Opr FrameMap::O5_opr; 9844743SmarkmLIR_Opr FrameMap::O6_opr; 9944743SmarkmLIR_Opr FrameMap::O7_opr; 10044743SmarkmLIR_Opr FrameMap::L0_opr; 10144743SmarkmLIR_Opr FrameMap::L1_opr; 10244743SmarkmLIR_Opr FrameMap::L2_opr; 10344743SmarkmLIR_Opr FrameMap::L3_opr; 10444743SmarkmLIR_Opr FrameMap::L4_opr; 10544743SmarkmLIR_Opr FrameMap::L5_opr; 10644743SmarkmLIR_Opr FrameMap::L6_opr; 10744743SmarkmLIR_Opr FrameMap::L7_opr; 10844743SmarkmLIR_Opr FrameMap::I0_opr; 10944743SmarkmLIR_Opr FrameMap::I1_opr; 11044743SmarkmLIR_Opr FrameMap::I2_opr; 11144743SmarkmLIR_Opr FrameMap::I3_opr; 11244743SmarkmLIR_Opr FrameMap::I4_opr; 11344743SmarkmLIR_Opr FrameMap::I5_opr; 11444743SmarkmLIR_Opr FrameMap::I6_opr; 11544743SmarkmLIR_Opr FrameMap::I7_opr; 11644743Smarkm 11744743SmarkmLIR_Opr FrameMap::G0_oop_opr; 11844743SmarkmLIR_Opr FrameMap::G1_oop_opr; 11944743SmarkmLIR_Opr FrameMap::G2_oop_opr; 12044743SmarkmLIR_Opr FrameMap::G3_oop_opr; 12144743SmarkmLIR_Opr FrameMap::G4_oop_opr; 12244743SmarkmLIR_Opr FrameMap::G5_oop_opr; 12344743SmarkmLIR_Opr FrameMap::G6_oop_opr; 12444743SmarkmLIR_Opr FrameMap::G7_oop_opr; 12544743SmarkmLIR_Opr FrameMap::O0_oop_opr; 12644743SmarkmLIR_Opr FrameMap::O1_oop_opr; 12744743SmarkmLIR_Opr FrameMap::O2_oop_opr; 12844743SmarkmLIR_Opr FrameMap::O3_oop_opr; 12944743SmarkmLIR_Opr FrameMap::O4_oop_opr; 13044743SmarkmLIR_Opr FrameMap::O5_oop_opr; 13144743SmarkmLIR_Opr FrameMap::O6_oop_opr; 13244743SmarkmLIR_Opr FrameMap::O7_oop_opr; 13344743SmarkmLIR_Opr FrameMap::L0_oop_opr; 13444743SmarkmLIR_Opr FrameMap::L1_oop_opr; 13544743SmarkmLIR_Opr FrameMap::L2_oop_opr; 13644743SmarkmLIR_Opr FrameMap::L3_oop_opr; 13744743SmarkmLIR_Opr FrameMap::L4_oop_opr; 13844743SmarkmLIR_Opr FrameMap::L5_oop_opr; 13944743SmarkmLIR_Opr FrameMap::L6_oop_opr; 14044743SmarkmLIR_Opr FrameMap::L7_oop_opr; 14144743SmarkmLIR_Opr FrameMap::I0_oop_opr; 14244743SmarkmLIR_Opr FrameMap::I1_oop_opr; 14344743SmarkmLIR_Opr FrameMap::I2_oop_opr; 14444743SmarkmLIR_Opr FrameMap::I3_oop_opr; 14544743SmarkmLIR_Opr FrameMap::I4_oop_opr; 14644743SmarkmLIR_Opr FrameMap::I5_oop_opr; 14744743SmarkmLIR_Opr FrameMap::I6_oop_opr; 14844743SmarkmLIR_Opr FrameMap::I7_oop_opr; 14944743Smarkm 15044743SmarkmLIR_Opr FrameMap::SP_opr; 15144743SmarkmLIR_Opr FrameMap::FP_opr; 15244743Smarkm 15344743SmarkmLIR_Opr FrameMap::Oexception_opr; 15444743SmarkmLIR_Opr FrameMap::Oissuing_pc_opr; 15544743Smarkm 15644743SmarkmLIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, }; 15744743SmarkmLIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, }; 15844743Smarkm 15944743Smarkm 16044743SmarkmFloatRegister FrameMap::nr2floatreg (int rnr) { 16144743Smarkm assert(_init_done, "tables not initialized"); 16244743Smarkm debug_only(fpu_range_check(rnr);) 16344743Smarkm return _fpu_regs[rnr]; 16444743Smarkm} 16544743Smarkm 16644743Smarkm 16744743Smarkm// returns true if reg could be smashed by a callee. 16844743Smarkmbool FrameMap::is_caller_save_register (LIR_Opr reg) { 16944743Smarkm if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; } 17044743Smarkm if (reg->is_double_cpu()) { 17144743Smarkm return is_caller_save_register(reg->as_register_lo()) || 17244743Smarkm is_caller_save_register(reg->as_register_hi()); 17344743Smarkm } 17444743Smarkm return is_caller_save_register(reg->as_register()); 17544743Smarkm} 17644743Smarkm 17744743Smarkm 17844743SmarkmNEEDS_CLEANUP // once the new calling convention is enabled, we no 17944743Smarkm // longer need to treat I5, I4 and L0 specially 18044743Smarkm// Because the interpreter destroys caller's I5, I4 and L0, 18144743Smarkm// we must spill them before doing a Java call as we may land in 18244743Smarkm// interpreter. 18344743Smarkmbool FrameMap::is_caller_save_register (Register r) { 18444743Smarkm return (r->is_global() && (r != G0)) || r->is_out(); 18544743Smarkm} 18644743Smarkm 18744743Smarkm 18844743Smarkmvoid FrameMap::initialize() { 18944743Smarkm assert(!_init_done, "once"); 19044743Smarkm 19144743Smarkm int i=0; 19244743Smarkm // Register usage: 19344743Smarkm // O6: sp 19444743Smarkm // I6: fp 19544743Smarkm // I7: return address 19644743Smarkm // G0: zero 19744743Smarkm // G2: thread 19844743Smarkm // G7: not available 19944743Smarkm // G6: not available 20044743Smarkm /* 0 */ map_register(i++, L0); 20144743Smarkm /* 1 */ map_register(i++, L1); 20244743Smarkm /* 2 */ map_register(i++, L2); 20344743Smarkm /* 3 */ map_register(i++, L3); 20444743Smarkm /* 4 */ map_register(i++, L4); 20544743Smarkm /* 5 */ map_register(i++, L5); 20644743Smarkm /* 6 */ map_register(i++, L6); 20744743Smarkm /* 7 */ map_register(i++, L7); 20844743Smarkm 20944743Smarkm /* 8 */ map_register(i++, I0); 21044743Smarkm /* 9 */ map_register(i++, I1); 21144743Smarkm /* 10 */ map_register(i++, I2); 21244743Smarkm /* 11 */ map_register(i++, I3); 21344743Smarkm /* 12 */ map_register(i++, I4); 21444743Smarkm /* 13 */ map_register(i++, I5); 21544743Smarkm /* 14 */ map_register(i++, O0); 21644743Smarkm /* 15 */ map_register(i++, O1); 21744743Smarkm /* 16 */ map_register(i++, O2); 21844743Smarkm /* 17 */ map_register(i++, O3); 21944743Smarkm /* 18 */ map_register(i++, O4); 22044743Smarkm /* 19 */ map_register(i++, O5); // <- last register visible in RegAlloc (RegAlloc::nof+cpu_regs) 22144743Smarkm /* 20 */ map_register(i++, G1); 22244743Smarkm /* 21 */ map_register(i++, G3); 22344743Smarkm /* 22 */ map_register(i++, G4); 22444743Smarkm /* 23 */ map_register(i++, G5); 22544743Smarkm /* 24 */ map_register(i++, G0); 22644743Smarkm 22744743Smarkm // the following registers are not normally available 22844743Smarkm /* 25 */ map_register(i++, O7); 22944743Smarkm /* 26 */ map_register(i++, G2); 23044743Smarkm /* 27 */ map_register(i++, O6); 23144743Smarkm /* 28 */ map_register(i++, I6); 23244743Smarkm /* 29 */ map_register(i++, I7); 23344743Smarkm /* 30 */ map_register(i++, G6); 23444743Smarkm /* 31 */ map_register(i++, G7); 23544743Smarkm assert(i == nof_cpu_regs, "number of CPU registers"); 23644743Smarkm 23744743Smarkm for (i = 0; i < nof_fpu_regs; i++) { 23844743Smarkm _fpu_regs[i] = as_FloatRegister(i); 23944743Smarkm } 24044743Smarkm 24144743Smarkm _init_done = true; 24244743Smarkm 24344743Smarkm in_long_opr = as_long_opr(I0); 24444743Smarkm out_long_opr = as_long_opr(O0); 24544743Smarkm g1_long_single_opr = as_long_single_opr(G1); 24644743Smarkm 24744743Smarkm G0_opr = as_opr(G0); 24844743Smarkm G1_opr = as_opr(G1); 24944743Smarkm G2_opr = as_opr(G2); 25044743Smarkm G3_opr = as_opr(G3); 25144743Smarkm G4_opr = as_opr(G4); 25244743Smarkm G5_opr = as_opr(G5); 25345256Sache G6_opr = as_opr(G6); 25445256Sache G7_opr = as_opr(G7); 25545256Sache O0_opr = as_opr(O0); 25644743Smarkm O1_opr = as_opr(O1); 25745256Sache O2_opr = as_opr(O2); 25844743Smarkm O3_opr = as_opr(O3); 25944743Smarkm O4_opr = as_opr(O4); 26044743Smarkm O5_opr = as_opr(O5); 26144743Smarkm O6_opr = as_opr(O6); 26244743Smarkm O7_opr = as_opr(O7); 26344743Smarkm L0_opr = as_opr(L0); 26444743Smarkm L1_opr = as_opr(L1); 26544743Smarkm L2_opr = as_opr(L2); 26644743Smarkm L3_opr = as_opr(L3); 26744743Smarkm L4_opr = as_opr(L4); 26844743Smarkm L5_opr = as_opr(L5); 26944743Smarkm L6_opr = as_opr(L6); 27044743Smarkm L7_opr = as_opr(L7); 27144743Smarkm I0_opr = as_opr(I0); 27244743Smarkm I1_opr = as_opr(I1); 27344743Smarkm I2_opr = as_opr(I2); 27444743Smarkm I3_opr = as_opr(I3); 27544743Smarkm I4_opr = as_opr(I4); 27644743Smarkm I5_opr = as_opr(I5); 27744743Smarkm I6_opr = as_opr(I6); 27844743Smarkm I7_opr = as_opr(I7); 27944743Smarkm 28044743Smarkm G0_oop_opr = as_oop_opr(G0); 28144743Smarkm G1_oop_opr = as_oop_opr(G1); 28244743Smarkm G2_oop_opr = as_oop_opr(G2); 28344743Smarkm G3_oop_opr = as_oop_opr(G3); 28444743Smarkm G4_oop_opr = as_oop_opr(G4); 28544743Smarkm G5_oop_opr = as_oop_opr(G5); 28644743Smarkm G6_oop_opr = as_oop_opr(G6); 28744743Smarkm G7_oop_opr = as_oop_opr(G7); 28844743Smarkm O0_oop_opr = as_oop_opr(O0); 28944743Smarkm O1_oop_opr = as_oop_opr(O1); 29044743Smarkm O2_oop_opr = as_oop_opr(O2); 29144743Smarkm O3_oop_opr = as_oop_opr(O3); 29244743Smarkm O4_oop_opr = as_oop_opr(O4); 29344743Smarkm O5_oop_opr = as_oop_opr(O5); 29444743Smarkm O6_oop_opr = as_oop_opr(O6); 29544743Smarkm O7_oop_opr = as_oop_opr(O7); 29644743Smarkm L0_oop_opr = as_oop_opr(L0); 29744743Smarkm L1_oop_opr = as_oop_opr(L1); 29844743Smarkm L2_oop_opr = as_oop_opr(L2); 29944743Smarkm L3_oop_opr = as_oop_opr(L3); 30044743Smarkm L4_oop_opr = as_oop_opr(L4); 30144743Smarkm L5_oop_opr = as_oop_opr(L5); 30244743Smarkm L6_oop_opr = as_oop_opr(L6); 30344743Smarkm L7_oop_opr = as_oop_opr(L7); 30444743Smarkm I0_oop_opr = as_oop_opr(I0); 30544743Smarkm I1_oop_opr = as_oop_opr(I1); 30644743Smarkm I2_oop_opr = as_oop_opr(I2); 30744743Smarkm I3_oop_opr = as_oop_opr(I3); 30844743Smarkm I4_oop_opr = as_oop_opr(I4); 30944743Smarkm I5_oop_opr = as_oop_opr(I5); 31044743Smarkm I6_oop_opr = as_oop_opr(I6); 31144743Smarkm I7_oop_opr = as_oop_opr(I7); 31244743Smarkm 31344743Smarkm FP_opr = as_pointer_opr(FP); 31444743Smarkm SP_opr = as_pointer_opr(SP); 31544743Smarkm 31644743Smarkm F0_opr = as_float_opr(F0); 31744743Smarkm F0_double_opr = as_double_opr(F0); 31844743Smarkm 31944743Smarkm Oexception_opr = as_oop_opr(Oexception); 32044743Smarkm Oissuing_pc_opr = as_opr(Oissuing_pc); 32144743Smarkm 32244743Smarkm _caller_save_cpu_regs[0] = FrameMap::O0_opr; 32344743Smarkm _caller_save_cpu_regs[1] = FrameMap::O1_opr; 324 _caller_save_cpu_regs[2] = FrameMap::O2_opr; 325 _caller_save_cpu_regs[3] = FrameMap::O3_opr; 326 _caller_save_cpu_regs[4] = FrameMap::O4_opr; 327 _caller_save_cpu_regs[5] = FrameMap::O5_opr; 328 _caller_save_cpu_regs[6] = FrameMap::G1_opr; 329 _caller_save_cpu_regs[7] = FrameMap::G3_opr; 330 _caller_save_cpu_regs[8] = FrameMap::G4_opr; 331 _caller_save_cpu_regs[9] = FrameMap::G5_opr; 332 for (int i = 0; i < nof_caller_save_fpu_regs; i++) { 333 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i); 334 } 335} 336 337 338Address FrameMap::make_new_address(ByteSize sp_offset) const { 339 return Address(SP, STACK_BIAS + in_bytes(sp_offset)); 340} 341 342 343VMReg FrameMap::fpu_regname (int n) { 344 return as_FloatRegister(n)->as_VMReg(); 345} 346 347 348LIR_Opr FrameMap::stack_pointer() { 349 return SP_opr; 350} 351 352 353// JSR 292 354LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() { 355 assert(L7 == L7_mh_SP_save, "must be same register"); 356 return L7_opr; 357} 358 359 360bool FrameMap::validate_frame() { 361 int max_offset = in_bytes(framesize_in_bytes()); 362 int java_index = 0; 363 for (int i = 0; i < _incoming_arguments->length(); i++) { 364 LIR_Opr opr = _incoming_arguments->at(i); 365 if (opr->is_stack()) { 366 max_offset = MAX2(_argument_locations->at(java_index), max_offset); 367 } 368 java_index += type2size[opr->type()]; 369 } 370 return Assembler::is_simm13(max_offset + STACK_BIAS); 371} 372