assembler_sparc.cpp revision 356:1ee8caae33af
1139804Simp/* 21541Srgrimes * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved. 31541Srgrimes * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 41541Srgrimes * 51541Srgrimes * This code is free software; you can redistribute it and/or modify it 61541Srgrimes * under the terms of the GNU General Public License version 2 only, as 71541Srgrimes * published by the Free Software Foundation. 81541Srgrimes * 91541Srgrimes * This code is distributed in the hope that it will be useful, but WITHOUT 101541Srgrimes * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 111541Srgrimes * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 121541Srgrimes * version 2 for more details (a copy is included in the LICENSE file that 131541Srgrimes * accompanied this code). 141541Srgrimes * 151541Srgrimes * You should have received a copy of the GNU General Public License version 161541Srgrimes * 2 along with this work; if not, write to the Free Software Foundation, 171541Srgrimes * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 181541Srgrimes * 191541Srgrimes * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 201541Srgrimes * CA 95054 USA or visit www.sun.com if you need additional information or 211541Srgrimes * have any questions. 221541Srgrimes * 231541Srgrimes */ 241541Srgrimes 251541Srgrimes#include "incls/_precompiled.incl" 261541Srgrimes#include "incls/_assembler_sparc.cpp.incl" 271541Srgrimes 281541Srgrimes// Implementation of Address 291541Srgrimes 301541SrgrimesAddress::Address( addr_type t, int which ) { 311541Srgrimes switch (t) { 32116182Sobrien case extra_in_argument: 33116182Sobrien case extra_out_argument: 34116182Sobrien _base = t == extra_in_argument ? FP : SP; 3513203Swollman _hi = 0; 36101123Srwatson// Warning: In LP64 mode, _disp will occupy more than 10 bits. 371541Srgrimes// This is inconsistent with the other constructors but op 381541Srgrimes// codes such as ld or ldx, only access disp() to get their 392112Swollman// simm13 argument. 4097993Sjhb _disp = ((which - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS; 4197993Sjhb break; 4297993Sjhb default: 4376166Smarkm ShouldNotReachHere(); 4476166Smarkm break; 45101123Srwatson } 4697993Sjhb} 4797993Sjhb 481541Srgrimesstatic const char* argumentNames[][2] = { 4997993Sjhb {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"}, 501541Srgrimes {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"}, 511541Srgrimes {"A(n>9)","P(n>9)"} 5274927Sjhb}; 5397993Sjhb 541541Srgrimesconst char* Argument::name() const { 5597993Sjhb int nofArgs = sizeof argumentNames / sizeof argumentNames[0]; 561541Srgrimes int num = number(); 5730354Sphk if (num >= nofArgs) num = nofArgs - 1; 5830309Sphk return argumentNames[num][is_in() ? 1 : 0]; 5913203Swollman} 6012577Sbde 6197993Sjhbvoid Assembler::print_instruction(int inst) { 6297993Sjhb const char* s; 6397993Sjhb switch (inv_op(inst)) { 6412819Sphk default: s = "????"; break; 6597993Sjhb case call_op: s = "call"; break; 6697993Sjhb case branch_op: 6797993Sjhb switch (inv_op2(inst)) { 6897993Sjhb case bpr_op2: s = "bpr"; break; 6997993Sjhb case fb_op2: s = "fb"; break; 7097993Sjhb case fbp_op2: s = "fbp"; break; 7197993Sjhb case br_op2: s = "br"; break; 7297993Sjhb case bp_op2: s = "bp"; break; 7397993Sjhb case cb_op2: s = "cb"; break; 7497993Sjhb default: s = "????"; break; 7597993Sjhb } 7697993Sjhb } 7797993Sjhb ::tty->print("%s", s); 7897993Sjhb} 7997993Sjhb 8097993Sjhb 8197993Sjhb// Patch instruction inst at offset inst_pos to refer to dest_pos 8297993Sjhb// and return the resulting instruction. 8397993Sjhb// We should have pcs, not offsets, but since all is relative, it will work out 8497993Sjhb// OK. 8597993Sjhbint Assembler::patched_branch(int dest_pos, int inst, int inst_pos) { 8697993Sjhb 8797993Sjhb int m; // mask for displacement field 8897993Sjhb int v; // new value for displacement field 8997993Sjhb const int word_aligned_ones = -4; 9097993Sjhb switch (inv_op(inst)) { 9197993Sjhb default: ShouldNotReachHere(); 9297993Sjhb case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break; 93141633Sphk case branch_op: 94103234Sjhb switch (inv_op2(inst)) { 95118607Sjhb case bpr_op2: m = wdisp16(word_aligned_ones, 0); v = wdisp16(dest_pos, inst_pos); break; 96103234Sjhb case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; 9797993Sjhb case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; 98118607Sjhb case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; 99103234Sjhb case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; 100103234Sjhb case cb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; 101103234Sjhb default: ShouldNotReachHere(); 102103234Sjhb } 10397993Sjhb } 10497993Sjhb return inst & ~m | v; 105126295Sjhb} 10697993Sjhb 10797993Sjhb// Return the offset of the branch destionation of instruction inst 10897993Sjhb// at offset pos. 109118607Sjhb// Should have pcs, but since all is relative, it works out. 11097993Sjhbint Assembler::branch_destination(int inst, int pos) { 11197993Sjhb int r; 11297993Sjhb switch (inv_op(inst)) { 11397993Sjhb default: ShouldNotReachHere(); 11497993Sjhb case call_op: r = inv_wdisp(inst, pos, 30); break; 11597993Sjhb case branch_op: 11697993Sjhb switch (inv_op2(inst)) { 11797993Sjhb case bpr_op2: r = inv_wdisp16(inst, pos); break; 11897993Sjhb case fbp_op2: r = inv_wdisp( inst, pos, 19); break; 11997993Sjhb case bp_op2: r = inv_wdisp( inst, pos, 19); break; 12097993Sjhb case fb_op2: r = inv_wdisp( inst, pos, 22); break; 1211541Srgrimes case br_op2: r = inv_wdisp( inst, pos, 22); break; 12297993Sjhb case cb_op2: r = inv_wdisp( inst, pos, 22); break; 12397993Sjhb default: ShouldNotReachHere(); 1241541Srgrimes } 12597993Sjhb } 126126295Sjhb return r; 12797993Sjhb} 12897993Sjhb 12997993Sjhbint AbstractAssembler::code_fill_byte() { 130111119Simp return 0x00; // illegal instruction 0x00000000 13197993Sjhb} 13297993Sjhb 133104354SscottlAssembler::Condition Assembler::reg_cond_to_cc_cond(Assembler::RCondition in) { 1341541Srgrimes switch (in) { 13597993Sjhb case rc_z: return equal; 1361541Srgrimes case rc_lez: return lessEqual; 13797993Sjhb case rc_lz: return less; 13897993Sjhb case rc_nz: return notEqual; 13997993Sjhb case rc_gz: return greater; 14097993Sjhb case rc_gez: return greaterEqual; 141118607Sjhb default: 14297993Sjhb ShouldNotReachHere(); 14397993Sjhb } 14497993Sjhb return equal; 14597993Sjhb} 14697993Sjhb 14797993Sjhb// Generate a bunch 'o stuff (including v9's 14897993Sjhb#ifndef PRODUCT 149118607Sjhbvoid Assembler::test_v9() { 15097993Sjhb add( G0, G1, G2 ); 15197993Sjhb add( G3, 0, G4 ); 152118607Sjhb 15397993Sjhb addcc( G5, G6, G7 ); 15497993Sjhb addcc( I0, 1, I1 ); 15597993Sjhb addc( I2, I3, I4 ); 156116101Sjhb addc( I5, -1, I6 ); 15797993Sjhb addccc( I7, L0, L1 ); 15897993Sjhb addccc( L2, (1 << 12) - 2, L3 ); 15997993Sjhb 16097993Sjhb Label lbl1, lbl2, lbl3; 161116101Sjhb 162118607Sjhb bind(lbl1); 16397993Sjhb 16497993Sjhb bpr( rc_z, true, pn, L4, pc(), relocInfo::oop_type ); 165122478Sjkoshy delayed()->nop(); 16697993Sjhb bpr( rc_lez, false, pt, L5, lbl1); 16797993Sjhb delayed()->nop(); 16897993Sjhb 169103234Sjhb fb( f_never, true, pc() + 4, relocInfo::none); 17097993Sjhb delayed()->nop(); 17197993Sjhb fb( f_notEqual, false, lbl2 ); 172118607Sjhb delayed()->nop(); 173118607Sjhb 17497993Sjhb fbp( f_notZero, true, fcc0, pn, pc() - 4, relocInfo::none); 17597993Sjhb delayed()->nop(); 176122478Sjkoshy fbp( f_lessOrGreater, false, fcc1, pt, lbl3 ); 17797993Sjhb delayed()->nop(); 17897993Sjhb 17997993Sjhb br( equal, true, pc() + 1024, relocInfo::none); 180122478Sjkoshy delayed()->nop(); 181122478Sjkoshy br( lessEqual, false, lbl1 ); 182122478Sjkoshy delayed()->nop(); 183122478Sjkoshy br( never, false, lbl1 ); 18497993Sjhb delayed()->nop(); 185122478Sjkoshy 18697993Sjhb bp( less, true, icc, pn, pc(), relocInfo::none); 18797993Sjhb delayed()->nop(); 18897993Sjhb bp( lessEqualUnsigned, false, xcc, pt, lbl2 ); 18997993Sjhb delayed()->nop(); 19097993Sjhb 19197993Sjhb call( pc(), relocInfo::none); 19297993Sjhb delayed()->nop(); 19397993Sjhb call( lbl3 ); 19497993Sjhb delayed()->nop(); 19597993Sjhb 19697993Sjhb 197122478Sjkoshy casa( L6, L7, O0 ); 19897993Sjhb casxa( O1, O2, O3, 0 ); 19997993Sjhb 200111119Simp udiv( O4, O5, O7 ); 20197993Sjhb udiv( G0, (1 << 12) - 1, G1 ); 20297993Sjhb sdiv( G1, G2, G3 ); 20397993Sjhb sdiv( G4, -((1 << 12) - 1), G5 ); 20497993Sjhb udivcc( G6, G7, I0 ); 20597993Sjhb udivcc( I1, -((1 << 12) - 2), I2 ); 20697993Sjhb sdivcc( I3, I4, I5 ); 20797993Sjhb sdivcc( I6, -((1 << 12) - 0), I7 ); 20897993Sjhb 20997993Sjhb done(); 21097993Sjhb retry(); 21197993Sjhb 21297993Sjhb fadd( FloatRegisterImpl::S, F0, F1, F2 ); 21397993Sjhb fsub( FloatRegisterImpl::D, F34, F0, F62 ); 21497993Sjhb 21597993Sjhb fcmp( FloatRegisterImpl::Q, fcc0, F0, F60); 216116101Sjhb fcmpe( FloatRegisterImpl::S, fcc1, F31, F30); 21797993Sjhb 21897993Sjhb ftox( FloatRegisterImpl::D, F2, F4 ); 21997993Sjhb ftoi( FloatRegisterImpl::Q, F4, F8 ); 220116101Sjhb 22197993Sjhb ftof( FloatRegisterImpl::S, FloatRegisterImpl::Q, F3, F12 ); 22297993Sjhb 22397993Sjhb fxtof( FloatRegisterImpl::S, F4, F5 ); 22497993Sjhb fitof( FloatRegisterImpl::D, F6, F8 ); 22597993Sjhb 22697993Sjhb fmov( FloatRegisterImpl::Q, F16, F20 ); 227112199Sjhb fneg( FloatRegisterImpl::S, F6, F7 ); 228112199Sjhb fabs( FloatRegisterImpl::D, F10, F12 ); 229112199Sjhb 230112199Sjhb fmul( FloatRegisterImpl::Q, F24, F28, F32 ); 231112198Sjhb fmul( FloatRegisterImpl::S, FloatRegisterImpl::D, F8, F9, F14 ); 232112198Sjhb fdiv( FloatRegisterImpl::S, F10, F11, F12 ); 233112198Sjhb 234112198Sjhb fsqrt( FloatRegisterImpl::S, F13, F14 ); 235112198Sjhb 23697993Sjhb flush( L0, L1 ); 23797993Sjhb flush( L2, -1 ); 23897993Sjhb 23997993Sjhb flushw(); 24097993Sjhb 24197993Sjhb illtrap( (1 << 22) - 2); 24297993Sjhb 243112199Sjhb impdep1( 17, (1 << 19) - 1 ); 24497993Sjhb impdep2( 3, 0 ); 24597993Sjhb 24697993Sjhb jmpl( L3, L4, L5 ); 24797993Sjhb delayed()->nop(); 24897993Sjhb jmpl( L6, -1, L7, Relocation::spec_simple(relocInfo::none)); 249116101Sjhb delayed()->nop(); 25097993Sjhb 25197993Sjhb 25297993Sjhb ldf( FloatRegisterImpl::S, O0, O1, F15 ); 25397993Sjhb ldf( FloatRegisterImpl::D, O2, -1, F14 ); 25497993Sjhb 25597993Sjhb 25697993Sjhb ldfsr( O3, O4 ); 25797993Sjhb ldfsr( O5, -1 ); 25897993Sjhb ldxfsr( O6, O7 ); 25997993Sjhb ldxfsr( I0, -1 ); 260126295Sjhb 261118599Sjhb ldfa( FloatRegisterImpl::D, I1, I2, 1, F16 ); 262116101Sjhb ldfa( FloatRegisterImpl::Q, I3, -1, F36 ); 26397993Sjhb 26497993Sjhb ldsb( I4, I5, I6 ); 26597993Sjhb ldsb( I7, -1, G0 ); 26697993Sjhb ldsh( G1, G3, G4 ); 26797993Sjhb ldsh( G5, -1, G6 ); 26897993Sjhb ldsw( G7, L0, L1 ); 26997993Sjhb ldsw( L2, -1, L3 ); 270101153Sjhb ldub( L4, L5, L6 ); 271101153Sjhb ldub( L7, -1, O0 ); 272101153Sjhb lduh( O1, O2, O3 ); 273101153Sjhb lduh( O4, -1, O5 ); 274101153Sjhb lduw( O6, O7, G0 ); 275103235Sjhb lduw( G1, -1, G2 ); 276103235Sjhb ldx( G3, G4, G5 ); 27797993Sjhb ldx( G6, -1, G7 ); 27897993Sjhb ldd( I0, I1, I2 ); 27997993Sjhb ldd( I3, -1, I4 ); 28097993Sjhb 28197993Sjhb ldsba( I5, I6, 2, I7 ); 28297993Sjhb ldsba( L0, -1, L1 ); 28397993Sjhb ldsha( L2, L3, 3, L4 ); 28497993Sjhb ldsha( L5, -1, L6 ); 28597993Sjhb ldswa( L7, O0, (1 << 8) - 1, O1 ); 28697993Sjhb ldswa( O2, -1, O3 ); 28797993Sjhb lduba( O4, O5, 0, O6 ); 28897993Sjhb lduba( O7, -1, I0 ); 28997993Sjhb lduha( I1, I2, 1, I3 ); 29097993Sjhb lduha( I4, -1, I5 ); 29197993Sjhb lduwa( I6, I7, 2, L0 ); 29297993Sjhb lduwa( L1, -1, L2 ); 29397993Sjhb ldxa( L3, L4, 3, L5 ); 294126295Sjhb ldxa( L6, -1, L7 ); 295126295Sjhb ldda( G0, G1, 4, G2 ); 29697993Sjhb ldda( G3, -1, G4 ); 29797993Sjhb 29897993Sjhb ldstub( G5, G6, G7 ); 299103236Sjhb ldstub( O0, -1, O1 ); 300103236Sjhb 301103236Sjhb ldstuba( O2, O3, 5, O4 ); 302103236Sjhb ldstuba( O5, -1, O6 ); 303103236Sjhb 304103236Sjhb and3( I0, L0, O0 ); 305103236Sjhb and3( G7, -1, O7 ); 306103236Sjhb andcc( L2, I2, G2 ); 307103236Sjhb andcc( L4, -1, G4 ); 308103236Sjhb andn( I5, I6, I7 ); 309103236Sjhb andn( I6, -1, I7 ); 31097993Sjhb andncc( I5, I6, I7 ); 31197993Sjhb andncc( I7, -1, I6 ); 31297993Sjhb or3( I5, I6, I7 ); 31397993Sjhb or3( I7, -1, I6 ); 31482585Sdillon orcc( I5, I6, I7 ); 31582585Sdillon orcc( I7, -1, I6 ); 31682585Sdillon orn( I5, I6, I7 ); 3171549Srgrimes orn( I7, -1, I6 ); 31897993Sjhb orncc( I5, I6, I7 ); 31947955Sdt orncc( I7, -1, I6 ); 32047955Sdt xor3( I5, I6, I7 ); 3211541Srgrimes xor3( I7, -1, I6 ); 32297993Sjhb xorcc( I5, I6, I7 ); 32397993Sjhb xorcc( I7, -1, I6 ); 32497993Sjhb xnor( I5, I6, I7 ); 325103233Sjhb xnor( I7, -1, I6 ); 3261541Srgrimes xnorcc( I5, I6, I7 ); 327103233Sjhb xnorcc( I7, -1, I6 ); 328103233Sjhb 329111119Simp membar( Membar_mask_bits(StoreStore | LoadStore | StoreLoad | LoadLoad | Sync | MemIssue | Lookaside ) ); 330103233Sjhb membar( StoreStore ); 331103233Sjhb membar( LoadStore ); 33297993Sjhb membar( StoreLoad ); 333104230Sphk membar( LoadLoad ); 334104230Sphk membar( Sync ); 335104230Sphk membar( MemIssue ); 33697993Sjhb membar( Lookaside ); 337104230Sphk 33897993Sjhb fmov( FloatRegisterImpl::S, f_ordered, true, fcc2, F16, F17 ); 3391541Srgrimes fmov( FloatRegisterImpl::D, rc_lz, L5, F18, F20 ); 3401541Srgrimes 34197993Sjhb movcc( overflowClear, false, icc, I6, L4 ); 34297993Sjhb movcc( f_unorderedOrEqual, true, fcc2, (1 << 10) - 1, O0 ); 343103233Sjhb 34497993Sjhb movr( rc_nz, I5, I6, I7 ); 34597993Sjhb movr( rc_gz, L1, -1, L2 ); 3461541Srgrimes 3471541Srgrimes mulx( I5, I6, I7 ); 34882585Sdillon mulx( I7, -1, I6 ); 34982585Sdillon sdivx( I5, I6, I7 ); 35082585Sdillon sdivx( I7, -1, I6 ); 3511549Srgrimes udivx( I5, I6, I7 ); 35297993Sjhb udivx( I7, -1, I6 ); 35347955Sdt 35447955Sdt umul( I5, I6, I7 ); 3551541Srgrimes umul( I7, -1, I6 ); 35697993Sjhb smul( I5, I6, I7 ); 35797993Sjhb smul( I7, -1, I6 ); 3581541Srgrimes umulcc( I5, I6, I7 ); 35997993Sjhb umulcc( I7, -1, I6 ); 36097993Sjhb smulcc( I5, I6, I7 ); 36197993Sjhb smulcc( I7, -1, I6 ); 36297993Sjhb 36397993Sjhb mulscc( I5, I6, I7 ); 36497993Sjhb mulscc( I7, -1, I6 ); 36597993Sjhb 36697993Sjhb nop(); 3671541Srgrimes 3681541Srgrimes 3691549Srgrimes popc( G0, G1); 37097993Sjhb popc( -1, G2); 3711541Srgrimes 3721541Srgrimes prefetch( L1, L2, severalReads ); 37397993Sjhb prefetch( L3, -1, oneRead ); 37497993Sjhb prefetcha( O3, O2, 6, severalWritesAndPossiblyReads ); 375103233Sjhb prefetcha( G2, -1, oneWrite ); 3761541Srgrimes 377103233Sjhb rett( I7, I7); 378103233Sjhb delayed()->nop(); 379111119Simp rett( G0, -1, relocInfo::none); 380103233Sjhb delayed()->nop(); 381103233Sjhb 38297993Sjhb save( I5, I6, I7 ); 383104230Sphk save( I7, -1, I6 ); 384104230Sphk restore( I5, I6, I7 ); 385104230Sphk restore( I7, -1, I6 ); 38697993Sjhb 387104230Sphk saved(); 38897993Sjhb restored(); 38997993Sjhb 390103233Sjhb sethi( 0xaaaaaaaa, I3, Relocation::spec_simple(relocInfo::none)); 39197993Sjhb 39297993Sjhb sll( I5, I6, I7 ); 3931541Srgrimes sll( I7, 31, I6 ); 3941541Srgrimes srl( I5, I6, I7 ); 39597993Sjhb srl( I7, 0, I6 ); 39697993Sjhb sra( I5, I6, I7 ); 39797993Sjhb sra( I7, 30, I6 ); 39897993Sjhb sllx( I5, I6, I7 ); 39997993Sjhb sllx( I7, 63, I6 ); 40097993Sjhb srlx( I5, I6, I7 ); 40197993Sjhb srlx( I7, 0, I6 ); 40297993Sjhb srax( I5, I6, I7 ); 40397993Sjhb srax( I7, 62, I6 ); 4041549Srgrimes 40597993Sjhb sir( -1 ); 4061541Srgrimes 4071541Srgrimes stbar(); 40862378Sgreen 40962378Sgreen stf( FloatRegisterImpl::Q, F40, G0, I7 ); 4101541Srgrimes stf( FloatRegisterImpl::S, F18, I3, -1 ); 41197993Sjhb 41297993Sjhb stfsr( L1, L2 ); 413103235Sjhb stfsr( I7, -1 ); 414103235Sjhb stxfsr( I6, I5 ); 4158876Srgrimes stxfsr( L4, -1 ); 416131897Sphk 417131897Sphk stfa( FloatRegisterImpl::D, F22, I6, I7, 7 ); 4181541Srgrimes stfa( FloatRegisterImpl::Q, F44, G0, -1 ); 419131897Sphk 420103235Sjhb stb( L5, O2, I7 ); 421103235Sjhb stb( I7, I6, -1 ); 422103235Sjhb sth( L5, O2, I7 ); 423111119Simp sth( I7, I6, -1 ); 424131897Sphk stw( L5, O2, I7 ); 425131897Sphk stw( I7, I6, -1 ); 426131897Sphk stx( L5, O2, I7 ); 427103235Sjhb stx( I7, I6, -1 ); 428103235Sjhb std( L5, O2, I7 ); 429103235Sjhb std( I7, I6, -1 ); 43097993Sjhb 431103235Sjhb stba( L5, O2, I7, 8 ); 432103235Sjhb stba( I7, I6, -1 ); 43397993Sjhb stha( L5, O2, I7, 9 ); 434103235Sjhb stha( I7, I6, -1 ); 43597993Sjhb stwa( L5, O2, I7, 0 ); 43697993Sjhb stwa( I7, I6, -1 ); 43797993Sjhb stxa( L5, O2, I7, 11 ); 438103235Sjhb stxa( I7, I6, -1 ); 439103235Sjhb stda( L5, O2, I7, 12 ); 44097993Sjhb stda( I7, I6, -1 ); 4411541Srgrimes 4421541Srgrimes sub( I5, I6, I7 ); 4431549Srgrimes sub( I7, -1, I6 ); 44497993Sjhb subcc( I5, I6, I7 ); 44551941Smarcel subcc( I7, -1, I6 ); 4461541Srgrimes subc( I5, I6, I7 ); 44751791Smarcel subc( I7, -1, I6 ); 44851941Smarcel subccc( I5, I6, I7 ); 4491541Srgrimes subccc( I7, -1, I6 ); 45097993Sjhb 45197993Sjhb swap( I5, I6, I7 ); 4521541Srgrimes swap( I7, -1, I6 ); 45397993Sjhb 45497993Sjhb swapa( G0, G1, 13, G2 ); 45597993Sjhb swapa( I7, -1, I6 ); 45697993Sjhb 45797993Sjhb taddcc( I5, I6, I7 ); 45897993Sjhb taddcc( I7, -1, I6 ); 45997993Sjhb taddcctv( I5, I6, I7 ); 46097993Sjhb taddcctv( I7, -1, I6 ); 46197993Sjhb 4621541Srgrimes tsubcc( I5, I6, I7 ); 4631541Srgrimes tsubcc( I7, -1, I6 ); 4641549Srgrimes tsubcctv( I5, I6, I7 ); 46597993Sjhb tsubcctv( I7, -1, I6 ); 4661541Srgrimes 4671541Srgrimes trap( overflowClear, xcc, G0, G1 ); 46897993Sjhb trap( lessEqual, icc, I7, 17 ); 46997993Sjhb 4701541Srgrimes bind(lbl2); 47197993Sjhb bind(lbl3); 47297993Sjhb 47397993Sjhb code()->decode(); 47497993Sjhb} 47597993Sjhb 47697993Sjhb// Generate a bunch 'o stuff unique to V8 47797993Sjhbvoid Assembler::test_v8_onlys() { 4781541Srgrimes Label lbl1; 479114026Sjhb 4801541Srgrimes cb( cp_0or1or2, false, pc() - 4, relocInfo::none); 4811541Srgrimes delayed()->nop(); 4821541Srgrimes cb( cp_never, true, lbl1); 4831541Srgrimes delayed()->nop(); 4841541Srgrimes 485114026Sjhb cpop1(1, 2, 3, 4); 486114026Sjhb cpop2(5, 6, 7, 8); 4871541Srgrimes 48812221Sbde ldc( I0, I1, 31); 4891541Srgrimes ldc( I2, -1, 0); 4901541Srgrimes 4911541Srgrimes lddc( I4, I4, 30); 4921541Srgrimes lddc( I6, 0, 1 ); 4931541Srgrimes 4941541Srgrimes ldcsr( L0, L1, 0); 49512221Sbde ldcsr( L1, (1 << 12) - 1, 17 ); 4961541Srgrimes 4971549Srgrimes stc( 31, L4, L5); 49883366Sjulian stc( 30, L6, -(1 << 12) ); 49983366Sjulian 5001541Srgrimes stdc( 0, L7, G0); 5011541Srgrimes stdc( 1, G1, 0 ); 50213203Swollman 5031541Srgrimes stcsr( 16, G2, G3); 5041541Srgrimes stcsr( 17, G4, 1 ); 5051541Srgrimes 5061541Srgrimes stdcq( 4, G5, G6); 5071541Srgrimes stdcq( 5, G7, -1 ); 5081541Srgrimes 509147576Spjd bind(lbl1); 51062550Smckusick 5111541Srgrimes code()->decode(); 512112198Sjhb} 5131541Srgrimes#endif 514114026Sjhb 515114026Sjhb// Implementation of MacroAssembler 516114026Sjhb 517114026Sjhbvoid MacroAssembler::null_check(Register reg, int offset) { 518114026Sjhb if (needs_explicit_null_check((intptr_t)offset)) { 519114026Sjhb // provoke OS NULL exception if reg = NULL by 520116101Sjhb // accessing M[reg] w/o changing any registers 5211541Srgrimes ld_ptr(reg, 0, G0); 5221541Srgrimes } 5231541Srgrimes else { 5241541Srgrimes // nothing to do, (later) access of M[reg + offset] 52583366Sjulian // will provoke OS NULL exception if reg = NULL 52662550Smckusick } 527114026Sjhb} 528118094Sphk 5293308Sphk// Ring buffer jumps 530114026Sjhb 531116101Sjhb#ifndef PRODUCT 5321541Srgrimesvoid MacroAssembler::ret( bool trace ) { if (trace) { 5331541Srgrimes mov(I7, O7); // traceable register 53454655Seivind JMP(O7, 2 * BytesPerInstWord); 5351541Srgrimes } else { 53683366Sjulian jmpl( I7, 2 * BytesPerInstWord, G0 ); 5371541Srgrimes } 53891406Sjhb } 539114026Sjhb 540116101Sjhbvoid MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord); 5411541Srgrimes else jmpl( O7, 2 * BytesPerInstWord, G0 ); } 5421541Srgrimes#endif /* PRODUCT */ 543114026Sjhb 5441541Srgrimes 5451541Srgrimesvoid MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) { 54685397Sdillon assert_not_delayed(); 5471541Srgrimes // This can only be traceable if r1 & r2 are visible after a window save 5481541Srgrimes if (TraceJumps) { 54974927Sjhb#ifndef PRODUCT 55053212Sphk save_frame(0); 55194618Sjhb verify_thread(); 552112198Sjhb ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); 55397993Sjhb add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); 55497993Sjhb sll(O0, exact_log2(4*sizeof(intptr_t)), O2); 555112198Sjhb add(O2, O1, O1); 556112198Sjhb 557112198Sjhb add(r1->after_save(), r2->after_save(), O2); 5581541Srgrimes set((intptr_t)file, O3); 55997993Sjhb set(line, O4); 56094618Sjhb Label L; 561114026Sjhb // get nearby pc, store jmp target 5621541Srgrimes call(L, relocInfo::none); // No relocation for call to pc+0x8 563112198Sjhb delayed()->st(O2, O1, 0); 564114026Sjhb bind(L); 565112198Sjhb 56685397Sdillon // store nearby pc 56794618Sjhb st(O7, O1, sizeof(intptr_t)); 5681541Srgrimes // store file 56985397Sdillon st(O3, O1, 2*sizeof(intptr_t)); 57094618Sjhb // store line 57194618Sjhb st(O4, O1, 3*sizeof(intptr_t)); 5721541Srgrimes add(O0, 1, O0); 57374927Sjhb and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); 5741541Srgrimes st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); 5751541Srgrimes restore(); 5761541Srgrimes#endif /* PRODUCT */ 5771541Srgrimes } 5781541Srgrimes jmpl(r1, r2, G0); 579114026Sjhb} 5801541Srgrimesvoid MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) { 5811541Srgrimes assert_not_delayed(); 5821541Srgrimes // This can only be traceable if r1 is visible after a window save 5831541Srgrimes if (TraceJumps) { 5841541Srgrimes#ifndef PRODUCT 5851541Srgrimes save_frame(0); 58694861Sjhb verify_thread(); 5871541Srgrimes ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); 5881541Srgrimes add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); 5891541Srgrimes sll(O0, exact_log2(4*sizeof(intptr_t)), O2); 59091140Stanimura add(O2, O1, O1); 59191140Stanimura 59294861Sjhb add(r1->after_save(), offset, O2); 59391140Stanimura set((intptr_t)file, O3); 59491140Stanimura set(line, O4); 595147576Spjd Label L; 596147576Spjd // get nearby pc, store jmp target 597147576Spjd call(L, relocInfo::none); // No relocation for call to pc+0x8 598147576Spjd delayed()->st(O2, O1, 0); 599147576Spjd bind(L); 600147576Spjd 601147576Spjd // store nearby pc 602147576Spjd st(O7, O1, sizeof(intptr_t)); 603147576Spjd // store file 6041541Srgrimes st(O3, O1, 2*sizeof(intptr_t)); 60594618Sjhb // store line 6068876Srgrimes st(O4, O1, 3*sizeof(intptr_t)); 60794618Sjhb add(O0, 1, O0); 608147576Spjd and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); 609147576Spjd st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); 610147576Spjd restore(); 611147576Spjd#endif /* PRODUCT */ 612147576Spjd } 613147576Spjd jmp(r1, offset); 6141541Srgrimes} 6151541Srgrimes 6161541Srgrimes// This code sequence is relocatable to any address, even on LP64. 6171541Srgrimesvoid MacroAssembler::jumpl( Address& a, Register d, int offset, const char* file, int line ) { 6181541Srgrimes assert_not_delayed(); 6191541Srgrimes // Force fixed length sethi because NativeJump and NativeFarCall don't handle 620114026Sjhb // variable length instruction streams. 6211541Srgrimes sethi(a, /*ForceRelocatable=*/ true); 6221541Srgrimes if (TraceJumps) { 6231541Srgrimes#ifndef PRODUCT 624147183Spjd // Must do the add here so relocation can find the remainder of the 625114026Sjhb // value to be relocated. 626114026Sjhb add(a.base(), a.disp() + offset, a.base(), a.rspec(offset)); 627114026Sjhb save_frame(0); 628114026Sjhb verify_thread(); 62975893Sjhb ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); 630147520Spjd add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); 631147520Spjd sll(O0, exact_log2(4*sizeof(intptr_t)), O2); 632147183Spjd add(O2, O1, O1); 633147520Spjd 6341541Srgrimes set((intptr_t)file, O3); 63594618Sjhb set(line, O4); 6361541Srgrimes Label L; 63794618Sjhb 6381541Srgrimes // get nearby pc, store jmp target 639114026Sjhb call(L, relocInfo::none); // No relocation for call to pc+0x8 6401541Srgrimes delayed()->st(a.base()->after_save(), O1, 0); 6411541Srgrimes bind(L); 6421541Srgrimes 643114026Sjhb // store nearby pc 644114026Sjhb st(O7, O1, sizeof(intptr_t)); 64591406Sjhb // store file 646114026Sjhb st(O3, O1, 2*sizeof(intptr_t)); 647114026Sjhb // store line 648116101Sjhb st(O4, O1, 3*sizeof(intptr_t)); 6491541Srgrimes add(O0, 1, O0); 650114026Sjhb and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); 651114026Sjhb st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); 652114026Sjhb restore(); 6531541Srgrimes jmpl(a.base(), G0, d); 6541541Srgrimes#else 65518398Sphk jmpl(a, d, offset); 65618398Sphk#endif /* PRODUCT */ 657114026Sjhb } else { 658114026Sjhb jmpl(a, d, offset); 65918398Sphk } 66018398Sphk} 66118398Sphk 66283366Sjulianvoid MacroAssembler::jump( Address& a, int offset, const char* file, int line ) { 66383366Sjulian jumpl( a, G0, offset, file, line ); 66418398Sphk} 66518398Sphk 66683366Sjulian 66713203Swollman// Convert to C varargs format 66897993Sjhbvoid MacroAssembler::set_varargs( Argument inArg, Register d ) { 66999009Salfred // spill register-resident args to their memory slots 670103237Sjhb // (SPARC calling convention requires callers to have already preallocated these) 67118398Sphk // Note that the inArg might in fact be an outgoing argument, 672103237Sjhb // if a leaf routine or stub does some tricky argument shuffling. 673103237Sjhb // This routine must work even though one of the saved arguments 67470792Salfred // is in the d register (e.g., set_varargs(Argument(0, false), O0)). 67570707Salfred for (Argument savePtr = inArg; 676111119Simp savePtr.is_register(); 677103237Sjhb savePtr = savePtr.successor()) { 678104230Sphk st_ptr(savePtr.as_register(), savePtr.address_in_frame()); 679104230Sphk } 680103237Sjhb // return the address of the first memory slot 681104230Sphk add(inArg.address_in_frame(), d); 68297993Sjhb} 683104230Sphk 684104230Sphk// Conditional breakpoint (for assertion checks in assembly code) 685122457Sjkoshyvoid MacroAssembler::breakpoint_trap(Condition c, CC cc) { 686104230Sphk trap(c, cc, G0, ST_RESERVED_FOR_USER_0); 687103237Sjhb} 688103237Sjhb 689103237Sjhb// We want to use ST_BREAKPOINT here, but the debugger is confused by it. 69018398Sphkvoid MacroAssembler::breakpoint_trap() { 691114026Sjhb trap(ST_RESERVED_FOR_USER_0); 69218398Sphk} 693114026Sjhb 69418398Sphk// flush windows (except current) using flushw instruction if avail. 69518398Sphkvoid MacroAssembler::flush_windows() { 69618398Sphk if (VM_Version::v9_instructions_work()) flushw(); 69712819Sphk else flush_windows_trap(); 69894618Sjhb} 69994618Sjhb 70094618Sjhb// Write serialization page so VM thread can do a pseudo remote membar 7011541Srgrimes// We use the current thread pointer to calculate a thread specific 7021541Srgrimes// offset to write to within the page. This minimizes bus traffic 7031541Srgrimes// due to cache line collision. 70497993Sjhbvoid MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) { 705112198Sjhb Address mem_serialize_page(tmp1, os::get_memory_serialize_page()); 7061541Srgrimes srl(thread, os::get_serialize_page_shift_count(), tmp2); 70794618Sjhb if (Assembler::is_simm13(os::vm_page_size())) { 70894618Sjhb and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2); 70994618Sjhb } 7101541Srgrimes else { 71194618Sjhb set((os::vm_page_size() - sizeof(int)), tmp1); 71297993Sjhb and3(tmp2, tmp1, tmp2); 7131541Srgrimes } 714112198Sjhb load_address(mem_serialize_page); 7151541Srgrimes st(G0, tmp1, tmp2); 71694618Sjhb} 7171541Srgrimes 718112198Sjhb 71997993Sjhb 720112198Sjhbvoid MacroAssembler::enter() { 7211541Srgrimes Unimplemented(); 722112198Sjhb} 723112198Sjhb 724112198Sjhbvoid MacroAssembler::leave() { 725112198Sjhb Unimplemented(); 7261541Srgrimes} 72794618Sjhb 7281541Srgrimesvoid MacroAssembler::mult(Register s1, Register s2, Register d) { 7298876Srgrimes if(VM_Version::v9_instructions_work()) { 7301541Srgrimes mulx (s1, s2, d); 7311541Srgrimes } else { 7321541Srgrimes smul (s1, s2, d); 7331541Srgrimes } 734112198Sjhb} 735112198Sjhb 736112198Sjhbvoid MacroAssembler::mult(Register s1, int simm13a, Register d) { 737112198Sjhb if(VM_Version::v9_instructions_work()) { 7381541Srgrimes mulx (s1, simm13a, d); 7391541Srgrimes } else { 74097993Sjhb smul (s1, simm13a, d); 74194618Sjhb } 742114026Sjhb} 743114026Sjhb 74497993Sjhb 745114026Sjhb#ifdef ASSERT 746114026Sjhbvoid MacroAssembler::read_ccr_v8_assert(Register ccr_save) { 747112198Sjhb const Register s1 = G3_scratch; 748112198Sjhb const Register s2 = G4_scratch; 7491541Srgrimes Label get_psr_test; 7501541Srgrimes // Get the condition codes the V8 way. 7511541Srgrimes read_ccr_trap(s1); 7521541Srgrimes mov(ccr_save, s2); 75312819Sphk // This is a test of V8 which has icc but not xcc 75494618Sjhb // so mask off the xcc bits 75594618Sjhb and3(s2, 0xf, s2); 75694618Sjhb // Compare condition codes from the V8 and V9 ways. 7571541Srgrimes subcc(s2, s1, G0); 7581541Srgrimes br(Assembler::notEqual, true, Assembler::pt, get_psr_test); 7591541Srgrimes delayed()->breakpoint_trap(); 7601541Srgrimes bind(get_psr_test); 7611541Srgrimes} 7621541Srgrimes 7631541Srgrimesvoid MacroAssembler::write_ccr_v8_assert(Register ccr_save) { 764114026Sjhb const Register s1 = G3_scratch; 7651541Srgrimes const Register s2 = G4_scratch; 76694618Sjhb Label set_psr_test; 7671541Srgrimes // Write out the saved condition codes the V8 way 7681541Srgrimes write_ccr_trap(ccr_save, s1, s2); 7691541Srgrimes // Read back the condition codes using the V9 instruction 7701541Srgrimes rdccr(s1); 7711541Srgrimes mov(ccr_save, s2); 77253212Sphk // This is a test of V8 which has icc but not xcc 77353212Sphk // so mask off the xcc bits 7741541Srgrimes and3(s2, 0xf, s2); 775114026Sjhb and3(s1, 0xf, s1); 7761541Srgrimes // Compare the V8 way with the V9 way. 77753212Sphk subcc(s2, s1, G0); 77853212Sphk br(Assembler::notEqual, true, Assembler::pt, set_psr_test); 7791541Srgrimes delayed()->breakpoint_trap(); 7801541Srgrimes bind(set_psr_test); 78114529Shsu} 7821541Srgrimes#else 7831541Srgrimes#define read_ccr_v8_assert(x) 7841541Srgrimes#define write_ccr_v8_assert(x) 7851541Srgrimes#endif // ASSERT 7861541Srgrimes 78712819Sphkvoid MacroAssembler::read_ccr(Register ccr_save) { 78897993Sjhb if (VM_Version::v9_instructions_work()) { 78997993Sjhb rdccr(ccr_save); 79097993Sjhb // Test code sequence used on V8. Do not move above rdccr. 7911541Srgrimes read_ccr_v8_assert(ccr_save); 79297993Sjhb } else { 79397993Sjhb read_ccr_trap(ccr_save); 79497993Sjhb } 7951541Srgrimes} 79697993Sjhb 79762976Smckusickvoid MacroAssembler::write_ccr(Register ccr_save) { 79897993Sjhb if (VM_Version::v9_instructions_work()) { 7991541Srgrimes // Test code sequence used on V8. Do not move below wrccr. 8001541Srgrimes write_ccr_v8_assert(ccr_save); 80197993Sjhb wrccr(ccr_save); 80297993Sjhb } else { 80397993Sjhb const Register temp_reg1 = G3_scratch; 80497993Sjhb const Register temp_reg2 = G4_scratch; 80597993Sjhb write_ccr_trap(ccr_save, temp_reg1, temp_reg2); 8061541Srgrimes } 8071541Srgrimes} 80897993Sjhb 809118607Sjhb 81097993Sjhb// Calls to C land 81197993Sjhb 81297993Sjhb#ifdef ASSERT 8131541Srgrimes// a hook for debugging 8141541Srgrimesstatic Thread* reinitialize_thread() { 8151541Srgrimes return ThreadLocalStorage::thread(); 8161541Srgrimes} 8171541Srgrimes#else 8181541Srgrimes#define reinitialize_thread ThreadLocalStorage::thread 8191541Srgrimes#endif 8201541Srgrimes 82197993Sjhb#ifdef ASSERT 82297993Sjhbaddress last_get_thread = NULL; 82397993Sjhb#endif 82497993Sjhb 82597993Sjhb// call this when G2_thread is not known to be valid 8261541Srgrimesvoid MacroAssembler::get_thread() { 82797993Sjhb save_frame(0); // to avoid clobbering O0 8281541Srgrimes mov(G1, L0); // avoid clobbering G1 82997993Sjhb mov(G5_method, L1); // avoid clobbering G5 83097993Sjhb mov(G3, L2); // avoid clobbering G3 also 83197993Sjhb mov(G4, L5); // avoid clobbering G4 83297993Sjhb#ifdef ASSERT 83397993Sjhb Address last_get_thread_addr(L3, (address)&last_get_thread); 83497993Sjhb sethi(last_get_thread_addr); 835103235Sjhb inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call 83697993Sjhb st_ptr(L4, last_get_thread_addr); 83762976Smckusick#endif 83883366Sjulian call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type); 83997993Sjhb delayed()->nop(); 840101123Srwatson mov(L0, G1); 841102129Srwatson mov(L1, G5_method); 842101123Srwatson mov(L2, G3); 843101123Srwatson mov(L5, G4); 844101123Srwatson restore(O0, 0, G2_thread); 84583366Sjulian} 84662976Smckusick 84797993Sjhbstatic Thread* verify_thread_subroutine(Thread* gthread_value) { 8481541Srgrimes Thread* correct_value = ThreadLocalStorage::thread(); 8491541Srgrimes guarantee(gthread_value == correct_value, "G2_thread value must be the thread"); 8501541Srgrimes return correct_value; 85197993Sjhb} 85297993Sjhb 85397993Sjhbvoid MacroAssembler::verify_thread() { 8541541Srgrimes if (VerifyThread) { 8551541Srgrimes // NOTE: this chops off the heads of the 64-bit O registers. 8561541Srgrimes#ifdef CC_INTERP 85797993Sjhb save_frame(0); 85897993Sjhb#else 85997993Sjhb // make sure G2_thread contains the right value 86097993Sjhb save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof) 86197993Sjhb mov(G1, L1); // avoid clobbering G1 86297993Sjhb // G2 saved below 86397993Sjhb mov(G3, L3); // avoid clobbering G3 86497993Sjhb mov(G4, L4); // avoid clobbering G4 865112198Sjhb mov(G5_method, L5); // avoid clobbering G5_method 86674927Sjhb#endif /* CC_INTERP */ 86753212Sphk#if defined(COMPILER2) && !defined(_LP64) 86897993Sjhb // Save & restore possible 64-bit Long arguments in G-regs 869112198Sjhb srlx(G1,32,L0); 87097993Sjhb srlx(G4,32,L6); 871112198Sjhb#endif 8721541Srgrimes call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type); 873112198Sjhb delayed()->mov(G2_thread, O0); 874112198Sjhb 87597993Sjhb mov(L1, G1); // Restore G1 87697993Sjhb // G2 restored below 8771541Srgrimes mov(L3, G3); // restore G3 87897993Sjhb mov(L4, G4); // restore G4 879112198Sjhb mov(L5, G5_method); // restore G5_method 880112198Sjhb#if defined(COMPILER2) && !defined(_LP64) 881112198Sjhb // Save & restore possible 64-bit Long arguments in G-regs 882112198Sjhb sllx(L0,32,G2); // Move old high G1 bits high in G2 8831541Srgrimes sllx(G1, 0,G1); // Clear current high G1 bits 88474927Sjhb or3 (G1,G2,G1); // Recover 64-bit G1 88597993Sjhb sllx(L6,32,G2); // Move old high G4 bits high in G2 88697993Sjhb sllx(G4, 0,G4); // Clear current high G4 bits 88797993Sjhb or3 (G4,G2,G4); // Recover 64-bit G4 88897993Sjhb#endif 88997993Sjhb restore(O0, 0, G2_thread); 89097993Sjhb } 89197993Sjhb} 89297993Sjhb 89397993Sjhb 89497993Sjhbvoid MacroAssembler::save_thread(const Register thread_cache) { 89597993Sjhb verify_thread(); 89697993Sjhb if (thread_cache->is_valid()) { 89797993Sjhb assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); 89897993Sjhb mov(G2_thread, thread_cache); 89997993Sjhb } 9001541Srgrimes if (VerifyThread) { 9011541Srgrimes // smash G2_thread, as if the VM were about to anyway 9021541Srgrimes set(0x67676767, G2_thread); 9031541Srgrimes } 9041541Srgrimes} 9051541Srgrimes 9068876Srgrimes 9071541Srgrimesvoid MacroAssembler::restore_thread(const Register thread_cache) { 9081541Srgrimes if (thread_cache->is_valid()) { 90912819Sphk assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); 91094618Sjhb mov(thread_cache, G2_thread); 91194618Sjhb verify_thread(); 91294618Sjhb } else { 9131541Srgrimes // do it the slow way 9141541Srgrimes get_thread(); 91594618Sjhb } 91679335Srwatson} 917132653Scperciva 91846155Sphk 9191541Srgrimes// %%% maybe get rid of [re]set_last_Java_frame 92096886Sjhbvoid MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) { 92179335Srwatson assert_not_delayed(); 92279335Srwatson Address flags(G2_thread, 92379335Srwatson 0, 9241541Srgrimes in_bytes(JavaThread::frame_anchor_offset()) + 9251541Srgrimes in_bytes(JavaFrameAnchor::flags_offset())); 92613203Swollman Address pc_addr(G2_thread, 927 0, 928 in_bytes(JavaThread::last_Java_pc_offset())); 929 930 // Always set last_Java_pc and flags first because once last_Java_sp is visible 931 // has_last_Java_frame is true and users will look at the rest of the fields. 932 // (Note: flags should always be zero before we get here so doesn't need to be set.) 933 934#ifdef ASSERT 935 // Verify that flags was zeroed on return to Java 936 Label PcOk; 937 save_frame(0); // to avoid clobbering O0 938 ld_ptr(pc_addr, L0); 939 tst(L0); 940#ifdef _LP64 941 brx(Assembler::zero, false, Assembler::pt, PcOk); 942#else 943 br(Assembler::zero, false, Assembler::pt, PcOk); 944#endif // _LP64 945 delayed() -> nop(); 946 stop("last_Java_pc not zeroed before leaving Java"); 947 bind(PcOk); 948 949 // Verify that flags was zeroed on return to Java 950 Label FlagsOk; 951 ld(flags, L0); 952 tst(L0); 953 br(Assembler::zero, false, Assembler::pt, FlagsOk); 954 delayed() -> restore(); 955 stop("flags not zeroed before leaving Java"); 956 bind(FlagsOk); 957#endif /* ASSERT */ 958 // 959 // When returning from calling out from Java mode the frame anchor's last_Java_pc 960 // will always be set to NULL. It is set here so that if we are doing a call to 961 // native (not VM) that we capture the known pc and don't have to rely on the 962 // native call having a standard frame linkage where we can find the pc. 963 964 if (last_Java_pc->is_valid()) { 965 st_ptr(last_Java_pc, pc_addr); 966 } 967 968#ifdef _LP64 969#ifdef ASSERT 970 // Make sure that we have an odd stack 971 Label StackOk; 972 andcc(last_java_sp, 0x01, G0); 973 br(Assembler::notZero, false, Assembler::pt, StackOk); 974 delayed() -> nop(); 975 stop("Stack Not Biased in set_last_Java_frame"); 976 bind(StackOk); 977#endif // ASSERT 978 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame"); 979 add( last_java_sp, STACK_BIAS, G4_scratch ); 980 st_ptr(G4_scratch, Address(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset()))); 981#else 982 st_ptr(last_java_sp, Address(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset()))); 983#endif // _LP64 984} 985 986void MacroAssembler::reset_last_Java_frame(void) { 987 assert_not_delayed(); 988 989 Address sp_addr(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset())); 990 Address pc_addr(G2_thread, 991 0, 992 in_bytes(JavaThread::frame_anchor_offset()) + in_bytes(JavaFrameAnchor::last_Java_pc_offset())); 993 Address flags(G2_thread, 994 0, 995 in_bytes(JavaThread::frame_anchor_offset()) + in_bytes(JavaFrameAnchor::flags_offset())); 996 997#ifdef ASSERT 998 // check that it WAS previously set 999#ifdef CC_INTERP 1000 save_frame(0); 1001#else 1002 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof 1003#endif /* CC_INTERP */ 1004 ld_ptr(sp_addr, L0); 1005 tst(L0); 1006 breakpoint_trap(Assembler::zero, Assembler::ptr_cc); 1007 restore(); 1008#endif // ASSERT 1009 1010 st_ptr(G0, sp_addr); 1011 // Always return last_Java_pc to zero 1012 st_ptr(G0, pc_addr); 1013 // Always null flags after return to Java 1014 st(G0, flags); 1015} 1016 1017 1018void MacroAssembler::call_VM_base( 1019 Register oop_result, 1020 Register thread_cache, 1021 Register last_java_sp, 1022 address entry_point, 1023 int number_of_arguments, 1024 bool check_exceptions) 1025{ 1026 assert_not_delayed(); 1027 1028 // determine last_java_sp register 1029 if (!last_java_sp->is_valid()) { 1030 last_java_sp = SP; 1031 } 1032 // debugging support 1033 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 1034 1035 // 64-bit last_java_sp is biased! 1036 set_last_Java_frame(last_java_sp, noreg); 1037 if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early 1038 save_thread(thread_cache); 1039 // do the call 1040 call(entry_point, relocInfo::runtime_call_type); 1041 if (!VerifyThread) 1042 delayed()->mov(G2_thread, O0); // pass thread as first argument 1043 else 1044 delayed()->nop(); // (thread already passed) 1045 restore_thread(thread_cache); 1046 reset_last_Java_frame(); 1047 1048 // check for pending exceptions. use Gtemp as scratch register. 1049 if (check_exceptions) { 1050 check_and_forward_exception(Gtemp); 1051 } 1052 1053 // get oop result if there is one and reset the value in the thread 1054 if (oop_result->is_valid()) { 1055 get_vm_result(oop_result); 1056 } 1057} 1058 1059void MacroAssembler::check_and_forward_exception(Register scratch_reg) 1060{ 1061 Label L; 1062 1063 check_and_handle_popframe(scratch_reg); 1064 check_and_handle_earlyret(scratch_reg); 1065 1066 Address exception_addr(G2_thread, 0, in_bytes(Thread::pending_exception_offset())); 1067 ld_ptr(exception_addr, scratch_reg); 1068 br_null(scratch_reg,false,pt,L); 1069 delayed()->nop(); 1070 // we use O7 linkage so that forward_exception_entry has the issuing PC 1071 call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type); 1072 delayed()->nop(); 1073 bind(L); 1074} 1075 1076 1077void MacroAssembler::check_and_handle_popframe(Register scratch_reg) { 1078} 1079 1080 1081void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) { 1082} 1083 1084 1085void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 1086 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); 1087} 1088 1089 1090void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) { 1091 // O0 is reserved for the thread 1092 mov(arg_1, O1); 1093 call_VM(oop_result, entry_point, 1, check_exceptions); 1094} 1095 1096 1097void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { 1098 // O0 is reserved for the thread 1099 mov(arg_1, O1); 1100 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); 1101 call_VM(oop_result, entry_point, 2, check_exceptions); 1102} 1103 1104 1105void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { 1106 // O0 is reserved for the thread 1107 mov(arg_1, O1); 1108 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); 1109 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); 1110 call_VM(oop_result, entry_point, 3, check_exceptions); 1111} 1112 1113 1114 1115// Note: The following call_VM overloadings are useful when a "save" 1116// has already been performed by a stub, and the last Java frame is 1117// the previous one. In that case, last_java_sp must be passed as FP 1118// instead of SP. 1119 1120 1121void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) { 1122 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions); 1123} 1124 1125 1126void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) { 1127 // O0 is reserved for the thread 1128 mov(arg_1, O1); 1129 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 1130} 1131 1132 1133void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { 1134 // O0 is reserved for the thread 1135 mov(arg_1, O1); 1136 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); 1137 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 1138} 1139 1140 1141void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { 1142 // O0 is reserved for the thread 1143 mov(arg_1, O1); 1144 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); 1145 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); 1146 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 1147} 1148 1149 1150 1151void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) { 1152 assert_not_delayed(); 1153 save_thread(thread_cache); 1154 // do the call 1155 call(entry_point, relocInfo::runtime_call_type); 1156 delayed()->nop(); 1157 restore_thread(thread_cache); 1158} 1159 1160 1161void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) { 1162 call_VM_leaf_base(thread_cache, entry_point, number_of_arguments); 1163} 1164 1165 1166void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) { 1167 mov(arg_1, O0); 1168 call_VM_leaf(thread_cache, entry_point, 1); 1169} 1170 1171 1172void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) { 1173 mov(arg_1, O0); 1174 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); 1175 call_VM_leaf(thread_cache, entry_point, 2); 1176} 1177 1178 1179void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) { 1180 mov(arg_1, O0); 1181 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); 1182 mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument"); 1183 call_VM_leaf(thread_cache, entry_point, 3); 1184} 1185 1186 1187void MacroAssembler::get_vm_result(Register oop_result) { 1188 verify_thread(); 1189 Address vm_result_addr(G2_thread, 0, in_bytes(JavaThread::vm_result_offset())); 1190 ld_ptr( vm_result_addr, oop_result); 1191 st_ptr(G0, vm_result_addr); 1192 verify_oop(oop_result); 1193} 1194 1195 1196void MacroAssembler::get_vm_result_2(Register oop_result) { 1197 verify_thread(); 1198 Address vm_result_addr_2(G2_thread, 0, in_bytes(JavaThread::vm_result_2_offset())); 1199 ld_ptr(vm_result_addr_2, oop_result); 1200 st_ptr(G0, vm_result_addr_2); 1201 verify_oop(oop_result); 1202} 1203 1204 1205// We require that C code which does not return a value in vm_result will 1206// leave it undisturbed. 1207void MacroAssembler::set_vm_result(Register oop_result) { 1208 verify_thread(); 1209 Address vm_result_addr(G2_thread, 0, in_bytes(JavaThread::vm_result_offset())); 1210 verify_oop(oop_result); 1211 1212# ifdef ASSERT 1213 // Check that we are not overwriting any other oop. 1214#ifdef CC_INTERP 1215 save_frame(0); 1216#else 1217 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof 1218#endif /* CC_INTERP */ 1219 ld_ptr(vm_result_addr, L0); 1220 tst(L0); 1221 restore(); 1222 breakpoint_trap(notZero, Assembler::ptr_cc); 1223 // } 1224# endif 1225 1226 st_ptr(oop_result, vm_result_addr); 1227} 1228 1229 1230void MacroAssembler::card_table_write(jbyte* byte_map_base, 1231 Register tmp, Register obj) { 1232#ifdef _LP64 1233 srlx(obj, CardTableModRefBS::card_shift, obj); 1234#else 1235 srl(obj, CardTableModRefBS::card_shift, obj); 1236#endif 1237 assert( tmp != obj, "need separate temp reg"); 1238 Address rs(tmp, (address)byte_map_base); 1239 load_address(rs); 1240 stb(G0, rs.base(), obj); 1241} 1242 1243// %%% Note: The following six instructions have been moved, 1244// unchanged, from assembler_sparc.inline.hpp. 1245// They will be refactored at a later date. 1246 1247void MacroAssembler::sethi(intptr_t imm22a, 1248 Register d, 1249 bool ForceRelocatable, 1250 RelocationHolder const& rspec) { 1251 Address adr( d, (address)imm22a, rspec ); 1252 MacroAssembler::sethi( adr, ForceRelocatable ); 1253} 1254 1255 1256void MacroAssembler::sethi(Address& a, bool ForceRelocatable) { 1257 address save_pc; 1258 int shiftcnt; 1259 // if addr of local, do not need to load it 1260 assert(a.base() != FP && a.base() != SP, "just use ld or st for locals"); 1261#ifdef _LP64 1262# ifdef CHECK_DELAY 1263 assert_not_delayed( (char *)"cannot put two instructions in delay slot" ); 1264# endif 1265 v9_dep(); 1266// ForceRelocatable = 1; 1267 save_pc = pc(); 1268 if (a.hi32() == 0 && a.low32() >= 0) { 1269 Assembler::sethi(a.low32(), a.base(), a.rspec()); 1270 } 1271 else if (a.hi32() == -1) { 1272 Assembler::sethi(~a.low32(), a.base(), a.rspec()); 1273 xor3(a.base(), ~low10(~0), a.base()); 1274 } 1275 else { 1276 Assembler::sethi(a.hi32(), a.base(), a.rspec() ); // 22 1277 if ( a.hi32() & 0x3ff ) // Any bits? 1278 or3( a.base(), a.hi32() & 0x3ff ,a.base() ); // High 32 bits are now in low 32 1279 if ( a.low32() & 0xFFFFFC00 ) { // done? 1280 if( (a.low32() >> 20) & 0xfff ) { // Any bits set? 1281 sllx(a.base(), 12, a.base()); // Make room for next 12 bits 1282 or3( a.base(), (a.low32() >> 20) & 0xfff,a.base() ); // Or in next 12 1283 shiftcnt = 0; // We already shifted 1284 } 1285 else 1286 shiftcnt = 12; 1287 if( (a.low32() >> 10) & 0x3ff ) { 1288 sllx(a.base(), shiftcnt+10, a.base());// Make room for last 10 bits 1289 or3( a.base(), (a.low32() >> 10) & 0x3ff,a.base() ); // Or in next 10 1290 shiftcnt = 0; 1291 } 1292 else 1293 shiftcnt = 10; 1294 sllx(a.base(), shiftcnt+10 , a.base()); // Shift leaving disp field 0'd 1295 } 1296 else 1297 sllx( a.base(), 32, a.base() ); 1298 } 1299 // Pad out the instruction sequence so it can be 1300 // patched later. 1301 if ( ForceRelocatable || (a.rtype() != relocInfo::none && 1302 a.rtype() != relocInfo::runtime_call_type) ) { 1303 while ( pc() < (save_pc + (7 * BytesPerInstWord )) ) 1304 nop(); 1305 } 1306#else 1307 Assembler::sethi(a.hi(), a.base(), a.rspec()); 1308#endif 1309 1310} 1311 1312int MacroAssembler::size_of_sethi(address a, bool worst_case) { 1313#ifdef _LP64 1314 if (worst_case) return 7; 1315 intptr_t iaddr = (intptr_t)a; 1316 int hi32 = (int)(iaddr >> 32); 1317 int lo32 = (int)(iaddr); 1318 int inst_count; 1319 if (hi32 == 0 && lo32 >= 0) 1320 inst_count = 1; 1321 else if (hi32 == -1) 1322 inst_count = 2; 1323 else { 1324 inst_count = 2; 1325 if ( hi32 & 0x3ff ) 1326 inst_count++; 1327 if ( lo32 & 0xFFFFFC00 ) { 1328 if( (lo32 >> 20) & 0xfff ) inst_count += 2; 1329 if( (lo32 >> 10) & 0x3ff ) inst_count += 2; 1330 } 1331 } 1332 return BytesPerInstWord * inst_count; 1333#else 1334 return BytesPerInstWord; 1335#endif 1336} 1337 1338int MacroAssembler::worst_case_size_of_set() { 1339 return size_of_sethi(NULL, true) + 1; 1340} 1341 1342void MacroAssembler::set(intptr_t value, Register d, 1343 RelocationHolder const& rspec) { 1344 Address val( d, (address)value, rspec); 1345 1346 if ( rspec.type() == relocInfo::none ) { 1347 // can optimize 1348 if (-4096 <= value && value <= 4095) { 1349 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended) 1350 return; 1351 } 1352 if (inv_hi22(hi22(value)) == value) { 1353 sethi(val); 1354 return; 1355 } 1356 } 1357 assert_not_delayed( (char *)"cannot put two instructions in delay slot" ); 1358 sethi( val ); 1359 if (rspec.type() != relocInfo::none || (value & 0x3ff) != 0) { 1360 add( d, value & 0x3ff, d, rspec); 1361 } 1362} 1363 1364void MacroAssembler::setsw(int value, Register d, 1365 RelocationHolder const& rspec) { 1366 Address val( d, (address)value, rspec); 1367 if ( rspec.type() == relocInfo::none ) { 1368 // can optimize 1369 if (-4096 <= value && value <= 4095) { 1370 or3(G0, value, d); 1371 return; 1372 } 1373 if (inv_hi22(hi22(value)) == value) { 1374 sethi( val ); 1375#ifndef _LP64 1376 if ( value < 0 ) { 1377 assert_not_delayed(); 1378 sra (d, G0, d); 1379 } 1380#endif 1381 return; 1382 } 1383 } 1384 assert_not_delayed(); 1385 sethi( val ); 1386 add( d, value & 0x3ff, d, rspec); 1387 1388 // (A negative value could be loaded in 2 insns with sethi/xor, 1389 // but it would take a more complex relocation.) 1390#ifndef _LP64 1391 if ( value < 0) 1392 sra(d, G0, d); 1393#endif 1394} 1395 1396// %%% End of moved six set instructions. 1397 1398 1399void MacroAssembler::set64(jlong value, Register d, Register tmp) { 1400 assert_not_delayed(); 1401 v9_dep(); 1402 1403 int hi = (int)(value >> 32); 1404 int lo = (int)(value & ~0); 1405 // (Matcher::isSimpleConstant64 knows about the following optimizations.) 1406 if (Assembler::is_simm13(lo) && value == lo) { 1407 or3(G0, lo, d); 1408 } else if (hi == 0) { 1409 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32 1410 if (low10(lo) != 0) 1411 or3(d, low10(lo), d); 1412 } 1413 else if (hi == -1) { 1414 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32 1415 xor3(d, low10(lo) ^ ~low10(~0), d); 1416 } 1417 else if (lo == 0) { 1418 if (Assembler::is_simm13(hi)) { 1419 or3(G0, hi, d); 1420 } else { 1421 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32 1422 if (low10(hi) != 0) 1423 or3(d, low10(hi), d); 1424 } 1425 sllx(d, 32, d); 1426 } 1427 else { 1428 Assembler::sethi(hi, tmp); 1429 Assembler::sethi(lo, d); // macro assembler version sign-extends 1430 if (low10(hi) != 0) 1431 or3 (tmp, low10(hi), tmp); 1432 if (low10(lo) != 0) 1433 or3 ( d, low10(lo), d); 1434 sllx(tmp, 32, tmp); 1435 or3 (d, tmp, d); 1436 } 1437} 1438 1439// compute size in bytes of sparc frame, given 1440// number of extraWords 1441int MacroAssembler::total_frame_size_in_bytes(int extraWords) { 1442 1443 int nWords = frame::memory_parameter_word_sp_offset; 1444 1445 nWords += extraWords; 1446 1447 if (nWords & 1) ++nWords; // round up to double-word 1448 1449 return nWords * BytesPerWord; 1450} 1451 1452 1453// save_frame: given number of "extra" words in frame, 1454// issue approp. save instruction (p 200, v8 manual) 1455 1456void MacroAssembler::save_frame(int extraWords = 0) { 1457 int delta = -total_frame_size_in_bytes(extraWords); 1458 if (is_simm13(delta)) { 1459 save(SP, delta, SP); 1460 } else { 1461 set(delta, G3_scratch); 1462 save(SP, G3_scratch, SP); 1463 } 1464} 1465 1466 1467void MacroAssembler::save_frame_c1(int size_in_bytes) { 1468 if (is_simm13(-size_in_bytes)) { 1469 save(SP, -size_in_bytes, SP); 1470 } else { 1471 set(-size_in_bytes, G3_scratch); 1472 save(SP, G3_scratch, SP); 1473 } 1474} 1475 1476 1477void MacroAssembler::save_frame_and_mov(int extraWords, 1478 Register s1, Register d1, 1479 Register s2, Register d2) { 1480 assert_not_delayed(); 1481 1482 // The trick here is to use precisely the same memory word 1483 // that trap handlers also use to save the register. 1484 // This word cannot be used for any other purpose, but 1485 // it works fine to save the register's value, whether or not 1486 // an interrupt flushes register windows at any given moment! 1487 Address s1_addr; 1488 if (s1->is_valid() && (s1->is_in() || s1->is_local())) { 1489 s1_addr = s1->address_in_saved_window(); 1490 st_ptr(s1, s1_addr); 1491 } 1492 1493 Address s2_addr; 1494 if (s2->is_valid() && (s2->is_in() || s2->is_local())) { 1495 s2_addr = s2->address_in_saved_window(); 1496 st_ptr(s2, s2_addr); 1497 } 1498 1499 save_frame(extraWords); 1500 1501 if (s1_addr.base() == SP) { 1502 ld_ptr(s1_addr.after_save(), d1); 1503 } else if (s1->is_valid()) { 1504 mov(s1->after_save(), d1); 1505 } 1506 1507 if (s2_addr.base() == SP) { 1508 ld_ptr(s2_addr.after_save(), d2); 1509 } else if (s2->is_valid()) { 1510 mov(s2->after_save(), d2); 1511 } 1512} 1513 1514 1515Address MacroAssembler::allocate_oop_address(jobject obj, Register d) { 1516 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); 1517 int oop_index = oop_recorder()->allocate_index(obj); 1518 return Address(d, address(obj), oop_Relocation::spec(oop_index)); 1519} 1520 1521 1522Address MacroAssembler::constant_oop_address(jobject obj, Register d) { 1523 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); 1524 int oop_index = oop_recorder()->find_index(obj); 1525 return Address(d, address(obj), oop_Relocation::spec(oop_index)); 1526} 1527 1528void MacroAssembler::set_narrow_oop(jobject obj, Register d) { 1529 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); 1530 int oop_index = oop_recorder()->find_index(obj); 1531 RelocationHolder rspec = oop_Relocation::spec(oop_index); 1532 1533 assert_not_delayed(); 1534 // Relocation with special format (see relocInfo_sparc.hpp). 1535 relocate(rspec, 1); 1536 // Assembler::sethi(0x3fffff, d); 1537 emit_long( op(branch_op) | rd(d) | op2(sethi_op2) | hi22(0x3fffff) ); 1538 // Don't add relocation for 'add'. Do patching during 'sethi' processing. 1539 add(d, 0x3ff, d); 1540 1541} 1542 1543 1544void MacroAssembler::align(int modulus) { 1545 while (offset() % modulus != 0) nop(); 1546} 1547 1548 1549void MacroAssembler::safepoint() { 1550 relocate(breakpoint_Relocation::spec(breakpoint_Relocation::safepoint)); 1551} 1552 1553 1554void RegistersForDebugging::print(outputStream* s) { 1555 int j; 1556 for ( j = 0; j < 8; ++j ) 1557 if ( j != 6 ) s->print_cr("i%d = 0x%.16lx", j, i[j]); 1558 else s->print_cr( "fp = 0x%.16lx", i[j]); 1559 s->cr(); 1560 1561 for ( j = 0; j < 8; ++j ) 1562 s->print_cr("l%d = 0x%.16lx", j, l[j]); 1563 s->cr(); 1564 1565 for ( j = 0; j < 8; ++j ) 1566 if ( j != 6 ) s->print_cr("o%d = 0x%.16lx", j, o[j]); 1567 else s->print_cr( "sp = 0x%.16lx", o[j]); 1568 s->cr(); 1569 1570 for ( j = 0; j < 8; ++j ) 1571 s->print_cr("g%d = 0x%.16lx", j, g[j]); 1572 s->cr(); 1573 1574 // print out floats with compression 1575 for (j = 0; j < 32; ) { 1576 jfloat val = f[j]; 1577 int last = j; 1578 for ( ; last+1 < 32; ++last ) { 1579 char b1[1024], b2[1024]; 1580 sprintf(b1, "%f", val); 1581 sprintf(b2, "%f", f[last+1]); 1582 if (strcmp(b1, b2)) 1583 break; 1584 } 1585 s->print("f%d", j); 1586 if ( j != last ) s->print(" - f%d", last); 1587 s->print(" = %f", val); 1588 s->fill_to(25); 1589 s->print_cr(" (0x%x)", val); 1590 j = last + 1; 1591 } 1592 s->cr(); 1593 1594 // and doubles (evens only) 1595 for (j = 0; j < 32; ) { 1596 jdouble val = d[j]; 1597 int last = j; 1598 for ( ; last+1 < 32; ++last ) { 1599 char b1[1024], b2[1024]; 1600 sprintf(b1, "%f", val); 1601 sprintf(b2, "%f", d[last+1]); 1602 if (strcmp(b1, b2)) 1603 break; 1604 } 1605 s->print("d%d", 2 * j); 1606 if ( j != last ) s->print(" - d%d", last); 1607 s->print(" = %f", val); 1608 s->fill_to(30); 1609 s->print("(0x%x)", *(int*)&val); 1610 s->fill_to(42); 1611 s->print_cr("(0x%x)", *(1 + (int*)&val)); 1612 j = last + 1; 1613 } 1614 s->cr(); 1615} 1616 1617void RegistersForDebugging::save_registers(MacroAssembler* a) { 1618 a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0); 1619 a->flush_windows(); 1620 int i; 1621 for (i = 0; i < 8; ++i) { 1622 a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i)); 1623 a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i)); 1624 a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i)); 1625 a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i)); 1626 } 1627 for (i = 0; i < 32; ++i) { 1628 a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i)); 1629 } 1630 for (i = 0; i < (VM_Version::v9_instructions_work() ? 64 : 32); i += 2) { 1631 a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i)); 1632 } 1633} 1634 1635void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) { 1636 for (int i = 1; i < 8; ++i) { 1637 a->ld_ptr(r, g_offset(i), as_gRegister(i)); 1638 } 1639 for (int j = 0; j < 32; ++j) { 1640 a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j)); 1641 } 1642 for (int k = 0; k < (VM_Version::v9_instructions_work() ? 64 : 32); k += 2) { 1643 a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k)); 1644 } 1645} 1646 1647 1648// pushes double TOS element of FPU stack on CPU stack; pops from FPU stack 1649void MacroAssembler::push_fTOS() { 1650 // %%%%%% need to implement this 1651} 1652 1653// pops double TOS element from CPU stack and pushes on FPU stack 1654void MacroAssembler::pop_fTOS() { 1655 // %%%%%% need to implement this 1656} 1657 1658void MacroAssembler::empty_FPU_stack() { 1659 // %%%%%% need to implement this 1660} 1661 1662void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) { 1663 // plausibility check for oops 1664 if (!VerifyOops) return; 1665 1666 if (reg == G0) return; // always NULL, which is always an oop 1667 1668 char buffer[64]; 1669#ifdef COMPILER1 1670 if (CommentedAssembly) { 1671 snprintf(buffer, sizeof(buffer), "verify_oop at %d", offset()); 1672 block_comment(buffer); 1673 } 1674#endif 1675 1676 int len = strlen(file) + strlen(msg) + 1 + 4; 1677 sprintf(buffer, "%d", line); 1678 len += strlen(buffer); 1679 sprintf(buffer, " at offset %d ", offset()); 1680 len += strlen(buffer); 1681 char * real_msg = new char[len]; 1682 sprintf(real_msg, "%s%s(%s:%d)", msg, buffer, file, line); 1683 1684 // Call indirectly to solve generation ordering problem 1685 Address a(O7, (address)StubRoutines::verify_oop_subroutine_entry_address()); 1686 1687 // Make some space on stack above the current register window. 1688 // Enough to hold 8 64-bit registers. 1689 add(SP,-8*8,SP); 1690 1691 // Save some 64-bit registers; a normal 'save' chops the heads off 1692 // of 64-bit longs in the 32-bit build. 1693 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); 1694 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); 1695 mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed 1696 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); 1697 1698 set((intptr_t)real_msg, O1); 1699 // Load address to call to into O7 1700 load_ptr_contents(a, O7); 1701 // Register call to verify_oop_subroutine 1702 callr(O7, G0); 1703 delayed()->nop(); 1704 // recover frame size 1705 add(SP, 8*8,SP); 1706} 1707 1708void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) { 1709 // plausibility check for oops 1710 if (!VerifyOops) return; 1711 1712 char buffer[64]; 1713 sprintf(buffer, "%d", line); 1714 int len = strlen(file) + strlen(msg) + 1 + 4 + strlen(buffer); 1715 sprintf(buffer, " at SP+%d ", addr.disp()); 1716 len += strlen(buffer); 1717 char * real_msg = new char[len]; 1718 sprintf(real_msg, "%s at SP+%d (%s:%d)", msg, addr.disp(), file, line); 1719 1720 // Call indirectly to solve generation ordering problem 1721 Address a(O7, (address)StubRoutines::verify_oop_subroutine_entry_address()); 1722 1723 // Make some space on stack above the current register window. 1724 // Enough to hold 8 64-bit registers. 1725 add(SP,-8*8,SP); 1726 1727 // Save some 64-bit registers; a normal 'save' chops the heads off 1728 // of 64-bit longs in the 32-bit build. 1729 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); 1730 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); 1731 ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed 1732 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); 1733 1734 set((intptr_t)real_msg, O1); 1735 // Load address to call to into O7 1736 load_ptr_contents(a, O7); 1737 // Register call to verify_oop_subroutine 1738 callr(O7, G0); 1739 delayed()->nop(); 1740 // recover frame size 1741 add(SP, 8*8,SP); 1742} 1743 1744// side-door communication with signalHandler in os_solaris.cpp 1745address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL }; 1746 1747// This macro is expanded just once; it creates shared code. Contract: 1748// receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY 1749// registers, including flags. May not use a register 'save', as this blows 1750// the high bits of the O-regs if they contain Long values. Acts as a 'leaf' 1751// call. 1752void MacroAssembler::verify_oop_subroutine() { 1753 assert( VM_Version::v9_instructions_work(), "VerifyOops not supported for V8" ); 1754 1755 // Leaf call; no frame. 1756 Label succeed, fail, null_or_fail; 1757 1758 // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home). 1759 // O0 is now the oop to be checked. O7 is the return address. 1760 Register O0_obj = O0; 1761 1762 // Save some more registers for temps. 1763 stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8); 1764 stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8); 1765 stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8); 1766 stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8); 1767 1768 // Save flags 1769 Register O5_save_flags = O5; 1770 rdccr( O5_save_flags ); 1771 1772 { // count number of verifies 1773 Register O2_adr = O2; 1774 Register O3_accum = O3; 1775 Address count_addr( O2_adr, (address) StubRoutines::verify_oop_count_addr() ); 1776 sethi(count_addr); 1777 ld(count_addr, O3_accum); 1778 inc(O3_accum); 1779 st(O3_accum, count_addr); 1780 } 1781 1782 Register O2_mask = O2; 1783 Register O3_bits = O3; 1784 Register O4_temp = O4; 1785 1786 // mark lower end of faulting range 1787 assert(_verify_oop_implicit_branch[0] == NULL, "set once"); 1788 _verify_oop_implicit_branch[0] = pc(); 1789 1790 // We can't check the mark oop because it could be in the process of 1791 // locking or unlocking while this is running. 1792 set(Universe::verify_oop_mask (), O2_mask); 1793 set(Universe::verify_oop_bits (), O3_bits); 1794 1795 // assert((obj & oop_mask) == oop_bits); 1796 and3(O0_obj, O2_mask, O4_temp); 1797 cmp(O4_temp, O3_bits); 1798 brx(notEqual, false, pn, null_or_fail); 1799 delayed()->nop(); 1800 1801 if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) { 1802 // the null_or_fail case is useless; must test for null separately 1803 br_null(O0_obj, false, pn, succeed); 1804 delayed()->nop(); 1805 } 1806 1807 // Check the klassOop of this object for being in the right area of memory. 1808 // Cannot do the load in the delay above slot in case O0 is null 1809 load_klass(O0_obj, O0_obj); 1810 // assert((klass & klass_mask) == klass_bits); 1811 if( Universe::verify_klass_mask() != Universe::verify_oop_mask() ) 1812 set(Universe::verify_klass_mask(), O2_mask); 1813 if( Universe::verify_klass_bits() != Universe::verify_oop_bits() ) 1814 set(Universe::verify_klass_bits(), O3_bits); 1815 and3(O0_obj, O2_mask, O4_temp); 1816 cmp(O4_temp, O3_bits); 1817 brx(notEqual, false, pn, fail); 1818 delayed()->nop(); 1819 // Check the klass's klass 1820 load_klass(O0_obj, O0_obj); 1821 and3(O0_obj, O2_mask, O4_temp); 1822 cmp(O4_temp, O3_bits); 1823 brx(notEqual, false, pn, fail); 1824 delayed()->wrccr( O5_save_flags ); // Restore CCR's 1825 1826 // mark upper end of faulting range 1827 _verify_oop_implicit_branch[1] = pc(); 1828 1829 //----------------------- 1830 // all tests pass 1831 bind(succeed); 1832 1833 // Restore prior 64-bit registers 1834 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0); 1835 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1); 1836 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2); 1837 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3); 1838 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4); 1839 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5); 1840 1841 retl(); // Leaf return; restore prior O7 in delay slot 1842 delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7); 1843 1844 //----------------------- 1845 bind(null_or_fail); // nulls are less common but OK 1846 br_null(O0_obj, false, pt, succeed); 1847 delayed()->wrccr( O5_save_flags ); // Restore CCR's 1848 1849 //----------------------- 1850 // report failure: 1851 bind(fail); 1852 _verify_oop_implicit_branch[2] = pc(); 1853 1854 wrccr( O5_save_flags ); // Restore CCR's 1855 1856 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); 1857 1858 // stop_subroutine expects message pointer in I1. 1859 mov(I1, O1); 1860 1861 // Restore prior 64-bit registers 1862 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0); 1863 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1); 1864 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2); 1865 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3); 1866 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4); 1867 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5); 1868 1869 // factor long stop-sequence into subroutine to save space 1870 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); 1871 1872 // call indirectly to solve generation ordering problem 1873 Address a(O5, (address)StubRoutines::Sparc::stop_subroutine_entry_address()); 1874 load_ptr_contents(a, O5); 1875 jmpl(O5, 0, O7); 1876 delayed()->nop(); 1877} 1878 1879 1880void MacroAssembler::stop(const char* msg) { 1881 // save frame first to get O7 for return address 1882 // add one word to size in case struct is odd number of words long 1883 // It must be doubleword-aligned for storing doubles into it. 1884 1885 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); 1886 1887 // stop_subroutine expects message pointer in I1. 1888 set((intptr_t)msg, O1); 1889 1890 // factor long stop-sequence into subroutine to save space 1891 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); 1892 1893 // call indirectly to solve generation ordering problem 1894 Address a(O5, (address)StubRoutines::Sparc::stop_subroutine_entry_address()); 1895 load_ptr_contents(a, O5); 1896 jmpl(O5, 0, O7); 1897 delayed()->nop(); 1898 1899 breakpoint_trap(); // make stop actually stop rather than writing 1900 // unnoticeable results in the output files. 1901 1902 // restore(); done in callee to save space! 1903} 1904 1905 1906void MacroAssembler::warn(const char* msg) { 1907 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); 1908 RegistersForDebugging::save_registers(this); 1909 mov(O0, L0); 1910 set((intptr_t)msg, O0); 1911 call( CAST_FROM_FN_PTR(address, warning) ); 1912 delayed()->nop(); 1913// ret(); 1914// delayed()->restore(); 1915 RegistersForDebugging::restore_registers(this, L0); 1916 restore(); 1917} 1918 1919 1920void MacroAssembler::untested(const char* what) { 1921 // We must be able to turn interactive prompting off 1922 // in order to run automated test scripts on the VM 1923 // Use the flag ShowMessageBoxOnError 1924 1925 char* b = new char[1024]; 1926 sprintf(b, "untested: %s", what); 1927 1928 if ( ShowMessageBoxOnError ) stop(b); 1929 else warn(b); 1930} 1931 1932 1933void MacroAssembler::stop_subroutine() { 1934 RegistersForDebugging::save_registers(this); 1935 1936 // for the sake of the debugger, stick a PC on the current frame 1937 // (this assumes that the caller has performed an extra "save") 1938 mov(I7, L7); 1939 add(O7, -7 * BytesPerInt, I7); 1940 1941 save_frame(); // one more save to free up another O7 register 1942 mov(I0, O1); // addr of reg save area 1943 1944 // We expect pointer to message in I1. Caller must set it up in O1 1945 mov(I1, O0); // get msg 1946 call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type); 1947 delayed()->nop(); 1948 1949 restore(); 1950 1951 RegistersForDebugging::restore_registers(this, O0); 1952 1953 save_frame(0); 1954 call(CAST_FROM_FN_PTR(address,breakpoint)); 1955 delayed()->nop(); 1956 restore(); 1957 1958 mov(L7, I7); 1959 retl(); 1960 delayed()->restore(); // see stop above 1961} 1962 1963 1964void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) { 1965 if ( ShowMessageBoxOnError ) { 1966 JavaThreadState saved_state = JavaThread::current()->thread_state(); 1967 JavaThread::current()->set_thread_state(_thread_in_vm); 1968 { 1969 // In order to get locks work, we need to fake a in_VM state 1970 ttyLocker ttyl; 1971 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg); 1972 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 1973 ::tty->print_cr("Interpreter::bytecode_counter = %d", BytecodeCounter::counter_value()); 1974 } 1975 if (os::message_box(msg, "Execution stopped, print registers?")) 1976 regs->print(::tty); 1977 } 1978 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state); 1979 } 1980 else 1981 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 1982 assert(false, "error"); 1983} 1984 1985 1986#ifndef PRODUCT 1987void MacroAssembler::test() { 1988 ResourceMark rm; 1989 1990 CodeBuffer cb("test", 10000, 10000); 1991 MacroAssembler* a = new MacroAssembler(&cb); 1992 VM_Version::allow_all(); 1993 a->test_v9(); 1994 a->test_v8_onlys(); 1995 VM_Version::revert(); 1996 1997 StubRoutines::Sparc::test_stop_entry()(); 1998} 1999#endif 2000 2001 2002void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) { 2003 subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words? 2004 Label no_extras; 2005 br( negative, true, pt, no_extras ); // if neg, clear reg 2006 delayed()->set( 0, Rresult); // annuled, so only if taken 2007 bind( no_extras ); 2008} 2009 2010 2011void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) { 2012#ifdef _LP64 2013 add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult); 2014#else 2015 add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult); 2016#endif 2017 bclr(1, Rresult); 2018 sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes 2019} 2020 2021 2022void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) { 2023 calc_frame_size(Rextra_words, Rresult); 2024 neg(Rresult); 2025 save(SP, Rresult, SP); 2026} 2027 2028 2029// --------------------------------------------------------- 2030Assembler::RCondition cond2rcond(Assembler::Condition c) { 2031 switch (c) { 2032 /*case zero: */ 2033 case Assembler::equal: return Assembler::rc_z; 2034 case Assembler::lessEqual: return Assembler::rc_lez; 2035 case Assembler::less: return Assembler::rc_lz; 2036 /*case notZero:*/ 2037 case Assembler::notEqual: return Assembler::rc_nz; 2038 case Assembler::greater: return Assembler::rc_gz; 2039 case Assembler::greaterEqual: return Assembler::rc_gez; 2040 } 2041 ShouldNotReachHere(); 2042 return Assembler::rc_z; 2043} 2044 2045// compares register with zero and branches. NOT FOR USE WITH 64-bit POINTERS 2046void MacroAssembler::br_zero( Condition c, bool a, Predict p, Register s1, Label& L) { 2047 tst(s1); 2048 br (c, a, p, L); 2049} 2050 2051 2052// Compares a pointer register with zero and branches on null. 2053// Does a test & branch on 32-bit systems and a register-branch on 64-bit. 2054void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) { 2055 assert_not_delayed(); 2056#ifdef _LP64 2057 bpr( rc_z, a, p, s1, L ); 2058#else 2059 tst(s1); 2060 br ( zero, a, p, L ); 2061#endif 2062} 2063 2064void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) { 2065 assert_not_delayed(); 2066#ifdef _LP64 2067 bpr( rc_nz, a, p, s1, L ); 2068#else 2069 tst(s1); 2070 br ( notZero, a, p, L ); 2071#endif 2072} 2073 2074void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p, 2075 Register s1, address d, 2076 relocInfo::relocType rt ) { 2077 if (VM_Version::v9_instructions_work()) { 2078 bpr(rc, a, p, s1, d, rt); 2079 } else { 2080 tst(s1); 2081 br(reg_cond_to_cc_cond(rc), a, p, d, rt); 2082 } 2083} 2084 2085void MacroAssembler::br_on_reg_cond( RCondition rc, bool a, Predict p, 2086 Register s1, Label& L ) { 2087 if (VM_Version::v9_instructions_work()) { 2088 bpr(rc, a, p, s1, L); 2089 } else { 2090 tst(s1); 2091 br(reg_cond_to_cc_cond(rc), a, p, L); 2092 } 2093} 2094 2095 2096// instruction sequences factored across compiler & interpreter 2097 2098 2099void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low, 2100 Register Rb_hi, Register Rb_low, 2101 Register Rresult) { 2102 2103 Label check_low_parts, done; 2104 2105 cmp(Ra_hi, Rb_hi ); // compare hi parts 2106 br(equal, true, pt, check_low_parts); 2107 delayed()->cmp(Ra_low, Rb_low); // test low parts 2108 2109 // And, with an unsigned comparison, it does not matter if the numbers 2110 // are negative or not. 2111 // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff. 2112 // The second one is bigger (unsignedly). 2113 2114 // Other notes: The first move in each triplet can be unconditional 2115 // (and therefore probably prefetchable). 2116 // And the equals case for the high part does not need testing, 2117 // since that triplet is reached only after finding the high halves differ. 2118 2119 if (VM_Version::v9_instructions_work()) { 2120 2121 mov ( -1, Rresult); 2122 ba( false, done ); delayed()-> movcc(greater, false, icc, 1, Rresult); 2123 } 2124 else { 2125 br(less, true, pt, done); delayed()-> set(-1, Rresult); 2126 br(greater, true, pt, done); delayed()-> set( 1, Rresult); 2127 } 2128 2129 bind( check_low_parts ); 2130 2131 if (VM_Version::v9_instructions_work()) { 2132 mov( -1, Rresult); 2133 movcc(equal, false, icc, 0, Rresult); 2134 movcc(greaterUnsigned, false, icc, 1, Rresult); 2135 } 2136 else { 2137 set(-1, Rresult); 2138 br(equal, true, pt, done); delayed()->set( 0, Rresult); 2139 br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult); 2140 } 2141 bind( done ); 2142} 2143 2144void MacroAssembler::lneg( Register Rhi, Register Rlow ) { 2145 subcc( G0, Rlow, Rlow ); 2146 subc( G0, Rhi, Rhi ); 2147} 2148 2149void MacroAssembler::lshl( Register Rin_high, Register Rin_low, 2150 Register Rcount, 2151 Register Rout_high, Register Rout_low, 2152 Register Rtemp ) { 2153 2154 2155 Register Ralt_count = Rtemp; 2156 Register Rxfer_bits = Rtemp; 2157 2158 assert( Ralt_count != Rin_high 2159 && Ralt_count != Rin_low 2160 && Ralt_count != Rcount 2161 && Rxfer_bits != Rin_low 2162 && Rxfer_bits != Rin_high 2163 && Rxfer_bits != Rcount 2164 && Rxfer_bits != Rout_low 2165 && Rout_low != Rin_high, 2166 "register alias checks"); 2167 2168 Label big_shift, done; 2169 2170 // This code can be optimized to use the 64 bit shifts in V9. 2171 // Here we use the 32 bit shifts. 2172 2173 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits 2174 subcc(Rcount, 31, Ralt_count); 2175 br(greater, true, pn, big_shift); 2176 delayed()-> 2177 dec(Ralt_count); 2178 2179 // shift < 32 bits, Ralt_count = Rcount-31 2180 2181 // We get the transfer bits by shifting right by 32-count the low 2182 // register. This is done by shifting right by 31-count and then by one 2183 // more to take care of the special (rare) case where count is zero 2184 // (shifting by 32 would not work). 2185 2186 neg( Ralt_count ); 2187 2188 // The order of the next two instructions is critical in the case where 2189 // Rin and Rout are the same and should not be reversed. 2190 2191 srl( Rin_low, Ralt_count, Rxfer_bits ); // shift right by 31-count 2192 if (Rcount != Rout_low) { 2193 sll( Rin_low, Rcount, Rout_low ); // low half 2194 } 2195 sll( Rin_high, Rcount, Rout_high ); 2196 if (Rcount == Rout_low) { 2197 sll( Rin_low, Rcount, Rout_low ); // low half 2198 } 2199 srl( Rxfer_bits, 1, Rxfer_bits ); // shift right by one more 2200 ba (false, done); 2201 delayed()-> 2202 or3( Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low 2203 2204 // shift >= 32 bits, Ralt_count = Rcount-32 2205 bind(big_shift); 2206 sll( Rin_low, Ralt_count, Rout_high ); 2207 clr( Rout_low ); 2208 2209 bind(done); 2210} 2211 2212 2213void MacroAssembler::lshr( Register Rin_high, Register Rin_low, 2214 Register Rcount, 2215 Register Rout_high, Register Rout_low, 2216 Register Rtemp ) { 2217 2218 Register Ralt_count = Rtemp; 2219 Register Rxfer_bits = Rtemp; 2220 2221 assert( Ralt_count != Rin_high 2222 && Ralt_count != Rin_low 2223 && Ralt_count != Rcount 2224 && Rxfer_bits != Rin_low 2225 && Rxfer_bits != Rin_high 2226 && Rxfer_bits != Rcount 2227 && Rxfer_bits != Rout_high 2228 && Rout_high != Rin_low, 2229 "register alias checks"); 2230 2231 Label big_shift, done; 2232 2233 // This code can be optimized to use the 64 bit shifts in V9. 2234 // Here we use the 32 bit shifts. 2235 2236 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits 2237 subcc(Rcount, 31, Ralt_count); 2238 br(greater, true, pn, big_shift); 2239 delayed()->dec(Ralt_count); 2240 2241 // shift < 32 bits, Ralt_count = Rcount-31 2242 2243 // We get the transfer bits by shifting left by 32-count the high 2244 // register. This is done by shifting left by 31-count and then by one 2245 // more to take care of the special (rare) case where count is zero 2246 // (shifting by 32 would not work). 2247 2248 neg( Ralt_count ); 2249 if (Rcount != Rout_low) { 2250 srl( Rin_low, Rcount, Rout_low ); 2251 } 2252 2253 // The order of the next two instructions is critical in the case where 2254 // Rin and Rout are the same and should not be reversed. 2255 2256 sll( Rin_high, Ralt_count, Rxfer_bits ); // shift left by 31-count 2257 sra( Rin_high, Rcount, Rout_high ); // high half 2258 sll( Rxfer_bits, 1, Rxfer_bits ); // shift left by one more 2259 if (Rcount == Rout_low) { 2260 srl( Rin_low, Rcount, Rout_low ); 2261 } 2262 ba (false, done); 2263 delayed()-> 2264 or3( Rout_low, Rxfer_bits, Rout_low ); // new low value: or shifted old low part and xfer from high 2265 2266 // shift >= 32 bits, Ralt_count = Rcount-32 2267 bind(big_shift); 2268 2269 sra( Rin_high, Ralt_count, Rout_low ); 2270 sra( Rin_high, 31, Rout_high ); // sign into hi 2271 2272 bind( done ); 2273} 2274 2275 2276 2277void MacroAssembler::lushr( Register Rin_high, Register Rin_low, 2278 Register Rcount, 2279 Register Rout_high, Register Rout_low, 2280 Register Rtemp ) { 2281 2282 Register Ralt_count = Rtemp; 2283 Register Rxfer_bits = Rtemp; 2284 2285 assert( Ralt_count != Rin_high 2286 && Ralt_count != Rin_low 2287 && Ralt_count != Rcount 2288 && Rxfer_bits != Rin_low 2289 && Rxfer_bits != Rin_high 2290 && Rxfer_bits != Rcount 2291 && Rxfer_bits != Rout_high 2292 && Rout_high != Rin_low, 2293 "register alias checks"); 2294 2295 Label big_shift, done; 2296 2297 // This code can be optimized to use the 64 bit shifts in V9. 2298 // Here we use the 32 bit shifts. 2299 2300 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits 2301 subcc(Rcount, 31, Ralt_count); 2302 br(greater, true, pn, big_shift); 2303 delayed()->dec(Ralt_count); 2304 2305 // shift < 32 bits, Ralt_count = Rcount-31 2306 2307 // We get the transfer bits by shifting left by 32-count the high 2308 // register. This is done by shifting left by 31-count and then by one 2309 // more to take care of the special (rare) case where count is zero 2310 // (shifting by 32 would not work). 2311 2312 neg( Ralt_count ); 2313 if (Rcount != Rout_low) { 2314 srl( Rin_low, Rcount, Rout_low ); 2315 } 2316 2317 // The order of the next two instructions is critical in the case where 2318 // Rin and Rout are the same and should not be reversed. 2319 2320 sll( Rin_high, Ralt_count, Rxfer_bits ); // shift left by 31-count 2321 srl( Rin_high, Rcount, Rout_high ); // high half 2322 sll( Rxfer_bits, 1, Rxfer_bits ); // shift left by one more 2323 if (Rcount == Rout_low) { 2324 srl( Rin_low, Rcount, Rout_low ); 2325 } 2326 ba (false, done); 2327 delayed()-> 2328 or3( Rout_low, Rxfer_bits, Rout_low ); // new low value: or shifted old low part and xfer from high 2329 2330 // shift >= 32 bits, Ralt_count = Rcount-32 2331 bind(big_shift); 2332 2333 srl( Rin_high, Ralt_count, Rout_low ); 2334 clr( Rout_high ); 2335 2336 bind( done ); 2337} 2338 2339#ifdef _LP64 2340void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) { 2341 cmp(Ra, Rb); 2342 mov( -1, Rresult); 2343 movcc(equal, false, xcc, 0, Rresult); 2344 movcc(greater, false, xcc, 1, Rresult); 2345} 2346#endif 2347 2348 2349void MacroAssembler::float_cmp( bool is_float, int unordered_result, 2350 FloatRegister Fa, FloatRegister Fb, 2351 Register Rresult) { 2352 2353 fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb); 2354 2355 Condition lt = unordered_result == -1 ? f_unorderedOrLess : f_less; 2356 Condition eq = f_equal; 2357 Condition gt = unordered_result == 1 ? f_unorderedOrGreater : f_greater; 2358 2359 if (VM_Version::v9_instructions_work()) { 2360 2361 mov( -1, Rresult ); 2362 movcc( eq, true, fcc0, 0, Rresult ); 2363 movcc( gt, true, fcc0, 1, Rresult ); 2364 2365 } else { 2366 Label done; 2367 2368 set( -1, Rresult ); 2369 //fb(lt, true, pn, done); delayed()->set( -1, Rresult ); 2370 fb( eq, true, pn, done); delayed()->set( 0, Rresult ); 2371 fb( gt, true, pn, done); delayed()->set( 1, Rresult ); 2372 2373 bind (done); 2374 } 2375} 2376 2377 2378void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) 2379{ 2380 if (VM_Version::v9_instructions_work()) { 2381 Assembler::fneg(w, s, d); 2382 } else { 2383 if (w == FloatRegisterImpl::S) { 2384 Assembler::fneg(w, s, d); 2385 } else if (w == FloatRegisterImpl::D) { 2386 // number() does a sanity check on the alignment. 2387 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && 2388 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); 2389 2390 Assembler::fneg(FloatRegisterImpl::S, s, d); 2391 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); 2392 } else { 2393 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); 2394 2395 // number() does a sanity check on the alignment. 2396 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && 2397 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); 2398 2399 Assembler::fneg(FloatRegisterImpl::S, s, d); 2400 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); 2401 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); 2402 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); 2403 } 2404 } 2405} 2406 2407void MacroAssembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) 2408{ 2409 if (VM_Version::v9_instructions_work()) { 2410 Assembler::fmov(w, s, d); 2411 } else { 2412 if (w == FloatRegisterImpl::S) { 2413 Assembler::fmov(w, s, d); 2414 } else if (w == FloatRegisterImpl::D) { 2415 // number() does a sanity check on the alignment. 2416 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && 2417 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); 2418 2419 Assembler::fmov(FloatRegisterImpl::S, s, d); 2420 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); 2421 } else { 2422 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); 2423 2424 // number() does a sanity check on the alignment. 2425 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && 2426 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); 2427 2428 Assembler::fmov(FloatRegisterImpl::S, s, d); 2429 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); 2430 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); 2431 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); 2432 } 2433 } 2434} 2435 2436void MacroAssembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) 2437{ 2438 if (VM_Version::v9_instructions_work()) { 2439 Assembler::fabs(w, s, d); 2440 } else { 2441 if (w == FloatRegisterImpl::S) { 2442 Assembler::fabs(w, s, d); 2443 } else if (w == FloatRegisterImpl::D) { 2444 // number() does a sanity check on the alignment. 2445 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && 2446 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); 2447 2448 Assembler::fabs(FloatRegisterImpl::S, s, d); 2449 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); 2450 } else { 2451 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); 2452 2453 // number() does a sanity check on the alignment. 2454 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && 2455 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); 2456 2457 Assembler::fabs(FloatRegisterImpl::S, s, d); 2458 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); 2459 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); 2460 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); 2461 } 2462 } 2463} 2464 2465void MacroAssembler::save_all_globals_into_locals() { 2466 mov(G1,L1); 2467 mov(G2,L2); 2468 mov(G3,L3); 2469 mov(G4,L4); 2470 mov(G5,L5); 2471 mov(G6,L6); 2472 mov(G7,L7); 2473} 2474 2475void MacroAssembler::restore_globals_from_locals() { 2476 mov(L1,G1); 2477 mov(L2,G2); 2478 mov(L3,G3); 2479 mov(L4,G4); 2480 mov(L5,G5); 2481 mov(L6,G6); 2482 mov(L7,G7); 2483} 2484 2485// Use for 64 bit operation. 2486void MacroAssembler::casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm) 2487{ 2488 // store ptr_reg as the new top value 2489#ifdef _LP64 2490 casx(top_ptr_reg, top_reg, ptr_reg); 2491#else 2492 cas_under_lock(top_ptr_reg, top_reg, ptr_reg, lock_addr, use_call_vm); 2493#endif // _LP64 2494} 2495 2496// [RGV] This routine does not handle 64 bit operations. 2497// use casx_under_lock() or casx directly!!! 2498void MacroAssembler::cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm) 2499{ 2500 // store ptr_reg as the new top value 2501 if (VM_Version::v9_instructions_work()) { 2502 cas(top_ptr_reg, top_reg, ptr_reg); 2503 } else { 2504 2505 // If the register is not an out nor global, it is not visible 2506 // after the save. Allocate a register for it, save its 2507 // value in the register save area (the save may not flush 2508 // registers to the save area). 2509 2510 Register top_ptr_reg_after_save; 2511 Register top_reg_after_save; 2512 Register ptr_reg_after_save; 2513 2514 if (top_ptr_reg->is_out() || top_ptr_reg->is_global()) { 2515 top_ptr_reg_after_save = top_ptr_reg->after_save(); 2516 } else { 2517 Address reg_save_addr = top_ptr_reg->address_in_saved_window(); 2518 top_ptr_reg_after_save = L0; 2519 st(top_ptr_reg, reg_save_addr); 2520 } 2521 2522 if (top_reg->is_out() || top_reg->is_global()) { 2523 top_reg_after_save = top_reg->after_save(); 2524 } else { 2525 Address reg_save_addr = top_reg->address_in_saved_window(); 2526 top_reg_after_save = L1; 2527 st(top_reg, reg_save_addr); 2528 } 2529 2530 if (ptr_reg->is_out() || ptr_reg->is_global()) { 2531 ptr_reg_after_save = ptr_reg->after_save(); 2532 } else { 2533 Address reg_save_addr = ptr_reg->address_in_saved_window(); 2534 ptr_reg_after_save = L2; 2535 st(ptr_reg, reg_save_addr); 2536 } 2537 2538 const Register& lock_reg = L3; 2539 const Register& lock_ptr_reg = L4; 2540 const Register& value_reg = L5; 2541 const Register& yield_reg = L6; 2542 const Register& yieldall_reg = L7; 2543 2544 save_frame(); 2545 2546 if (top_ptr_reg_after_save == L0) { 2547 ld(top_ptr_reg->address_in_saved_window().after_save(), top_ptr_reg_after_save); 2548 } 2549 2550 if (top_reg_after_save == L1) { 2551 ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save); 2552 } 2553 2554 if (ptr_reg_after_save == L2) { 2555 ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save); 2556 } 2557 2558 Label(retry_get_lock); 2559 Label(not_same); 2560 Label(dont_yield); 2561 2562 assert(lock_addr, "lock_address should be non null for v8"); 2563 set((intptr_t)lock_addr, lock_ptr_reg); 2564 // Initialize yield counter 2565 mov(G0,yield_reg); 2566 mov(G0, yieldall_reg); 2567 set(StubRoutines::Sparc::locked, lock_reg); 2568 2569 bind(retry_get_lock); 2570 cmp(yield_reg, V8AtomicOperationUnderLockSpinCount); 2571 br(Assembler::less, false, Assembler::pt, dont_yield); 2572 delayed()->nop(); 2573 2574 if(use_call_vm) { 2575 Untested("Need to verify global reg consistancy"); 2576 call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg); 2577 } else { 2578 // Save the regs and make space for a C call 2579 save(SP, -96, SP); 2580 save_all_globals_into_locals(); 2581 call(CAST_FROM_FN_PTR(address,os::yield_all)); 2582 delayed()->mov(yieldall_reg, O0); 2583 restore_globals_from_locals(); 2584 restore(); 2585 } 2586 2587 // reset the counter 2588 mov(G0,yield_reg); 2589 add(yieldall_reg, 1, yieldall_reg); 2590 2591 bind(dont_yield); 2592 // try to get lock 2593 swap(lock_ptr_reg, 0, lock_reg); 2594 2595 // did we get the lock? 2596 cmp(lock_reg, StubRoutines::Sparc::unlocked); 2597 br(Assembler::notEqual, true, Assembler::pn, retry_get_lock); 2598 delayed()->add(yield_reg,1,yield_reg); 2599 2600 // yes, got lock. do we have the same top? 2601 ld(top_ptr_reg_after_save, 0, value_reg); 2602 cmp(value_reg, top_reg_after_save); 2603 br(Assembler::notEqual, false, Assembler::pn, not_same); 2604 delayed()->nop(); 2605 2606 // yes, same top. 2607 st(ptr_reg_after_save, top_ptr_reg_after_save, 0); 2608 membar(Assembler::StoreStore); 2609 2610 bind(not_same); 2611 mov(value_reg, ptr_reg_after_save); 2612 st(lock_reg, lock_ptr_reg, 0); // unlock 2613 2614 restore(); 2615 } 2616} 2617 2618void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg, 2619 Label& done, Label* slow_case, 2620 BiasedLockingCounters* counters) { 2621 assert(UseBiasedLocking, "why call this otherwise?"); 2622 2623 if (PrintBiasedLockingStatistics) { 2624 assert_different_registers(obj_reg, mark_reg, temp_reg, O7); 2625 if (counters == NULL) 2626 counters = BiasedLocking::counters(); 2627 } 2628 2629 Label cas_label; 2630 2631 // Biased locking 2632 // See whether the lock is currently biased toward our thread and 2633 // whether the epoch is still valid 2634 // Note that the runtime guarantees sufficient alignment of JavaThread 2635 // pointers to allow age to be placed into low bits 2636 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 2637 and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); 2638 cmp(temp_reg, markOopDesc::biased_lock_pattern); 2639 brx(Assembler::notEqual, false, Assembler::pn, cas_label); 2640 delayed()->nop(); 2641 2642 load_klass(obj_reg, temp_reg); 2643 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); 2644 or3(G2_thread, temp_reg, temp_reg); 2645 xor3(mark_reg, temp_reg, temp_reg); 2646 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg); 2647 if (counters != NULL) { 2648 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg); 2649 // Reload mark_reg as we may need it later 2650 ld_ptr(Address(obj_reg, 0, oopDesc::mark_offset_in_bytes()), mark_reg); 2651 } 2652 brx(Assembler::equal, true, Assembler::pt, done); 2653 delayed()->nop(); 2654 2655 Label try_revoke_bias; 2656 Label try_rebias; 2657 Address mark_addr = Address(obj_reg, 0, oopDesc::mark_offset_in_bytes()); 2658 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); 2659 2660 // At this point we know that the header has the bias pattern and 2661 // that we are not the bias owner in the current epoch. We need to 2662 // figure out more details about the state of the header in order to 2663 // know what operations can be legally performed on the object's 2664 // header. 2665 2666 // If the low three bits in the xor result aren't clear, that means 2667 // the prototype header is no longer biased and we have to revoke 2668 // the bias on this object. 2669 btst(markOopDesc::biased_lock_mask_in_place, temp_reg); 2670 brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias); 2671 2672 // Biasing is still enabled for this data type. See whether the 2673 // epoch of the current bias is still valid, meaning that the epoch 2674 // bits of the mark word are equal to the epoch bits of the 2675 // prototype header. (Note that the prototype header's epoch bits 2676 // only change at a safepoint.) If not, attempt to rebias the object 2677 // toward the current thread. Note that we must be absolutely sure 2678 // that the current epoch is invalid in order to do this because 2679 // otherwise the manipulations it performs on the mark word are 2680 // illegal. 2681 delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg); 2682 brx(Assembler::notZero, false, Assembler::pn, try_rebias); 2683 2684 // The epoch of the current bias is still valid but we know nothing 2685 // about the owner; it might be set or it might be clear. Try to 2686 // acquire the bias of the object using an atomic operation. If this 2687 // fails we will go in to the runtime to revoke the object's bias. 2688 // Note that we first construct the presumed unbiased header so we 2689 // don't accidentally blow away another thread's valid bias. 2690 delayed()->and3(mark_reg, 2691 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place, 2692 mark_reg); 2693 or3(G2_thread, mark_reg, temp_reg); 2694 casx_under_lock(mark_addr.base(), mark_reg, temp_reg, 2695 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); 2696 // If the biasing toward our thread failed, this means that 2697 // another thread succeeded in biasing it toward itself and we 2698 // need to revoke that bias. The revocation will occur in the 2699 // interpreter runtime in the slow case. 2700 cmp(mark_reg, temp_reg); 2701 if (counters != NULL) { 2702 cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg); 2703 } 2704 if (slow_case != NULL) { 2705 brx(Assembler::notEqual, true, Assembler::pn, *slow_case); 2706 delayed()->nop(); 2707 } 2708 br(Assembler::always, false, Assembler::pt, done); 2709 delayed()->nop(); 2710 2711 bind(try_rebias); 2712 // At this point we know the epoch has expired, meaning that the 2713 // current "bias owner", if any, is actually invalid. Under these 2714 // circumstances _only_, we are allowed to use the current header's 2715 // value as the comparison value when doing the cas to acquire the 2716 // bias in the current epoch. In other words, we allow transfer of 2717 // the bias from one thread to another directly in this situation. 2718 // 2719 // FIXME: due to a lack of registers we currently blow away the age 2720 // bits in this situation. Should attempt to preserve them. 2721 load_klass(obj_reg, temp_reg); 2722 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); 2723 or3(G2_thread, temp_reg, temp_reg); 2724 casx_under_lock(mark_addr.base(), mark_reg, temp_reg, 2725 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); 2726 // If the biasing toward our thread failed, this means that 2727 // another thread succeeded in biasing it toward itself and we 2728 // need to revoke that bias. The revocation will occur in the 2729 // interpreter runtime in the slow case. 2730 cmp(mark_reg, temp_reg); 2731 if (counters != NULL) { 2732 cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg); 2733 } 2734 if (slow_case != NULL) { 2735 brx(Assembler::notEqual, true, Assembler::pn, *slow_case); 2736 delayed()->nop(); 2737 } 2738 br(Assembler::always, false, Assembler::pt, done); 2739 delayed()->nop(); 2740 2741 bind(try_revoke_bias); 2742 // The prototype mark in the klass doesn't have the bias bit set any 2743 // more, indicating that objects of this data type are not supposed 2744 // to be biased any more. We are going to try to reset the mark of 2745 // this object to the prototype value and fall through to the 2746 // CAS-based locking scheme. Note that if our CAS fails, it means 2747 // that another thread raced us for the privilege of revoking the 2748 // bias of this particular object, so it's okay to continue in the 2749 // normal locking code. 2750 // 2751 // FIXME: due to a lack of registers we currently blow away the age 2752 // bits in this situation. Should attempt to preserve them. 2753 load_klass(obj_reg, temp_reg); 2754 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); 2755 casx_under_lock(mark_addr.base(), mark_reg, temp_reg, 2756 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); 2757 // Fall through to the normal CAS-based lock, because no matter what 2758 // the result of the above CAS, some thread must have succeeded in 2759 // removing the bias bit from the object's header. 2760 if (counters != NULL) { 2761 cmp(mark_reg, temp_reg); 2762 cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg); 2763 } 2764 2765 bind(cas_label); 2766} 2767 2768void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done, 2769 bool allow_delay_slot_filling) { 2770 // Check for biased locking unlock case, which is a no-op 2771 // Note: we do not have to check the thread ID for two reasons. 2772 // First, the interpreter checks for IllegalMonitorStateException at 2773 // a higher level. Second, if the bias was revoked while we held the 2774 // lock, the object could not be rebiased toward another thread, so 2775 // the bias bit would be clear. 2776 ld_ptr(mark_addr, temp_reg); 2777 and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); 2778 cmp(temp_reg, markOopDesc::biased_lock_pattern); 2779 brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done); 2780 delayed(); 2781 if (!allow_delay_slot_filling) { 2782 nop(); 2783 } 2784} 2785 2786 2787// CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by 2788// Solaris/SPARC's "as". Another apt name would be cas_ptr() 2789 2790void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) { 2791 casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()) ; 2792} 2793 2794 2795 2796// compiler_lock_object() and compiler_unlock_object() are direct transliterations 2797// of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments. 2798// The code could be tightened up considerably. 2799// 2800// box->dhw disposition - post-conditions at DONE_LABEL. 2801// - Successful inflated lock: box->dhw != 0. 2802// Any non-zero value suffices. 2803// Consider G2_thread, rsp, boxReg, or unused_mark() 2804// - Successful Stack-lock: box->dhw == mark. 2805// box->dhw must contain the displaced mark word value 2806// - Failure -- icc.ZFlag == 0 and box->dhw is undefined. 2807// The slow-path fast_enter() and slow_enter() operators 2808// are responsible for setting box->dhw = NonZero (typically ::unused_mark). 2809// - Biased: box->dhw is undefined 2810// 2811// SPARC refworkload performance - specifically jetstream and scimark - are 2812// extremely sensitive to the size of the code emitted by compiler_lock_object 2813// and compiler_unlock_object. Critically, the key factor is code size, not path 2814// length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the 2815// effect). 2816 2817 2818void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark, Register Rbox, Register Rscratch, 2819 BiasedLockingCounters* counters) { 2820 Address mark_addr(Roop, 0, oopDesc::mark_offset_in_bytes()); 2821 2822 verify_oop(Roop); 2823 Label done ; 2824 2825 if (counters != NULL) { 2826 inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch); 2827 } 2828 2829 if (EmitSync & 1) { 2830 mov (3, Rscratch) ; 2831 st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2832 cmp (SP, G0) ; 2833 return ; 2834 } 2835 2836 if (EmitSync & 2) { 2837 2838 // Fetch object's markword 2839 ld_ptr(mark_addr, Rmark); 2840 2841 if (UseBiasedLocking) { 2842 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); 2843 } 2844 2845 // Save Rbox in Rscratch to be used for the cas operation 2846 mov(Rbox, Rscratch); 2847 2848 // set Rmark to markOop | markOopDesc::unlocked_value 2849 or3(Rmark, markOopDesc::unlocked_value, Rmark); 2850 2851 // Initialize the box. (Must happen before we update the object mark!) 2852 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2853 2854 // compare object markOop with Rmark and if equal exchange Rscratch with object markOop 2855 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); 2856 casx_under_lock(mark_addr.base(), Rmark, Rscratch, 2857 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); 2858 2859 // if compare/exchange succeeded we found an unlocked object and we now have locked it 2860 // hence we are done 2861 cmp(Rmark, Rscratch); 2862#ifdef _LP64 2863 sub(Rscratch, STACK_BIAS, Rscratch); 2864#endif 2865 brx(Assembler::equal, false, Assembler::pt, done); 2866 delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot 2867 2868 // we did not find an unlocked object so see if this is a recursive case 2869 // sub(Rscratch, SP, Rscratch); 2870 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); 2871 andcc(Rscratch, 0xfffff003, Rscratch); 2872 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2873 bind (done) ; 2874 return ; 2875 } 2876 2877 Label Egress ; 2878 2879 if (EmitSync & 256) { 2880 Label IsInflated ; 2881 2882 ld_ptr (mark_addr, Rmark); // fetch obj->mark 2883 // Triage: biased, stack-locked, neutral, inflated 2884 if (UseBiasedLocking) { 2885 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); 2886 // Invariant: if control reaches this point in the emitted stream 2887 // then Rmark has not been modified. 2888 } 2889 2890 // Store mark into displaced mark field in the on-stack basic-lock "box" 2891 // Critically, this must happen before the CAS 2892 // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty. 2893 st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2894 andcc (Rmark, 2, G0) ; 2895 brx (Assembler::notZero, false, Assembler::pn, IsInflated) ; 2896 delayed() -> 2897 2898 // Try stack-lock acquisition. 2899 // Beware: the 1st instruction is in a delay slot 2900 mov (Rbox, Rscratch); 2901 or3 (Rmark, markOopDesc::unlocked_value, Rmark); 2902 assert (mark_addr.disp() == 0, "cas must take a zero displacement"); 2903 casn (mark_addr.base(), Rmark, Rscratch) ; 2904 cmp (Rmark, Rscratch); 2905 brx (Assembler::equal, false, Assembler::pt, done); 2906 delayed()->sub(Rscratch, SP, Rscratch); 2907 2908 // Stack-lock attempt failed - check for recursive stack-lock. 2909 // See the comments below about how we might remove this case. 2910#ifdef _LP64 2911 sub (Rscratch, STACK_BIAS, Rscratch); 2912#endif 2913 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); 2914 andcc (Rscratch, 0xfffff003, Rscratch); 2915 br (Assembler::always, false, Assembler::pt, done) ; 2916 delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2917 2918 bind (IsInflated) ; 2919 if (EmitSync & 64) { 2920 // If m->owner != null goto IsLocked 2921 // Pessimistic form: Test-and-CAS vs CAS 2922 // The optimistic form avoids RTS->RTO cache line upgrades. 2923 ld_ptr (Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2), Rscratch) ; 2924 andcc (Rscratch, Rscratch, G0) ; 2925 brx (Assembler::notZero, false, Assembler::pn, done) ; 2926 delayed()->nop() ; 2927 // m->owner == null : it's unlocked. 2928 } 2929 2930 // Try to CAS m->owner from null to Self 2931 // Invariant: if we acquire the lock then _recursions should be 0. 2932 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ; 2933 mov (G2_thread, Rscratch) ; 2934 casn (Rmark, G0, Rscratch) ; 2935 cmp (Rscratch, G0) ; 2936 // Intentional fall-through into done 2937 } else { 2938 // Aggressively avoid the Store-before-CAS penalty 2939 // Defer the store into box->dhw until after the CAS 2940 Label IsInflated, Recursive ; 2941 2942// Anticipate CAS -- Avoid RTS->RTO upgrade 2943// prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ; 2944 2945 ld_ptr (mark_addr, Rmark); // fetch obj->mark 2946 // Triage: biased, stack-locked, neutral, inflated 2947 2948 if (UseBiasedLocking) { 2949 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); 2950 // Invariant: if control reaches this point in the emitted stream 2951 // then Rmark has not been modified. 2952 } 2953 andcc (Rmark, 2, G0) ; 2954 brx (Assembler::notZero, false, Assembler::pn, IsInflated) ; 2955 delayed()-> // Beware - dangling delay-slot 2956 2957 // Try stack-lock acquisition. 2958 // Transiently install BUSY (0) encoding in the mark word. 2959 // if the CAS of 0 into the mark was successful then we execute: 2960 // ST box->dhw = mark -- save fetched mark in on-stack basiclock box 2961 // ST obj->mark = box -- overwrite transient 0 value 2962 // This presumes TSO, of course. 2963 2964 mov (0, Rscratch) ; 2965 or3 (Rmark, markOopDesc::unlocked_value, Rmark); 2966 assert (mark_addr.disp() == 0, "cas must take a zero displacement"); 2967 casn (mark_addr.base(), Rmark, Rscratch) ; 2968// prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ; 2969 cmp (Rscratch, Rmark) ; 2970 brx (Assembler::notZero, false, Assembler::pn, Recursive) ; 2971 delayed() -> 2972 st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2973 if (counters != NULL) { 2974 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); 2975 } 2976 br (Assembler::always, false, Assembler::pt, done); 2977 delayed() -> 2978 st_ptr (Rbox, mark_addr) ; 2979 2980 bind (Recursive) ; 2981 // Stack-lock attempt failed - check for recursive stack-lock. 2982 // Tests show that we can remove the recursive case with no impact 2983 // on refworkload 0.83. If we need to reduce the size of the code 2984 // emitted by compiler_lock_object() the recursive case is perfect 2985 // candidate. 2986 // 2987 // A more extreme idea is to always inflate on stack-lock recursion. 2988 // This lets us eliminate the recursive checks in compiler_lock_object 2989 // and compiler_unlock_object and the (box->dhw == 0) encoding. 2990 // A brief experiment - requiring changes to synchronizer.cpp, interpreter, 2991 // and showed a performance *increase*. In the same experiment I eliminated 2992 // the fast-path stack-lock code from the interpreter and always passed 2993 // control to the "slow" operators in synchronizer.cpp. 2994 2995 // RScratch contains the fetched obj->mark value from the failed CASN. 2996#ifdef _LP64 2997 sub (Rscratch, STACK_BIAS, Rscratch); 2998#endif 2999 sub(Rscratch, SP, Rscratch); 3000 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); 3001 andcc (Rscratch, 0xfffff003, Rscratch); 3002 if (counters != NULL) { 3003 // Accounting needs the Rscratch register 3004 st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 3005 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); 3006 br (Assembler::always, false, Assembler::pt, done) ; 3007 delayed()->nop() ; 3008 } else { 3009 br (Assembler::always, false, Assembler::pt, done) ; 3010 delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 3011 } 3012 3013 bind (IsInflated) ; 3014 if (EmitSync & 64) { 3015 // If m->owner != null goto IsLocked 3016 // Test-and-CAS vs CAS 3017 // Pessimistic form avoids futile (doomed) CAS attempts 3018 // The optimistic form avoids RTS->RTO cache line upgrades. 3019 ld_ptr (Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2), Rscratch) ; 3020 andcc (Rscratch, Rscratch, G0) ; 3021 brx (Assembler::notZero, false, Assembler::pn, done) ; 3022 delayed()->nop() ; 3023 // m->owner == null : it's unlocked. 3024 } 3025 3026 // Try to CAS m->owner from null to Self 3027 // Invariant: if we acquire the lock then _recursions should be 0. 3028 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ; 3029 mov (G2_thread, Rscratch) ; 3030 casn (Rmark, G0, Rscratch) ; 3031 cmp (Rscratch, G0) ; 3032 // ST box->displaced_header = NonZero. 3033 // Any non-zero value suffices: 3034 // unused_mark(), G2_thread, RBox, RScratch, rsp, etc. 3035 st_ptr (Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes()); 3036 // Intentional fall-through into done 3037 } 3038 3039 bind (done) ; 3040} 3041 3042void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark, Register Rbox, Register Rscratch) { 3043 Address mark_addr(Roop, 0, oopDesc::mark_offset_in_bytes()); 3044 3045 Label done ; 3046 3047 if (EmitSync & 4) { 3048 cmp (SP, G0) ; 3049 return ; 3050 } 3051 3052 if (EmitSync & 8) { 3053 if (UseBiasedLocking) { 3054 biased_locking_exit(mark_addr, Rscratch, done); 3055 } 3056 3057 // Test first if it is a fast recursive unlock 3058 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark); 3059 cmp(Rmark, G0); 3060 brx(Assembler::equal, false, Assembler::pt, done); 3061 delayed()->nop(); 3062 3063 // Check if it is still a light weight lock, this is is true if we see 3064 // the stack address of the basicLock in the markOop of the object 3065 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); 3066 casx_under_lock(mark_addr.base(), Rbox, Rmark, 3067 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); 3068 br (Assembler::always, false, Assembler::pt, done); 3069 delayed()->cmp(Rbox, Rmark); 3070 bind (done) ; 3071 return ; 3072 } 3073 3074 // Beware ... If the aggregate size of the code emitted by CLO and CUO is 3075 // is too large performance rolls abruptly off a cliff. 3076 // This could be related to inlining policies, code cache management, or 3077 // I$ effects. 3078 Label LStacked ; 3079 3080 if (UseBiasedLocking) { 3081 // TODO: eliminate redundant LDs of obj->mark 3082 biased_locking_exit(mark_addr, Rscratch, done); 3083 } 3084 3085 ld_ptr (Roop, oopDesc::mark_offset_in_bytes(), Rmark) ; 3086 ld_ptr (Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch); 3087 andcc (Rscratch, Rscratch, G0); 3088 brx (Assembler::zero, false, Assembler::pn, done); 3089 delayed()-> nop() ; // consider: relocate fetch of mark, above, into this DS 3090 andcc (Rmark, 2, G0) ; 3091 brx (Assembler::zero, false, Assembler::pt, LStacked) ; 3092 delayed()-> nop() ; 3093 3094 // It's inflated 3095 // Conceptually we need a #loadstore|#storestore "release" MEMBAR before 3096 // the ST of 0 into _owner which releases the lock. This prevents loads 3097 // and stores within the critical section from reordering (floating) 3098 // past the store that releases the lock. But TSO is a strong memory model 3099 // and that particular flavor of barrier is a noop, so we can safely elide it. 3100 // Note that we use 1-0 locking by default for the inflated case. We 3101 // close the resultant (and rare) race by having contented threads in 3102 // monitorenter periodically poll _owner. 3103 ld_ptr (Address(Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2), Rscratch) ; 3104 ld_ptr (Address(Rmark, 0, ObjectMonitor::recursions_offset_in_bytes()-2), Rbox) ; 3105 xor3 (Rscratch, G2_thread, Rscratch) ; 3106 orcc (Rbox, Rscratch, Rbox) ; 3107 brx (Assembler::notZero, false, Assembler::pn, done) ; 3108 delayed()-> 3109 ld_ptr (Address (Rmark, 0, ObjectMonitor::EntryList_offset_in_bytes()-2), Rscratch) ; 3110 ld_ptr (Address (Rmark, 0, ObjectMonitor::cxq_offset_in_bytes()-2), Rbox) ; 3111 orcc (Rbox, Rscratch, G0) ; 3112 if (EmitSync & 65536) { 3113 Label LSucc ; 3114 brx (Assembler::notZero, false, Assembler::pn, LSucc) ; 3115 delayed()->nop() ; 3116 br (Assembler::always, false, Assembler::pt, done) ; 3117 delayed()-> 3118 st_ptr (G0, Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3119 3120 bind (LSucc) ; 3121 st_ptr (G0, Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3122 if (os::is_MP()) { membar (StoreLoad) ; } 3123 ld_ptr (Address (Rmark, 0, ObjectMonitor::succ_offset_in_bytes()-2), Rscratch) ; 3124 andcc (Rscratch, Rscratch, G0) ; 3125 brx (Assembler::notZero, false, Assembler::pt, done) ; 3126 delayed()-> andcc (G0, G0, G0) ; 3127 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ; 3128 mov (G2_thread, Rscratch) ; 3129 casn (Rmark, G0, Rscratch) ; 3130 cmp (Rscratch, G0) ; 3131 // invert icc.zf and goto done 3132 brx (Assembler::notZero, false, Assembler::pt, done) ; 3133 delayed() -> cmp (G0, G0) ; 3134 br (Assembler::always, false, Assembler::pt, done); 3135 delayed() -> cmp (G0, 1) ; 3136 } else { 3137 brx (Assembler::notZero, false, Assembler::pn, done) ; 3138 delayed()->nop() ; 3139 br (Assembler::always, false, Assembler::pt, done) ; 3140 delayed()-> 3141 st_ptr (G0, Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3142 } 3143 3144 bind (LStacked) ; 3145 // Consider: we could replace the expensive CAS in the exit 3146 // path with a simple ST of the displaced mark value fetched from 3147 // the on-stack basiclock box. That admits a race where a thread T2 3148 // in the slow lock path -- inflating with monitor M -- could race a 3149 // thread T1 in the fast unlock path, resulting in a missed wakeup for T2. 3150 // More precisely T1 in the stack-lock unlock path could "stomp" the 3151 // inflated mark value M installed by T2, resulting in an orphan 3152 // object monitor M and T2 becoming stranded. We can remedy that situation 3153 // by having T2 periodically poll the object's mark word using timed wait 3154 // operations. If T2 discovers that a stomp has occurred it vacates 3155 // the monitor M and wakes any other threads stranded on the now-orphan M. 3156 // In addition the monitor scavenger, which performs deflation, 3157 // would also need to check for orpan monitors and stranded threads. 3158 // 3159 // Finally, inflation is also used when T2 needs to assign a hashCode 3160 // to O and O is stack-locked by T1. The "stomp" race could cause 3161 // an assigned hashCode value to be lost. We can avoid that condition 3162 // and provide the necessary hashCode stability invariants by ensuring 3163 // that hashCode generation is idempotent between copying GCs. 3164 // For example we could compute the hashCode of an object O as 3165 // O's heap address XOR some high quality RNG value that is refreshed 3166 // at GC-time. The monitor scavenger would install the hashCode 3167 // found in any orphan monitors. Again, the mechanism admits a 3168 // lost-update "stomp" WAW race but detects and recovers as needed. 3169 // 3170 // A prototype implementation showed excellent results, although 3171 // the scavenger and timeout code was rather involved. 3172 3173 casn (mark_addr.base(), Rbox, Rscratch) ; 3174 cmp (Rbox, Rscratch); 3175 // Intentional fall through into done ... 3176 3177 bind (done) ; 3178} 3179 3180 3181 3182void MacroAssembler::print_CPU_state() { 3183 // %%%%% need to implement this 3184} 3185 3186void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 3187 // %%%%% need to implement this 3188} 3189 3190void MacroAssembler::push_IU_state() { 3191 // %%%%% need to implement this 3192} 3193 3194 3195void MacroAssembler::pop_IU_state() { 3196 // %%%%% need to implement this 3197} 3198 3199 3200void MacroAssembler::push_FPU_state() { 3201 // %%%%% need to implement this 3202} 3203 3204 3205void MacroAssembler::pop_FPU_state() { 3206 // %%%%% need to implement this 3207} 3208 3209 3210void MacroAssembler::push_CPU_state() { 3211 // %%%%% need to implement this 3212} 3213 3214 3215void MacroAssembler::pop_CPU_state() { 3216 // %%%%% need to implement this 3217} 3218 3219 3220 3221void MacroAssembler::verify_tlab() { 3222#ifdef ASSERT 3223 if (UseTLAB && VerifyOops) { 3224 Label next, next2, ok; 3225 Register t1 = L0; 3226 Register t2 = L1; 3227 Register t3 = L2; 3228 3229 save_frame(0); 3230 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); 3231 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2); 3232 or3(t1, t2, t3); 3233 cmp(t1, t2); 3234 br(Assembler::greaterEqual, false, Assembler::pn, next); 3235 delayed()->nop(); 3236 stop("assert(top >= start)"); 3237 should_not_reach_here(); 3238 3239 bind(next); 3240 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); 3241 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2); 3242 or3(t3, t2, t3); 3243 cmp(t1, t2); 3244 br(Assembler::lessEqual, false, Assembler::pn, next2); 3245 delayed()->nop(); 3246 stop("assert(top <= end)"); 3247 should_not_reach_here(); 3248 3249 bind(next2); 3250 and3(t3, MinObjAlignmentInBytesMask, t3); 3251 cmp(t3, 0); 3252 br(Assembler::lessEqual, false, Assembler::pn, ok); 3253 delayed()->nop(); 3254 stop("assert(aligned)"); 3255 should_not_reach_here(); 3256 3257 bind(ok); 3258 restore(); 3259 } 3260#endif 3261} 3262 3263 3264void MacroAssembler::eden_allocate( 3265 Register obj, // result: pointer to object after successful allocation 3266 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 3267 int con_size_in_bytes, // object size in bytes if known at compile time 3268 Register t1, // temp register 3269 Register t2, // temp register 3270 Label& slow_case // continuation point if fast allocation fails 3271){ 3272 // make sure arguments make sense 3273 assert_different_registers(obj, var_size_in_bytes, t1, t2); 3274 assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size"); 3275 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); 3276 3277 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { 3278 // No allocation in the shared eden. 3279 br(Assembler::always, false, Assembler::pt, slow_case); 3280 delayed()->nop(); 3281 } else { 3282 // get eden boundaries 3283 // note: we need both top & top_addr! 3284 const Register top_addr = t1; 3285 const Register end = t2; 3286 3287 CollectedHeap* ch = Universe::heap(); 3288 set((intx)ch->top_addr(), top_addr); 3289 intx delta = (intx)ch->end_addr() - (intx)ch->top_addr(); 3290 ld_ptr(top_addr, delta, end); 3291 ld_ptr(top_addr, 0, obj); 3292 3293 // try to allocate 3294 Label retry; 3295 bind(retry); 3296#ifdef ASSERT 3297 // make sure eden top is properly aligned 3298 { 3299 Label L; 3300 btst(MinObjAlignmentInBytesMask, obj); 3301 br(Assembler::zero, false, Assembler::pt, L); 3302 delayed()->nop(); 3303 stop("eden top is not properly aligned"); 3304 bind(L); 3305 } 3306#endif // ASSERT 3307 const Register free = end; 3308 sub(end, obj, free); // compute amount of free space 3309 if (var_size_in_bytes->is_valid()) { 3310 // size is unknown at compile time 3311 cmp(free, var_size_in_bytes); 3312 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case 3313 delayed()->add(obj, var_size_in_bytes, end); 3314 } else { 3315 // size is known at compile time 3316 cmp(free, con_size_in_bytes); 3317 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case 3318 delayed()->add(obj, con_size_in_bytes, end); 3319 } 3320 // Compare obj with the value at top_addr; if still equal, swap the value of 3321 // end with the value at top_addr. If not equal, read the value at top_addr 3322 // into end. 3323 casx_under_lock(top_addr, obj, end, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); 3324 // if someone beat us on the allocation, try again, otherwise continue 3325 cmp(obj, end); 3326 brx(Assembler::notEqual, false, Assembler::pn, retry); 3327 delayed()->mov(end, obj); // nop if successfull since obj == end 3328 3329#ifdef ASSERT 3330 // make sure eden top is properly aligned 3331 { 3332 Label L; 3333 const Register top_addr = t1; 3334 3335 set((intx)ch->top_addr(), top_addr); 3336 ld_ptr(top_addr, 0, top_addr); 3337 btst(MinObjAlignmentInBytesMask, top_addr); 3338 br(Assembler::zero, false, Assembler::pt, L); 3339 delayed()->nop(); 3340 stop("eden top is not properly aligned"); 3341 bind(L); 3342 } 3343#endif // ASSERT 3344 } 3345} 3346 3347 3348void MacroAssembler::tlab_allocate( 3349 Register obj, // result: pointer to object after successful allocation 3350 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 3351 int con_size_in_bytes, // object size in bytes if known at compile time 3352 Register t1, // temp register 3353 Label& slow_case // continuation point if fast allocation fails 3354){ 3355 // make sure arguments make sense 3356 assert_different_registers(obj, var_size_in_bytes, t1); 3357 assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size"); 3358 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); 3359 3360 const Register free = t1; 3361 3362 verify_tlab(); 3363 3364 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj); 3365 3366 // calculate amount of free space 3367 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free); 3368 sub(free, obj, free); 3369 3370 Label done; 3371 if (var_size_in_bytes == noreg) { 3372 cmp(free, con_size_in_bytes); 3373 } else { 3374 cmp(free, var_size_in_bytes); 3375 } 3376 br(Assembler::less, false, Assembler::pn, slow_case); 3377 // calculate the new top pointer 3378 if (var_size_in_bytes == noreg) { 3379 delayed()->add(obj, con_size_in_bytes, free); 3380 } else { 3381 delayed()->add(obj, var_size_in_bytes, free); 3382 } 3383 3384 bind(done); 3385 3386#ifdef ASSERT 3387 // make sure new free pointer is properly aligned 3388 { 3389 Label L; 3390 btst(MinObjAlignmentInBytesMask, free); 3391 br(Assembler::zero, false, Assembler::pt, L); 3392 delayed()->nop(); 3393 stop("updated TLAB free is not properly aligned"); 3394 bind(L); 3395 } 3396#endif // ASSERT 3397 3398 // update the tlab top pointer 3399 st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset())); 3400 verify_tlab(); 3401} 3402 3403 3404void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) { 3405 Register top = O0; 3406 Register t1 = G1; 3407 Register t2 = G3; 3408 Register t3 = O1; 3409 assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */); 3410 Label do_refill, discard_tlab; 3411 3412 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { 3413 // No allocation in the shared eden. 3414 br(Assembler::always, false, Assembler::pt, slow_case); 3415 delayed()->nop(); 3416 } 3417 3418 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top); 3419 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1); 3420 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2); 3421 3422 // calculate amount of free space 3423 sub(t1, top, t1); 3424 srl_ptr(t1, LogHeapWordSize, t1); 3425 3426 // Retain tlab and allocate object in shared space if 3427 // the amount free in the tlab is too large to discard. 3428 cmp(t1, t2); 3429 brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab); 3430 3431 // increment waste limit to prevent getting stuck on this slow path 3432 delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2); 3433 st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())); 3434 if (TLABStats) { 3435 // increment number of slow_allocations 3436 ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2); 3437 add(t2, 1, t2); 3438 stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset())); 3439 } 3440 br(Assembler::always, false, Assembler::pt, try_eden); 3441 delayed()->nop(); 3442 3443 bind(discard_tlab); 3444 if (TLABStats) { 3445 // increment number of refills 3446 ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2); 3447 add(t2, 1, t2); 3448 stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset())); 3449 // accumulate wastage 3450 ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2); 3451 add(t2, t1, t2); 3452 stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())); 3453 } 3454 3455 // if tlab is currently allocated (top or end != null) then 3456 // fill [top, end + alignment_reserve) with array object 3457 br_null(top, false, Assembler::pn, do_refill); 3458 delayed()->nop(); 3459 3460 set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2); 3461 st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word 3462 // set klass to intArrayKlass 3463 sub(t1, typeArrayOopDesc::header_size(T_INT), t1); 3464 add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1); 3465 sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1); 3466 st(t1, top, arrayOopDesc::length_offset_in_bytes()); 3467 set((intptr_t)Universe::intArrayKlassObj_addr(), t2); 3468 ld_ptr(t2, 0, t2); 3469 // store klass last. concurrent gcs assumes klass length is valid if 3470 // klass field is not null. 3471 store_klass(t2, top); 3472 verify_oop(top); 3473 3474 // refill the tlab with an eden allocation 3475 bind(do_refill); 3476 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1); 3477 sll_ptr(t1, LogHeapWordSize, t1); 3478 // add object_size ?? 3479 eden_allocate(top, t1, 0, t2, t3, slow_case); 3480 3481 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset())); 3482 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset())); 3483#ifdef ASSERT 3484 // check that tlab_size (t1) is still valid 3485 { 3486 Label ok; 3487 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2); 3488 sll_ptr(t2, LogHeapWordSize, t2); 3489 cmp(t1, t2); 3490 br(Assembler::equal, false, Assembler::pt, ok); 3491 delayed()->nop(); 3492 stop("assert(t1 == tlab_size)"); 3493 should_not_reach_here(); 3494 3495 bind(ok); 3496 } 3497#endif // ASSERT 3498 add(top, t1, top); // t1 is tlab_size 3499 sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top); 3500 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset())); 3501 verify_tlab(); 3502 br(Assembler::always, false, Assembler::pt, retry); 3503 delayed()->nop(); 3504} 3505 3506Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 3507 switch (cond) { 3508 // Note some conditions are synonyms for others 3509 case Assembler::never: return Assembler::always; 3510 case Assembler::zero: return Assembler::notZero; 3511 case Assembler::lessEqual: return Assembler::greater; 3512 case Assembler::less: return Assembler::greaterEqual; 3513 case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned; 3514 case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned; 3515 case Assembler::negative: return Assembler::positive; 3516 case Assembler::overflowSet: return Assembler::overflowClear; 3517 case Assembler::always: return Assembler::never; 3518 case Assembler::notZero: return Assembler::zero; 3519 case Assembler::greater: return Assembler::lessEqual; 3520 case Assembler::greaterEqual: return Assembler::less; 3521 case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned; 3522 case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned; 3523 case Assembler::positive: return Assembler::negative; 3524 case Assembler::overflowClear: return Assembler::overflowSet; 3525 } 3526 3527 ShouldNotReachHere(); return Assembler::overflowClear; 3528} 3529 3530void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr, 3531 Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) { 3532 Condition negated_cond = negate_condition(cond); 3533 Label L; 3534 brx(negated_cond, false, Assembler::pt, L); 3535 delayed()->nop(); 3536 inc_counter(counter_ptr, Rtmp1, Rtmp2); 3537 bind(L); 3538} 3539 3540void MacroAssembler::inc_counter(address counter_ptr, Register Rtmp1, Register Rtmp2) { 3541 Address counter_addr(Rtmp1, counter_ptr); 3542 load_contents(counter_addr, Rtmp2); 3543 inc(Rtmp2); 3544 store_contents(Rtmp2, counter_addr); 3545} 3546 3547SkipIfEqual::SkipIfEqual( 3548 MacroAssembler* masm, Register temp, const bool* flag_addr, 3549 Assembler::Condition condition) { 3550 _masm = masm; 3551 Address flag(temp, (address)flag_addr, relocInfo::none); 3552 _masm->sethi(flag); 3553 _masm->ldub(flag, temp); 3554 _masm->tst(temp); 3555 _masm->br(condition, false, Assembler::pt, _label); 3556 _masm->delayed()->nop(); 3557} 3558 3559SkipIfEqual::~SkipIfEqual() { 3560 _masm->bind(_label); 3561} 3562 3563 3564// Writes to stack successive pages until offset reached to check for 3565// stack overflow + shadow pages. This clobbers tsp and scratch. 3566void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp, 3567 Register Rscratch) { 3568 // Use stack pointer in temp stack pointer 3569 mov(SP, Rtsp); 3570 3571 // Bang stack for total size given plus stack shadow page size. 3572 // Bang one page at a time because a large size can overflow yellow and 3573 // red zones (the bang will fail but stack overflow handling can't tell that 3574 // it was a stack overflow bang vs a regular segv). 3575 int offset = os::vm_page_size(); 3576 Register Roffset = Rscratch; 3577 3578 Label loop; 3579 bind(loop); 3580 set((-offset)+STACK_BIAS, Rscratch); 3581 st(G0, Rtsp, Rscratch); 3582 set(offset, Roffset); 3583 sub(Rsize, Roffset, Rsize); 3584 cmp(Rsize, G0); 3585 br(Assembler::greater, false, Assembler::pn, loop); 3586 delayed()->sub(Rtsp, Roffset, Rtsp); 3587 3588 // Bang down shadow pages too. 3589 // The -1 because we already subtracted 1 page. 3590 for (int i = 0; i< StackShadowPages-1; i++) { 3591 set((-i*offset)+STACK_BIAS, Rscratch); 3592 st(G0, Rtsp, Rscratch); 3593 } 3594} 3595 3596/////////////////////////////////////////////////////////////////////////////////// 3597#ifndef SERIALGC 3598 3599static uint num_stores = 0; 3600static uint num_null_pre_stores = 0; 3601 3602static void count_null_pre_vals(void* pre_val) { 3603 num_stores++; 3604 if (pre_val == NULL) num_null_pre_stores++; 3605 if ((num_stores % 1000000) == 0) { 3606 tty->print_cr(UINT32_FORMAT " stores, " UINT32_FORMAT " (%5.2f%%) with null pre-vals.", 3607 num_stores, num_null_pre_stores, 3608 100.0*(float)num_null_pre_stores/(float)num_stores); 3609 } 3610} 3611 3612static address satb_log_enqueue_with_frame = 0; 3613static u_char* satb_log_enqueue_with_frame_end = 0; 3614 3615static address satb_log_enqueue_frameless = 0; 3616static u_char* satb_log_enqueue_frameless_end = 0; 3617 3618static int EnqueueCodeSize = 128 DEBUG_ONLY( + 256); // Instructions? 3619 3620// The calls to this don't work. We'd need to do a fair amount of work to 3621// make it work. 3622static void check_index(int ind) { 3623 assert(0 <= ind && ind <= 64*K && ((ind % oopSize) == 0), 3624 "Invariants.") 3625} 3626 3627static void generate_satb_log_enqueue(bool with_frame) { 3628 BufferBlob* bb = BufferBlob::create("enqueue_with_frame", EnqueueCodeSize); 3629 CodeBuffer buf(bb->instructions_begin(), bb->instructions_size()); 3630 MacroAssembler masm(&buf); 3631 address start = masm.pc(); 3632 Register pre_val; 3633 3634 Label refill, restart; 3635 if (with_frame) { 3636 masm.save_frame(0); 3637 pre_val = I0; // Was O0 before the save. 3638 } else { 3639 pre_val = O0; 3640 } 3641 int satb_q_index_byte_offset = 3642 in_bytes(JavaThread::satb_mark_queue_offset() + 3643 PtrQueue::byte_offset_of_index()); 3644 int satb_q_buf_byte_offset = 3645 in_bytes(JavaThread::satb_mark_queue_offset() + 3646 PtrQueue::byte_offset_of_buf()); 3647 assert(in_bytes(PtrQueue::byte_width_of_index()) == sizeof(intptr_t) && 3648 in_bytes(PtrQueue::byte_width_of_buf()) == sizeof(intptr_t), 3649 "check sizes in assembly below"); 3650 3651 masm.bind(restart); 3652 masm.ld_ptr(G2_thread, satb_q_index_byte_offset, L0); 3653 3654 masm.br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn, L0, refill); 3655 // If the branch is taken, no harm in executing this in the delay slot. 3656 masm.delayed()->ld_ptr(G2_thread, satb_q_buf_byte_offset, L1); 3657 masm.sub(L0, oopSize, L0); 3658 3659 masm.st_ptr(pre_val, L1, L0); // [_buf + index] := I0 3660 if (!with_frame) { 3661 // Use return-from-leaf 3662 masm.retl(); 3663 masm.delayed()->st_ptr(L0, G2_thread, satb_q_index_byte_offset); 3664 } else { 3665 // Not delayed. 3666 masm.st_ptr(L0, G2_thread, satb_q_index_byte_offset); 3667 } 3668 if (with_frame) { 3669 masm.ret(); 3670 masm.delayed()->restore(); 3671 } 3672 masm.bind(refill); 3673 3674 address handle_zero = 3675 CAST_FROM_FN_PTR(address, 3676 &SATBMarkQueueSet::handle_zero_index_for_thread); 3677 // This should be rare enough that we can afford to save all the 3678 // scratch registers that the calling context might be using. 3679 masm.mov(G1_scratch, L0); 3680 masm.mov(G3_scratch, L1); 3681 masm.mov(G4, L2); 3682 // We need the value of O0 above (for the write into the buffer), so we 3683 // save and restore it. 3684 masm.mov(O0, L3); 3685 // Since the call will overwrite O7, we save and restore that, as well. 3686 masm.mov(O7, L4); 3687 masm.call_VM_leaf(L5, handle_zero, G2_thread); 3688 masm.mov(L0, G1_scratch); 3689 masm.mov(L1, G3_scratch); 3690 masm.mov(L2, G4); 3691 masm.mov(L3, O0); 3692 masm.br(Assembler::always, /*annul*/false, Assembler::pt, restart); 3693 masm.delayed()->mov(L4, O7); 3694 3695 if (with_frame) { 3696 satb_log_enqueue_with_frame = start; 3697 satb_log_enqueue_with_frame_end = masm.pc(); 3698 } else { 3699 satb_log_enqueue_frameless = start; 3700 satb_log_enqueue_frameless_end = masm.pc(); 3701 } 3702} 3703 3704static inline void generate_satb_log_enqueue_if_necessary(bool with_frame) { 3705 if (with_frame) { 3706 if (satb_log_enqueue_with_frame == 0) { 3707 generate_satb_log_enqueue(with_frame); 3708 assert(satb_log_enqueue_with_frame != 0, "postcondition."); 3709 if (G1SATBPrintStubs) { 3710 tty->print_cr("Generated with-frame satb enqueue:"); 3711 Disassembler::decode((u_char*)satb_log_enqueue_with_frame, 3712 satb_log_enqueue_with_frame_end, 3713 tty); 3714 } 3715 } 3716 } else { 3717 if (satb_log_enqueue_frameless == 0) { 3718 generate_satb_log_enqueue(with_frame); 3719 assert(satb_log_enqueue_frameless != 0, "postcondition."); 3720 if (G1SATBPrintStubs) { 3721 tty->print_cr("Generated frameless satb enqueue:"); 3722 Disassembler::decode((u_char*)satb_log_enqueue_frameless, 3723 satb_log_enqueue_frameless_end, 3724 tty); 3725 } 3726 } 3727 } 3728} 3729 3730void MacroAssembler::g1_write_barrier_pre(Register obj, Register index, int offset, Register tmp, bool preserve_o_regs) { 3731 assert(offset == 0 || index == noreg, "choose one"); 3732 3733 if (G1DisablePreBarrier) return; 3734 // satb_log_barrier(tmp, obj, offset, preserve_o_regs); 3735 Label filtered; 3736 // satb_log_barrier_work0(tmp, filtered); 3737 if (in_bytes(PtrQueue::byte_width_of_active()) == 4) { 3738 ld(G2, 3739 in_bytes(JavaThread::satb_mark_queue_offset() + 3740 PtrQueue::byte_offset_of_active()), 3741 tmp); 3742 } else { 3743 guarantee(in_bytes(PtrQueue::byte_width_of_active()) == 1, 3744 "Assumption"); 3745 ldsb(G2, 3746 in_bytes(JavaThread::satb_mark_queue_offset() + 3747 PtrQueue::byte_offset_of_active()), 3748 tmp); 3749 } 3750 // Check on whether to annul. 3751 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered); 3752 delayed() -> nop(); 3753 3754 // satb_log_barrier_work1(tmp, offset); 3755 if (index == noreg) { 3756 if (Assembler::is_simm13(offset)) { 3757 ld_ptr(obj, offset, tmp); 3758 } else { 3759 set(offset, tmp); 3760 ld_ptr(obj, tmp, tmp); 3761 } 3762 } else { 3763 ld_ptr(obj, index, tmp); 3764 } 3765 3766 // satb_log_barrier_work2(obj, tmp, offset); 3767 3768 // satb_log_barrier_work3(tmp, filtered, preserve_o_regs); 3769 3770 const Register pre_val = tmp; 3771 3772 if (G1SATBBarrierPrintNullPreVals) { 3773 save_frame(0); 3774 mov(pre_val, O0); 3775 // Save G-regs that target may use. 3776 mov(G1, L1); 3777 mov(G2, L2); 3778 mov(G3, L3); 3779 mov(G4, L4); 3780 mov(G5, L5); 3781 call(CAST_FROM_FN_PTR(address, &count_null_pre_vals)); 3782 delayed()->nop(); 3783 // Restore G-regs that target may have used. 3784 mov(L1, G1); 3785 mov(L2, G2); 3786 mov(L3, G3); 3787 mov(L4, G4); 3788 mov(L5, G5); 3789 restore(G0, G0, G0); 3790 } 3791 3792 // Check on whether to annul. 3793 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, pre_val, filtered); 3794 delayed() -> nop(); 3795 3796 // OK, it's not filtered, so we'll need to call enqueue. In the normal 3797 // case, pre_val will be a scratch G-reg, but there's some cases in which 3798 // it's an O-reg. In the first case, do a normal call. In the latter, 3799 // do a save here and call the frameless version. 3800 3801 guarantee(pre_val->is_global() || pre_val->is_out(), 3802 "Or we need to think harder."); 3803 if (pre_val->is_global() && !preserve_o_regs) { 3804 generate_satb_log_enqueue_if_necessary(true); // with frame. 3805 call(satb_log_enqueue_with_frame); 3806 delayed()->mov(pre_val, O0); 3807 } else { 3808 generate_satb_log_enqueue_if_necessary(false); // with frameless. 3809 save_frame(0); 3810 call(satb_log_enqueue_frameless); 3811 delayed()->mov(pre_val->after_save(), O0); 3812 restore(); 3813 } 3814 3815 bind(filtered); 3816} 3817 3818static jint num_ct_writes = 0; 3819static jint num_ct_writes_filtered_in_hr = 0; 3820static jint num_ct_writes_filtered_null = 0; 3821static jint num_ct_writes_filtered_pop = 0; 3822static G1CollectedHeap* g1 = NULL; 3823 3824static Thread* count_ct_writes(void* filter_val, void* new_val) { 3825 Atomic::inc(&num_ct_writes); 3826 if (filter_val == NULL) { 3827 Atomic::inc(&num_ct_writes_filtered_in_hr); 3828 } else if (new_val == NULL) { 3829 Atomic::inc(&num_ct_writes_filtered_null); 3830 } else { 3831 if (g1 == NULL) { 3832 g1 = G1CollectedHeap::heap(); 3833 } 3834 if ((HeapWord*)new_val < g1->popular_object_boundary()) { 3835 Atomic::inc(&num_ct_writes_filtered_pop); 3836 } 3837 } 3838 if ((num_ct_writes % 1000000) == 0) { 3839 jint num_ct_writes_filtered = 3840 num_ct_writes_filtered_in_hr + 3841 num_ct_writes_filtered_null + 3842 num_ct_writes_filtered_pop; 3843 3844 tty->print_cr("%d potential CT writes: %5.2f%% filtered\n" 3845 " (%5.2f%% intra-HR, %5.2f%% null, %5.2f%% popular).", 3846 num_ct_writes, 3847 100.0*(float)num_ct_writes_filtered/(float)num_ct_writes, 3848 100.0*(float)num_ct_writes_filtered_in_hr/ 3849 (float)num_ct_writes, 3850 100.0*(float)num_ct_writes_filtered_null/ 3851 (float)num_ct_writes, 3852 100.0*(float)num_ct_writes_filtered_pop/ 3853 (float)num_ct_writes); 3854 } 3855 return Thread::current(); 3856} 3857 3858static address dirty_card_log_enqueue = 0; 3859static u_char* dirty_card_log_enqueue_end = 0; 3860 3861// This gets to assume that o0 contains the object address. 3862static void generate_dirty_card_log_enqueue(jbyte* byte_map_base) { 3863 BufferBlob* bb = BufferBlob::create("dirty_card_enqueue", EnqueueCodeSize*2); 3864 CodeBuffer buf(bb->instructions_begin(), bb->instructions_size()); 3865 MacroAssembler masm(&buf); 3866 address start = masm.pc(); 3867 3868 Label not_already_dirty, restart, refill; 3869 3870#ifdef _LP64 3871 masm.srlx(O0, CardTableModRefBS::card_shift, O0); 3872#else 3873 masm.srl(O0, CardTableModRefBS::card_shift, O0); 3874#endif 3875 Address rs(O1, (address)byte_map_base); 3876 masm.load_address(rs); // O1 := <card table base> 3877 masm.ldub(O0, O1, O2); // O2 := [O0 + O1] 3878 3879 masm.br_on_reg_cond(Assembler::rc_nz, /*annul*/false, Assembler::pt, 3880 O2, not_already_dirty); 3881 // Get O1 + O2 into a reg by itself -- useful in the take-the-branch 3882 // case, harmless if not. 3883 masm.delayed()->add(O0, O1, O3); 3884 3885 // We didn't take the branch, so we're already dirty: return. 3886 // Use return-from-leaf 3887 masm.retl(); 3888 masm.delayed()->nop(); 3889 3890 // Not dirty. 3891 masm.bind(not_already_dirty); 3892 // First, dirty it. 3893 masm.stb(G0, O3, G0); // [cardPtr] := 0 (i.e., dirty). 3894 int dirty_card_q_index_byte_offset = 3895 in_bytes(JavaThread::dirty_card_queue_offset() + 3896 PtrQueue::byte_offset_of_index()); 3897 int dirty_card_q_buf_byte_offset = 3898 in_bytes(JavaThread::dirty_card_queue_offset() + 3899 PtrQueue::byte_offset_of_buf()); 3900 masm.bind(restart); 3901 masm.ld_ptr(G2_thread, dirty_card_q_index_byte_offset, L0); 3902 3903 masm.br_on_reg_cond(Assembler::rc_z, /*annul*/false, Assembler::pn, 3904 L0, refill); 3905 // If the branch is taken, no harm in executing this in the delay slot. 3906 masm.delayed()->ld_ptr(G2_thread, dirty_card_q_buf_byte_offset, L1); 3907 masm.sub(L0, oopSize, L0); 3908 3909 masm.st_ptr(O3, L1, L0); // [_buf + index] := I0 3910 // Use return-from-leaf 3911 masm.retl(); 3912 masm.delayed()->st_ptr(L0, G2_thread, dirty_card_q_index_byte_offset); 3913 3914 masm.bind(refill); 3915 address handle_zero = 3916 CAST_FROM_FN_PTR(address, 3917 &DirtyCardQueueSet::handle_zero_index_for_thread); 3918 // This should be rare enough that we can afford to save all the 3919 // scratch registers that the calling context might be using. 3920 masm.mov(G1_scratch, L3); 3921 masm.mov(G3_scratch, L5); 3922 // We need the value of O3 above (for the write into the buffer), so we 3923 // save and restore it. 3924 masm.mov(O3, L6); 3925 // Since the call will overwrite O7, we save and restore that, as well. 3926 masm.mov(O7, L4); 3927 3928 masm.call_VM_leaf(L7_thread_cache, handle_zero, G2_thread); 3929 masm.mov(L3, G1_scratch); 3930 masm.mov(L5, G3_scratch); 3931 masm.mov(L6, O3); 3932 masm.br(Assembler::always, /*annul*/false, Assembler::pt, restart); 3933 masm.delayed()->mov(L4, O7); 3934 3935 dirty_card_log_enqueue = start; 3936 dirty_card_log_enqueue_end = masm.pc(); 3937 // XXX Should have a guarantee here about not going off the end! 3938 // Does it already do so? Do an experiment... 3939} 3940 3941static inline void 3942generate_dirty_card_log_enqueue_if_necessary(jbyte* byte_map_base) { 3943 if (dirty_card_log_enqueue == 0) { 3944 generate_dirty_card_log_enqueue(byte_map_base); 3945 assert(dirty_card_log_enqueue != 0, "postcondition."); 3946 if (G1SATBPrintStubs) { 3947 tty->print_cr("Generated dirty_card enqueue:"); 3948 Disassembler::decode((u_char*)dirty_card_log_enqueue, 3949 dirty_card_log_enqueue_end, 3950 tty); 3951 } 3952 } 3953} 3954 3955 3956void MacroAssembler::g1_write_barrier_post(Register store_addr, Register new_val, Register tmp) { 3957 3958 Label filtered; 3959 MacroAssembler* post_filter_masm = this; 3960 3961 if (new_val == G0) return; 3962 if (G1DisablePostBarrier) return; 3963 3964 G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set(); 3965 assert(bs->kind() == BarrierSet::G1SATBCT || 3966 bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier"); 3967 if (G1RSBarrierRegionFilter) { 3968 xor3(store_addr, new_val, tmp); 3969#ifdef _LP64 3970 srlx(tmp, HeapRegion::LogOfHRGrainBytes, tmp); 3971#else 3972 srl(tmp, HeapRegion::LogOfHRGrainBytes, tmp); 3973#endif 3974 if (G1PrintCTFilterStats) { 3975 guarantee(tmp->is_global(), "Or stats won't work..."); 3976 // This is a sleazy hack: I'm temporarily hijacking G2, which I 3977 // promise to restore. 3978 mov(new_val, G2); 3979 save_frame(0); 3980 mov(tmp, O0); 3981 mov(G2, O1); 3982 // Save G-regs that target may use. 3983 mov(G1, L1); 3984 mov(G2, L2); 3985 mov(G3, L3); 3986 mov(G4, L4); 3987 mov(G5, L5); 3988 call(CAST_FROM_FN_PTR(address, &count_ct_writes)); 3989 delayed()->nop(); 3990 mov(O0, G2); 3991 // Restore G-regs that target may have used. 3992 mov(L1, G1); 3993 mov(L3, G3); 3994 mov(L4, G4); 3995 mov(L5, G5); 3996 restore(G0, G0, G0); 3997 } 3998 // XXX Should I predict this taken or not? Does it mattern? 3999 br_on_reg_cond(rc_z, /*annul*/false, Assembler::pt, tmp, filtered); 4000 delayed()->nop(); 4001 } 4002 4003 // Now we decide how to generate the card table write. If we're 4004 // enqueueing, we call out to a generated function. Otherwise, we do it 4005 // inline here. 4006 4007 if (G1RSBarrierUseQueue) { 4008 // If the "store_addr" register is an "in" or "local" register, move it to 4009 // a scratch reg so we can pass it as an argument. 4010 bool use_scr = !(store_addr->is_global() || store_addr->is_out()); 4011 // Pick a scratch register different from "tmp". 4012 Register scr = (tmp == G1_scratch ? G3_scratch : G1_scratch); 4013 // Make sure we use up the delay slot! 4014 if (use_scr) { 4015 post_filter_masm->mov(store_addr, scr); 4016 } else { 4017 post_filter_masm->nop(); 4018 } 4019 generate_dirty_card_log_enqueue_if_necessary(bs->byte_map_base); 4020 save_frame(0); 4021 call(dirty_card_log_enqueue); 4022 if (use_scr) { 4023 delayed()->mov(scr, O0); 4024 } else { 4025 delayed()->mov(store_addr->after_save(), O0); 4026 } 4027 restore(); 4028 4029 } else { 4030 4031#ifdef _LP64 4032 post_filter_masm->srlx(store_addr, CardTableModRefBS::card_shift, store_addr); 4033#else 4034 post_filter_masm->srl(store_addr, CardTableModRefBS::card_shift, store_addr); 4035#endif 4036 assert( tmp != store_addr, "need separate temp reg"); 4037 Address rs(tmp, (address)bs->byte_map_base); 4038 load_address(rs); 4039 stb(G0, rs.base(), store_addr); 4040 } 4041 4042 bind(filtered); 4043 4044} 4045 4046#endif // SERIALGC 4047/////////////////////////////////////////////////////////////////////////////////// 4048 4049void MacroAssembler::card_write_barrier_post(Register store_addr, Register new_val, Register tmp) { 4050 // If we're writing constant NULL, we can skip the write barrier. 4051 if (new_val == G0) return; 4052 CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set(); 4053 assert(bs->kind() == BarrierSet::CardTableModRef || 4054 bs->kind() == BarrierSet::CardTableExtension, "wrong barrier"); 4055 card_table_write(bs->byte_map_base, tmp, store_addr); 4056} 4057 4058void MacroAssembler::load_klass(Register src_oop, Register klass) { 4059 // The number of bytes in this code is used by 4060 // MachCallDynamicJavaNode::ret_addr_offset() 4061 // if this changes, change that. 4062 if (UseCompressedOops) { 4063 lduw(src_oop, oopDesc::klass_offset_in_bytes(), klass); 4064 decode_heap_oop_not_null(klass); 4065 } else { 4066 ld_ptr(src_oop, oopDesc::klass_offset_in_bytes(), klass); 4067 } 4068} 4069 4070void MacroAssembler::store_klass(Register klass, Register dst_oop) { 4071 if (UseCompressedOops) { 4072 assert(dst_oop != klass, "not enough registers"); 4073 encode_heap_oop_not_null(klass); 4074 st(klass, dst_oop, oopDesc::klass_offset_in_bytes()); 4075 } else { 4076 st_ptr(klass, dst_oop, oopDesc::klass_offset_in_bytes()); 4077 } 4078} 4079 4080void MacroAssembler::store_klass_gap(Register s, Register d) { 4081 if (UseCompressedOops) { 4082 assert(s != d, "not enough registers"); 4083 st(s, d, oopDesc::klass_gap_offset_in_bytes()); 4084 } 4085} 4086 4087void MacroAssembler::load_heap_oop(const Address& s, Register d, int offset) { 4088 if (UseCompressedOops) { 4089 lduw(s, d, offset); 4090 decode_heap_oop(d); 4091 } else { 4092 ld_ptr(s, d, offset); 4093 } 4094} 4095 4096void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) { 4097 if (UseCompressedOops) { 4098 lduw(s1, s2, d); 4099 decode_heap_oop(d, d); 4100 } else { 4101 ld_ptr(s1, s2, d); 4102 } 4103} 4104 4105void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) { 4106 if (UseCompressedOops) { 4107 lduw(s1, simm13a, d); 4108 decode_heap_oop(d, d); 4109 } else { 4110 ld_ptr(s1, simm13a, d); 4111 } 4112} 4113 4114void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) { 4115 if (UseCompressedOops) { 4116 assert(s1 != d && s2 != d, "not enough registers"); 4117 encode_heap_oop(d); 4118 st(d, s1, s2); 4119 } else { 4120 st_ptr(d, s1, s2); 4121 } 4122} 4123 4124void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) { 4125 if (UseCompressedOops) { 4126 assert(s1 != d, "not enough registers"); 4127 encode_heap_oop(d); 4128 st(d, s1, simm13a); 4129 } else { 4130 st_ptr(d, s1, simm13a); 4131 } 4132} 4133 4134void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) { 4135 if (UseCompressedOops) { 4136 assert(a.base() != d, "not enough registers"); 4137 encode_heap_oop(d); 4138 st(d, a, offset); 4139 } else { 4140 st_ptr(d, a, offset); 4141 } 4142} 4143 4144 4145void MacroAssembler::encode_heap_oop(Register src, Register dst) { 4146 assert (UseCompressedOops, "must be compressed"); 4147 verify_oop(src); 4148 Label done; 4149 if (src == dst) { 4150 // optimize for frequent case src == dst 4151 bpr(rc_nz, true, Assembler::pt, src, done); 4152 delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken 4153 bind(done); 4154 srlx(src, LogMinObjAlignmentInBytes, dst); 4155 } else { 4156 bpr(rc_z, false, Assembler::pn, src, done); 4157 delayed() -> mov(G0, dst); 4158 // could be moved before branch, and annulate delay, 4159 // but may add some unneeded work decoding null 4160 sub(src, G6_heapbase, dst); 4161 srlx(dst, LogMinObjAlignmentInBytes, dst); 4162 bind(done); 4163 } 4164} 4165 4166 4167void MacroAssembler::encode_heap_oop_not_null(Register r) { 4168 assert (UseCompressedOops, "must be compressed"); 4169 verify_oop(r); 4170 sub(r, G6_heapbase, r); 4171 srlx(r, LogMinObjAlignmentInBytes, r); 4172} 4173 4174void MacroAssembler::encode_heap_oop_not_null(Register src, Register dst) { 4175 assert (UseCompressedOops, "must be compressed"); 4176 verify_oop(src); 4177 sub(src, G6_heapbase, dst); 4178 srlx(dst, LogMinObjAlignmentInBytes, dst); 4179} 4180 4181// Same algorithm as oops.inline.hpp decode_heap_oop. 4182void MacroAssembler::decode_heap_oop(Register src, Register dst) { 4183 assert (UseCompressedOops, "must be compressed"); 4184 Label done; 4185 sllx(src, LogMinObjAlignmentInBytes, dst); 4186 bpr(rc_nz, true, Assembler::pt, dst, done); 4187 delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken 4188 bind(done); 4189 verify_oop(dst); 4190} 4191 4192void MacroAssembler::decode_heap_oop_not_null(Register r) { 4193 // Do not add assert code to this unless you change vtableStubs_sparc.cpp 4194 // pd_code_size_limit. 4195 // Also do not verify_oop as this is called by verify_oop. 4196 assert (UseCompressedOops, "must be compressed"); 4197 sllx(r, LogMinObjAlignmentInBytes, r); 4198 add(r, G6_heapbase, r); 4199} 4200 4201void MacroAssembler::decode_heap_oop_not_null(Register src, Register dst) { 4202 // Do not add assert code to this unless you change vtableStubs_sparc.cpp 4203 // pd_code_size_limit. 4204 // Also do not verify_oop as this is called by verify_oop. 4205 assert (UseCompressedOops, "must be compressed"); 4206 sllx(src, LogMinObjAlignmentInBytes, dst); 4207 add(dst, G6_heapbase, dst); 4208} 4209 4210void MacroAssembler::reinit_heapbase() { 4211 if (UseCompressedOops) { 4212 // call indirectly to solve generation ordering problem 4213 Address base(G6_heapbase, (address)Universe::heap_base_addr()); 4214 load_ptr_contents(base, G6_heapbase); 4215 } 4216} 4217