assembler_sparc.cpp revision 113:ba764ed4b6f2
1/* 2 * Copyright 1997-2007 Sun Microsystems, Inc. All Rights Reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 * CA 95054 USA or visit www.sun.com if you need additional information or 21 * have any questions. 22 * 23 */ 24 25#include "incls/_precompiled.incl" 26#include "incls/_assembler_sparc.cpp.incl" 27 28// Implementation of Address 29 30Address::Address( addr_type t, int which ) { 31 switch (t) { 32 case extra_in_argument: 33 case extra_out_argument: 34 _base = t == extra_in_argument ? FP : SP; 35 _hi = 0; 36// Warning: In LP64 mode, _disp will occupy more than 10 bits. 37// This is inconsistent with the other constructors but op 38// codes such as ld or ldx, only access disp() to get their 39// simm13 argument. 40 _disp = ((which - Argument::n_register_parameters + frame::memory_parameter_word_sp_offset) * BytesPerWord) + STACK_BIAS; 41 break; 42 default: 43 ShouldNotReachHere(); 44 break; 45 } 46} 47 48static const char* argumentNames[][2] = { 49 {"A0","P0"}, {"A1","P1"}, {"A2","P2"}, {"A3","P3"}, {"A4","P4"}, 50 {"A5","P5"}, {"A6","P6"}, {"A7","P7"}, {"A8","P8"}, {"A9","P9"}, 51 {"A(n>9)","P(n>9)"} 52}; 53 54const char* Argument::name() const { 55 int nofArgs = sizeof argumentNames / sizeof argumentNames[0]; 56 int num = number(); 57 if (num >= nofArgs) num = nofArgs - 1; 58 return argumentNames[num][is_in() ? 1 : 0]; 59} 60 61void Assembler::print_instruction(int inst) { 62 const char* s; 63 switch (inv_op(inst)) { 64 default: s = "????"; break; 65 case call_op: s = "call"; break; 66 case branch_op: 67 switch (inv_op2(inst)) { 68 case bpr_op2: s = "bpr"; break; 69 case fb_op2: s = "fb"; break; 70 case fbp_op2: s = "fbp"; break; 71 case br_op2: s = "br"; break; 72 case bp_op2: s = "bp"; break; 73 case cb_op2: s = "cb"; break; 74 default: s = "????"; break; 75 } 76 } 77 ::tty->print("%s", s); 78} 79 80 81// Patch instruction inst at offset inst_pos to refer to dest_pos 82// and return the resulting instruction. 83// We should have pcs, not offsets, but since all is relative, it will work out 84// OK. 85int Assembler::patched_branch(int dest_pos, int inst, int inst_pos) { 86 87 int m; // mask for displacement field 88 int v; // new value for displacement field 89 const int word_aligned_ones = -4; 90 switch (inv_op(inst)) { 91 default: ShouldNotReachHere(); 92 case call_op: m = wdisp(word_aligned_ones, 0, 30); v = wdisp(dest_pos, inst_pos, 30); break; 93 case branch_op: 94 switch (inv_op2(inst)) { 95 case bpr_op2: m = wdisp16(word_aligned_ones, 0); v = wdisp16(dest_pos, inst_pos); break; 96 case fbp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; 97 case bp_op2: m = wdisp( word_aligned_ones, 0, 19); v = wdisp( dest_pos, inst_pos, 19); break; 98 case fb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; 99 case br_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; 100 case cb_op2: m = wdisp( word_aligned_ones, 0, 22); v = wdisp( dest_pos, inst_pos, 22); break; 101 default: ShouldNotReachHere(); 102 } 103 } 104 return inst & ~m | v; 105} 106 107// Return the offset of the branch destionation of instruction inst 108// at offset pos. 109// Should have pcs, but since all is relative, it works out. 110int Assembler::branch_destination(int inst, int pos) { 111 int r; 112 switch (inv_op(inst)) { 113 default: ShouldNotReachHere(); 114 case call_op: r = inv_wdisp(inst, pos, 30); break; 115 case branch_op: 116 switch (inv_op2(inst)) { 117 case bpr_op2: r = inv_wdisp16(inst, pos); break; 118 case fbp_op2: r = inv_wdisp( inst, pos, 19); break; 119 case bp_op2: r = inv_wdisp( inst, pos, 19); break; 120 case fb_op2: r = inv_wdisp( inst, pos, 22); break; 121 case br_op2: r = inv_wdisp( inst, pos, 22); break; 122 case cb_op2: r = inv_wdisp( inst, pos, 22); break; 123 default: ShouldNotReachHere(); 124 } 125 } 126 return r; 127} 128 129int AbstractAssembler::code_fill_byte() { 130 return 0x00; // illegal instruction 0x00000000 131} 132 133// Generate a bunch 'o stuff (including v9's 134#ifndef PRODUCT 135void Assembler::test_v9() { 136 add( G0, G1, G2 ); 137 add( G3, 0, G4 ); 138 139 addcc( G5, G6, G7 ); 140 addcc( I0, 1, I1 ); 141 addc( I2, I3, I4 ); 142 addc( I5, -1, I6 ); 143 addccc( I7, L0, L1 ); 144 addccc( L2, (1 << 12) - 2, L3 ); 145 146 Label lbl1, lbl2, lbl3; 147 148 bind(lbl1); 149 150 bpr( rc_z, true, pn, L4, pc(), relocInfo::oop_type ); 151 delayed()->nop(); 152 bpr( rc_lez, false, pt, L5, lbl1); 153 delayed()->nop(); 154 155 fb( f_never, true, pc() + 4, relocInfo::none); 156 delayed()->nop(); 157 fb( f_notEqual, false, lbl2 ); 158 delayed()->nop(); 159 160 fbp( f_notZero, true, fcc0, pn, pc() - 4, relocInfo::none); 161 delayed()->nop(); 162 fbp( f_lessOrGreater, false, fcc1, pt, lbl3 ); 163 delayed()->nop(); 164 165 br( equal, true, pc() + 1024, relocInfo::none); 166 delayed()->nop(); 167 br( lessEqual, false, lbl1 ); 168 delayed()->nop(); 169 br( never, false, lbl1 ); 170 delayed()->nop(); 171 172 bp( less, true, icc, pn, pc(), relocInfo::none); 173 delayed()->nop(); 174 bp( lessEqualUnsigned, false, xcc, pt, lbl2 ); 175 delayed()->nop(); 176 177 call( pc(), relocInfo::none); 178 delayed()->nop(); 179 call( lbl3 ); 180 delayed()->nop(); 181 182 183 casa( L6, L7, O0 ); 184 casxa( O1, O2, O3, 0 ); 185 186 udiv( O4, O5, O7 ); 187 udiv( G0, (1 << 12) - 1, G1 ); 188 sdiv( G1, G2, G3 ); 189 sdiv( G4, -((1 << 12) - 1), G5 ); 190 udivcc( G6, G7, I0 ); 191 udivcc( I1, -((1 << 12) - 2), I2 ); 192 sdivcc( I3, I4, I5 ); 193 sdivcc( I6, -((1 << 12) - 0), I7 ); 194 195 done(); 196 retry(); 197 198 fadd( FloatRegisterImpl::S, F0, F1, F2 ); 199 fsub( FloatRegisterImpl::D, F34, F0, F62 ); 200 201 fcmp( FloatRegisterImpl::Q, fcc0, F0, F60); 202 fcmpe( FloatRegisterImpl::S, fcc1, F31, F30); 203 204 ftox( FloatRegisterImpl::D, F2, F4 ); 205 ftoi( FloatRegisterImpl::Q, F4, F8 ); 206 207 ftof( FloatRegisterImpl::S, FloatRegisterImpl::Q, F3, F12 ); 208 209 fxtof( FloatRegisterImpl::S, F4, F5 ); 210 fitof( FloatRegisterImpl::D, F6, F8 ); 211 212 fmov( FloatRegisterImpl::Q, F16, F20 ); 213 fneg( FloatRegisterImpl::S, F6, F7 ); 214 fabs( FloatRegisterImpl::D, F10, F12 ); 215 216 fmul( FloatRegisterImpl::Q, F24, F28, F32 ); 217 fmul( FloatRegisterImpl::S, FloatRegisterImpl::D, F8, F9, F14 ); 218 fdiv( FloatRegisterImpl::S, F10, F11, F12 ); 219 220 fsqrt( FloatRegisterImpl::S, F13, F14 ); 221 222 flush( L0, L1 ); 223 flush( L2, -1 ); 224 225 flushw(); 226 227 illtrap( (1 << 22) - 2); 228 229 impdep1( 17, (1 << 19) - 1 ); 230 impdep2( 3, 0 ); 231 232 jmpl( L3, L4, L5 ); 233 delayed()->nop(); 234 jmpl( L6, -1, L7, Relocation::spec_simple(relocInfo::none)); 235 delayed()->nop(); 236 237 238 ldf( FloatRegisterImpl::S, O0, O1, F15 ); 239 ldf( FloatRegisterImpl::D, O2, -1, F14 ); 240 241 242 ldfsr( O3, O4 ); 243 ldfsr( O5, -1 ); 244 ldxfsr( O6, O7 ); 245 ldxfsr( I0, -1 ); 246 247 ldfa( FloatRegisterImpl::D, I1, I2, 1, F16 ); 248 ldfa( FloatRegisterImpl::Q, I3, -1, F36 ); 249 250 ldsb( I4, I5, I6 ); 251 ldsb( I7, -1, G0 ); 252 ldsh( G1, G3, G4 ); 253 ldsh( G5, -1, G6 ); 254 ldsw( G7, L0, L1 ); 255 ldsw( L2, -1, L3 ); 256 ldub( L4, L5, L6 ); 257 ldub( L7, -1, O0 ); 258 lduh( O1, O2, O3 ); 259 lduh( O4, -1, O5 ); 260 lduw( O6, O7, G0 ); 261 lduw( G1, -1, G2 ); 262 ldx( G3, G4, G5 ); 263 ldx( G6, -1, G7 ); 264 ldd( I0, I1, I2 ); 265 ldd( I3, -1, I4 ); 266 267 ldsba( I5, I6, 2, I7 ); 268 ldsba( L0, -1, L1 ); 269 ldsha( L2, L3, 3, L4 ); 270 ldsha( L5, -1, L6 ); 271 ldswa( L7, O0, (1 << 8) - 1, O1 ); 272 ldswa( O2, -1, O3 ); 273 lduba( O4, O5, 0, O6 ); 274 lduba( O7, -1, I0 ); 275 lduha( I1, I2, 1, I3 ); 276 lduha( I4, -1, I5 ); 277 lduwa( I6, I7, 2, L0 ); 278 lduwa( L1, -1, L2 ); 279 ldxa( L3, L4, 3, L5 ); 280 ldxa( L6, -1, L7 ); 281 ldda( G0, G1, 4, G2 ); 282 ldda( G3, -1, G4 ); 283 284 ldstub( G5, G6, G7 ); 285 ldstub( O0, -1, O1 ); 286 287 ldstuba( O2, O3, 5, O4 ); 288 ldstuba( O5, -1, O6 ); 289 290 and3( I0, L0, O0 ); 291 and3( G7, -1, O7 ); 292 andcc( L2, I2, G2 ); 293 andcc( L4, -1, G4 ); 294 andn( I5, I6, I7 ); 295 andn( I6, -1, I7 ); 296 andncc( I5, I6, I7 ); 297 andncc( I7, -1, I6 ); 298 or3( I5, I6, I7 ); 299 or3( I7, -1, I6 ); 300 orcc( I5, I6, I7 ); 301 orcc( I7, -1, I6 ); 302 orn( I5, I6, I7 ); 303 orn( I7, -1, I6 ); 304 orncc( I5, I6, I7 ); 305 orncc( I7, -1, I6 ); 306 xor3( I5, I6, I7 ); 307 xor3( I7, -1, I6 ); 308 xorcc( I5, I6, I7 ); 309 xorcc( I7, -1, I6 ); 310 xnor( I5, I6, I7 ); 311 xnor( I7, -1, I6 ); 312 xnorcc( I5, I6, I7 ); 313 xnorcc( I7, -1, I6 ); 314 315 membar( Membar_mask_bits(StoreStore | LoadStore | StoreLoad | LoadLoad | Sync | MemIssue | Lookaside ) ); 316 membar( StoreStore ); 317 membar( LoadStore ); 318 membar( StoreLoad ); 319 membar( LoadLoad ); 320 membar( Sync ); 321 membar( MemIssue ); 322 membar( Lookaside ); 323 324 fmov( FloatRegisterImpl::S, f_ordered, true, fcc2, F16, F17 ); 325 fmov( FloatRegisterImpl::D, rc_lz, L5, F18, F20 ); 326 327 movcc( overflowClear, false, icc, I6, L4 ); 328 movcc( f_unorderedOrEqual, true, fcc2, (1 << 10) - 1, O0 ); 329 330 movr( rc_nz, I5, I6, I7 ); 331 movr( rc_gz, L1, -1, L2 ); 332 333 mulx( I5, I6, I7 ); 334 mulx( I7, -1, I6 ); 335 sdivx( I5, I6, I7 ); 336 sdivx( I7, -1, I6 ); 337 udivx( I5, I6, I7 ); 338 udivx( I7, -1, I6 ); 339 340 umul( I5, I6, I7 ); 341 umul( I7, -1, I6 ); 342 smul( I5, I6, I7 ); 343 smul( I7, -1, I6 ); 344 umulcc( I5, I6, I7 ); 345 umulcc( I7, -1, I6 ); 346 smulcc( I5, I6, I7 ); 347 smulcc( I7, -1, I6 ); 348 349 mulscc( I5, I6, I7 ); 350 mulscc( I7, -1, I6 ); 351 352 nop(); 353 354 355 popc( G0, G1); 356 popc( -1, G2); 357 358 prefetch( L1, L2, severalReads ); 359 prefetch( L3, -1, oneRead ); 360 prefetcha( O3, O2, 6, severalWritesAndPossiblyReads ); 361 prefetcha( G2, -1, oneWrite ); 362 363 rett( I7, I7); 364 delayed()->nop(); 365 rett( G0, -1, relocInfo::none); 366 delayed()->nop(); 367 368 save( I5, I6, I7 ); 369 save( I7, -1, I6 ); 370 restore( I5, I6, I7 ); 371 restore( I7, -1, I6 ); 372 373 saved(); 374 restored(); 375 376 sethi( 0xaaaaaaaa, I3, Relocation::spec_simple(relocInfo::none)); 377 378 sll( I5, I6, I7 ); 379 sll( I7, 31, I6 ); 380 srl( I5, I6, I7 ); 381 srl( I7, 0, I6 ); 382 sra( I5, I6, I7 ); 383 sra( I7, 30, I6 ); 384 sllx( I5, I6, I7 ); 385 sllx( I7, 63, I6 ); 386 srlx( I5, I6, I7 ); 387 srlx( I7, 0, I6 ); 388 srax( I5, I6, I7 ); 389 srax( I7, 62, I6 ); 390 391 sir( -1 ); 392 393 stbar(); 394 395 stf( FloatRegisterImpl::Q, F40, G0, I7 ); 396 stf( FloatRegisterImpl::S, F18, I3, -1 ); 397 398 stfsr( L1, L2 ); 399 stfsr( I7, -1 ); 400 stxfsr( I6, I5 ); 401 stxfsr( L4, -1 ); 402 403 stfa( FloatRegisterImpl::D, F22, I6, I7, 7 ); 404 stfa( FloatRegisterImpl::Q, F44, G0, -1 ); 405 406 stb( L5, O2, I7 ); 407 stb( I7, I6, -1 ); 408 sth( L5, O2, I7 ); 409 sth( I7, I6, -1 ); 410 stw( L5, O2, I7 ); 411 stw( I7, I6, -1 ); 412 stx( L5, O2, I7 ); 413 stx( I7, I6, -1 ); 414 std( L5, O2, I7 ); 415 std( I7, I6, -1 ); 416 417 stba( L5, O2, I7, 8 ); 418 stba( I7, I6, -1 ); 419 stha( L5, O2, I7, 9 ); 420 stha( I7, I6, -1 ); 421 stwa( L5, O2, I7, 0 ); 422 stwa( I7, I6, -1 ); 423 stxa( L5, O2, I7, 11 ); 424 stxa( I7, I6, -1 ); 425 stda( L5, O2, I7, 12 ); 426 stda( I7, I6, -1 ); 427 428 sub( I5, I6, I7 ); 429 sub( I7, -1, I6 ); 430 subcc( I5, I6, I7 ); 431 subcc( I7, -1, I6 ); 432 subc( I5, I6, I7 ); 433 subc( I7, -1, I6 ); 434 subccc( I5, I6, I7 ); 435 subccc( I7, -1, I6 ); 436 437 swap( I5, I6, I7 ); 438 swap( I7, -1, I6 ); 439 440 swapa( G0, G1, 13, G2 ); 441 swapa( I7, -1, I6 ); 442 443 taddcc( I5, I6, I7 ); 444 taddcc( I7, -1, I6 ); 445 taddcctv( I5, I6, I7 ); 446 taddcctv( I7, -1, I6 ); 447 448 tsubcc( I5, I6, I7 ); 449 tsubcc( I7, -1, I6 ); 450 tsubcctv( I5, I6, I7 ); 451 tsubcctv( I7, -1, I6 ); 452 453 trap( overflowClear, xcc, G0, G1 ); 454 trap( lessEqual, icc, I7, 17 ); 455 456 bind(lbl2); 457 bind(lbl3); 458 459 code()->decode(); 460} 461 462// Generate a bunch 'o stuff unique to V8 463void Assembler::test_v8_onlys() { 464 Label lbl1; 465 466 cb( cp_0or1or2, false, pc() - 4, relocInfo::none); 467 delayed()->nop(); 468 cb( cp_never, true, lbl1); 469 delayed()->nop(); 470 471 cpop1(1, 2, 3, 4); 472 cpop2(5, 6, 7, 8); 473 474 ldc( I0, I1, 31); 475 ldc( I2, -1, 0); 476 477 lddc( I4, I4, 30); 478 lddc( I6, 0, 1 ); 479 480 ldcsr( L0, L1, 0); 481 ldcsr( L1, (1 << 12) - 1, 17 ); 482 483 stc( 31, L4, L5); 484 stc( 30, L6, -(1 << 12) ); 485 486 stdc( 0, L7, G0); 487 stdc( 1, G1, 0 ); 488 489 stcsr( 16, G2, G3); 490 stcsr( 17, G4, 1 ); 491 492 stdcq( 4, G5, G6); 493 stdcq( 5, G7, -1 ); 494 495 bind(lbl1); 496 497 code()->decode(); 498} 499#endif 500 501// Implementation of MacroAssembler 502 503void MacroAssembler::null_check(Register reg, int offset) { 504 if (needs_explicit_null_check((intptr_t)offset)) { 505 // provoke OS NULL exception if reg = NULL by 506 // accessing M[reg] w/o changing any registers 507 ld_ptr(reg, 0, G0); 508 } 509 else { 510 // nothing to do, (later) access of M[reg + offset] 511 // will provoke OS NULL exception if reg = NULL 512 } 513} 514 515// Ring buffer jumps 516 517#ifndef PRODUCT 518void MacroAssembler::ret( bool trace ) { if (trace) { 519 mov(I7, O7); // traceable register 520 JMP(O7, 2 * BytesPerInstWord); 521 } else { 522 jmpl( I7, 2 * BytesPerInstWord, G0 ); 523 } 524 } 525 526void MacroAssembler::retl( bool trace ) { if (trace) JMP(O7, 2 * BytesPerInstWord); 527 else jmpl( O7, 2 * BytesPerInstWord, G0 ); } 528#endif /* PRODUCT */ 529 530 531void MacroAssembler::jmp2(Register r1, Register r2, const char* file, int line ) { 532 assert_not_delayed(); 533 // This can only be traceable if r1 & r2 are visible after a window save 534 if (TraceJumps) { 535#ifndef PRODUCT 536 save_frame(0); 537 verify_thread(); 538 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); 539 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); 540 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); 541 add(O2, O1, O1); 542 543 add(r1->after_save(), r2->after_save(), O2); 544 set((intptr_t)file, O3); 545 set(line, O4); 546 Label L; 547 // get nearby pc, store jmp target 548 call(L, relocInfo::none); // No relocation for call to pc+0x8 549 delayed()->st(O2, O1, 0); 550 bind(L); 551 552 // store nearby pc 553 st(O7, O1, sizeof(intptr_t)); 554 // store file 555 st(O3, O1, 2*sizeof(intptr_t)); 556 // store line 557 st(O4, O1, 3*sizeof(intptr_t)); 558 add(O0, 1, O0); 559 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); 560 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); 561 restore(); 562#endif /* PRODUCT */ 563 } 564 jmpl(r1, r2, G0); 565} 566void MacroAssembler::jmp(Register r1, int offset, const char* file, int line ) { 567 assert_not_delayed(); 568 // This can only be traceable if r1 is visible after a window save 569 if (TraceJumps) { 570#ifndef PRODUCT 571 save_frame(0); 572 verify_thread(); 573 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); 574 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); 575 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); 576 add(O2, O1, O1); 577 578 add(r1->after_save(), offset, O2); 579 set((intptr_t)file, O3); 580 set(line, O4); 581 Label L; 582 // get nearby pc, store jmp target 583 call(L, relocInfo::none); // No relocation for call to pc+0x8 584 delayed()->st(O2, O1, 0); 585 bind(L); 586 587 // store nearby pc 588 st(O7, O1, sizeof(intptr_t)); 589 // store file 590 st(O3, O1, 2*sizeof(intptr_t)); 591 // store line 592 st(O4, O1, 3*sizeof(intptr_t)); 593 add(O0, 1, O0); 594 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); 595 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); 596 restore(); 597#endif /* PRODUCT */ 598 } 599 jmp(r1, offset); 600} 601 602// This code sequence is relocatable to any address, even on LP64. 603void MacroAssembler::jumpl( Address& a, Register d, int offset, const char* file, int line ) { 604 assert_not_delayed(); 605 // Force fixed length sethi because NativeJump and NativeFarCall don't handle 606 // variable length instruction streams. 607 sethi(a, /*ForceRelocatable=*/ true); 608 if (TraceJumps) { 609#ifndef PRODUCT 610 // Must do the add here so relocation can find the remainder of the 611 // value to be relocated. 612 add(a.base(), a.disp() + offset, a.base(), a.rspec(offset)); 613 save_frame(0); 614 verify_thread(); 615 ld(G2_thread, in_bytes(JavaThread::jmp_ring_index_offset()), O0); 616 add(G2_thread, in_bytes(JavaThread::jmp_ring_offset()), O1); 617 sll(O0, exact_log2(4*sizeof(intptr_t)), O2); 618 add(O2, O1, O1); 619 620 set((intptr_t)file, O3); 621 set(line, O4); 622 Label L; 623 624 // get nearby pc, store jmp target 625 call(L, relocInfo::none); // No relocation for call to pc+0x8 626 delayed()->st(a.base()->after_save(), O1, 0); 627 bind(L); 628 629 // store nearby pc 630 st(O7, O1, sizeof(intptr_t)); 631 // store file 632 st(O3, O1, 2*sizeof(intptr_t)); 633 // store line 634 st(O4, O1, 3*sizeof(intptr_t)); 635 add(O0, 1, O0); 636 and3(O0, JavaThread::jump_ring_buffer_size - 1, O0); 637 st(O0, G2_thread, in_bytes(JavaThread::jmp_ring_index_offset())); 638 restore(); 639 jmpl(a.base(), G0, d); 640#else 641 jmpl(a, d, offset); 642#endif /* PRODUCT */ 643 } else { 644 jmpl(a, d, offset); 645 } 646} 647 648void MacroAssembler::jump( Address& a, int offset, const char* file, int line ) { 649 jumpl( a, G0, offset, file, line ); 650} 651 652 653// Convert to C varargs format 654void MacroAssembler::set_varargs( Argument inArg, Register d ) { 655 // spill register-resident args to their memory slots 656 // (SPARC calling convention requires callers to have already preallocated these) 657 // Note that the inArg might in fact be an outgoing argument, 658 // if a leaf routine or stub does some tricky argument shuffling. 659 // This routine must work even though one of the saved arguments 660 // is in the d register (e.g., set_varargs(Argument(0, false), O0)). 661 for (Argument savePtr = inArg; 662 savePtr.is_register(); 663 savePtr = savePtr.successor()) { 664 st_ptr(savePtr.as_register(), savePtr.address_in_frame()); 665 } 666 // return the address of the first memory slot 667 add(inArg.address_in_frame(), d); 668} 669 670// Conditional breakpoint (for assertion checks in assembly code) 671void MacroAssembler::breakpoint_trap(Condition c, CC cc) { 672 trap(c, cc, G0, ST_RESERVED_FOR_USER_0); 673} 674 675// We want to use ST_BREAKPOINT here, but the debugger is confused by it. 676void MacroAssembler::breakpoint_trap() { 677 trap(ST_RESERVED_FOR_USER_0); 678} 679 680// flush windows (except current) using flushw instruction if avail. 681void MacroAssembler::flush_windows() { 682 if (VM_Version::v9_instructions_work()) flushw(); 683 else flush_windows_trap(); 684} 685 686// Write serialization page so VM thread can do a pseudo remote membar 687// We use the current thread pointer to calculate a thread specific 688// offset to write to within the page. This minimizes bus traffic 689// due to cache line collision. 690void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) { 691 Address mem_serialize_page(tmp1, os::get_memory_serialize_page()); 692 srl(thread, os::get_serialize_page_shift_count(), tmp2); 693 if (Assembler::is_simm13(os::vm_page_size())) { 694 and3(tmp2, (os::vm_page_size() - sizeof(int)), tmp2); 695 } 696 else { 697 set((os::vm_page_size() - sizeof(int)), tmp1); 698 and3(tmp2, tmp1, tmp2); 699 } 700 load_address(mem_serialize_page); 701 st(G0, tmp1, tmp2); 702} 703 704 705 706void MacroAssembler::enter() { 707 Unimplemented(); 708} 709 710void MacroAssembler::leave() { 711 Unimplemented(); 712} 713 714void MacroAssembler::mult(Register s1, Register s2, Register d) { 715 if(VM_Version::v9_instructions_work()) { 716 mulx (s1, s2, d); 717 } else { 718 smul (s1, s2, d); 719 } 720} 721 722void MacroAssembler::mult(Register s1, int simm13a, Register d) { 723 if(VM_Version::v9_instructions_work()) { 724 mulx (s1, simm13a, d); 725 } else { 726 smul (s1, simm13a, d); 727 } 728} 729 730 731#ifdef ASSERT 732void MacroAssembler::read_ccr_v8_assert(Register ccr_save) { 733 const Register s1 = G3_scratch; 734 const Register s2 = G4_scratch; 735 Label get_psr_test; 736 // Get the condition codes the V8 way. 737 read_ccr_trap(s1); 738 mov(ccr_save, s2); 739 // This is a test of V8 which has icc but not xcc 740 // so mask off the xcc bits 741 and3(s2, 0xf, s2); 742 // Compare condition codes from the V8 and V9 ways. 743 subcc(s2, s1, G0); 744 br(Assembler::notEqual, true, Assembler::pt, get_psr_test); 745 delayed()->breakpoint_trap(); 746 bind(get_psr_test); 747} 748 749void MacroAssembler::write_ccr_v8_assert(Register ccr_save) { 750 const Register s1 = G3_scratch; 751 const Register s2 = G4_scratch; 752 Label set_psr_test; 753 // Write out the saved condition codes the V8 way 754 write_ccr_trap(ccr_save, s1, s2); 755 // Read back the condition codes using the V9 instruction 756 rdccr(s1); 757 mov(ccr_save, s2); 758 // This is a test of V8 which has icc but not xcc 759 // so mask off the xcc bits 760 and3(s2, 0xf, s2); 761 and3(s1, 0xf, s1); 762 // Compare the V8 way with the V9 way. 763 subcc(s2, s1, G0); 764 br(Assembler::notEqual, true, Assembler::pt, set_psr_test); 765 delayed()->breakpoint_trap(); 766 bind(set_psr_test); 767} 768#else 769#define read_ccr_v8_assert(x) 770#define write_ccr_v8_assert(x) 771#endif // ASSERT 772 773void MacroAssembler::read_ccr(Register ccr_save) { 774 if (VM_Version::v9_instructions_work()) { 775 rdccr(ccr_save); 776 // Test code sequence used on V8. Do not move above rdccr. 777 read_ccr_v8_assert(ccr_save); 778 } else { 779 read_ccr_trap(ccr_save); 780 } 781} 782 783void MacroAssembler::write_ccr(Register ccr_save) { 784 if (VM_Version::v9_instructions_work()) { 785 // Test code sequence used on V8. Do not move below wrccr. 786 write_ccr_v8_assert(ccr_save); 787 wrccr(ccr_save); 788 } else { 789 const Register temp_reg1 = G3_scratch; 790 const Register temp_reg2 = G4_scratch; 791 write_ccr_trap(ccr_save, temp_reg1, temp_reg2); 792 } 793} 794 795 796// Calls to C land 797 798#ifdef ASSERT 799// a hook for debugging 800static Thread* reinitialize_thread() { 801 return ThreadLocalStorage::thread(); 802} 803#else 804#define reinitialize_thread ThreadLocalStorage::thread 805#endif 806 807#ifdef ASSERT 808address last_get_thread = NULL; 809#endif 810 811// call this when G2_thread is not known to be valid 812void MacroAssembler::get_thread() { 813 save_frame(0); // to avoid clobbering O0 814 mov(G1, L0); // avoid clobbering G1 815 mov(G5_method, L1); // avoid clobbering G5 816 mov(G3, L2); // avoid clobbering G3 also 817 mov(G4, L5); // avoid clobbering G4 818#ifdef ASSERT 819 Address last_get_thread_addr(L3, (address)&last_get_thread); 820 sethi(last_get_thread_addr); 821 inc(L4, get_pc(L4) + 2 * BytesPerInstWord); // skip getpc() code + inc + st_ptr to point L4 at call 822 st_ptr(L4, last_get_thread_addr); 823#endif 824 call(CAST_FROM_FN_PTR(address, reinitialize_thread), relocInfo::runtime_call_type); 825 delayed()->nop(); 826 mov(L0, G1); 827 mov(L1, G5_method); 828 mov(L2, G3); 829 mov(L5, G4); 830 restore(O0, 0, G2_thread); 831} 832 833static Thread* verify_thread_subroutine(Thread* gthread_value) { 834 Thread* correct_value = ThreadLocalStorage::thread(); 835 guarantee(gthread_value == correct_value, "G2_thread value must be the thread"); 836 return correct_value; 837} 838 839void MacroAssembler::verify_thread() { 840 if (VerifyThread) { 841 // NOTE: this chops off the heads of the 64-bit O registers. 842#ifdef CC_INTERP 843 save_frame(0); 844#else 845 // make sure G2_thread contains the right value 846 save_frame_and_mov(0, Lmethod, Lmethod); // to avoid clobbering O0 (and propagate Lmethod for -Xprof) 847 mov(G1, L1); // avoid clobbering G1 848 // G2 saved below 849 mov(G3, L3); // avoid clobbering G3 850 mov(G4, L4); // avoid clobbering G4 851 mov(G5_method, L5); // avoid clobbering G5_method 852#endif /* CC_INTERP */ 853#if defined(COMPILER2) && !defined(_LP64) 854 // Save & restore possible 64-bit Long arguments in G-regs 855 srlx(G1,32,L0); 856 srlx(G4,32,L6); 857#endif 858 call(CAST_FROM_FN_PTR(address,verify_thread_subroutine), relocInfo::runtime_call_type); 859 delayed()->mov(G2_thread, O0); 860 861 mov(L1, G1); // Restore G1 862 // G2 restored below 863 mov(L3, G3); // restore G3 864 mov(L4, G4); // restore G4 865 mov(L5, G5_method); // restore G5_method 866#if defined(COMPILER2) && !defined(_LP64) 867 // Save & restore possible 64-bit Long arguments in G-regs 868 sllx(L0,32,G2); // Move old high G1 bits high in G2 869 sllx(G1, 0,G1); // Clear current high G1 bits 870 or3 (G1,G2,G1); // Recover 64-bit G1 871 sllx(L6,32,G2); // Move old high G4 bits high in G2 872 sllx(G4, 0,G4); // Clear current high G4 bits 873 or3 (G4,G2,G4); // Recover 64-bit G4 874#endif 875 restore(O0, 0, G2_thread); 876 } 877} 878 879 880void MacroAssembler::save_thread(const Register thread_cache) { 881 verify_thread(); 882 if (thread_cache->is_valid()) { 883 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); 884 mov(G2_thread, thread_cache); 885 } 886 if (VerifyThread) { 887 // smash G2_thread, as if the VM were about to anyway 888 set(0x67676767, G2_thread); 889 } 890} 891 892 893void MacroAssembler::restore_thread(const Register thread_cache) { 894 if (thread_cache->is_valid()) { 895 assert(thread_cache->is_local() || thread_cache->is_in(), "bad volatile"); 896 mov(thread_cache, G2_thread); 897 verify_thread(); 898 } else { 899 // do it the slow way 900 get_thread(); 901 } 902} 903 904 905// %%% maybe get rid of [re]set_last_Java_frame 906void MacroAssembler::set_last_Java_frame(Register last_java_sp, Register last_Java_pc) { 907 assert_not_delayed(); 908 Address flags(G2_thread, 909 0, 910 in_bytes(JavaThread::frame_anchor_offset()) + 911 in_bytes(JavaFrameAnchor::flags_offset())); 912 Address pc_addr(G2_thread, 913 0, 914 in_bytes(JavaThread::last_Java_pc_offset())); 915 916 // Always set last_Java_pc and flags first because once last_Java_sp is visible 917 // has_last_Java_frame is true and users will look at the rest of the fields. 918 // (Note: flags should always be zero before we get here so doesn't need to be set.) 919 920#ifdef ASSERT 921 // Verify that flags was zeroed on return to Java 922 Label PcOk; 923 save_frame(0); // to avoid clobbering O0 924 ld_ptr(pc_addr, L0); 925 tst(L0); 926#ifdef _LP64 927 brx(Assembler::zero, false, Assembler::pt, PcOk); 928#else 929 br(Assembler::zero, false, Assembler::pt, PcOk); 930#endif // _LP64 931 delayed() -> nop(); 932 stop("last_Java_pc not zeroed before leaving Java"); 933 bind(PcOk); 934 935 // Verify that flags was zeroed on return to Java 936 Label FlagsOk; 937 ld(flags, L0); 938 tst(L0); 939 br(Assembler::zero, false, Assembler::pt, FlagsOk); 940 delayed() -> restore(); 941 stop("flags not zeroed before leaving Java"); 942 bind(FlagsOk); 943#endif /* ASSERT */ 944 // 945 // When returning from calling out from Java mode the frame anchor's last_Java_pc 946 // will always be set to NULL. It is set here so that if we are doing a call to 947 // native (not VM) that we capture the known pc and don't have to rely on the 948 // native call having a standard frame linkage where we can find the pc. 949 950 if (last_Java_pc->is_valid()) { 951 st_ptr(last_Java_pc, pc_addr); 952 } 953 954#ifdef _LP64 955#ifdef ASSERT 956 // Make sure that we have an odd stack 957 Label StackOk; 958 andcc(last_java_sp, 0x01, G0); 959 br(Assembler::notZero, false, Assembler::pt, StackOk); 960 delayed() -> nop(); 961 stop("Stack Not Biased in set_last_Java_frame"); 962 bind(StackOk); 963#endif // ASSERT 964 assert( last_java_sp != G4_scratch, "bad register usage in set_last_Java_frame"); 965 add( last_java_sp, STACK_BIAS, G4_scratch ); 966 st_ptr(G4_scratch, Address(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset()))); 967#else 968 st_ptr(last_java_sp, Address(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset()))); 969#endif // _LP64 970} 971 972void MacroAssembler::reset_last_Java_frame(void) { 973 assert_not_delayed(); 974 975 Address sp_addr(G2_thread, 0, in_bytes(JavaThread::last_Java_sp_offset())); 976 Address pc_addr(G2_thread, 977 0, 978 in_bytes(JavaThread::frame_anchor_offset()) + in_bytes(JavaFrameAnchor::last_Java_pc_offset())); 979 Address flags(G2_thread, 980 0, 981 in_bytes(JavaThread::frame_anchor_offset()) + in_bytes(JavaFrameAnchor::flags_offset())); 982 983#ifdef ASSERT 984 // check that it WAS previously set 985#ifdef CC_INTERP 986 save_frame(0); 987#else 988 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod to helper frame for -Xprof 989#endif /* CC_INTERP */ 990 ld_ptr(sp_addr, L0); 991 tst(L0); 992 breakpoint_trap(Assembler::zero, Assembler::ptr_cc); 993 restore(); 994#endif // ASSERT 995 996 st_ptr(G0, sp_addr); 997 // Always return last_Java_pc to zero 998 st_ptr(G0, pc_addr); 999 // Always null flags after return to Java 1000 st(G0, flags); 1001} 1002 1003 1004void MacroAssembler::call_VM_base( 1005 Register oop_result, 1006 Register thread_cache, 1007 Register last_java_sp, 1008 address entry_point, 1009 int number_of_arguments, 1010 bool check_exceptions) 1011{ 1012 assert_not_delayed(); 1013 1014 // determine last_java_sp register 1015 if (!last_java_sp->is_valid()) { 1016 last_java_sp = SP; 1017 } 1018 // debugging support 1019 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 1020 1021 // 64-bit last_java_sp is biased! 1022 set_last_Java_frame(last_java_sp, noreg); 1023 if (VerifyThread) mov(G2_thread, O0); // about to be smashed; pass early 1024 save_thread(thread_cache); 1025 // do the call 1026 call(entry_point, relocInfo::runtime_call_type); 1027 if (!VerifyThread) 1028 delayed()->mov(G2_thread, O0); // pass thread as first argument 1029 else 1030 delayed()->nop(); // (thread already passed) 1031 restore_thread(thread_cache); 1032 reset_last_Java_frame(); 1033 1034 // check for pending exceptions. use Gtemp as scratch register. 1035 if (check_exceptions) { 1036 check_and_forward_exception(Gtemp); 1037 } 1038 1039 // get oop result if there is one and reset the value in the thread 1040 if (oop_result->is_valid()) { 1041 get_vm_result(oop_result); 1042 } 1043} 1044 1045void MacroAssembler::check_and_forward_exception(Register scratch_reg) 1046{ 1047 Label L; 1048 1049 check_and_handle_popframe(scratch_reg); 1050 check_and_handle_earlyret(scratch_reg); 1051 1052 Address exception_addr(G2_thread, 0, in_bytes(Thread::pending_exception_offset())); 1053 ld_ptr(exception_addr, scratch_reg); 1054 br_null(scratch_reg,false,pt,L); 1055 delayed()->nop(); 1056 // we use O7 linkage so that forward_exception_entry has the issuing PC 1057 call(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type); 1058 delayed()->nop(); 1059 bind(L); 1060} 1061 1062 1063void MacroAssembler::check_and_handle_popframe(Register scratch_reg) { 1064} 1065 1066 1067void MacroAssembler::check_and_handle_earlyret(Register scratch_reg) { 1068} 1069 1070 1071void MacroAssembler::call_VM(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 1072 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions); 1073} 1074 1075 1076void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) { 1077 // O0 is reserved for the thread 1078 mov(arg_1, O1); 1079 call_VM(oop_result, entry_point, 1, check_exceptions); 1080} 1081 1082 1083void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { 1084 // O0 is reserved for the thread 1085 mov(arg_1, O1); 1086 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); 1087 call_VM(oop_result, entry_point, 2, check_exceptions); 1088} 1089 1090 1091void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { 1092 // O0 is reserved for the thread 1093 mov(arg_1, O1); 1094 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); 1095 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); 1096 call_VM(oop_result, entry_point, 3, check_exceptions); 1097} 1098 1099 1100 1101// Note: The following call_VM overloadings are useful when a "save" 1102// has already been performed by a stub, and the last Java frame is 1103// the previous one. In that case, last_java_sp must be passed as FP 1104// instead of SP. 1105 1106 1107void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments, bool check_exceptions) { 1108 call_VM_base(oop_result, noreg, last_java_sp, entry_point, number_of_arguments, check_exceptions); 1109} 1110 1111 1112void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) { 1113 // O0 is reserved for the thread 1114 mov(arg_1, O1); 1115 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 1116} 1117 1118 1119void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) { 1120 // O0 is reserved for the thread 1121 mov(arg_1, O1); 1122 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); 1123 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 1124} 1125 1126 1127void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions) { 1128 // O0 is reserved for the thread 1129 mov(arg_1, O1); 1130 mov(arg_2, O2); assert(arg_2 != O1, "smashed argument"); 1131 mov(arg_3, O3); assert(arg_3 != O1 && arg_3 != O2, "smashed argument"); 1132 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 1133} 1134 1135 1136 1137void MacroAssembler::call_VM_leaf_base(Register thread_cache, address entry_point, int number_of_arguments) { 1138 assert_not_delayed(); 1139 save_thread(thread_cache); 1140 // do the call 1141 call(entry_point, relocInfo::runtime_call_type); 1142 delayed()->nop(); 1143 restore_thread(thread_cache); 1144} 1145 1146 1147void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, int number_of_arguments) { 1148 call_VM_leaf_base(thread_cache, entry_point, number_of_arguments); 1149} 1150 1151 1152void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1) { 1153 mov(arg_1, O0); 1154 call_VM_leaf(thread_cache, entry_point, 1); 1155} 1156 1157 1158void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2) { 1159 mov(arg_1, O0); 1160 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); 1161 call_VM_leaf(thread_cache, entry_point, 2); 1162} 1163 1164 1165void MacroAssembler::call_VM_leaf(Register thread_cache, address entry_point, Register arg_1, Register arg_2, Register arg_3) { 1166 mov(arg_1, O0); 1167 mov(arg_2, O1); assert(arg_2 != O0, "smashed argument"); 1168 mov(arg_3, O2); assert(arg_3 != O0 && arg_3 != O1, "smashed argument"); 1169 call_VM_leaf(thread_cache, entry_point, 3); 1170} 1171 1172 1173void MacroAssembler::get_vm_result(Register oop_result) { 1174 verify_thread(); 1175 Address vm_result_addr(G2_thread, 0, in_bytes(JavaThread::vm_result_offset())); 1176 ld_ptr( vm_result_addr, oop_result); 1177 st_ptr(G0, vm_result_addr); 1178 verify_oop(oop_result); 1179} 1180 1181 1182void MacroAssembler::get_vm_result_2(Register oop_result) { 1183 verify_thread(); 1184 Address vm_result_addr_2(G2_thread, 0, in_bytes(JavaThread::vm_result_2_offset())); 1185 ld_ptr(vm_result_addr_2, oop_result); 1186 st_ptr(G0, vm_result_addr_2); 1187 verify_oop(oop_result); 1188} 1189 1190 1191// We require that C code which does not return a value in vm_result will 1192// leave it undisturbed. 1193void MacroAssembler::set_vm_result(Register oop_result) { 1194 verify_thread(); 1195 Address vm_result_addr(G2_thread, 0, in_bytes(JavaThread::vm_result_offset())); 1196 verify_oop(oop_result); 1197 1198# ifdef ASSERT 1199 // Check that we are not overwriting any other oop. 1200#ifdef CC_INTERP 1201 save_frame(0); 1202#else 1203 save_frame_and_mov(0, Lmethod, Lmethod); // Propagate Lmethod for -Xprof 1204#endif /* CC_INTERP */ 1205 ld_ptr(vm_result_addr, L0); 1206 tst(L0); 1207 restore(); 1208 breakpoint_trap(notZero, Assembler::ptr_cc); 1209 // } 1210# endif 1211 1212 st_ptr(oop_result, vm_result_addr); 1213} 1214 1215 1216void MacroAssembler::store_check(Register tmp, Register obj) { 1217 // Use two shifts to clear out those low order two bits! (Cannot opt. into 1.) 1218 1219 /* $$$ This stuff needs to go into one of the BarrierSet generator 1220 functions. (The particular barrier sets will have to be friends of 1221 MacroAssembler, I guess.) */ 1222 BarrierSet* bs = Universe::heap()->barrier_set(); 1223 assert(bs->kind() == BarrierSet::CardTableModRef, "Wrong barrier set kind"); 1224 CardTableModRefBS* ct = (CardTableModRefBS*)bs; 1225 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 1226#ifdef _LP64 1227 srlx(obj, CardTableModRefBS::card_shift, obj); 1228#else 1229 srl(obj, CardTableModRefBS::card_shift, obj); 1230#endif 1231 assert( tmp != obj, "need separate temp reg"); 1232 Address rs(tmp, (address)ct->byte_map_base); 1233 load_address(rs); 1234 stb(G0, rs.base(), obj); 1235} 1236 1237void MacroAssembler::store_check(Register tmp, Register obj, Register offset) { 1238 store_check(tmp, obj); 1239} 1240 1241// %%% Note: The following six instructions have been moved, 1242// unchanged, from assembler_sparc.inline.hpp. 1243// They will be refactored at a later date. 1244 1245void MacroAssembler::sethi(intptr_t imm22a, 1246 Register d, 1247 bool ForceRelocatable, 1248 RelocationHolder const& rspec) { 1249 Address adr( d, (address)imm22a, rspec ); 1250 MacroAssembler::sethi( adr, ForceRelocatable ); 1251} 1252 1253 1254void MacroAssembler::sethi(Address& a, bool ForceRelocatable) { 1255 address save_pc; 1256 int shiftcnt; 1257 // if addr of local, do not need to load it 1258 assert(a.base() != FP && a.base() != SP, "just use ld or st for locals"); 1259#ifdef _LP64 1260# ifdef CHECK_DELAY 1261 assert_not_delayed( (char *)"cannot put two instructions in delay slot" ); 1262# endif 1263 v9_dep(); 1264// ForceRelocatable = 1; 1265 save_pc = pc(); 1266 if (a.hi32() == 0 && a.low32() >= 0) { 1267 Assembler::sethi(a.low32(), a.base(), a.rspec()); 1268 } 1269 else if (a.hi32() == -1) { 1270 Assembler::sethi(~a.low32(), a.base(), a.rspec()); 1271 xor3(a.base(), ~low10(~0), a.base()); 1272 } 1273 else { 1274 Assembler::sethi(a.hi32(), a.base(), a.rspec() ); // 22 1275 if ( a.hi32() & 0x3ff ) // Any bits? 1276 or3( a.base(), a.hi32() & 0x3ff ,a.base() ); // High 32 bits are now in low 32 1277 if ( a.low32() & 0xFFFFFC00 ) { // done? 1278 if( (a.low32() >> 20) & 0xfff ) { // Any bits set? 1279 sllx(a.base(), 12, a.base()); // Make room for next 12 bits 1280 or3( a.base(), (a.low32() >> 20) & 0xfff,a.base() ); // Or in next 12 1281 shiftcnt = 0; // We already shifted 1282 } 1283 else 1284 shiftcnt = 12; 1285 if( (a.low32() >> 10) & 0x3ff ) { 1286 sllx(a.base(), shiftcnt+10, a.base());// Make room for last 10 bits 1287 or3( a.base(), (a.low32() >> 10) & 0x3ff,a.base() ); // Or in next 10 1288 shiftcnt = 0; 1289 } 1290 else 1291 shiftcnt = 10; 1292 sllx(a.base(), shiftcnt+10 , a.base()); // Shift leaving disp field 0'd 1293 } 1294 else 1295 sllx( a.base(), 32, a.base() ); 1296 } 1297 // Pad out the instruction sequence so it can be 1298 // patched later. 1299 if ( ForceRelocatable || (a.rtype() != relocInfo::none && 1300 a.rtype() != relocInfo::runtime_call_type) ) { 1301 while ( pc() < (save_pc + (7 * BytesPerInstWord )) ) 1302 nop(); 1303 } 1304#else 1305 Assembler::sethi(a.hi(), a.base(), a.rspec()); 1306#endif 1307 1308} 1309 1310int MacroAssembler::size_of_sethi(address a, bool worst_case) { 1311#ifdef _LP64 1312 if (worst_case) return 7; 1313 intptr_t iaddr = (intptr_t)a; 1314 int hi32 = (int)(iaddr >> 32); 1315 int lo32 = (int)(iaddr); 1316 int inst_count; 1317 if (hi32 == 0 && lo32 >= 0) 1318 inst_count = 1; 1319 else if (hi32 == -1) 1320 inst_count = 2; 1321 else { 1322 inst_count = 2; 1323 if ( hi32 & 0x3ff ) 1324 inst_count++; 1325 if ( lo32 & 0xFFFFFC00 ) { 1326 if( (lo32 >> 20) & 0xfff ) inst_count += 2; 1327 if( (lo32 >> 10) & 0x3ff ) inst_count += 2; 1328 } 1329 } 1330 return BytesPerInstWord * inst_count; 1331#else 1332 return BytesPerInstWord; 1333#endif 1334} 1335 1336int MacroAssembler::worst_case_size_of_set() { 1337 return size_of_sethi(NULL, true) + 1; 1338} 1339 1340void MacroAssembler::set(intptr_t value, Register d, 1341 RelocationHolder const& rspec) { 1342 Address val( d, (address)value, rspec); 1343 1344 if ( rspec.type() == relocInfo::none ) { 1345 // can optimize 1346 if (-4096 <= value && value <= 4095) { 1347 or3(G0, value, d); // setsw (this leaves upper 32 bits sign-extended) 1348 return; 1349 } 1350 if (inv_hi22(hi22(value)) == value) { 1351 sethi(val); 1352 return; 1353 } 1354 } 1355 assert_not_delayed( (char *)"cannot put two instructions in delay slot" ); 1356 sethi( val ); 1357 if (rspec.type() != relocInfo::none || (value & 0x3ff) != 0) { 1358 add( d, value & 0x3ff, d, rspec); 1359 } 1360} 1361 1362void MacroAssembler::setsw(int value, Register d, 1363 RelocationHolder const& rspec) { 1364 Address val( d, (address)value, rspec); 1365 if ( rspec.type() == relocInfo::none ) { 1366 // can optimize 1367 if (-4096 <= value && value <= 4095) { 1368 or3(G0, value, d); 1369 return; 1370 } 1371 if (inv_hi22(hi22(value)) == value) { 1372 sethi( val ); 1373#ifndef _LP64 1374 if ( value < 0 ) { 1375 assert_not_delayed(); 1376 sra (d, G0, d); 1377 } 1378#endif 1379 return; 1380 } 1381 } 1382 assert_not_delayed(); 1383 sethi( val ); 1384 add( d, value & 0x3ff, d, rspec); 1385 1386 // (A negative value could be loaded in 2 insns with sethi/xor, 1387 // but it would take a more complex relocation.) 1388#ifndef _LP64 1389 if ( value < 0) 1390 sra(d, G0, d); 1391#endif 1392} 1393 1394// %%% End of moved six set instructions. 1395 1396 1397void MacroAssembler::set64(jlong value, Register d, Register tmp) { 1398 assert_not_delayed(); 1399 v9_dep(); 1400 1401 int hi = (int)(value >> 32); 1402 int lo = (int)(value & ~0); 1403 // (Matcher::isSimpleConstant64 knows about the following optimizations.) 1404 if (Assembler::is_simm13(lo) && value == lo) { 1405 or3(G0, lo, d); 1406 } else if (hi == 0) { 1407 Assembler::sethi(lo, d); // hardware version zero-extends to upper 32 1408 if (low10(lo) != 0) 1409 or3(d, low10(lo), d); 1410 } 1411 else if (hi == -1) { 1412 Assembler::sethi(~lo, d); // hardware version zero-extends to upper 32 1413 xor3(d, low10(lo) ^ ~low10(~0), d); 1414 } 1415 else if (lo == 0) { 1416 if (Assembler::is_simm13(hi)) { 1417 or3(G0, hi, d); 1418 } else { 1419 Assembler::sethi(hi, d); // hardware version zero-extends to upper 32 1420 if (low10(hi) != 0) 1421 or3(d, low10(hi), d); 1422 } 1423 sllx(d, 32, d); 1424 } 1425 else { 1426 Assembler::sethi(hi, tmp); 1427 Assembler::sethi(lo, d); // macro assembler version sign-extends 1428 if (low10(hi) != 0) 1429 or3 (tmp, low10(hi), tmp); 1430 if (low10(lo) != 0) 1431 or3 ( d, low10(lo), d); 1432 sllx(tmp, 32, tmp); 1433 or3 (d, tmp, d); 1434 } 1435} 1436 1437// compute size in bytes of sparc frame, given 1438// number of extraWords 1439int MacroAssembler::total_frame_size_in_bytes(int extraWords) { 1440 1441 int nWords = frame::memory_parameter_word_sp_offset; 1442 1443 nWords += extraWords; 1444 1445 if (nWords & 1) ++nWords; // round up to double-word 1446 1447 return nWords * BytesPerWord; 1448} 1449 1450 1451// save_frame: given number of "extra" words in frame, 1452// issue approp. save instruction (p 200, v8 manual) 1453 1454void MacroAssembler::save_frame(int extraWords = 0) { 1455 int delta = -total_frame_size_in_bytes(extraWords); 1456 if (is_simm13(delta)) { 1457 save(SP, delta, SP); 1458 } else { 1459 set(delta, G3_scratch); 1460 save(SP, G3_scratch, SP); 1461 } 1462} 1463 1464 1465void MacroAssembler::save_frame_c1(int size_in_bytes) { 1466 if (is_simm13(-size_in_bytes)) { 1467 save(SP, -size_in_bytes, SP); 1468 } else { 1469 set(-size_in_bytes, G3_scratch); 1470 save(SP, G3_scratch, SP); 1471 } 1472} 1473 1474 1475void MacroAssembler::save_frame_and_mov(int extraWords, 1476 Register s1, Register d1, 1477 Register s2, Register d2) { 1478 assert_not_delayed(); 1479 1480 // The trick here is to use precisely the same memory word 1481 // that trap handlers also use to save the register. 1482 // This word cannot be used for any other purpose, but 1483 // it works fine to save the register's value, whether or not 1484 // an interrupt flushes register windows at any given moment! 1485 Address s1_addr; 1486 if (s1->is_valid() && (s1->is_in() || s1->is_local())) { 1487 s1_addr = s1->address_in_saved_window(); 1488 st_ptr(s1, s1_addr); 1489 } 1490 1491 Address s2_addr; 1492 if (s2->is_valid() && (s2->is_in() || s2->is_local())) { 1493 s2_addr = s2->address_in_saved_window(); 1494 st_ptr(s2, s2_addr); 1495 } 1496 1497 save_frame(extraWords); 1498 1499 if (s1_addr.base() == SP) { 1500 ld_ptr(s1_addr.after_save(), d1); 1501 } else if (s1->is_valid()) { 1502 mov(s1->after_save(), d1); 1503 } 1504 1505 if (s2_addr.base() == SP) { 1506 ld_ptr(s2_addr.after_save(), d2); 1507 } else if (s2->is_valid()) { 1508 mov(s2->after_save(), d2); 1509 } 1510} 1511 1512 1513Address MacroAssembler::allocate_oop_address(jobject obj, Register d) { 1514 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); 1515 int oop_index = oop_recorder()->allocate_index(obj); 1516 return Address(d, address(obj), oop_Relocation::spec(oop_index)); 1517} 1518 1519 1520Address MacroAssembler::constant_oop_address(jobject obj, Register d) { 1521 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder"); 1522 int oop_index = oop_recorder()->find_index(obj); 1523 return Address(d, address(obj), oop_Relocation::spec(oop_index)); 1524} 1525 1526 1527void MacroAssembler::align(int modulus) { 1528 while (offset() % modulus != 0) nop(); 1529} 1530 1531 1532void MacroAssembler::safepoint() { 1533 relocate(breakpoint_Relocation::spec(breakpoint_Relocation::safepoint)); 1534} 1535 1536 1537void RegistersForDebugging::print(outputStream* s) { 1538 int j; 1539 for ( j = 0; j < 8; ++j ) 1540 if ( j != 6 ) s->print_cr("i%d = 0x%.16lx", j, i[j]); 1541 else s->print_cr( "fp = 0x%.16lx", i[j]); 1542 s->cr(); 1543 1544 for ( j = 0; j < 8; ++j ) 1545 s->print_cr("l%d = 0x%.16lx", j, l[j]); 1546 s->cr(); 1547 1548 for ( j = 0; j < 8; ++j ) 1549 if ( j != 6 ) s->print_cr("o%d = 0x%.16lx", j, o[j]); 1550 else s->print_cr( "sp = 0x%.16lx", o[j]); 1551 s->cr(); 1552 1553 for ( j = 0; j < 8; ++j ) 1554 s->print_cr("g%d = 0x%.16lx", j, g[j]); 1555 s->cr(); 1556 1557 // print out floats with compression 1558 for (j = 0; j < 32; ) { 1559 jfloat val = f[j]; 1560 int last = j; 1561 for ( ; last+1 < 32; ++last ) { 1562 char b1[1024], b2[1024]; 1563 sprintf(b1, "%f", val); 1564 sprintf(b2, "%f", f[last+1]); 1565 if (strcmp(b1, b2)) 1566 break; 1567 } 1568 s->print("f%d", j); 1569 if ( j != last ) s->print(" - f%d", last); 1570 s->print(" = %f", val); 1571 s->fill_to(25); 1572 s->print_cr(" (0x%x)", val); 1573 j = last + 1; 1574 } 1575 s->cr(); 1576 1577 // and doubles (evens only) 1578 for (j = 0; j < 32; ) { 1579 jdouble val = d[j]; 1580 int last = j; 1581 for ( ; last+1 < 32; ++last ) { 1582 char b1[1024], b2[1024]; 1583 sprintf(b1, "%f", val); 1584 sprintf(b2, "%f", d[last+1]); 1585 if (strcmp(b1, b2)) 1586 break; 1587 } 1588 s->print("d%d", 2 * j); 1589 if ( j != last ) s->print(" - d%d", last); 1590 s->print(" = %f", val); 1591 s->fill_to(30); 1592 s->print("(0x%x)", *(int*)&val); 1593 s->fill_to(42); 1594 s->print_cr("(0x%x)", *(1 + (int*)&val)); 1595 j = last + 1; 1596 } 1597 s->cr(); 1598} 1599 1600void RegistersForDebugging::save_registers(MacroAssembler* a) { 1601 a->sub(FP, round_to(sizeof(RegistersForDebugging), sizeof(jdouble)) - STACK_BIAS, O0); 1602 a->flush_windows(); 1603 int i; 1604 for (i = 0; i < 8; ++i) { 1605 a->ld_ptr(as_iRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, i_offset(i)); 1606 a->ld_ptr(as_lRegister(i)->address_in_saved_window().after_save(), L1); a->st_ptr( L1, O0, l_offset(i)); 1607 a->st_ptr(as_oRegister(i)->after_save(), O0, o_offset(i)); 1608 a->st_ptr(as_gRegister(i)->after_save(), O0, g_offset(i)); 1609 } 1610 for (i = 0; i < 32; ++i) { 1611 a->stf(FloatRegisterImpl::S, as_FloatRegister(i), O0, f_offset(i)); 1612 } 1613 for (i = 0; i < (VM_Version::v9_instructions_work() ? 64 : 32); i += 2) { 1614 a->stf(FloatRegisterImpl::D, as_FloatRegister(i), O0, d_offset(i)); 1615 } 1616} 1617 1618void RegistersForDebugging::restore_registers(MacroAssembler* a, Register r) { 1619 for (int i = 1; i < 8; ++i) { 1620 a->ld_ptr(r, g_offset(i), as_gRegister(i)); 1621 } 1622 for (int j = 0; j < 32; ++j) { 1623 a->ldf(FloatRegisterImpl::S, O0, f_offset(j), as_FloatRegister(j)); 1624 } 1625 for (int k = 0; k < (VM_Version::v9_instructions_work() ? 64 : 32); k += 2) { 1626 a->ldf(FloatRegisterImpl::D, O0, d_offset(k), as_FloatRegister(k)); 1627 } 1628} 1629 1630 1631// pushes double TOS element of FPU stack on CPU stack; pops from FPU stack 1632void MacroAssembler::push_fTOS() { 1633 // %%%%%% need to implement this 1634} 1635 1636// pops double TOS element from CPU stack and pushes on FPU stack 1637void MacroAssembler::pop_fTOS() { 1638 // %%%%%% need to implement this 1639} 1640 1641void MacroAssembler::empty_FPU_stack() { 1642 // %%%%%% need to implement this 1643} 1644 1645void MacroAssembler::_verify_oop(Register reg, const char* msg, const char * file, int line) { 1646 // plausibility check for oops 1647 if (!VerifyOops) return; 1648 1649 if (reg == G0) return; // always NULL, which is always an oop 1650 1651 char buffer[16]; 1652 sprintf(buffer, "%d", line); 1653 int len = strlen(file) + strlen(msg) + 1 + 4 + strlen(buffer); 1654 char * real_msg = new char[len]; 1655 sprintf(real_msg, "%s (%s:%d)", msg, file, line); 1656 1657 // Call indirectly to solve generation ordering problem 1658 Address a(O7, (address)StubRoutines::verify_oop_subroutine_entry_address()); 1659 1660 // Make some space on stack above the current register window. 1661 // Enough to hold 8 64-bit registers. 1662 add(SP,-8*8,SP); 1663 1664 // Save some 64-bit registers; a normal 'save' chops the heads off 1665 // of 64-bit longs in the 32-bit build. 1666 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); 1667 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); 1668 mov(reg,O0); // Move arg into O0; arg might be in O7 which is about to be crushed 1669 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); 1670 1671 set((intptr_t)real_msg, O1); 1672 // Load address to call to into O7 1673 load_ptr_contents(a, O7); 1674 // Register call to verify_oop_subroutine 1675 callr(O7, G0); 1676 delayed()->nop(); 1677 // recover frame size 1678 add(SP, 8*8,SP); 1679} 1680 1681void MacroAssembler::_verify_oop_addr(Address addr, const char* msg, const char * file, int line) { 1682 // plausibility check for oops 1683 if (!VerifyOops) return; 1684 1685 char buffer[64]; 1686 sprintf(buffer, "%d", line); 1687 int len = strlen(file) + strlen(msg) + 1 + 4 + strlen(buffer); 1688 sprintf(buffer, " at SP+%d ", addr.disp()); 1689 len += strlen(buffer); 1690 char * real_msg = new char[len]; 1691 sprintf(real_msg, "%s at SP+%d (%s:%d)", msg, addr.disp(), file, line); 1692 1693 // Call indirectly to solve generation ordering problem 1694 Address a(O7, (address)StubRoutines::verify_oop_subroutine_entry_address()); 1695 1696 // Make some space on stack above the current register window. 1697 // Enough to hold 8 64-bit registers. 1698 add(SP,-8*8,SP); 1699 1700 // Save some 64-bit registers; a normal 'save' chops the heads off 1701 // of 64-bit longs in the 32-bit build. 1702 stx(O0,SP,frame::register_save_words*wordSize+STACK_BIAS+0*8); 1703 stx(O1,SP,frame::register_save_words*wordSize+STACK_BIAS+1*8); 1704 ld_ptr(addr.base(), addr.disp() + 8*8, O0); // Load arg into O0; arg might be in O7 which is about to be crushed 1705 stx(O7,SP,frame::register_save_words*wordSize+STACK_BIAS+7*8); 1706 1707 set((intptr_t)real_msg, O1); 1708 // Load address to call to into O7 1709 load_ptr_contents(a, O7); 1710 // Register call to verify_oop_subroutine 1711 callr(O7, G0); 1712 delayed()->nop(); 1713 // recover frame size 1714 add(SP, 8*8,SP); 1715} 1716 1717// side-door communication with signalHandler in os_solaris.cpp 1718address MacroAssembler::_verify_oop_implicit_branch[3] = { NULL }; 1719 1720// This macro is expanded just once; it creates shared code. Contract: 1721// receives an oop in O0. Must restore O0 & O7 from TLS. Must not smash ANY 1722// registers, including flags. May not use a register 'save', as this blows 1723// the high bits of the O-regs if they contain Long values. Acts as a 'leaf' 1724// call. 1725void MacroAssembler::verify_oop_subroutine() { 1726 assert( VM_Version::v9_instructions_work(), "VerifyOops not supported for V8" ); 1727 1728 // Leaf call; no frame. 1729 Label succeed, fail, null_or_fail; 1730 1731 // O0 and O7 were saved already (O0 in O0's TLS home, O7 in O5's TLS home). 1732 // O0 is now the oop to be checked. O7 is the return address. 1733 Register O0_obj = O0; 1734 1735 // Save some more registers for temps. 1736 stx(O2,SP,frame::register_save_words*wordSize+STACK_BIAS+2*8); 1737 stx(O3,SP,frame::register_save_words*wordSize+STACK_BIAS+3*8); 1738 stx(O4,SP,frame::register_save_words*wordSize+STACK_BIAS+4*8); 1739 stx(O5,SP,frame::register_save_words*wordSize+STACK_BIAS+5*8); 1740 1741 // Save flags 1742 Register O5_save_flags = O5; 1743 rdccr( O5_save_flags ); 1744 1745 { // count number of verifies 1746 Register O2_adr = O2; 1747 Register O3_accum = O3; 1748 Address count_addr( O2_adr, (address) StubRoutines::verify_oop_count_addr() ); 1749 sethi(count_addr); 1750 ld(count_addr, O3_accum); 1751 inc(O3_accum); 1752 st(O3_accum, count_addr); 1753 } 1754 1755 Register O2_mask = O2; 1756 Register O3_bits = O3; 1757 Register O4_temp = O4; 1758 1759 // mark lower end of faulting range 1760 assert(_verify_oop_implicit_branch[0] == NULL, "set once"); 1761 _verify_oop_implicit_branch[0] = pc(); 1762 1763 // We can't check the mark oop because it could be in the process of 1764 // locking or unlocking while this is running. 1765 set(Universe::verify_oop_mask (), O2_mask); 1766 set(Universe::verify_oop_bits (), O3_bits); 1767 1768 // assert((obj & oop_mask) == oop_bits); 1769 and3(O0_obj, O2_mask, O4_temp); 1770 cmp(O4_temp, O3_bits); 1771 brx(notEqual, false, pn, null_or_fail); 1772 delayed()->nop(); 1773 1774 if ((NULL_WORD & Universe::verify_oop_mask()) == Universe::verify_oop_bits()) { 1775 // the null_or_fail case is useless; must test for null separately 1776 br_null(O0_obj, false, pn, succeed); 1777 delayed()->nop(); 1778 } 1779 1780 // Check the klassOop of this object for being in the right area of memory. 1781 // Cannot do the load in the delay above slot in case O0 is null 1782 load_klass(O0_obj, O0_obj); 1783 // assert((klass & klass_mask) == klass_bits); 1784 if( Universe::verify_klass_mask() != Universe::verify_oop_mask() ) 1785 set(Universe::verify_klass_mask(), O2_mask); 1786 if( Universe::verify_klass_bits() != Universe::verify_oop_bits() ) 1787 set(Universe::verify_klass_bits(), O3_bits); 1788 and3(O0_obj, O2_mask, O4_temp); 1789 cmp(O4_temp, O3_bits); 1790 brx(notEqual, false, pn, fail); 1791 delayed()->nop(); 1792 // Check the klass's klass 1793 load_klass(O0_obj, O0_obj); 1794 and3(O0_obj, O2_mask, O4_temp); 1795 cmp(O4_temp, O3_bits); 1796 brx(notEqual, false, pn, fail); 1797 delayed()->wrccr( O5_save_flags ); // Restore CCR's 1798 1799 // mark upper end of faulting range 1800 _verify_oop_implicit_branch[1] = pc(); 1801 1802 //----------------------- 1803 // all tests pass 1804 bind(succeed); 1805 1806 // Restore prior 64-bit registers 1807 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+0*8,O0); 1808 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+1*8,O1); 1809 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+2*8,O2); 1810 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+3*8,O3); 1811 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+4*8,O4); 1812 ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+5*8,O5); 1813 1814 retl(); // Leaf return; restore prior O7 in delay slot 1815 delayed()->ldx(SP,frame::register_save_words*wordSize+STACK_BIAS+7*8,O7); 1816 1817 //----------------------- 1818 bind(null_or_fail); // nulls are less common but OK 1819 br_null(O0_obj, false, pt, succeed); 1820 delayed()->wrccr( O5_save_flags ); // Restore CCR's 1821 1822 //----------------------- 1823 // report failure: 1824 bind(fail); 1825 _verify_oop_implicit_branch[2] = pc(); 1826 1827 wrccr( O5_save_flags ); // Restore CCR's 1828 1829 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); 1830 1831 // stop_subroutine expects message pointer in I1. 1832 mov(I1, O1); 1833 1834 // Restore prior 64-bit registers 1835 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+0*8,I0); 1836 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+1*8,I1); 1837 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+2*8,I2); 1838 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+3*8,I3); 1839 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+4*8,I4); 1840 ldx(FP,frame::register_save_words*wordSize+STACK_BIAS+5*8,I5); 1841 1842 // factor long stop-sequence into subroutine to save space 1843 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); 1844 1845 // call indirectly to solve generation ordering problem 1846 Address a(O5, (address)StubRoutines::Sparc::stop_subroutine_entry_address()); 1847 load_ptr_contents(a, O5); 1848 jmpl(O5, 0, O7); 1849 delayed()->nop(); 1850} 1851 1852 1853void MacroAssembler::stop(const char* msg) { 1854 // save frame first to get O7 for return address 1855 // add one word to size in case struct is odd number of words long 1856 // It must be doubleword-aligned for storing doubles into it. 1857 1858 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); 1859 1860 // stop_subroutine expects message pointer in I1. 1861 set((intptr_t)msg, O1); 1862 1863 // factor long stop-sequence into subroutine to save space 1864 assert(StubRoutines::Sparc::stop_subroutine_entry_address(), "hasn't been generated yet"); 1865 1866 // call indirectly to solve generation ordering problem 1867 Address a(O5, (address)StubRoutines::Sparc::stop_subroutine_entry_address()); 1868 load_ptr_contents(a, O5); 1869 jmpl(O5, 0, O7); 1870 delayed()->nop(); 1871 1872 breakpoint_trap(); // make stop actually stop rather than writing 1873 // unnoticeable results in the output files. 1874 1875 // restore(); done in callee to save space! 1876} 1877 1878 1879void MacroAssembler::warn(const char* msg) { 1880 save_frame(::round_to(sizeof(RegistersForDebugging) / BytesPerWord, 2)); 1881 RegistersForDebugging::save_registers(this); 1882 mov(O0, L0); 1883 set((intptr_t)msg, O0); 1884 call( CAST_FROM_FN_PTR(address, warning) ); 1885 delayed()->nop(); 1886// ret(); 1887// delayed()->restore(); 1888 RegistersForDebugging::restore_registers(this, L0); 1889 restore(); 1890} 1891 1892 1893void MacroAssembler::untested(const char* what) { 1894 // We must be able to turn interactive prompting off 1895 // in order to run automated test scripts on the VM 1896 // Use the flag ShowMessageBoxOnError 1897 1898 char* b = new char[1024]; 1899 sprintf(b, "untested: %s", what); 1900 1901 if ( ShowMessageBoxOnError ) stop(b); 1902 else warn(b); 1903} 1904 1905 1906void MacroAssembler::stop_subroutine() { 1907 RegistersForDebugging::save_registers(this); 1908 1909 // for the sake of the debugger, stick a PC on the current frame 1910 // (this assumes that the caller has performed an extra "save") 1911 mov(I7, L7); 1912 add(O7, -7 * BytesPerInt, I7); 1913 1914 save_frame(); // one more save to free up another O7 register 1915 mov(I0, O1); // addr of reg save area 1916 1917 // We expect pointer to message in I1. Caller must set it up in O1 1918 mov(I1, O0); // get msg 1919 call (CAST_FROM_FN_PTR(address, MacroAssembler::debug), relocInfo::runtime_call_type); 1920 delayed()->nop(); 1921 1922 restore(); 1923 1924 RegistersForDebugging::restore_registers(this, O0); 1925 1926 save_frame(0); 1927 call(CAST_FROM_FN_PTR(address,breakpoint)); 1928 delayed()->nop(); 1929 restore(); 1930 1931 mov(L7, I7); 1932 retl(); 1933 delayed()->restore(); // see stop above 1934} 1935 1936 1937void MacroAssembler::debug(char* msg, RegistersForDebugging* regs) { 1938 if ( ShowMessageBoxOnError ) { 1939 JavaThreadState saved_state = JavaThread::current()->thread_state(); 1940 JavaThread::current()->set_thread_state(_thread_in_vm); 1941 { 1942 // In order to get locks work, we need to fake a in_VM state 1943 ttyLocker ttyl; 1944 ::tty->print_cr("EXECUTION STOPPED: %s\n", msg); 1945 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 1946 ::tty->print_cr("Interpreter::bytecode_counter = %d", BytecodeCounter::counter_value()); 1947 } 1948 if (os::message_box(msg, "Execution stopped, print registers?")) 1949 regs->print(::tty); 1950 } 1951 ThreadStateTransition::transition(JavaThread::current(), _thread_in_vm, saved_state); 1952 } 1953 else 1954 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 1955 assert(false, "error"); 1956} 1957 1958 1959#ifndef PRODUCT 1960void MacroAssembler::test() { 1961 ResourceMark rm; 1962 1963 CodeBuffer cb("test", 10000, 10000); 1964 MacroAssembler* a = new MacroAssembler(&cb); 1965 VM_Version::allow_all(); 1966 a->test_v9(); 1967 a->test_v8_onlys(); 1968 VM_Version::revert(); 1969 1970 StubRoutines::Sparc::test_stop_entry()(); 1971} 1972#endif 1973 1974 1975void MacroAssembler::calc_mem_param_words(Register Rparam_words, Register Rresult) { 1976 subcc( Rparam_words, Argument::n_register_parameters, Rresult); // how many mem words? 1977 Label no_extras; 1978 br( negative, true, pt, no_extras ); // if neg, clear reg 1979 delayed()->set( 0, Rresult); // annuled, so only if taken 1980 bind( no_extras ); 1981} 1982 1983 1984void MacroAssembler::calc_frame_size(Register Rextra_words, Register Rresult) { 1985#ifdef _LP64 1986 add(Rextra_words, frame::memory_parameter_word_sp_offset, Rresult); 1987#else 1988 add(Rextra_words, frame::memory_parameter_word_sp_offset + 1, Rresult); 1989#endif 1990 bclr(1, Rresult); 1991 sll(Rresult, LogBytesPerWord, Rresult); // Rresult has total frame bytes 1992} 1993 1994 1995void MacroAssembler::calc_frame_size_and_save(Register Rextra_words, Register Rresult) { 1996 calc_frame_size(Rextra_words, Rresult); 1997 neg(Rresult); 1998 save(SP, Rresult, SP); 1999} 2000 2001 2002// --------------------------------------------------------- 2003Assembler::RCondition cond2rcond(Assembler::Condition c) { 2004 switch (c) { 2005 /*case zero: */ 2006 case Assembler::equal: return Assembler::rc_z; 2007 case Assembler::lessEqual: return Assembler::rc_lez; 2008 case Assembler::less: return Assembler::rc_lz; 2009 /*case notZero:*/ 2010 case Assembler::notEqual: return Assembler::rc_nz; 2011 case Assembler::greater: return Assembler::rc_gz; 2012 case Assembler::greaterEqual: return Assembler::rc_gez; 2013 } 2014 ShouldNotReachHere(); 2015 return Assembler::rc_z; 2016} 2017 2018// compares register with zero and branches. NOT FOR USE WITH 64-bit POINTERS 2019void MacroAssembler::br_zero( Condition c, bool a, Predict p, Register s1, Label& L) { 2020 tst(s1); 2021 br (c, a, p, L); 2022} 2023 2024 2025// Compares a pointer register with zero and branches on null. 2026// Does a test & branch on 32-bit systems and a register-branch on 64-bit. 2027void MacroAssembler::br_null( Register s1, bool a, Predict p, Label& L ) { 2028 assert_not_delayed(); 2029#ifdef _LP64 2030 bpr( rc_z, a, p, s1, L ); 2031#else 2032 tst(s1); 2033 br ( zero, a, p, L ); 2034#endif 2035} 2036 2037void MacroAssembler::br_notnull( Register s1, bool a, Predict p, Label& L ) { 2038 assert_not_delayed(); 2039#ifdef _LP64 2040 bpr( rc_nz, a, p, s1, L ); 2041#else 2042 tst(s1); 2043 br ( notZero, a, p, L ); 2044#endif 2045} 2046 2047 2048// instruction sequences factored across compiler & interpreter 2049 2050 2051void MacroAssembler::lcmp( Register Ra_hi, Register Ra_low, 2052 Register Rb_hi, Register Rb_low, 2053 Register Rresult) { 2054 2055 Label check_low_parts, done; 2056 2057 cmp(Ra_hi, Rb_hi ); // compare hi parts 2058 br(equal, true, pt, check_low_parts); 2059 delayed()->cmp(Ra_low, Rb_low); // test low parts 2060 2061 // And, with an unsigned comparison, it does not matter if the numbers 2062 // are negative or not. 2063 // E.g., -2 cmp -1: the low parts are 0xfffffffe and 0xffffffff. 2064 // The second one is bigger (unsignedly). 2065 2066 // Other notes: The first move in each triplet can be unconditional 2067 // (and therefore probably prefetchable). 2068 // And the equals case for the high part does not need testing, 2069 // since that triplet is reached only after finding the high halves differ. 2070 2071 if (VM_Version::v9_instructions_work()) { 2072 2073 mov ( -1, Rresult); 2074 ba( false, done ); delayed()-> movcc(greater, false, icc, 1, Rresult); 2075 } 2076 else { 2077 br(less, true, pt, done); delayed()-> set(-1, Rresult); 2078 br(greater, true, pt, done); delayed()-> set( 1, Rresult); 2079 } 2080 2081 bind( check_low_parts ); 2082 2083 if (VM_Version::v9_instructions_work()) { 2084 mov( -1, Rresult); 2085 movcc(equal, false, icc, 0, Rresult); 2086 movcc(greaterUnsigned, false, icc, 1, Rresult); 2087 } 2088 else { 2089 set(-1, Rresult); 2090 br(equal, true, pt, done); delayed()->set( 0, Rresult); 2091 br(greaterUnsigned, true, pt, done); delayed()->set( 1, Rresult); 2092 } 2093 bind( done ); 2094} 2095 2096void MacroAssembler::lneg( Register Rhi, Register Rlow ) { 2097 subcc( G0, Rlow, Rlow ); 2098 subc( G0, Rhi, Rhi ); 2099} 2100 2101void MacroAssembler::lshl( Register Rin_high, Register Rin_low, 2102 Register Rcount, 2103 Register Rout_high, Register Rout_low, 2104 Register Rtemp ) { 2105 2106 2107 Register Ralt_count = Rtemp; 2108 Register Rxfer_bits = Rtemp; 2109 2110 assert( Ralt_count != Rin_high 2111 && Ralt_count != Rin_low 2112 && Ralt_count != Rcount 2113 && Rxfer_bits != Rin_low 2114 && Rxfer_bits != Rin_high 2115 && Rxfer_bits != Rcount 2116 && Rxfer_bits != Rout_low 2117 && Rout_low != Rin_high, 2118 "register alias checks"); 2119 2120 Label big_shift, done; 2121 2122 // This code can be optimized to use the 64 bit shifts in V9. 2123 // Here we use the 32 bit shifts. 2124 2125 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits 2126 subcc(Rcount, 31, Ralt_count); 2127 br(greater, true, pn, big_shift); 2128 delayed()-> 2129 dec(Ralt_count); 2130 2131 // shift < 32 bits, Ralt_count = Rcount-31 2132 2133 // We get the transfer bits by shifting right by 32-count the low 2134 // register. This is done by shifting right by 31-count and then by one 2135 // more to take care of the special (rare) case where count is zero 2136 // (shifting by 32 would not work). 2137 2138 neg( Ralt_count ); 2139 2140 // The order of the next two instructions is critical in the case where 2141 // Rin and Rout are the same and should not be reversed. 2142 2143 srl( Rin_low, Ralt_count, Rxfer_bits ); // shift right by 31-count 2144 if (Rcount != Rout_low) { 2145 sll( Rin_low, Rcount, Rout_low ); // low half 2146 } 2147 sll( Rin_high, Rcount, Rout_high ); 2148 if (Rcount == Rout_low) { 2149 sll( Rin_low, Rcount, Rout_low ); // low half 2150 } 2151 srl( Rxfer_bits, 1, Rxfer_bits ); // shift right by one more 2152 ba (false, done); 2153 delayed()-> 2154 or3( Rout_high, Rxfer_bits, Rout_high); // new hi value: or in shifted old hi part and xfer from low 2155 2156 // shift >= 32 bits, Ralt_count = Rcount-32 2157 bind(big_shift); 2158 sll( Rin_low, Ralt_count, Rout_high ); 2159 clr( Rout_low ); 2160 2161 bind(done); 2162} 2163 2164 2165void MacroAssembler::lshr( Register Rin_high, Register Rin_low, 2166 Register Rcount, 2167 Register Rout_high, Register Rout_low, 2168 Register Rtemp ) { 2169 2170 Register Ralt_count = Rtemp; 2171 Register Rxfer_bits = Rtemp; 2172 2173 assert( Ralt_count != Rin_high 2174 && Ralt_count != Rin_low 2175 && Ralt_count != Rcount 2176 && Rxfer_bits != Rin_low 2177 && Rxfer_bits != Rin_high 2178 && Rxfer_bits != Rcount 2179 && Rxfer_bits != Rout_high 2180 && Rout_high != Rin_low, 2181 "register alias checks"); 2182 2183 Label big_shift, done; 2184 2185 // This code can be optimized to use the 64 bit shifts in V9. 2186 // Here we use the 32 bit shifts. 2187 2188 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits 2189 subcc(Rcount, 31, Ralt_count); 2190 br(greater, true, pn, big_shift); 2191 delayed()->dec(Ralt_count); 2192 2193 // shift < 32 bits, Ralt_count = Rcount-31 2194 2195 // We get the transfer bits by shifting left by 32-count the high 2196 // register. This is done by shifting left by 31-count and then by one 2197 // more to take care of the special (rare) case where count is zero 2198 // (shifting by 32 would not work). 2199 2200 neg( Ralt_count ); 2201 if (Rcount != Rout_low) { 2202 srl( Rin_low, Rcount, Rout_low ); 2203 } 2204 2205 // The order of the next two instructions is critical in the case where 2206 // Rin and Rout are the same and should not be reversed. 2207 2208 sll( Rin_high, Ralt_count, Rxfer_bits ); // shift left by 31-count 2209 sra( Rin_high, Rcount, Rout_high ); // high half 2210 sll( Rxfer_bits, 1, Rxfer_bits ); // shift left by one more 2211 if (Rcount == Rout_low) { 2212 srl( Rin_low, Rcount, Rout_low ); 2213 } 2214 ba (false, done); 2215 delayed()-> 2216 or3( Rout_low, Rxfer_bits, Rout_low ); // new low value: or shifted old low part and xfer from high 2217 2218 // shift >= 32 bits, Ralt_count = Rcount-32 2219 bind(big_shift); 2220 2221 sra( Rin_high, Ralt_count, Rout_low ); 2222 sra( Rin_high, 31, Rout_high ); // sign into hi 2223 2224 bind( done ); 2225} 2226 2227 2228 2229void MacroAssembler::lushr( Register Rin_high, Register Rin_low, 2230 Register Rcount, 2231 Register Rout_high, Register Rout_low, 2232 Register Rtemp ) { 2233 2234 Register Ralt_count = Rtemp; 2235 Register Rxfer_bits = Rtemp; 2236 2237 assert( Ralt_count != Rin_high 2238 && Ralt_count != Rin_low 2239 && Ralt_count != Rcount 2240 && Rxfer_bits != Rin_low 2241 && Rxfer_bits != Rin_high 2242 && Rxfer_bits != Rcount 2243 && Rxfer_bits != Rout_high 2244 && Rout_high != Rin_low, 2245 "register alias checks"); 2246 2247 Label big_shift, done; 2248 2249 // This code can be optimized to use the 64 bit shifts in V9. 2250 // Here we use the 32 bit shifts. 2251 2252 and3( Rcount, 0x3f, Rcount); // take least significant 6 bits 2253 subcc(Rcount, 31, Ralt_count); 2254 br(greater, true, pn, big_shift); 2255 delayed()->dec(Ralt_count); 2256 2257 // shift < 32 bits, Ralt_count = Rcount-31 2258 2259 // We get the transfer bits by shifting left by 32-count the high 2260 // register. This is done by shifting left by 31-count and then by one 2261 // more to take care of the special (rare) case where count is zero 2262 // (shifting by 32 would not work). 2263 2264 neg( Ralt_count ); 2265 if (Rcount != Rout_low) { 2266 srl( Rin_low, Rcount, Rout_low ); 2267 } 2268 2269 // The order of the next two instructions is critical in the case where 2270 // Rin and Rout are the same and should not be reversed. 2271 2272 sll( Rin_high, Ralt_count, Rxfer_bits ); // shift left by 31-count 2273 srl( Rin_high, Rcount, Rout_high ); // high half 2274 sll( Rxfer_bits, 1, Rxfer_bits ); // shift left by one more 2275 if (Rcount == Rout_low) { 2276 srl( Rin_low, Rcount, Rout_low ); 2277 } 2278 ba (false, done); 2279 delayed()-> 2280 or3( Rout_low, Rxfer_bits, Rout_low ); // new low value: or shifted old low part and xfer from high 2281 2282 // shift >= 32 bits, Ralt_count = Rcount-32 2283 bind(big_shift); 2284 2285 srl( Rin_high, Ralt_count, Rout_low ); 2286 clr( Rout_high ); 2287 2288 bind( done ); 2289} 2290 2291#ifdef _LP64 2292void MacroAssembler::lcmp( Register Ra, Register Rb, Register Rresult) { 2293 cmp(Ra, Rb); 2294 mov( -1, Rresult); 2295 movcc(equal, false, xcc, 0, Rresult); 2296 movcc(greater, false, xcc, 1, Rresult); 2297} 2298#endif 2299 2300 2301void MacroAssembler::float_cmp( bool is_float, int unordered_result, 2302 FloatRegister Fa, FloatRegister Fb, 2303 Register Rresult) { 2304 2305 fcmp(is_float ? FloatRegisterImpl::S : FloatRegisterImpl::D, fcc0, Fa, Fb); 2306 2307 Condition lt = unordered_result == -1 ? f_unorderedOrLess : f_less; 2308 Condition eq = f_equal; 2309 Condition gt = unordered_result == 1 ? f_unorderedOrGreater : f_greater; 2310 2311 if (VM_Version::v9_instructions_work()) { 2312 2313 mov( -1, Rresult ); 2314 movcc( eq, true, fcc0, 0, Rresult ); 2315 movcc( gt, true, fcc0, 1, Rresult ); 2316 2317 } else { 2318 Label done; 2319 2320 set( -1, Rresult ); 2321 //fb(lt, true, pn, done); delayed()->set( -1, Rresult ); 2322 fb( eq, true, pn, done); delayed()->set( 0, Rresult ); 2323 fb( gt, true, pn, done); delayed()->set( 1, Rresult ); 2324 2325 bind (done); 2326 } 2327} 2328 2329 2330void MacroAssembler::fneg( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) 2331{ 2332 if (VM_Version::v9_instructions_work()) { 2333 Assembler::fneg(w, s, d); 2334 } else { 2335 if (w == FloatRegisterImpl::S) { 2336 Assembler::fneg(w, s, d); 2337 } else if (w == FloatRegisterImpl::D) { 2338 // number() does a sanity check on the alignment. 2339 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && 2340 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); 2341 2342 Assembler::fneg(FloatRegisterImpl::S, s, d); 2343 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); 2344 } else { 2345 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); 2346 2347 // number() does a sanity check on the alignment. 2348 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && 2349 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); 2350 2351 Assembler::fneg(FloatRegisterImpl::S, s, d); 2352 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); 2353 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); 2354 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); 2355 } 2356 } 2357} 2358 2359void MacroAssembler::fmov( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) 2360{ 2361 if (VM_Version::v9_instructions_work()) { 2362 Assembler::fmov(w, s, d); 2363 } else { 2364 if (w == FloatRegisterImpl::S) { 2365 Assembler::fmov(w, s, d); 2366 } else if (w == FloatRegisterImpl::D) { 2367 // number() does a sanity check on the alignment. 2368 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && 2369 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); 2370 2371 Assembler::fmov(FloatRegisterImpl::S, s, d); 2372 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); 2373 } else { 2374 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); 2375 2376 // number() does a sanity check on the alignment. 2377 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && 2378 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); 2379 2380 Assembler::fmov(FloatRegisterImpl::S, s, d); 2381 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); 2382 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); 2383 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); 2384 } 2385 } 2386} 2387 2388void MacroAssembler::fabs( FloatRegisterImpl::Width w, FloatRegister s, FloatRegister d) 2389{ 2390 if (VM_Version::v9_instructions_work()) { 2391 Assembler::fabs(w, s, d); 2392 } else { 2393 if (w == FloatRegisterImpl::S) { 2394 Assembler::fabs(w, s, d); 2395 } else if (w == FloatRegisterImpl::D) { 2396 // number() does a sanity check on the alignment. 2397 assert(((s->encoding(FloatRegisterImpl::D) & 1) == 0) && 2398 ((d->encoding(FloatRegisterImpl::D) & 1) == 0), "float register alignment check"); 2399 2400 Assembler::fabs(FloatRegisterImpl::S, s, d); 2401 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); 2402 } else { 2403 assert(w == FloatRegisterImpl::Q, "Invalid float register width"); 2404 2405 // number() does a sanity check on the alignment. 2406 assert(((s->encoding(FloatRegisterImpl::D) & 3) == 0) && 2407 ((d->encoding(FloatRegisterImpl::D) & 3) == 0), "float register alignment check"); 2408 2409 Assembler::fabs(FloatRegisterImpl::S, s, d); 2410 Assembler::fmov(FloatRegisterImpl::S, s->successor(), d->successor()); 2411 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor(), d->successor()->successor()); 2412 Assembler::fmov(FloatRegisterImpl::S, s->successor()->successor()->successor(), d->successor()->successor()->successor()); 2413 } 2414 } 2415} 2416 2417void MacroAssembler::save_all_globals_into_locals() { 2418 mov(G1,L1); 2419 mov(G2,L2); 2420 mov(G3,L3); 2421 mov(G4,L4); 2422 mov(G5,L5); 2423 mov(G6,L6); 2424 mov(G7,L7); 2425} 2426 2427void MacroAssembler::restore_globals_from_locals() { 2428 mov(L1,G1); 2429 mov(L2,G2); 2430 mov(L3,G3); 2431 mov(L4,G4); 2432 mov(L5,G5); 2433 mov(L6,G6); 2434 mov(L7,G7); 2435} 2436 2437// Use for 64 bit operation. 2438void MacroAssembler::casx_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm) 2439{ 2440 // store ptr_reg as the new top value 2441#ifdef _LP64 2442 casx(top_ptr_reg, top_reg, ptr_reg); 2443#else 2444 cas_under_lock(top_ptr_reg, top_reg, ptr_reg, lock_addr, use_call_vm); 2445#endif // _LP64 2446} 2447 2448// [RGV] This routine does not handle 64 bit operations. 2449// use casx_under_lock() or casx directly!!! 2450void MacroAssembler::cas_under_lock(Register top_ptr_reg, Register top_reg, Register ptr_reg, address lock_addr, bool use_call_vm) 2451{ 2452 // store ptr_reg as the new top value 2453 if (VM_Version::v9_instructions_work()) { 2454 cas(top_ptr_reg, top_reg, ptr_reg); 2455 } else { 2456 2457 // If the register is not an out nor global, it is not visible 2458 // after the save. Allocate a register for it, save its 2459 // value in the register save area (the save may not flush 2460 // registers to the save area). 2461 2462 Register top_ptr_reg_after_save; 2463 Register top_reg_after_save; 2464 Register ptr_reg_after_save; 2465 2466 if (top_ptr_reg->is_out() || top_ptr_reg->is_global()) { 2467 top_ptr_reg_after_save = top_ptr_reg->after_save(); 2468 } else { 2469 Address reg_save_addr = top_ptr_reg->address_in_saved_window(); 2470 top_ptr_reg_after_save = L0; 2471 st(top_ptr_reg, reg_save_addr); 2472 } 2473 2474 if (top_reg->is_out() || top_reg->is_global()) { 2475 top_reg_after_save = top_reg->after_save(); 2476 } else { 2477 Address reg_save_addr = top_reg->address_in_saved_window(); 2478 top_reg_after_save = L1; 2479 st(top_reg, reg_save_addr); 2480 } 2481 2482 if (ptr_reg->is_out() || ptr_reg->is_global()) { 2483 ptr_reg_after_save = ptr_reg->after_save(); 2484 } else { 2485 Address reg_save_addr = ptr_reg->address_in_saved_window(); 2486 ptr_reg_after_save = L2; 2487 st(ptr_reg, reg_save_addr); 2488 } 2489 2490 const Register& lock_reg = L3; 2491 const Register& lock_ptr_reg = L4; 2492 const Register& value_reg = L5; 2493 const Register& yield_reg = L6; 2494 const Register& yieldall_reg = L7; 2495 2496 save_frame(); 2497 2498 if (top_ptr_reg_after_save == L0) { 2499 ld(top_ptr_reg->address_in_saved_window().after_save(), top_ptr_reg_after_save); 2500 } 2501 2502 if (top_reg_after_save == L1) { 2503 ld(top_reg->address_in_saved_window().after_save(), top_reg_after_save); 2504 } 2505 2506 if (ptr_reg_after_save == L2) { 2507 ld(ptr_reg->address_in_saved_window().after_save(), ptr_reg_after_save); 2508 } 2509 2510 Label(retry_get_lock); 2511 Label(not_same); 2512 Label(dont_yield); 2513 2514 assert(lock_addr, "lock_address should be non null for v8"); 2515 set((intptr_t)lock_addr, lock_ptr_reg); 2516 // Initialize yield counter 2517 mov(G0,yield_reg); 2518 mov(G0, yieldall_reg); 2519 set(StubRoutines::Sparc::locked, lock_reg); 2520 2521 bind(retry_get_lock); 2522 cmp(yield_reg, V8AtomicOperationUnderLockSpinCount); 2523 br(Assembler::less, false, Assembler::pt, dont_yield); 2524 delayed()->nop(); 2525 2526 if(use_call_vm) { 2527 Untested("Need to verify global reg consistancy"); 2528 call_VM(noreg, CAST_FROM_FN_PTR(address, SharedRuntime::yield_all), yieldall_reg); 2529 } else { 2530 // Save the regs and make space for a C call 2531 save(SP, -96, SP); 2532 save_all_globals_into_locals(); 2533 call(CAST_FROM_FN_PTR(address,os::yield_all)); 2534 delayed()->mov(yieldall_reg, O0); 2535 restore_globals_from_locals(); 2536 restore(); 2537 } 2538 2539 // reset the counter 2540 mov(G0,yield_reg); 2541 add(yieldall_reg, 1, yieldall_reg); 2542 2543 bind(dont_yield); 2544 // try to get lock 2545 swap(lock_ptr_reg, 0, lock_reg); 2546 2547 // did we get the lock? 2548 cmp(lock_reg, StubRoutines::Sparc::unlocked); 2549 br(Assembler::notEqual, true, Assembler::pn, retry_get_lock); 2550 delayed()->add(yield_reg,1,yield_reg); 2551 2552 // yes, got lock. do we have the same top? 2553 ld(top_ptr_reg_after_save, 0, value_reg); 2554 cmp(value_reg, top_reg_after_save); 2555 br(Assembler::notEqual, false, Assembler::pn, not_same); 2556 delayed()->nop(); 2557 2558 // yes, same top. 2559 st(ptr_reg_after_save, top_ptr_reg_after_save, 0); 2560 membar(Assembler::StoreStore); 2561 2562 bind(not_same); 2563 mov(value_reg, ptr_reg_after_save); 2564 st(lock_reg, lock_ptr_reg, 0); // unlock 2565 2566 restore(); 2567 } 2568} 2569 2570void MacroAssembler::biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg, 2571 Label& done, Label* slow_case, 2572 BiasedLockingCounters* counters) { 2573 assert(UseBiasedLocking, "why call this otherwise?"); 2574 2575 if (PrintBiasedLockingStatistics) { 2576 assert_different_registers(obj_reg, mark_reg, temp_reg, O7); 2577 if (counters == NULL) 2578 counters = BiasedLocking::counters(); 2579 } 2580 2581 Label cas_label; 2582 2583 // Biased locking 2584 // See whether the lock is currently biased toward our thread and 2585 // whether the epoch is still valid 2586 // Note that the runtime guarantees sufficient alignment of JavaThread 2587 // pointers to allow age to be placed into low bits 2588 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 2589 and3(mark_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); 2590 cmp(temp_reg, markOopDesc::biased_lock_pattern); 2591 brx(Assembler::notEqual, false, Assembler::pn, cas_label); 2592 delayed()->nop(); 2593 2594 load_klass(obj_reg, temp_reg); 2595 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); 2596 or3(G2_thread, temp_reg, temp_reg); 2597 xor3(mark_reg, temp_reg, temp_reg); 2598 andcc(temp_reg, ~((int) markOopDesc::age_mask_in_place), temp_reg); 2599 if (counters != NULL) { 2600 cond_inc(Assembler::equal, (address) counters->biased_lock_entry_count_addr(), mark_reg, temp_reg); 2601 // Reload mark_reg as we may need it later 2602 ld_ptr(Address(obj_reg, 0, oopDesc::mark_offset_in_bytes()), mark_reg); 2603 } 2604 brx(Assembler::equal, true, Assembler::pt, done); 2605 delayed()->nop(); 2606 2607 Label try_revoke_bias; 2608 Label try_rebias; 2609 Address mark_addr = Address(obj_reg, 0, oopDesc::mark_offset_in_bytes()); 2610 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); 2611 2612 // At this point we know that the header has the bias pattern and 2613 // that we are not the bias owner in the current epoch. We need to 2614 // figure out more details about the state of the header in order to 2615 // know what operations can be legally performed on the object's 2616 // header. 2617 2618 // If the low three bits in the xor result aren't clear, that means 2619 // the prototype header is no longer biased and we have to revoke 2620 // the bias on this object. 2621 btst(markOopDesc::biased_lock_mask_in_place, temp_reg); 2622 brx(Assembler::notZero, false, Assembler::pn, try_revoke_bias); 2623 2624 // Biasing is still enabled for this data type. See whether the 2625 // epoch of the current bias is still valid, meaning that the epoch 2626 // bits of the mark word are equal to the epoch bits of the 2627 // prototype header. (Note that the prototype header's epoch bits 2628 // only change at a safepoint.) If not, attempt to rebias the object 2629 // toward the current thread. Note that we must be absolutely sure 2630 // that the current epoch is invalid in order to do this because 2631 // otherwise the manipulations it performs on the mark word are 2632 // illegal. 2633 delayed()->btst(markOopDesc::epoch_mask_in_place, temp_reg); 2634 brx(Assembler::notZero, false, Assembler::pn, try_rebias); 2635 2636 // The epoch of the current bias is still valid but we know nothing 2637 // about the owner; it might be set or it might be clear. Try to 2638 // acquire the bias of the object using an atomic operation. If this 2639 // fails we will go in to the runtime to revoke the object's bias. 2640 // Note that we first construct the presumed unbiased header so we 2641 // don't accidentally blow away another thread's valid bias. 2642 delayed()->and3(mark_reg, 2643 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place, 2644 mark_reg); 2645 or3(G2_thread, mark_reg, temp_reg); 2646 casx_under_lock(mark_addr.base(), mark_reg, temp_reg, 2647 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); 2648 // If the biasing toward our thread failed, this means that 2649 // another thread succeeded in biasing it toward itself and we 2650 // need to revoke that bias. The revocation will occur in the 2651 // interpreter runtime in the slow case. 2652 cmp(mark_reg, temp_reg); 2653 if (counters != NULL) { 2654 cond_inc(Assembler::zero, (address) counters->anonymously_biased_lock_entry_count_addr(), mark_reg, temp_reg); 2655 } 2656 if (slow_case != NULL) { 2657 brx(Assembler::notEqual, true, Assembler::pn, *slow_case); 2658 delayed()->nop(); 2659 } 2660 br(Assembler::always, false, Assembler::pt, done); 2661 delayed()->nop(); 2662 2663 bind(try_rebias); 2664 // At this point we know the epoch has expired, meaning that the 2665 // current "bias owner", if any, is actually invalid. Under these 2666 // circumstances _only_, we are allowed to use the current header's 2667 // value as the comparison value when doing the cas to acquire the 2668 // bias in the current epoch. In other words, we allow transfer of 2669 // the bias from one thread to another directly in this situation. 2670 // 2671 // FIXME: due to a lack of registers we currently blow away the age 2672 // bits in this situation. Should attempt to preserve them. 2673 load_klass(obj_reg, temp_reg); 2674 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); 2675 or3(G2_thread, temp_reg, temp_reg); 2676 casx_under_lock(mark_addr.base(), mark_reg, temp_reg, 2677 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); 2678 // If the biasing toward our thread failed, this means that 2679 // another thread succeeded in biasing it toward itself and we 2680 // need to revoke that bias. The revocation will occur in the 2681 // interpreter runtime in the slow case. 2682 cmp(mark_reg, temp_reg); 2683 if (counters != NULL) { 2684 cond_inc(Assembler::zero, (address) counters->rebiased_lock_entry_count_addr(), mark_reg, temp_reg); 2685 } 2686 if (slow_case != NULL) { 2687 brx(Assembler::notEqual, true, Assembler::pn, *slow_case); 2688 delayed()->nop(); 2689 } 2690 br(Assembler::always, false, Assembler::pt, done); 2691 delayed()->nop(); 2692 2693 bind(try_revoke_bias); 2694 // The prototype mark in the klass doesn't have the bias bit set any 2695 // more, indicating that objects of this data type are not supposed 2696 // to be biased any more. We are going to try to reset the mark of 2697 // this object to the prototype value and fall through to the 2698 // CAS-based locking scheme. Note that if our CAS fails, it means 2699 // that another thread raced us for the privilege of revoking the 2700 // bias of this particular object, so it's okay to continue in the 2701 // normal locking code. 2702 // 2703 // FIXME: due to a lack of registers we currently blow away the age 2704 // bits in this situation. Should attempt to preserve them. 2705 load_klass(obj_reg, temp_reg); 2706 ld_ptr(Address(temp_reg, 0, Klass::prototype_header_offset_in_bytes() + klassOopDesc::klass_part_offset_in_bytes()), temp_reg); 2707 casx_under_lock(mark_addr.base(), mark_reg, temp_reg, 2708 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); 2709 // Fall through to the normal CAS-based lock, because no matter what 2710 // the result of the above CAS, some thread must have succeeded in 2711 // removing the bias bit from the object's header. 2712 if (counters != NULL) { 2713 cmp(mark_reg, temp_reg); 2714 cond_inc(Assembler::zero, (address) counters->revoked_lock_entry_count_addr(), mark_reg, temp_reg); 2715 } 2716 2717 bind(cas_label); 2718} 2719 2720void MacroAssembler::biased_locking_exit (Address mark_addr, Register temp_reg, Label& done, 2721 bool allow_delay_slot_filling) { 2722 // Check for biased locking unlock case, which is a no-op 2723 // Note: we do not have to check the thread ID for two reasons. 2724 // First, the interpreter checks for IllegalMonitorStateException at 2725 // a higher level. Second, if the bias was revoked while we held the 2726 // lock, the object could not be rebiased toward another thread, so 2727 // the bias bit would be clear. 2728 ld_ptr(mark_addr, temp_reg); 2729 and3(temp_reg, markOopDesc::biased_lock_mask_in_place, temp_reg); 2730 cmp(temp_reg, markOopDesc::biased_lock_pattern); 2731 brx(Assembler::equal, allow_delay_slot_filling, Assembler::pt, done); 2732 delayed(); 2733 if (!allow_delay_slot_filling) { 2734 nop(); 2735 } 2736} 2737 2738 2739// CASN -- 32-64 bit switch hitter similar to the synthetic CASN provided by 2740// Solaris/SPARC's "as". Another apt name would be cas_ptr() 2741 2742void MacroAssembler::casn (Register addr_reg, Register cmp_reg, Register set_reg ) { 2743 casx_under_lock (addr_reg, cmp_reg, set_reg, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()) ; 2744} 2745 2746 2747 2748// compiler_lock_object() and compiler_unlock_object() are direct transliterations 2749// of i486.ad fast_lock() and fast_unlock(). See those methods for detailed comments. 2750// The code could be tightened up considerably. 2751// 2752// box->dhw disposition - post-conditions at DONE_LABEL. 2753// - Successful inflated lock: box->dhw != 0. 2754// Any non-zero value suffices. 2755// Consider G2_thread, rsp, boxReg, or unused_mark() 2756// - Successful Stack-lock: box->dhw == mark. 2757// box->dhw must contain the displaced mark word value 2758// - Failure -- icc.ZFlag == 0 and box->dhw is undefined. 2759// The slow-path fast_enter() and slow_enter() operators 2760// are responsible for setting box->dhw = NonZero (typically ::unused_mark). 2761// - Biased: box->dhw is undefined 2762// 2763// SPARC refworkload performance - specifically jetstream and scimark - are 2764// extremely sensitive to the size of the code emitted by compiler_lock_object 2765// and compiler_unlock_object. Critically, the key factor is code size, not path 2766// length. (Simply experiments to pad CLO with unexecuted NOPs demonstrte the 2767// effect). 2768 2769 2770void MacroAssembler::compiler_lock_object(Register Roop, Register Rmark, Register Rbox, Register Rscratch, 2771 BiasedLockingCounters* counters) { 2772 Address mark_addr(Roop, 0, oopDesc::mark_offset_in_bytes()); 2773 2774 verify_oop(Roop); 2775 Label done ; 2776 2777 if (counters != NULL) { 2778 inc_counter((address) counters->total_entry_count_addr(), Rmark, Rscratch); 2779 } 2780 2781 if (EmitSync & 1) { 2782 mov (3, Rscratch) ; 2783 st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2784 cmp (SP, G0) ; 2785 return ; 2786 } 2787 2788 if (EmitSync & 2) { 2789 2790 // Fetch object's markword 2791 ld_ptr(mark_addr, Rmark); 2792 2793 if (UseBiasedLocking) { 2794 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); 2795 } 2796 2797 // Save Rbox in Rscratch to be used for the cas operation 2798 mov(Rbox, Rscratch); 2799 2800 // set Rmark to markOop | markOopDesc::unlocked_value 2801 or3(Rmark, markOopDesc::unlocked_value, Rmark); 2802 2803 // Initialize the box. (Must happen before we update the object mark!) 2804 st_ptr(Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2805 2806 // compare object markOop with Rmark and if equal exchange Rscratch with object markOop 2807 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); 2808 casx_under_lock(mark_addr.base(), Rmark, Rscratch, 2809 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); 2810 2811 // if compare/exchange succeeded we found an unlocked object and we now have locked it 2812 // hence we are done 2813 cmp(Rmark, Rscratch); 2814#ifdef _LP64 2815 sub(Rscratch, STACK_BIAS, Rscratch); 2816#endif 2817 brx(Assembler::equal, false, Assembler::pt, done); 2818 delayed()->sub(Rscratch, SP, Rscratch); //pull next instruction into delay slot 2819 2820 // we did not find an unlocked object so see if this is a recursive case 2821 // sub(Rscratch, SP, Rscratch); 2822 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); 2823 andcc(Rscratch, 0xfffff003, Rscratch); 2824 st_ptr(Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2825 bind (done) ; 2826 return ; 2827 } 2828 2829 Label Egress ; 2830 2831 if (EmitSync & 256) { 2832 Label IsInflated ; 2833 2834 ld_ptr (mark_addr, Rmark); // fetch obj->mark 2835 // Triage: biased, stack-locked, neutral, inflated 2836 if (UseBiasedLocking) { 2837 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); 2838 // Invariant: if control reaches this point in the emitted stream 2839 // then Rmark has not been modified. 2840 } 2841 2842 // Store mark into displaced mark field in the on-stack basic-lock "box" 2843 // Critically, this must happen before the CAS 2844 // Maximize the ST-CAS distance to minimize the ST-before-CAS penalty. 2845 st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2846 andcc (Rmark, 2, G0) ; 2847 brx (Assembler::notZero, false, Assembler::pn, IsInflated) ; 2848 delayed() -> 2849 2850 // Try stack-lock acquisition. 2851 // Beware: the 1st instruction is in a delay slot 2852 mov (Rbox, Rscratch); 2853 or3 (Rmark, markOopDesc::unlocked_value, Rmark); 2854 assert (mark_addr.disp() == 0, "cas must take a zero displacement"); 2855 casn (mark_addr.base(), Rmark, Rscratch) ; 2856 cmp (Rmark, Rscratch); 2857 brx (Assembler::equal, false, Assembler::pt, done); 2858 delayed()->sub(Rscratch, SP, Rscratch); 2859 2860 // Stack-lock attempt failed - check for recursive stack-lock. 2861 // See the comments below about how we might remove this case. 2862#ifdef _LP64 2863 sub (Rscratch, STACK_BIAS, Rscratch); 2864#endif 2865 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); 2866 andcc (Rscratch, 0xfffff003, Rscratch); 2867 br (Assembler::always, false, Assembler::pt, done) ; 2868 delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2869 2870 bind (IsInflated) ; 2871 if (EmitSync & 64) { 2872 // If m->owner != null goto IsLocked 2873 // Pessimistic form: Test-and-CAS vs CAS 2874 // The optimistic form avoids RTS->RTO cache line upgrades. 2875 ld_ptr (Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2), Rscratch) ; 2876 andcc (Rscratch, Rscratch, G0) ; 2877 brx (Assembler::notZero, false, Assembler::pn, done) ; 2878 delayed()->nop() ; 2879 // m->owner == null : it's unlocked. 2880 } 2881 2882 // Try to CAS m->owner from null to Self 2883 // Invariant: if we acquire the lock then _recursions should be 0. 2884 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ; 2885 mov (G2_thread, Rscratch) ; 2886 casn (Rmark, G0, Rscratch) ; 2887 cmp (Rscratch, G0) ; 2888 // Intentional fall-through into done 2889 } else { 2890 // Aggressively avoid the Store-before-CAS penalty 2891 // Defer the store into box->dhw until after the CAS 2892 Label IsInflated, Recursive ; 2893 2894// Anticipate CAS -- Avoid RTS->RTO upgrade 2895// prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ; 2896 2897 ld_ptr (mark_addr, Rmark); // fetch obj->mark 2898 // Triage: biased, stack-locked, neutral, inflated 2899 2900 if (UseBiasedLocking) { 2901 biased_locking_enter(Roop, Rmark, Rscratch, done, NULL, counters); 2902 // Invariant: if control reaches this point in the emitted stream 2903 // then Rmark has not been modified. 2904 } 2905 andcc (Rmark, 2, G0) ; 2906 brx (Assembler::notZero, false, Assembler::pn, IsInflated) ; 2907 delayed()-> // Beware - dangling delay-slot 2908 2909 // Try stack-lock acquisition. 2910 // Transiently install BUSY (0) encoding in the mark word. 2911 // if the CAS of 0 into the mark was successful then we execute: 2912 // ST box->dhw = mark -- save fetched mark in on-stack basiclock box 2913 // ST obj->mark = box -- overwrite transient 0 value 2914 // This presumes TSO, of course. 2915 2916 mov (0, Rscratch) ; 2917 or3 (Rmark, markOopDesc::unlocked_value, Rmark); 2918 assert (mark_addr.disp() == 0, "cas must take a zero displacement"); 2919 casn (mark_addr.base(), Rmark, Rscratch) ; 2920// prefetch (mark_addr, Assembler::severalWritesAndPossiblyReads) ; 2921 cmp (Rscratch, Rmark) ; 2922 brx (Assembler::notZero, false, Assembler::pn, Recursive) ; 2923 delayed() -> 2924 st_ptr (Rmark, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2925 if (counters != NULL) { 2926 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); 2927 } 2928 br (Assembler::always, false, Assembler::pt, done); 2929 delayed() -> 2930 st_ptr (Rbox, mark_addr) ; 2931 2932 bind (Recursive) ; 2933 // Stack-lock attempt failed - check for recursive stack-lock. 2934 // Tests show that we can remove the recursive case with no impact 2935 // on refworkload 0.83. If we need to reduce the size of the code 2936 // emitted by compiler_lock_object() the recursive case is perfect 2937 // candidate. 2938 // 2939 // A more extreme idea is to always inflate on stack-lock recursion. 2940 // This lets us eliminate the recursive checks in compiler_lock_object 2941 // and compiler_unlock_object and the (box->dhw == 0) encoding. 2942 // A brief experiment - requiring changes to synchronizer.cpp, interpreter, 2943 // and showed a performance *increase*. In the same experiment I eliminated 2944 // the fast-path stack-lock code from the interpreter and always passed 2945 // control to the "slow" operators in synchronizer.cpp. 2946 2947 // RScratch contains the fetched obj->mark value from the failed CASN. 2948#ifdef _LP64 2949 sub (Rscratch, STACK_BIAS, Rscratch); 2950#endif 2951 sub(Rscratch, SP, Rscratch); 2952 assert(os::vm_page_size() > 0xfff, "page size too small - change the constant"); 2953 andcc (Rscratch, 0xfffff003, Rscratch); 2954 if (counters != NULL) { 2955 // Accounting needs the Rscratch register 2956 st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2957 cond_inc(Assembler::equal, (address) counters->fast_path_entry_count_addr(), Rmark, Rscratch); 2958 br (Assembler::always, false, Assembler::pt, done) ; 2959 delayed()->nop() ; 2960 } else { 2961 br (Assembler::always, false, Assembler::pt, done) ; 2962 delayed()-> st_ptr (Rscratch, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2963 } 2964 2965 bind (IsInflated) ; 2966 if (EmitSync & 64) { 2967 // If m->owner != null goto IsLocked 2968 // Test-and-CAS vs CAS 2969 // Pessimistic form avoids futile (doomed) CAS attempts 2970 // The optimistic form avoids RTS->RTO cache line upgrades. 2971 ld_ptr (Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2), Rscratch) ; 2972 andcc (Rscratch, Rscratch, G0) ; 2973 brx (Assembler::notZero, false, Assembler::pn, done) ; 2974 delayed()->nop() ; 2975 // m->owner == null : it's unlocked. 2976 } 2977 2978 // Try to CAS m->owner from null to Self 2979 // Invariant: if we acquire the lock then _recursions should be 0. 2980 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ; 2981 mov (G2_thread, Rscratch) ; 2982 casn (Rmark, G0, Rscratch) ; 2983 cmp (Rscratch, G0) ; 2984 // ST box->displaced_header = NonZero. 2985 // Any non-zero value suffices: 2986 // unused_mark(), G2_thread, RBox, RScratch, rsp, etc. 2987 st_ptr (Rbox, Rbox, BasicLock::displaced_header_offset_in_bytes()); 2988 // Intentional fall-through into done 2989 } 2990 2991 bind (done) ; 2992} 2993 2994void MacroAssembler::compiler_unlock_object(Register Roop, Register Rmark, Register Rbox, Register Rscratch) { 2995 Address mark_addr(Roop, 0, oopDesc::mark_offset_in_bytes()); 2996 2997 Label done ; 2998 2999 if (EmitSync & 4) { 3000 cmp (SP, G0) ; 3001 return ; 3002 } 3003 3004 if (EmitSync & 8) { 3005 if (UseBiasedLocking) { 3006 biased_locking_exit(mark_addr, Rscratch, done); 3007 } 3008 3009 // Test first if it is a fast recursive unlock 3010 ld_ptr(Rbox, BasicLock::displaced_header_offset_in_bytes(), Rmark); 3011 cmp(Rmark, G0); 3012 brx(Assembler::equal, false, Assembler::pt, done); 3013 delayed()->nop(); 3014 3015 // Check if it is still a light weight lock, this is is true if we see 3016 // the stack address of the basicLock in the markOop of the object 3017 assert(mark_addr.disp() == 0, "cas must take a zero displacement"); 3018 casx_under_lock(mark_addr.base(), Rbox, Rmark, 3019 (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); 3020 br (Assembler::always, false, Assembler::pt, done); 3021 delayed()->cmp(Rbox, Rmark); 3022 bind (done) ; 3023 return ; 3024 } 3025 3026 // Beware ... If the aggregate size of the code emitted by CLO and CUO is 3027 // is too large performance rolls abruptly off a cliff. 3028 // This could be related to inlining policies, code cache management, or 3029 // I$ effects. 3030 Label LStacked ; 3031 3032 if (UseBiasedLocking) { 3033 // TODO: eliminate redundant LDs of obj->mark 3034 biased_locking_exit(mark_addr, Rscratch, done); 3035 } 3036 3037 ld_ptr (Roop, oopDesc::mark_offset_in_bytes(), Rmark) ; 3038 ld_ptr (Rbox, BasicLock::displaced_header_offset_in_bytes(), Rscratch); 3039 andcc (Rscratch, Rscratch, G0); 3040 brx (Assembler::zero, false, Assembler::pn, done); 3041 delayed()-> nop() ; // consider: relocate fetch of mark, above, into this DS 3042 andcc (Rmark, 2, G0) ; 3043 brx (Assembler::zero, false, Assembler::pt, LStacked) ; 3044 delayed()-> nop() ; 3045 3046 // It's inflated 3047 // Conceptually we need a #loadstore|#storestore "release" MEMBAR before 3048 // the ST of 0 into _owner which releases the lock. This prevents loads 3049 // and stores within the critical section from reordering (floating) 3050 // past the store that releases the lock. But TSO is a strong memory model 3051 // and that particular flavor of barrier is a noop, so we can safely elide it. 3052 // Note that we use 1-0 locking by default for the inflated case. We 3053 // close the resultant (and rare) race by having contented threads in 3054 // monitorenter periodically poll _owner. 3055 ld_ptr (Address(Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2), Rscratch) ; 3056 ld_ptr (Address(Rmark, 0, ObjectMonitor::recursions_offset_in_bytes()-2), Rbox) ; 3057 xor3 (Rscratch, G2_thread, Rscratch) ; 3058 orcc (Rbox, Rscratch, Rbox) ; 3059 brx (Assembler::notZero, false, Assembler::pn, done) ; 3060 delayed()-> 3061 ld_ptr (Address (Rmark, 0, ObjectMonitor::EntryList_offset_in_bytes()-2), Rscratch) ; 3062 ld_ptr (Address (Rmark, 0, ObjectMonitor::cxq_offset_in_bytes()-2), Rbox) ; 3063 orcc (Rbox, Rscratch, G0) ; 3064 if (EmitSync & 65536) { 3065 Label LSucc ; 3066 brx (Assembler::notZero, false, Assembler::pn, LSucc) ; 3067 delayed()->nop() ; 3068 br (Assembler::always, false, Assembler::pt, done) ; 3069 delayed()-> 3070 st_ptr (G0, Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3071 3072 bind (LSucc) ; 3073 st_ptr (G0, Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3074 if (os::is_MP()) { membar (StoreLoad) ; } 3075 ld_ptr (Address (Rmark, 0, ObjectMonitor::succ_offset_in_bytes()-2), Rscratch) ; 3076 andcc (Rscratch, Rscratch, G0) ; 3077 brx (Assembler::notZero, false, Assembler::pt, done) ; 3078 delayed()-> andcc (G0, G0, G0) ; 3079 add (Rmark, ObjectMonitor::owner_offset_in_bytes()-2, Rmark) ; 3080 mov (G2_thread, Rscratch) ; 3081 casn (Rmark, G0, Rscratch) ; 3082 cmp (Rscratch, G0) ; 3083 // invert icc.zf and goto done 3084 brx (Assembler::notZero, false, Assembler::pt, done) ; 3085 delayed() -> cmp (G0, G0) ; 3086 br (Assembler::always, false, Assembler::pt, done); 3087 delayed() -> cmp (G0, 1) ; 3088 } else { 3089 brx (Assembler::notZero, false, Assembler::pn, done) ; 3090 delayed()->nop() ; 3091 br (Assembler::always, false, Assembler::pt, done) ; 3092 delayed()-> 3093 st_ptr (G0, Address (Rmark, 0, ObjectMonitor::owner_offset_in_bytes()-2)) ; 3094 } 3095 3096 bind (LStacked) ; 3097 // Consider: we could replace the expensive CAS in the exit 3098 // path with a simple ST of the displaced mark value fetched from 3099 // the on-stack basiclock box. That admits a race where a thread T2 3100 // in the slow lock path -- inflating with monitor M -- could race a 3101 // thread T1 in the fast unlock path, resulting in a missed wakeup for T2. 3102 // More precisely T1 in the stack-lock unlock path could "stomp" the 3103 // inflated mark value M installed by T2, resulting in an orphan 3104 // object monitor M and T2 becoming stranded. We can remedy that situation 3105 // by having T2 periodically poll the object's mark word using timed wait 3106 // operations. If T2 discovers that a stomp has occurred it vacates 3107 // the monitor M and wakes any other threads stranded on the now-orphan M. 3108 // In addition the monitor scavenger, which performs deflation, 3109 // would also need to check for orpan monitors and stranded threads. 3110 // 3111 // Finally, inflation is also used when T2 needs to assign a hashCode 3112 // to O and O is stack-locked by T1. The "stomp" race could cause 3113 // an assigned hashCode value to be lost. We can avoid that condition 3114 // and provide the necessary hashCode stability invariants by ensuring 3115 // that hashCode generation is idempotent between copying GCs. 3116 // For example we could compute the hashCode of an object O as 3117 // O's heap address XOR some high quality RNG value that is refreshed 3118 // at GC-time. The monitor scavenger would install the hashCode 3119 // found in any orphan monitors. Again, the mechanism admits a 3120 // lost-update "stomp" WAW race but detects and recovers as needed. 3121 // 3122 // A prototype implementation showed excellent results, although 3123 // the scavenger and timeout code was rather involved. 3124 3125 casn (mark_addr.base(), Rbox, Rscratch) ; 3126 cmp (Rbox, Rscratch); 3127 // Intentional fall through into done ... 3128 3129 bind (done) ; 3130} 3131 3132 3133 3134void MacroAssembler::print_CPU_state() { 3135 // %%%%% need to implement this 3136} 3137 3138void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 3139 // %%%%% need to implement this 3140} 3141 3142void MacroAssembler::push_IU_state() { 3143 // %%%%% need to implement this 3144} 3145 3146 3147void MacroAssembler::pop_IU_state() { 3148 // %%%%% need to implement this 3149} 3150 3151 3152void MacroAssembler::push_FPU_state() { 3153 // %%%%% need to implement this 3154} 3155 3156 3157void MacroAssembler::pop_FPU_state() { 3158 // %%%%% need to implement this 3159} 3160 3161 3162void MacroAssembler::push_CPU_state() { 3163 // %%%%% need to implement this 3164} 3165 3166 3167void MacroAssembler::pop_CPU_state() { 3168 // %%%%% need to implement this 3169} 3170 3171 3172 3173void MacroAssembler::verify_tlab() { 3174#ifdef ASSERT 3175 if (UseTLAB && VerifyOops) { 3176 Label next, next2, ok; 3177 Register t1 = L0; 3178 Register t2 = L1; 3179 Register t3 = L2; 3180 3181 save_frame(0); 3182 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); 3183 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_start_offset()), t2); 3184 or3(t1, t2, t3); 3185 cmp(t1, t2); 3186 br(Assembler::greaterEqual, false, Assembler::pn, next); 3187 delayed()->nop(); 3188 stop("assert(top >= start)"); 3189 should_not_reach_here(); 3190 3191 bind(next); 3192 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), t1); 3193 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t2); 3194 or3(t3, t2, t3); 3195 cmp(t1, t2); 3196 br(Assembler::lessEqual, false, Assembler::pn, next2); 3197 delayed()->nop(); 3198 stop("assert(top <= end)"); 3199 should_not_reach_here(); 3200 3201 bind(next2); 3202 and3(t3, MinObjAlignmentInBytesMask, t3); 3203 cmp(t3, 0); 3204 br(Assembler::lessEqual, false, Assembler::pn, ok); 3205 delayed()->nop(); 3206 stop("assert(aligned)"); 3207 should_not_reach_here(); 3208 3209 bind(ok); 3210 restore(); 3211 } 3212#endif 3213} 3214 3215 3216void MacroAssembler::eden_allocate( 3217 Register obj, // result: pointer to object after successful allocation 3218 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 3219 int con_size_in_bytes, // object size in bytes if known at compile time 3220 Register t1, // temp register 3221 Register t2, // temp register 3222 Label& slow_case // continuation point if fast allocation fails 3223){ 3224 // make sure arguments make sense 3225 assert_different_registers(obj, var_size_in_bytes, t1, t2); 3226 assert(0 <= con_size_in_bytes && Assembler::is_simm13(con_size_in_bytes), "illegal object size"); 3227 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); 3228 3229 // get eden boundaries 3230 // note: we need both top & top_addr! 3231 const Register top_addr = t1; 3232 const Register end = t2; 3233 3234 CollectedHeap* ch = Universe::heap(); 3235 set((intx)ch->top_addr(), top_addr); 3236 intx delta = (intx)ch->end_addr() - (intx)ch->top_addr(); 3237 ld_ptr(top_addr, delta, end); 3238 ld_ptr(top_addr, 0, obj); 3239 3240 // try to allocate 3241 Label retry; 3242 bind(retry); 3243#ifdef ASSERT 3244 // make sure eden top is properly aligned 3245 { 3246 Label L; 3247 btst(MinObjAlignmentInBytesMask, obj); 3248 br(Assembler::zero, false, Assembler::pt, L); 3249 delayed()->nop(); 3250 stop("eden top is not properly aligned"); 3251 bind(L); 3252 } 3253#endif // ASSERT 3254 const Register free = end; 3255 sub(end, obj, free); // compute amount of free space 3256 if (var_size_in_bytes->is_valid()) { 3257 // size is unknown at compile time 3258 cmp(free, var_size_in_bytes); 3259 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case 3260 delayed()->add(obj, var_size_in_bytes, end); 3261 } else { 3262 // size is known at compile time 3263 cmp(free, con_size_in_bytes); 3264 br(Assembler::lessUnsigned, false, Assembler::pn, slow_case); // if there is not enough space go the slow case 3265 delayed()->add(obj, con_size_in_bytes, end); 3266 } 3267 // Compare obj with the value at top_addr; if still equal, swap the value of 3268 // end with the value at top_addr. If not equal, read the value at top_addr 3269 // into end. 3270 casx_under_lock(top_addr, obj, end, (address)StubRoutines::Sparc::atomic_memory_operation_lock_addr()); 3271 // if someone beat us on the allocation, try again, otherwise continue 3272 cmp(obj, end); 3273 brx(Assembler::notEqual, false, Assembler::pn, retry); 3274 delayed()->mov(end, obj); // nop if successfull since obj == end 3275 3276#ifdef ASSERT 3277 // make sure eden top is properly aligned 3278 { 3279 Label L; 3280 const Register top_addr = t1; 3281 3282 set((intx)ch->top_addr(), top_addr); 3283 ld_ptr(top_addr, 0, top_addr); 3284 btst(MinObjAlignmentInBytesMask, top_addr); 3285 br(Assembler::zero, false, Assembler::pt, L); 3286 delayed()->nop(); 3287 stop("eden top is not properly aligned"); 3288 bind(L); 3289 } 3290#endif // ASSERT 3291} 3292 3293 3294void MacroAssembler::tlab_allocate( 3295 Register obj, // result: pointer to object after successful allocation 3296 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 3297 int con_size_in_bytes, // object size in bytes if known at compile time 3298 Register t1, // temp register 3299 Label& slow_case // continuation point if fast allocation fails 3300){ 3301 // make sure arguments make sense 3302 assert_different_registers(obj, var_size_in_bytes, t1); 3303 assert(0 <= con_size_in_bytes && is_simm13(con_size_in_bytes), "illegal object size"); 3304 assert((con_size_in_bytes & MinObjAlignmentInBytesMask) == 0, "object size is not multiple of alignment"); 3305 3306 const Register free = t1; 3307 3308 verify_tlab(); 3309 3310 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), obj); 3311 3312 // calculate amount of free space 3313 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), free); 3314 sub(free, obj, free); 3315 3316 Label done; 3317 if (var_size_in_bytes == noreg) { 3318 cmp(free, con_size_in_bytes); 3319 } else { 3320 cmp(free, var_size_in_bytes); 3321 } 3322 br(Assembler::less, false, Assembler::pn, slow_case); 3323 // calculate the new top pointer 3324 if (var_size_in_bytes == noreg) { 3325 delayed()->add(obj, con_size_in_bytes, free); 3326 } else { 3327 delayed()->add(obj, var_size_in_bytes, free); 3328 } 3329 3330 bind(done); 3331 3332#ifdef ASSERT 3333 // make sure new free pointer is properly aligned 3334 { 3335 Label L; 3336 btst(MinObjAlignmentInBytesMask, free); 3337 br(Assembler::zero, false, Assembler::pt, L); 3338 delayed()->nop(); 3339 stop("updated TLAB free is not properly aligned"); 3340 bind(L); 3341 } 3342#endif // ASSERT 3343 3344 // update the tlab top pointer 3345 st_ptr(free, G2_thread, in_bytes(JavaThread::tlab_top_offset())); 3346 verify_tlab(); 3347} 3348 3349 3350void MacroAssembler::tlab_refill(Label& retry, Label& try_eden, Label& slow_case) { 3351 Register top = O0; 3352 Register t1 = G1; 3353 Register t2 = G3; 3354 Register t3 = O1; 3355 assert_different_registers(top, t1, t2, t3, G4, G5 /* preserve G4 and G5 */); 3356 Label do_refill, discard_tlab; 3357 3358 if (CMSIncrementalMode || !Universe::heap()->supports_inline_contig_alloc()) { 3359 // No allocation in the shared eden. 3360 br(Assembler::always, false, Assembler::pt, slow_case); 3361 delayed()->nop(); 3362 } 3363 3364 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_top_offset()), top); 3365 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_end_offset()), t1); 3366 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset()), t2); 3367 3368 // calculate amount of free space 3369 sub(t1, top, t1); 3370 srl_ptr(t1, LogHeapWordSize, t1); 3371 3372 // Retain tlab and allocate object in shared space if 3373 // the amount free in the tlab is too large to discard. 3374 cmp(t1, t2); 3375 brx(Assembler::lessEqual, false, Assembler::pt, discard_tlab); 3376 3377 // increment waste limit to prevent getting stuck on this slow path 3378 delayed()->add(t2, ThreadLocalAllocBuffer::refill_waste_limit_increment(), t2); 3379 st_ptr(t2, G2_thread, in_bytes(JavaThread::tlab_refill_waste_limit_offset())); 3380 if (TLABStats) { 3381 // increment number of slow_allocations 3382 ld(G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset()), t2); 3383 add(t2, 1, t2); 3384 stw(t2, G2_thread, in_bytes(JavaThread::tlab_slow_allocations_offset())); 3385 } 3386 br(Assembler::always, false, Assembler::pt, try_eden); 3387 delayed()->nop(); 3388 3389 bind(discard_tlab); 3390 if (TLABStats) { 3391 // increment number of refills 3392 ld(G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset()), t2); 3393 add(t2, 1, t2); 3394 stw(t2, G2_thread, in_bytes(JavaThread::tlab_number_of_refills_offset())); 3395 // accumulate wastage 3396 ld(G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset()), t2); 3397 add(t2, t1, t2); 3398 stw(t2, G2_thread, in_bytes(JavaThread::tlab_fast_refill_waste_offset())); 3399 } 3400 3401 // if tlab is currently allocated (top or end != null) then 3402 // fill [top, end + alignment_reserve) with array object 3403 br_null(top, false, Assembler::pn, do_refill); 3404 delayed()->nop(); 3405 3406 set((intptr_t)markOopDesc::prototype()->copy_set_hash(0x2), t2); 3407 st_ptr(t2, top, oopDesc::mark_offset_in_bytes()); // set up the mark word 3408 // set klass to intArrayKlass 3409 set((intptr_t)Universe::intArrayKlassObj_addr(), t2); 3410 ld_ptr(t2, 0, t2); 3411 store_klass(t2, top); 3412 sub(t1, typeArrayOopDesc::header_size(T_INT), t1); 3413 add(t1, ThreadLocalAllocBuffer::alignment_reserve(), t1); 3414 sll_ptr(t1, log2_intptr(HeapWordSize/sizeof(jint)), t1); 3415 st(t1, top, arrayOopDesc::length_offset_in_bytes()); 3416 verify_oop(top); 3417 3418 // refill the tlab with an eden allocation 3419 bind(do_refill); 3420 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t1); 3421 sll_ptr(t1, LogHeapWordSize, t1); 3422 // add object_size ?? 3423 eden_allocate(top, t1, 0, t2, t3, slow_case); 3424 3425 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_start_offset())); 3426 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_top_offset())); 3427#ifdef ASSERT 3428 // check that tlab_size (t1) is still valid 3429 { 3430 Label ok; 3431 ld_ptr(G2_thread, in_bytes(JavaThread::tlab_size_offset()), t2); 3432 sll_ptr(t2, LogHeapWordSize, t2); 3433 cmp(t1, t2); 3434 br(Assembler::equal, false, Assembler::pt, ok); 3435 delayed()->nop(); 3436 stop("assert(t1 == tlab_size)"); 3437 should_not_reach_here(); 3438 3439 bind(ok); 3440 } 3441#endif // ASSERT 3442 add(top, t1, top); // t1 is tlab_size 3443 sub(top, ThreadLocalAllocBuffer::alignment_reserve_in_bytes(), top); 3444 st_ptr(top, G2_thread, in_bytes(JavaThread::tlab_end_offset())); 3445 verify_tlab(); 3446 br(Assembler::always, false, Assembler::pt, retry); 3447 delayed()->nop(); 3448} 3449 3450Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 3451 switch (cond) { 3452 // Note some conditions are synonyms for others 3453 case Assembler::never: return Assembler::always; 3454 case Assembler::zero: return Assembler::notZero; 3455 case Assembler::lessEqual: return Assembler::greater; 3456 case Assembler::less: return Assembler::greaterEqual; 3457 case Assembler::lessEqualUnsigned: return Assembler::greaterUnsigned; 3458 case Assembler::lessUnsigned: return Assembler::greaterEqualUnsigned; 3459 case Assembler::negative: return Assembler::positive; 3460 case Assembler::overflowSet: return Assembler::overflowClear; 3461 case Assembler::always: return Assembler::never; 3462 case Assembler::notZero: return Assembler::zero; 3463 case Assembler::greater: return Assembler::lessEqual; 3464 case Assembler::greaterEqual: return Assembler::less; 3465 case Assembler::greaterUnsigned: return Assembler::lessEqualUnsigned; 3466 case Assembler::greaterEqualUnsigned: return Assembler::lessUnsigned; 3467 case Assembler::positive: return Assembler::negative; 3468 case Assembler::overflowClear: return Assembler::overflowSet; 3469 } 3470 3471 ShouldNotReachHere(); return Assembler::overflowClear; 3472} 3473 3474void MacroAssembler::cond_inc(Assembler::Condition cond, address counter_ptr, 3475 Register Rtmp1, Register Rtmp2 /*, Register Rtmp3, Register Rtmp4 */) { 3476 Condition negated_cond = negate_condition(cond); 3477 Label L; 3478 brx(negated_cond, false, Assembler::pt, L); 3479 delayed()->nop(); 3480 inc_counter(counter_ptr, Rtmp1, Rtmp2); 3481 bind(L); 3482} 3483 3484void MacroAssembler::inc_counter(address counter_ptr, Register Rtmp1, Register Rtmp2) { 3485 Address counter_addr(Rtmp1, counter_ptr); 3486 load_contents(counter_addr, Rtmp2); 3487 inc(Rtmp2); 3488 store_contents(Rtmp2, counter_addr); 3489} 3490 3491SkipIfEqual::SkipIfEqual( 3492 MacroAssembler* masm, Register temp, const bool* flag_addr, 3493 Assembler::Condition condition) { 3494 _masm = masm; 3495 Address flag(temp, (address)flag_addr, relocInfo::none); 3496 _masm->sethi(flag); 3497 _masm->ldub(flag, temp); 3498 _masm->tst(temp); 3499 _masm->br(condition, false, Assembler::pt, _label); 3500 _masm->delayed()->nop(); 3501} 3502 3503SkipIfEqual::~SkipIfEqual() { 3504 _masm->bind(_label); 3505} 3506 3507 3508// Writes to stack successive pages until offset reached to check for 3509// stack overflow + shadow pages. This clobbers tsp and scratch. 3510void MacroAssembler::bang_stack_size(Register Rsize, Register Rtsp, 3511 Register Rscratch) { 3512 // Use stack pointer in temp stack pointer 3513 mov(SP, Rtsp); 3514 3515 // Bang stack for total size given plus stack shadow page size. 3516 // Bang one page at a time because a large size can overflow yellow and 3517 // red zones (the bang will fail but stack overflow handling can't tell that 3518 // it was a stack overflow bang vs a regular segv). 3519 int offset = os::vm_page_size(); 3520 Register Roffset = Rscratch; 3521 3522 Label loop; 3523 bind(loop); 3524 set((-offset)+STACK_BIAS, Rscratch); 3525 st(G0, Rtsp, Rscratch); 3526 set(offset, Roffset); 3527 sub(Rsize, Roffset, Rsize); 3528 cmp(Rsize, G0); 3529 br(Assembler::greater, false, Assembler::pn, loop); 3530 delayed()->sub(Rtsp, Roffset, Rtsp); 3531 3532 // Bang down shadow pages too. 3533 // The -1 because we already subtracted 1 page. 3534 for (int i = 0; i< StackShadowPages-1; i++) { 3535 set((-i*offset)+STACK_BIAS, Rscratch); 3536 st(G0, Rtsp, Rscratch); 3537 } 3538} 3539 3540void MacroAssembler::load_klass(Register s, Register d) { 3541 // The number of bytes in this code is used by 3542 // MachCallDynamicJavaNode::ret_addr_offset() 3543 // if this changes, change that. 3544 if (UseCompressedOops) { 3545 lduw(s, oopDesc::klass_offset_in_bytes(), d); 3546 decode_heap_oop_not_null(d); 3547 } else { 3548 ld_ptr(s, oopDesc::klass_offset_in_bytes(), d); 3549 } 3550} 3551 3552// ??? figure out src vs. dst! 3553void MacroAssembler::store_klass(Register d, Register s1) { 3554 if (UseCompressedOops) { 3555 assert(s1 != d, "not enough registers"); 3556 encode_heap_oop_not_null(d); 3557 // Zero out entire klass field first. 3558 st_ptr(G0, s1, oopDesc::klass_offset_in_bytes()); 3559 st(d, s1, oopDesc::klass_offset_in_bytes()); 3560 } else { 3561 st_ptr(d, s1, oopDesc::klass_offset_in_bytes()); 3562 } 3563} 3564 3565void MacroAssembler::load_heap_oop(const Address& s, Register d, int offset) { 3566 if (UseCompressedOops) { 3567 lduw(s, d, offset); 3568 decode_heap_oop(d); 3569 } else { 3570 ld_ptr(s, d, offset); 3571 } 3572} 3573 3574void MacroAssembler::load_heap_oop(Register s1, Register s2, Register d) { 3575 if (UseCompressedOops) { 3576 lduw(s1, s2, d); 3577 decode_heap_oop(d, d); 3578 } else { 3579 ld_ptr(s1, s2, d); 3580 } 3581} 3582 3583void MacroAssembler::load_heap_oop(Register s1, int simm13a, Register d) { 3584 if (UseCompressedOops) { 3585 lduw(s1, simm13a, d); 3586 decode_heap_oop(d, d); 3587 } else { 3588 ld_ptr(s1, simm13a, d); 3589 } 3590} 3591 3592void MacroAssembler::store_heap_oop(Register d, Register s1, Register s2) { 3593 if (UseCompressedOops) { 3594 assert(s1 != d && s2 != d, "not enough registers"); 3595 encode_heap_oop(d); 3596 st(d, s1, s2); 3597 } else { 3598 st_ptr(d, s1, s2); 3599 } 3600} 3601 3602void MacroAssembler::store_heap_oop(Register d, Register s1, int simm13a) { 3603 if (UseCompressedOops) { 3604 assert(s1 != d, "not enough registers"); 3605 encode_heap_oop(d); 3606 st(d, s1, simm13a); 3607 } else { 3608 st_ptr(d, s1, simm13a); 3609 } 3610} 3611 3612void MacroAssembler::store_heap_oop(Register d, const Address& a, int offset) { 3613 if (UseCompressedOops) { 3614 assert(a.base() != d, "not enough registers"); 3615 encode_heap_oop(d); 3616 st(d, a, offset); 3617 } else { 3618 st_ptr(d, a, offset); 3619 } 3620} 3621 3622 3623void MacroAssembler::encode_heap_oop(Register src, Register dst) { 3624 assert (UseCompressedOops, "must be compressed"); 3625 Label done; 3626 if (src == dst) { 3627 // optimize for frequent case src == dst 3628 bpr(rc_nz, true, Assembler::pt, src, done); 3629 delayed() -> sub(src, G6_heapbase, dst); // annuled if not taken 3630 bind(done); 3631 srlx(src, LogMinObjAlignmentInBytes, dst); 3632 } else { 3633 bpr(rc_z, false, Assembler::pn, src, done); 3634 delayed() -> mov(G0, dst); 3635 // could be moved before branch, and annulate delay, 3636 // but may add some unneeded work decoding null 3637 sub(src, G6_heapbase, dst); 3638 srlx(dst, LogMinObjAlignmentInBytes, dst); 3639 bind(done); 3640 } 3641} 3642 3643 3644void MacroAssembler::encode_heap_oop_not_null(Register r) { 3645 assert (UseCompressedOops, "must be compressed"); 3646 sub(r, G6_heapbase, r); 3647 srlx(r, LogMinObjAlignmentInBytes, r); 3648} 3649 3650// Same algorithm as oops.inline.hpp decode_heap_oop. 3651void MacroAssembler::decode_heap_oop(Register src, Register dst) { 3652 assert (UseCompressedOops, "must be compressed"); 3653 Label done; 3654 sllx(src, LogMinObjAlignmentInBytes, dst); 3655 bpr(rc_nz, true, Assembler::pt, dst, done); 3656 delayed() -> add(dst, G6_heapbase, dst); // annuled if not taken 3657 bind(done); 3658} 3659 3660void MacroAssembler::decode_heap_oop_not_null(Register r) { 3661 // Do not add assert code to this unless you change vtableStubs_sparc.cpp 3662 // pd_code_size_limit. 3663 assert (UseCompressedOops, "must be compressed"); 3664 sllx(r, LogMinObjAlignmentInBytes, r); 3665 add(r, G6_heapbase, r); 3666} 3667 3668void MacroAssembler::reinit_heapbase() { 3669 if (UseCompressedOops) { 3670 // call indirectly to solve generation ordering problem 3671 Address base(G6_heapbase, (address)Universe::heap_base_addr()); 3672 load_ptr_contents(base, G6_heapbase); 3673 } 3674} 3675