vm_version_ppc.cpp revision 10434:687c4d83a4cc
1/* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2016 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26#include "precompiled.hpp" 27#include "asm/assembler.inline.hpp" 28#include "asm/macroAssembler.inline.hpp" 29#include "compiler/disassembler.hpp" 30#include "memory/resourceArea.hpp" 31#include "runtime/java.hpp" 32#include "runtime/os.hpp" 33#include "runtime/stubCodeGenerator.hpp" 34#include "utilities/defaultStream.hpp" 35#include "utilities/globalDefinitions.hpp" 36#include "vm_version_ppc.hpp" 37 38# include <sys/sysinfo.h> 39 40bool VM_Version::_is_determine_features_test_running = false; 41 42 43#define MSG(flag) \ 44 if (flag && !FLAG_IS_DEFAULT(flag)) \ 45 jio_fprintf(defaultStream::error_stream(), \ 46 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \ 47 " -XX:+" #flag " will be disabled!\n"); 48 49void VM_Version::initialize() { 50 51 // Test which instructions are supported and measure cache line size. 52 determine_features(); 53 54 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features. 55 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) { 56 if (VM_Version::has_lqarx()) { 57 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8); 58 } else if (VM_Version::has_popcntw()) { 59 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7); 60 } else if (VM_Version::has_cmpb()) { 61 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6); 62 } else if (VM_Version::has_popcntb()) { 63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5); 64 } else { 65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0); 66 } 67 } 68 69 bool PowerArchitecturePPC64_ok = false; 70 switch (PowerArchitecturePPC64) { 71 case 8: if (!VM_Version::has_lqarx() ) break; 72 case 7: if (!VM_Version::has_popcntw()) break; 73 case 6: if (!VM_Version::has_cmpb() ) break; 74 case 5: if (!VM_Version::has_popcntb()) break; 75 case 0: PowerArchitecturePPC64_ok = true; break; 76 default: break; 77 } 78 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to " 79 UINTX_FORMAT " on this machine", PowerArchitecturePPC64); 80 81 // Power 8: Configure Data Stream Control Register. 82 if (has_mfdscr()) { 83 config_dscr(); 84 } 85 86 if (!UseSIGTRAP) { 87 MSG(TrapBasedICMissChecks); 88 MSG(TrapBasedNotEntrantChecks); 89 MSG(TrapBasedNullChecks); 90 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false); 91 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false); 92 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false); 93 } 94 95#ifdef COMPILER2 96 if (!UseSIGTRAP) { 97 MSG(TrapBasedRangeChecks); 98 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false); 99 } 100 101 // On Power6 test for section size. 102 if (PowerArchitecturePPC64 == 6) { 103 determine_section_size(); 104 // TODO: PPC port } else { 105 // TODO: PPC port PdScheduling::power6SectorSize = 0x20; 106 } 107 108 MaxVectorSize = 8; 109#endif 110 111 // Create and print feature-string. 112 char buf[(num_features+1) * 16]; // Max 16 chars per feature. 113 jio_snprintf(buf, sizeof(buf), 114 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s", 115 (has_fsqrt() ? " fsqrt" : ""), 116 (has_isel() ? " isel" : ""), 117 (has_lxarxeh() ? " lxarxeh" : ""), 118 (has_cmpb() ? " cmpb" : ""), 119 //(has_mftgpr()? " mftgpr" : ""), 120 (has_popcntb() ? " popcntb" : ""), 121 (has_popcntw() ? " popcntw" : ""), 122 (has_fcfids() ? " fcfids" : ""), 123 (has_vand() ? " vand" : ""), 124 (has_lqarx() ? " lqarx" : ""), 125 (has_vcipher() ? " vcipher" : ""), 126 (has_vpmsumb() ? " vpmsumb" : ""), 127 (has_tcheck() ? " tcheck" : ""), 128 (has_mfdscr() ? " mfdscr" : "") 129 // Make sure number of %s matches num_features! 130 ); 131 _features_string = os::strdup(buf); 132 if (Verbose) { 133 print_features(); 134 } 135 136 // PPC64 supports 8-byte compare-exchange operations (see 137 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr) 138 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile). 139 _supports_cx8 = true; 140 141 // Used by C1. 142 _supports_atomic_getset4 = true; 143 _supports_atomic_getadd4 = true; 144 _supports_atomic_getset8 = true; 145 _supports_atomic_getadd8 = true; 146 147 UseSSE = 0; // Only on x86 and x64 148 149 intx cache_line_size = L1_data_cache_line_size(); 150 151 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1; 152 153 if (AllocatePrefetchStyle == 4) { 154 AllocatePrefetchStepSize = cache_line_size; // Need exact value. 155 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default. 156 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined? 157 } else { 158 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size; 159 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value. 160 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined? 161 } 162 163 assert(AllocatePrefetchLines > 0, "invalid value"); 164 if (AllocatePrefetchLines < 1) { // Set valid value in product VM. 165 AllocatePrefetchLines = 1; // Conservative value. 166 } 167 168 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) { 169 AllocatePrefetchStyle = 1; // Fall back if inappropriate. 170 } 171 172 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 173 174 // Implementation does not use any of the vector instructions 175 // available with Power8. Their exploitation is still pending. 176 if (!UseCRC32Intrinsics) { 177 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 178 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true); 179 } 180 } 181 182 if (UseCRC32CIntrinsics) { 183 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) 184 warning("CRC32C intrinsics are not available on this CPU"); 185 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 186 } 187 188 // The AES intrinsic stubs require AES instruction support. 189 if (UseAES) { 190 warning("AES instructions are not available on this CPU"); 191 FLAG_SET_DEFAULT(UseAES, false); 192 } 193 if (UseAESIntrinsics) { 194 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 195 warning("AES intrinsics are not available on this CPU"); 196 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 197 } 198 199 if (UseAESCTRIntrinsics) { 200 warning("AES/CTR intrinsics are not available on this CPU"); 201 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 202 } 203 204 if (UseGHASHIntrinsics) { 205 warning("GHASH intrinsics are not available on this CPU"); 206 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 207 } 208 209 if (UseSHA) { 210 warning("SHA instructions are not available on this CPU"); 211 FLAG_SET_DEFAULT(UseSHA, false); 212 } 213 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) { 214 warning("SHA intrinsics are not available on this CPU"); 215 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 216 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 217 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 218 } 219 220 if (UseAdler32Intrinsics) { 221 warning("Adler32Intrinsics not available on this CPU."); 222 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); 223 } 224 225 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 226 UseMultiplyToLenIntrinsic = true; 227 } 228 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 229 UseMontgomeryMultiplyIntrinsic = true; 230 } 231 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 232 UseMontgomerySquareIntrinsic = true; 233 } 234 235 if (UseVectorizedMismatchIntrinsic) { 236 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); 237 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 238 } 239 240 241 // Adjust RTM (Restricted Transactional Memory) flags. 242 if (UseRTMLocking) { 243 // If CPU or OS are too old: 244 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 245 // setting during arguments processing. See use_biased_locking(). 246 // VM_Version_init() is executed after UseBiasedLocking is used 247 // in Thread::allocate(). 248 if (!has_tcheck()) { 249 vm_exit_during_initialization("RTM instructions are not available on this CPU"); 250 } 251 bool os_too_old = true; 252#ifdef AIX 253 if (os::Aix::os_version() >= 0x0701031e) { // at least AIX 7.1.3.30 254 os_too_old = false; 255 } 256#endif 257#ifdef linux 258 // At least Linux kernel 4.2, as the problematic behavior of syscalls 259 // being called in the middle of a transaction has been addressed. 260 // Please, refer to commit b4b56f9ecab40f3b4ef53e130c9f6663be491894 261 // in Linux kernel source tree: https://goo.gl/Kc5i7A 262 if (os::Linux::os_version_is_known()) { 263 if (os::Linux::os_version() >= 0x040200) 264 os_too_old = false; 265 } else { 266 vm_exit_during_initialization("RTM can not be enabled: kernel version is unknown."); 267 } 268#endif 269 if (os_too_old) { 270 vm_exit_during_initialization("RTM is not supported on this OS version."); 271 } 272 } 273 274 if (UseRTMLocking) { 275#if INCLUDE_RTM_OPT 276 if (!UnlockExperimentalVMOptions) { 277 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. " 278 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag."); 279 } else { 280 warning("UseRTMLocking is only available as experimental option on this platform."); 281 } 282 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { 283 // RTM locking should be used only for applications with 284 // high lock contention. For now we do not use it by default. 285 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); 286 } 287 if (!is_power_of_2(RTMTotalCountIncrRate)) { 288 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64"); 289 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64); 290 } 291 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) { 292 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50"); 293 FLAG_SET_DEFAULT(RTMAbortRatio, 50); 294 } 295 guarantee(RTMSpinLoopCount > 0, "unsupported"); 296#else 297 // Only C2 does RTM locking optimization. 298 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 299 // setting during arguments processing. See use_biased_locking(). 300 vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); 301#endif 302 } else { // !UseRTMLocking 303 if (UseRTMForStackLocks) { 304 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { 305 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); 306 } 307 FLAG_SET_DEFAULT(UseRTMForStackLocks, false); 308 } 309 if (UseRTMDeopt) { 310 FLAG_SET_DEFAULT(UseRTMDeopt, false); 311 } 312 if (PrintPreciseRTMLockingStatistics) { 313 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); 314 } 315 } 316 317 // This machine allows unaligned memory accesses 318 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { 319 FLAG_SET_DEFAULT(UseUnalignedAccesses, true); 320 } 321} 322 323bool VM_Version::use_biased_locking() { 324#if INCLUDE_RTM_OPT 325 // RTM locking is most useful when there is high lock contention and 326 // low data contention. With high lock contention the lock is usually 327 // inflated and biased locking is not suitable for that case. 328 // RTM locking code requires that biased locking is off. 329 // Note: we can't switch off UseBiasedLocking in get_processor_features() 330 // because it is used by Thread::allocate() which is called before 331 // VM_Version::initialize(). 332 if (UseRTMLocking && UseBiasedLocking) { 333 if (FLAG_IS_DEFAULT(UseBiasedLocking)) { 334 FLAG_SET_DEFAULT(UseBiasedLocking, false); 335 } else { 336 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); 337 UseBiasedLocking = false; 338 } 339 } 340#endif 341 return UseBiasedLocking; 342} 343 344void VM_Version::print_features() { 345 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size()); 346} 347 348#ifdef COMPILER2 349// Determine section size on power6: If section size is 8 instructions, 350// there should be a difference between the two testloops of ~15 %. If 351// no difference is detected the section is assumed to be 32 instructions. 352void VM_Version::determine_section_size() { 353 354 int unroll = 80; 355 356 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord; 357 358 // Allocate space for the code. 359 ResourceMark rm; 360 CodeBuffer cb("detect_section_size", code_size, 0); 361 MacroAssembler* a = new MacroAssembler(&cb); 362 363 uint32_t *code = (uint32_t *)a->pc(); 364 // Emit code. 365 void (*test1)() = (void(*)())(void *)a->function_entry(); 366 367 Label l1; 368 369 a->li(R4, 1); 370 a->sldi(R4, R4, 28); 371 a->b(l1); 372 a->align(CodeEntryAlignment); 373 374 a->bind(l1); 375 376 for (int i = 0; i < unroll; i++) { 377 // Schleife 1 378 // ------- sector 0 ------------ 379 // ;; 0 380 a->nop(); // 1 381 a->fpnop0(); // 2 382 a->fpnop1(); // 3 383 a->addi(R4,R4, -1); // 4 384 385 // ;; 1 386 a->nop(); // 5 387 a->fmr(F6, F6); // 6 388 a->fmr(F7, F7); // 7 389 a->endgroup(); // 8 390 // ------- sector 8 ------------ 391 392 // ;; 2 393 a->nop(); // 9 394 a->nop(); // 10 395 a->fmr(F8, F8); // 11 396 a->fmr(F9, F9); // 12 397 398 // ;; 3 399 a->nop(); // 13 400 a->fmr(F10, F10); // 14 401 a->fmr(F11, F11); // 15 402 a->endgroup(); // 16 403 // -------- sector 16 ------------- 404 405 // ;; 4 406 a->nop(); // 17 407 a->nop(); // 18 408 a->fmr(F15, F15); // 19 409 a->fmr(F16, F16); // 20 410 411 // ;; 5 412 a->nop(); // 21 413 a->fmr(F17, F17); // 22 414 a->fmr(F18, F18); // 23 415 a->endgroup(); // 24 416 // ------- sector 24 ------------ 417 418 // ;; 6 419 a->nop(); // 25 420 a->nop(); // 26 421 a->fmr(F19, F19); // 27 422 a->fmr(F20, F20); // 28 423 424 // ;; 7 425 a->nop(); // 29 426 a->fmr(F21, F21); // 30 427 a->fmr(F22, F22); // 31 428 a->brnop0(); // 32 429 430 // ------- sector 32 ------------ 431 } 432 433 // ;; 8 434 a->cmpdi(CCR0, R4, unroll); // 33 435 a->bge(CCR0, l1); // 34 436 a->blr(); 437 438 // Emit code. 439 void (*test2)() = (void(*)())(void *)a->function_entry(); 440 // uint32_t *code = (uint32_t *)a->pc(); 441 442 Label l2; 443 444 a->li(R4, 1); 445 a->sldi(R4, R4, 28); 446 a->b(l2); 447 a->align(CodeEntryAlignment); 448 449 a->bind(l2); 450 451 for (int i = 0; i < unroll; i++) { 452 // Schleife 2 453 // ------- sector 0 ------------ 454 // ;; 0 455 a->brnop0(); // 1 456 a->nop(); // 2 457 //a->cmpdi(CCR0, R4, unroll); 458 a->fpnop0(); // 3 459 a->fpnop1(); // 4 460 a->addi(R4,R4, -1); // 5 461 462 // ;; 1 463 464 a->nop(); // 6 465 a->fmr(F6, F6); // 7 466 a->fmr(F7, F7); // 8 467 // ------- sector 8 --------------- 468 469 // ;; 2 470 a->endgroup(); // 9 471 472 // ;; 3 473 a->nop(); // 10 474 a->nop(); // 11 475 a->fmr(F8, F8); // 12 476 477 // ;; 4 478 a->fmr(F9, F9); // 13 479 a->nop(); // 14 480 a->fmr(F10, F10); // 15 481 482 // ;; 5 483 a->fmr(F11, F11); // 16 484 // -------- sector 16 ------------- 485 486 // ;; 6 487 a->endgroup(); // 17 488 489 // ;; 7 490 a->nop(); // 18 491 a->nop(); // 19 492 a->fmr(F15, F15); // 20 493 494 // ;; 8 495 a->fmr(F16, F16); // 21 496 a->nop(); // 22 497 a->fmr(F17, F17); // 23 498 499 // ;; 9 500 a->fmr(F18, F18); // 24 501 // -------- sector 24 ------------- 502 503 // ;; 10 504 a->endgroup(); // 25 505 506 // ;; 11 507 a->nop(); // 26 508 a->nop(); // 27 509 a->fmr(F19, F19); // 28 510 511 // ;; 12 512 a->fmr(F20, F20); // 29 513 a->nop(); // 30 514 a->fmr(F21, F21); // 31 515 516 // ;; 13 517 a->fmr(F22, F22); // 32 518 } 519 520 // -------- sector 32 ------------- 521 // ;; 14 522 a->cmpdi(CCR0, R4, unroll); // 33 523 a->bge(CCR0, l2); // 34 524 525 a->blr(); 526 uint32_t *code_end = (uint32_t *)a->pc(); 527 a->flush(); 528 529 double loop1_seconds,loop2_seconds, rel_diff; 530 uint64_t start1, stop1; 531 532 start1 = os::current_thread_cpu_time(false); 533 (*test1)(); 534 stop1 = os::current_thread_cpu_time(false); 535 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0); 536 537 538 start1 = os::current_thread_cpu_time(false); 539 (*test2)(); 540 stop1 = os::current_thread_cpu_time(false); 541 542 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0); 543 544 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100; 545 546 if (PrintAssembly) { 547 ttyLocker ttyl; 548 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 549 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 550 tty->print_cr("Time loop1 :%f", loop1_seconds); 551 tty->print_cr("Time loop2 :%f", loop2_seconds); 552 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff); 553 554 if (rel_diff > 12.0) { 555 tty->print_cr("Section Size 8 Instructions"); 556 } else{ 557 tty->print_cr("Section Size 32 Instructions or Power5"); 558 } 559 } 560 561#if 0 // TODO: PPC port 562 // Set sector size (if not set explicitly). 563 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) { 564 if (rel_diff > 12.0) { 565 PdScheduling::power6SectorSize = 0x20; 566 } else { 567 PdScheduling::power6SectorSize = 0x80; 568 } 569 } else if (Power6SectorSize128PPC64) { 570 PdScheduling::power6SectorSize = 0x80; 571 } else { 572 PdScheduling::power6SectorSize = 0x20; 573 } 574#endif 575 if (UsePower6SchedulerPPC64) Unimplemented(); 576} 577#endif // COMPILER2 578 579void VM_Version::determine_features() { 580#if defined(ABI_ELFv2) 581 // 1 InstWord per call for the blr instruction. 582 const int code_size = (num_features+1+2*1)*BytesPerInstWord; 583#else 584 // 7 InstWords for each call (function descriptor + blr instruction). 585 const int code_size = (num_features+1+2*7)*BytesPerInstWord; 586#endif 587 int features = 0; 588 589 // create test area 590 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size). 591 char test_area[BUFFER_SIZE]; 592 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1]; 593 594 // Allocate space for the code. 595 ResourceMark rm; 596 CodeBuffer cb("detect_cpu_features", code_size, 0); 597 MacroAssembler* a = new MacroAssembler(&cb); 598 599 // Must be set to true so we can generate the test code. 600 _features = VM_Version::all_features_m; 601 602 // Emit code. 603 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry(); 604 uint32_t *code = (uint32_t *)a->pc(); 605 // Don't use R0 in ldarx. 606 // Keep R3_ARG1 unmodified, it contains &field (see below). 607 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below). 608 a->fsqrt(F3, F4); // code[0] -> fsqrt_m 609 a->fsqrts(F3, F4); // code[1] -> fsqrts_m 610 a->isel(R7, R5, R6, 0); // code[2] -> isel_m 611 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m 612 a->cmpb(R7, R5, R6); // code[4] -> cmpb 613 a->popcntb(R7, R5); // code[5] -> popcntb 614 a->popcntw(R7, R5); // code[6] -> popcntw 615 a->fcfids(F3, F4); // code[7] -> fcfids 616 a->vand(VR0, VR0, VR0); // code[8] -> vand 617 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16 618 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m 619 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher 620 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb 621 a->tcheck(0); // code[12] -> tcheck 622 a->mfdscr(R0); // code[13] -> mfdscr 623 a->blr(); 624 625 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it. 626 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry(); 627 a->dcbz(R3_ARG1); // R3_ARG1 = addr 628 a->blr(); 629 630 uint32_t *code_end = (uint32_t *)a->pc(); 631 a->flush(); 632 _features = VM_Version::unknown_m; 633 634 // Print the detection code. 635 if (PrintAssembly) { 636 ttyLocker ttyl; 637 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 638 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 639 } 640 641 // Measure cache line size. 642 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF. 643 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle. 644 int count = 0; // count zeroed bytes 645 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++; 646 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2"); 647 _L1_data_cache_line_size = count; 648 649 // Execute code. Illegal instructions will be replaced by 0 in the signal handler. 650 VM_Version::_is_determine_features_test_running = true; 651 // We must align the first argument to 16 bytes because of the lqarx check. 652 (*test)((address)align_size_up((intptr_t)mid_of_test_area, 16), (uint64_t)0); 653 VM_Version::_is_determine_features_test_running = false; 654 655 // determine which instructions are legal. 656 int feature_cntr = 0; 657 if (code[feature_cntr++]) features |= fsqrt_m; 658 if (code[feature_cntr++]) features |= fsqrts_m; 659 if (code[feature_cntr++]) features |= isel_m; 660 if (code[feature_cntr++]) features |= lxarxeh_m; 661 if (code[feature_cntr++]) features |= cmpb_m; 662 if (code[feature_cntr++]) features |= popcntb_m; 663 if (code[feature_cntr++]) features |= popcntw_m; 664 if (code[feature_cntr++]) features |= fcfids_m; 665 if (code[feature_cntr++]) features |= vand_m; 666 if (code[feature_cntr++]) features |= lqarx_m; 667 if (code[feature_cntr++]) features |= vcipher_m; 668 if (code[feature_cntr++]) features |= vpmsumb_m; 669 if (code[feature_cntr++]) features |= tcheck_m; 670 if (code[feature_cntr++]) features |= mfdscr_m; 671 672 // Print the detection code. 673 if (PrintAssembly) { 674 ttyLocker ttyl; 675 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code)); 676 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 677 } 678 679 _features = features; 680} 681 682// Power 8: Configure Data Stream Control Register. 683void VM_Version::config_dscr() { 684 // 7 InstWords for each call (function descriptor + blr instruction). 685 const int code_size = (2+2*7)*BytesPerInstWord; 686 687 // Allocate space for the code. 688 ResourceMark rm; 689 CodeBuffer cb("config_dscr", code_size, 0); 690 MacroAssembler* a = new MacroAssembler(&cb); 691 692 // Emit code. 693 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry(); 694 uint32_t *code = (uint32_t *)a->pc(); 695 a->mfdscr(R3); 696 a->blr(); 697 698 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry(); 699 a->mtdscr(R3); 700 a->blr(); 701 702 uint32_t *code_end = (uint32_t *)a->pc(); 703 a->flush(); 704 705 // Print the detection code. 706 if (PrintAssembly) { 707 ttyLocker ttyl; 708 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code)); 709 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 710 } 711 712 // Apply the configuration if needed. 713 uint64_t dscr_val = (*get_dscr)(); 714 if (Verbose) { 715 tty->print_cr("dscr value was 0x%lx" , dscr_val); 716 } 717 bool change_requested = false; 718 if (DSCR_PPC64 != (uintx)-1) { 719 dscr_val = DSCR_PPC64; 720 change_requested = true; 721 } 722 if (DSCR_DPFD_PPC64 <= 7) { 723 uint64_t mask = 0x7; 724 if ((dscr_val & mask) != DSCR_DPFD_PPC64) { 725 dscr_val = (dscr_val & ~mask) | (DSCR_DPFD_PPC64); 726 change_requested = true; 727 } 728 } 729 if (DSCR_URG_PPC64 <= 7) { 730 uint64_t mask = 0x7 << 6; 731 if ((dscr_val & mask) != DSCR_DPFD_PPC64 << 6) { 732 dscr_val = (dscr_val & ~mask) | (DSCR_URG_PPC64 << 6); 733 change_requested = true; 734 } 735 } 736 if (change_requested) { 737 (*set_dscr)(dscr_val); 738 if (Verbose) { 739 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)()); 740 } 741 } 742} 743 744static uint64_t saved_features = 0; 745 746void VM_Version::allow_all() { 747 saved_features = _features; 748 _features = all_features_m; 749} 750 751void VM_Version::revert() { 752 _features = saved_features; 753} 754