assembler_ppc.hpp revision 9751:4a24de859a87
1/* 2 * Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved. 3 * Copyright 2012, 2015 SAP AG. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26#ifndef CPU_PPC_VM_ASSEMBLER_PPC_HPP 27#define CPU_PPC_VM_ASSEMBLER_PPC_HPP 28 29#include "asm/register.hpp" 30 31// Address is an abstraction used to represent a memory location 32// as used in assembler instructions. 33// PPC instructions grok either baseReg + indexReg or baseReg + disp. 34class Address VALUE_OBJ_CLASS_SPEC { 35 private: 36 Register _base; // Base register. 37 Register _index; // Index register. 38 intptr_t _disp; // Displacement. 39 40 public: 41 Address(Register b, Register i, address d = 0) 42 : _base(b), _index(i), _disp((intptr_t)d) { 43 assert(i == noreg || d == 0, "can't have both"); 44 } 45 46 Address(Register b, address d = 0) 47 : _base(b), _index(noreg), _disp((intptr_t)d) {} 48 49 Address(Register b, intptr_t d) 50 : _base(b), _index(noreg), _disp(d) {} 51 52 Address(Register b, RegisterOrConstant roc) 53 : _base(b), _index(noreg), _disp(0) { 54 if (roc.is_constant()) _disp = roc.as_constant(); else _index = roc.as_register(); 55 } 56 57 Address() 58 : _base(noreg), _index(noreg), _disp(0) {} 59 60 // accessors 61 Register base() const { return _base; } 62 Register index() const { return _index; } 63 int disp() const { return (int)_disp; } 64 bool is_const() const { return _base == noreg && _index == noreg; } 65}; 66 67class AddressLiteral VALUE_OBJ_CLASS_SPEC { 68 private: 69 address _address; 70 RelocationHolder _rspec; 71 72 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { 73 switch (rtype) { 74 case relocInfo::external_word_type: 75 return external_word_Relocation::spec(addr); 76 case relocInfo::internal_word_type: 77 return internal_word_Relocation::spec(addr); 78 case relocInfo::opt_virtual_call_type: 79 return opt_virtual_call_Relocation::spec(); 80 case relocInfo::static_call_type: 81 return static_call_Relocation::spec(); 82 case relocInfo::runtime_call_type: 83 return runtime_call_Relocation::spec(); 84 case relocInfo::none: 85 return RelocationHolder(); 86 default: 87 ShouldNotReachHere(); 88 return RelocationHolder(); 89 } 90 } 91 92 protected: 93 // creation 94 AddressLiteral() : _address(NULL), _rspec(NULL) {} 95 96 public: 97 AddressLiteral(address addr, RelocationHolder const& rspec) 98 : _address(addr), 99 _rspec(rspec) {} 100 101 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) 102 : _address((address) addr), 103 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 104 105 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none) 106 : _address((address) addr), 107 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 108 109 intptr_t value() const { return (intptr_t) _address; } 110 111 const RelocationHolder& rspec() const { return _rspec; } 112}; 113 114// Argument is an abstraction used to represent an outgoing 115// actual argument or an incoming formal parameter, whether 116// it resides in memory or in a register, in a manner consistent 117// with the PPC Application Binary Interface, or ABI. This is 118// often referred to as the native or C calling convention. 119 120class Argument VALUE_OBJ_CLASS_SPEC { 121 private: 122 int _number; // The number of the argument. 123 public: 124 enum { 125 // Only 8 registers may contain integer parameters. 126 n_register_parameters = 8, 127 // Can have up to 8 floating registers. 128 n_float_register_parameters = 8, 129 130 // PPC C calling conventions. 131 // The first eight arguments are passed in int regs if they are int. 132 n_int_register_parameters_c = 8, 133 // The first thirteen float arguments are passed in float regs. 134 n_float_register_parameters_c = 13, 135 // Only the first 8 parameters are not placed on the stack. Aix disassembly 136 // shows that xlC places all float args after argument 8 on the stack AND 137 // in a register. This is not documented, but we follow this convention, too. 138 n_regs_not_on_stack_c = 8, 139 }; 140 // creation 141 Argument(int number) : _number(number) {} 142 143 int number() const { return _number; } 144 145 // Locating register-based arguments: 146 bool is_register() const { return _number < n_register_parameters; } 147 148 Register as_register() const { 149 assert(is_register(), "must be a register argument"); 150 return as_Register(number() + R3_ARG1->encoding()); 151 } 152}; 153 154#if !defined(ABI_ELFv2) 155// A ppc64 function descriptor. 156struct FunctionDescriptor VALUE_OBJ_CLASS_SPEC { 157 private: 158 address _entry; 159 address _toc; 160 address _env; 161 162 public: 163 inline address entry() const { return _entry; } 164 inline address toc() const { return _toc; } 165 inline address env() const { return _env; } 166 167 inline void set_entry(address entry) { _entry = entry; } 168 inline void set_toc( address toc) { _toc = toc; } 169 inline void set_env( address env) { _env = env; } 170 171 inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); } 172 inline static ByteSize toc_offset() { return byte_offset_of(FunctionDescriptor, _toc); } 173 inline static ByteSize env_offset() { return byte_offset_of(FunctionDescriptor, _env); } 174 175 // Friend functions can be called without loading toc and env. 176 enum { 177 friend_toc = 0xcafe, 178 friend_env = 0xc0de 179 }; 180 181 inline bool is_friend_function() const { 182 return (toc() == (address) friend_toc) && (env() == (address) friend_env); 183 } 184 185 // Constructor for stack-allocated instances. 186 FunctionDescriptor() { 187 _entry = (address) 0xbad; 188 _toc = (address) 0xbad; 189 _env = (address) 0xbad; 190 } 191}; 192#endif 193 194 195// The PPC Assembler: Pure assembler doing NO optimizations on the 196// instruction level; i.e., what you write is what you get. The 197// Assembler is generating code into a CodeBuffer. 198 199class Assembler : public AbstractAssembler { 200 protected: 201 // Displacement routines 202 static int patched_branch(int dest_pos, int inst, int inst_pos); 203 static int branch_destination(int inst, int pos); 204 205 friend class AbstractAssembler; 206 207 // Code patchers need various routines like inv_wdisp() 208 friend class NativeInstruction; 209 friend class NativeGeneralJump; 210 friend class Relocation; 211 212 public: 213 214 enum shifts { 215 XO_21_29_SHIFT = 2, 216 XO_21_30_SHIFT = 1, 217 XO_27_29_SHIFT = 2, 218 XO_30_31_SHIFT = 0, 219 SPR_5_9_SHIFT = 11u, // SPR_5_9 field in bits 11 -- 15 220 SPR_0_4_SHIFT = 16u, // SPR_0_4 field in bits 16 -- 20 221 RS_SHIFT = 21u, // RS field in bits 21 -- 25 222 OPCODE_SHIFT = 26u, // opcode in bits 26 -- 31 223 }; 224 225 enum opcdxos_masks { 226 XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 227 ADDI_OPCODE_MASK = (63u << OPCODE_SHIFT), 228 ADDIS_OPCODE_MASK = (63u << OPCODE_SHIFT), 229 BXX_OPCODE_MASK = (63u << OPCODE_SHIFT), 230 BCXX_OPCODE_MASK = (63u << OPCODE_SHIFT), 231 // trap instructions 232 TDI_OPCODE_MASK = (63u << OPCODE_SHIFT), 233 TWI_OPCODE_MASK = (63u << OPCODE_SHIFT), 234 TD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 235 TW_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 236 LD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM 237 STD_OPCODE_MASK = LD_OPCODE_MASK, 238 STDU_OPCODE_MASK = STD_OPCODE_MASK, 239 STDX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 240 STDUX_OPCODE_MASK = STDX_OPCODE_MASK, 241 STW_OPCODE_MASK = (63u << OPCODE_SHIFT), 242 STWU_OPCODE_MASK = STW_OPCODE_MASK, 243 STWX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 244 STWUX_OPCODE_MASK = STWX_OPCODE_MASK, 245 MTCTR_OPCODE_MASK = ~(31u << RS_SHIFT), 246 ORI_OPCODE_MASK = (63u << OPCODE_SHIFT), 247 ORIS_OPCODE_MASK = (63u << OPCODE_SHIFT), 248 RLDICR_OPCODE_MASK = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT) 249 }; 250 251 enum opcdxos { 252 ADD_OPCODE = (31u << OPCODE_SHIFT | 266u << 1), 253 ADDC_OPCODE = (31u << OPCODE_SHIFT | 10u << 1), 254 ADDI_OPCODE = (14u << OPCODE_SHIFT), 255 ADDIS_OPCODE = (15u << OPCODE_SHIFT), 256 ADDIC__OPCODE = (13u << OPCODE_SHIFT), 257 ADDE_OPCODE = (31u << OPCODE_SHIFT | 138u << 1), 258 ADDME_OPCODE = (31u << OPCODE_SHIFT | 234u << 1), 259 ADDZE_OPCODE = (31u << OPCODE_SHIFT | 202u << 1), 260 SUBF_OPCODE = (31u << OPCODE_SHIFT | 40u << 1), 261 SUBFC_OPCODE = (31u << OPCODE_SHIFT | 8u << 1), 262 SUBFE_OPCODE = (31u << OPCODE_SHIFT | 136u << 1), 263 SUBFIC_OPCODE = (8u << OPCODE_SHIFT), 264 SUBFME_OPCODE = (31u << OPCODE_SHIFT | 232u << 1), 265 SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1), 266 DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1), 267 MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1), 268 MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1), 269 MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1), 270 MULLI_OPCODE = (7u << OPCODE_SHIFT), 271 AND_OPCODE = (31u << OPCODE_SHIFT | 28u << 1), 272 ANDI_OPCODE = (28u << OPCODE_SHIFT), 273 ANDIS_OPCODE = (29u << OPCODE_SHIFT), 274 ANDC_OPCODE = (31u << OPCODE_SHIFT | 60u << 1), 275 ORC_OPCODE = (31u << OPCODE_SHIFT | 412u << 1), 276 OR_OPCODE = (31u << OPCODE_SHIFT | 444u << 1), 277 ORI_OPCODE = (24u << OPCODE_SHIFT), 278 ORIS_OPCODE = (25u << OPCODE_SHIFT), 279 XOR_OPCODE = (31u << OPCODE_SHIFT | 316u << 1), 280 XORI_OPCODE = (26u << OPCODE_SHIFT), 281 XORIS_OPCODE = (27u << OPCODE_SHIFT), 282 283 NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1), 284 285 RLWINM_OPCODE = (21u << OPCODE_SHIFT), 286 CLRRWI_OPCODE = RLWINM_OPCODE, 287 CLRLWI_OPCODE = RLWINM_OPCODE, 288 289 RLWIMI_OPCODE = (20u << OPCODE_SHIFT), 290 291 SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1), 292 SLWI_OPCODE = RLWINM_OPCODE, 293 SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1), 294 SRWI_OPCODE = RLWINM_OPCODE, 295 SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1), 296 SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1), 297 298 CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1), 299 CMPI_OPCODE = (11u << OPCODE_SHIFT), 300 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1), 301 CMPLI_OPCODE = (10u << OPCODE_SHIFT), 302 303 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1), 304 305 // Special purpose registers 306 MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1), 307 MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1), 308 309 MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT), 310 MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT), 311 312 MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT), 313 MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT), 314 315 MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT), 316 MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT), 317 318 MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT), 319 MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT), 320 321 // Attention: Higher and lower half are inserted in reversed order. 322 MTTFHAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 323 MFTFHAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 324 MTTFIAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT), 325 MFTFIAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT), 326 MTTEXASR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT), 327 MFTEXASR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT), 328 MTTEXASRU_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT), 329 MFTEXASRU_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT), 330 331 MTVRSAVE_OPCODE = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 332 MFVRSAVE_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 333 334 MFTB_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT), 335 336 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1), 337 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1), 338 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1), 339 340 // condition register logic instructions 341 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1), 342 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1), 343 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1), 344 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1), 345 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1), 346 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1), 347 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1), 348 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1), 349 350 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1), 351 BXX_OPCODE = (18u << OPCODE_SHIFT), 352 BCXX_OPCODE = (16u << OPCODE_SHIFT), 353 354 // CTR-related opcodes 355 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1), 356 357 LWZ_OPCODE = (32u << OPCODE_SHIFT), 358 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1), 359 LWZU_OPCODE = (33u << OPCODE_SHIFT), 360 LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1), 361 362 LHA_OPCODE = (42u << OPCODE_SHIFT), 363 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1), 364 LHAU_OPCODE = (43u << OPCODE_SHIFT), 365 366 LHZ_OPCODE = (40u << OPCODE_SHIFT), 367 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1), 368 LHZU_OPCODE = (41u << OPCODE_SHIFT), 369 LHBRX_OPCODE = (31u << OPCODE_SHIFT | 790 << 1), 370 371 LBZ_OPCODE = (34u << OPCODE_SHIFT), 372 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1), 373 LBZU_OPCODE = (35u << OPCODE_SHIFT), 374 375 STW_OPCODE = (36u << OPCODE_SHIFT), 376 STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1), 377 STWU_OPCODE = (37u << OPCODE_SHIFT), 378 STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1), 379 380 STH_OPCODE = (44u << OPCODE_SHIFT), 381 STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1), 382 STHU_OPCODE = (45u << OPCODE_SHIFT), 383 384 STB_OPCODE = (38u << OPCODE_SHIFT), 385 STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1), 386 STBU_OPCODE = (39u << OPCODE_SHIFT), 387 388 EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1), 389 EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1), 390 EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1), // X-FORM 391 392 // 32 bit opcode encodings 393 394 LWA_OPCODE = (58u << OPCODE_SHIFT | 2u << XO_30_31_SHIFT), // DS-FORM 395 LWAX_OPCODE = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM 396 397 CNTLZW_OPCODE = (31u << OPCODE_SHIFT | 26u << XO_21_30_SHIFT), // X-FORM 398 399 // 64 bit opcode encodings 400 401 LD_OPCODE = (58u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM 402 LDU_OPCODE = (58u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM 403 LDX_OPCODE = (31u << OPCODE_SHIFT | 21u << XO_21_30_SHIFT), // X-FORM 404 405 STD_OPCODE = (62u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM 406 STDU_OPCODE = (62u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM 407 STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM 408 STDX_OPCODE = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM 409 410 RLDICR_OPCODE = (30u << OPCODE_SHIFT | 1u << XO_27_29_SHIFT), // MD-FORM 411 RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM 412 RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM 413 RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM 414 415 SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM 416 417 SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM 418 SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM 419 SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM 420 421 MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM 422 MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM 423 MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM 424 DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM 425 426 CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM 427 NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM 428 NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM 429 430 431 // opcodes only used for floating arithmetic 432 FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1), 433 FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1), 434 FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1), 435 FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1), 436 FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1), 437 FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1), 438 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx" 439 // on Power7. Do not use. 440 // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1), 441 // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1), 442 CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1), 443 POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1), 444 POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1), 445 POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1), 446 FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1), 447 FNABS_OPCODE = (63u << OPCODE_SHIFT | 136u << 1), 448 FMUL_OPCODE = (63u << OPCODE_SHIFT | 25u << 1), 449 FMULS_OPCODE = (59u << OPCODE_SHIFT | 25u << 1), 450 FNEG_OPCODE = (63u << OPCODE_SHIFT | 40u << 1), 451 FSUB_OPCODE = (63u << OPCODE_SHIFT | 20u << 1), 452 FSUBS_OPCODE = (59u << OPCODE_SHIFT | 20u << 1), 453 454 // PPC64-internal FPU conversion opcodes 455 FCFID_OPCODE = (63u << OPCODE_SHIFT | 846u << 1), 456 FCFIDS_OPCODE = (59u << OPCODE_SHIFT | 846u << 1), 457 FCTID_OPCODE = (63u << OPCODE_SHIFT | 814u << 1), 458 FCTIDZ_OPCODE = (63u << OPCODE_SHIFT | 815u << 1), 459 FCTIW_OPCODE = (63u << OPCODE_SHIFT | 14u << 1), 460 FCTIWZ_OPCODE = (63u << OPCODE_SHIFT | 15u << 1), 461 FRSP_OPCODE = (63u << OPCODE_SHIFT | 12u << 1), 462 463 // WARNING: using fmadd results in a non-compliant vm. Some floating 464 // point tck tests will fail. 465 FMADD_OPCODE = (59u << OPCODE_SHIFT | 29u << 1), 466 DMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1), 467 FMSUB_OPCODE = (59u << OPCODE_SHIFT | 28u << 1), 468 DMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1), 469 FNMADD_OPCODE = (59u << OPCODE_SHIFT | 31u << 1), 470 DNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1), 471 FNMSUB_OPCODE = (59u << OPCODE_SHIFT | 30u << 1), 472 DNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1), 473 474 LFD_OPCODE = (50u << OPCODE_SHIFT | 00u << 1), 475 LFDU_OPCODE = (51u << OPCODE_SHIFT | 00u << 1), 476 LFDX_OPCODE = (31u << OPCODE_SHIFT | 599u << 1), 477 LFS_OPCODE = (48u << OPCODE_SHIFT | 00u << 1), 478 LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1), 479 LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1), 480 481 STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1), 482 STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1), 483 STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1), 484 STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1), 485 STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1), 486 STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1), 487 488 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM 489 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM 490 491 // Vector instruction support for >= Power6 492 // Vector Storage Access 493 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1), 494 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1), 495 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1), 496 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1), 497 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1), 498 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1), 499 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1), 500 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1), 501 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1), 502 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1), 503 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1), 504 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1), 505 506 // Vector Permute and Formatting 507 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ), 508 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ), 509 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ), 510 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ), 511 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ), 512 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ), 513 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ), 514 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ), 515 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ), 516 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ), 517 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ), 518 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ), 519 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ), 520 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ), 521 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ), 522 523 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ), 524 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ), 525 VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ), 526 VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ), 527 VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ), 528 VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ), 529 530 VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ), 531 VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ), 532 VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ), 533 VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ), 534 VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ), 535 VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ), 536 537 VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ), 538 VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ), 539 540 VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ), 541 VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ), 542 VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ), 543 VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ), 544 VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ), 545 546 // Vector Integer 547 VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ), 548 VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ), 549 VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ), 550 VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ), 551 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ), 552 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ), 553 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ), 554 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ), 555 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ), 556 VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ), 557 VSUBCUW_OPCODE = (4u << OPCODE_SHIFT | 1408u ), 558 VSUBSHS_OPCODE = (4u << OPCODE_SHIFT | 1856u ), 559 VSUBSBS_OPCODE = (4u << OPCODE_SHIFT | 1792u ), 560 VSUBSWS_OPCODE = (4u << OPCODE_SHIFT | 1920u ), 561 VSUBUBM_OPCODE = (4u << OPCODE_SHIFT | 1024u ), 562 VSUBUWM_OPCODE = (4u << OPCODE_SHIFT | 1152u ), 563 VSUBUHM_OPCODE = (4u << OPCODE_SHIFT | 1088u ), 564 VSUBUBS_OPCODE = (4u << OPCODE_SHIFT | 1536u ), 565 VSUBUWS_OPCODE = (4u << OPCODE_SHIFT | 1664u ), 566 VSUBUHS_OPCODE = (4u << OPCODE_SHIFT | 1600u ), 567 568 VMULESB_OPCODE = (4u << OPCODE_SHIFT | 776u ), 569 VMULEUB_OPCODE = (4u << OPCODE_SHIFT | 520u ), 570 VMULESH_OPCODE = (4u << OPCODE_SHIFT | 840u ), 571 VMULEUH_OPCODE = (4u << OPCODE_SHIFT | 584u ), 572 VMULOSB_OPCODE = (4u << OPCODE_SHIFT | 264u ), 573 VMULOUB_OPCODE = (4u << OPCODE_SHIFT | 8u ), 574 VMULOSH_OPCODE = (4u << OPCODE_SHIFT | 328u ), 575 VMULOUH_OPCODE = (4u << OPCODE_SHIFT | 72u ), 576 VMHADDSHS_OPCODE=(4u << OPCODE_SHIFT | 32u ), 577 VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT | 33u ), 578 VMLADDUHM_OPCODE=(4u << OPCODE_SHIFT | 34u ), 579 VMSUBUHM_OPCODE= (4u << OPCODE_SHIFT | 36u ), 580 VMSUMMBM_OPCODE= (4u << OPCODE_SHIFT | 37u ), 581 VMSUMSHM_OPCODE= (4u << OPCODE_SHIFT | 40u ), 582 VMSUMSHS_OPCODE= (4u << OPCODE_SHIFT | 41u ), 583 VMSUMUHM_OPCODE= (4u << OPCODE_SHIFT | 38u ), 584 VMSUMUHS_OPCODE= (4u << OPCODE_SHIFT | 39u ), 585 586 VSUMSWS_OPCODE = (4u << OPCODE_SHIFT | 1928u ), 587 VSUM2SWS_OPCODE= (4u << OPCODE_SHIFT | 1672u ), 588 VSUM4SBS_OPCODE= (4u << OPCODE_SHIFT | 1800u ), 589 VSUM4UBS_OPCODE= (4u << OPCODE_SHIFT | 1544u ), 590 VSUM4SHS_OPCODE= (4u << OPCODE_SHIFT | 1608u ), 591 592 VAVGSB_OPCODE = (4u << OPCODE_SHIFT | 1282u ), 593 VAVGSW_OPCODE = (4u << OPCODE_SHIFT | 1410u ), 594 VAVGSH_OPCODE = (4u << OPCODE_SHIFT | 1346u ), 595 VAVGUB_OPCODE = (4u << OPCODE_SHIFT | 1026u ), 596 VAVGUW_OPCODE = (4u << OPCODE_SHIFT | 1154u ), 597 VAVGUH_OPCODE = (4u << OPCODE_SHIFT | 1090u ), 598 599 VMAXSB_OPCODE = (4u << OPCODE_SHIFT | 258u ), 600 VMAXSW_OPCODE = (4u << OPCODE_SHIFT | 386u ), 601 VMAXSH_OPCODE = (4u << OPCODE_SHIFT | 322u ), 602 VMAXUB_OPCODE = (4u << OPCODE_SHIFT | 2u ), 603 VMAXUW_OPCODE = (4u << OPCODE_SHIFT | 130u ), 604 VMAXUH_OPCODE = (4u << OPCODE_SHIFT | 66u ), 605 VMINSB_OPCODE = (4u << OPCODE_SHIFT | 770u ), 606 VMINSW_OPCODE = (4u << OPCODE_SHIFT | 898u ), 607 VMINSH_OPCODE = (4u << OPCODE_SHIFT | 834u ), 608 VMINUB_OPCODE = (4u << OPCODE_SHIFT | 514u ), 609 VMINUW_OPCODE = (4u << OPCODE_SHIFT | 642u ), 610 VMINUH_OPCODE = (4u << OPCODE_SHIFT | 578u ), 611 612 VCMPEQUB_OPCODE= (4u << OPCODE_SHIFT | 6u ), 613 VCMPEQUH_OPCODE= (4u << OPCODE_SHIFT | 70u ), 614 VCMPEQUW_OPCODE= (4u << OPCODE_SHIFT | 134u ), 615 VCMPGTSH_OPCODE= (4u << OPCODE_SHIFT | 838u ), 616 VCMPGTSB_OPCODE= (4u << OPCODE_SHIFT | 774u ), 617 VCMPGTSW_OPCODE= (4u << OPCODE_SHIFT | 902u ), 618 VCMPGTUB_OPCODE= (4u << OPCODE_SHIFT | 518u ), 619 VCMPGTUH_OPCODE= (4u << OPCODE_SHIFT | 582u ), 620 VCMPGTUW_OPCODE= (4u << OPCODE_SHIFT | 646u ), 621 622 VAND_OPCODE = (4u << OPCODE_SHIFT | 1028u ), 623 VANDC_OPCODE = (4u << OPCODE_SHIFT | 1092u ), 624 VNOR_OPCODE = (4u << OPCODE_SHIFT | 1284u ), 625 VOR_OPCODE = (4u << OPCODE_SHIFT | 1156u ), 626 VXOR_OPCODE = (4u << OPCODE_SHIFT | 1220u ), 627 VRLB_OPCODE = (4u << OPCODE_SHIFT | 4u ), 628 VRLW_OPCODE = (4u << OPCODE_SHIFT | 132u ), 629 VRLH_OPCODE = (4u << OPCODE_SHIFT | 68u ), 630 VSLB_OPCODE = (4u << OPCODE_SHIFT | 260u ), 631 VSKW_OPCODE = (4u << OPCODE_SHIFT | 388u ), 632 VSLH_OPCODE = (4u << OPCODE_SHIFT | 324u ), 633 VSRB_OPCODE = (4u << OPCODE_SHIFT | 516u ), 634 VSRW_OPCODE = (4u << OPCODE_SHIFT | 644u ), 635 VSRH_OPCODE = (4u << OPCODE_SHIFT | 580u ), 636 VSRAB_OPCODE = (4u << OPCODE_SHIFT | 772u ), 637 VSRAW_OPCODE = (4u << OPCODE_SHIFT | 900u ), 638 VSRAH_OPCODE = (4u << OPCODE_SHIFT | 836u ), 639 640 // Vector Floating-Point 641 // not implemented yet 642 643 // Vector Status and Control 644 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ), 645 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ), 646 647 // AES (introduced with Power 8) 648 VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u), 649 VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u), 650 VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u), 651 VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u), 652 VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u), 653 654 // SHA (introduced with Power 8) 655 VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u), 656 VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u), 657 658 // Vector Binary Polynomial Multiplication (introduced with Power 8) 659 VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u), 660 VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u), 661 VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u), 662 VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u), 663 664 // Vector Permute and Xor (introduced with Power 8) 665 VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u), 666 667 // Transactional Memory instructions (introduced with Power 8) 668 TBEGIN_OPCODE = (31u << OPCODE_SHIFT | 654u << 1), 669 TEND_OPCODE = (31u << OPCODE_SHIFT | 686u << 1), 670 TABORT_OPCODE = (31u << OPCODE_SHIFT | 910u << 1), 671 TABORTWC_OPCODE = (31u << OPCODE_SHIFT | 782u << 1), 672 TABORTWCI_OPCODE = (31u << OPCODE_SHIFT | 846u << 1), 673 TABORTDC_OPCODE = (31u << OPCODE_SHIFT | 814u << 1), 674 TABORTDCI_OPCODE = (31u << OPCODE_SHIFT | 878u << 1), 675 TSR_OPCODE = (31u << OPCODE_SHIFT | 750u << 1), 676 TCHECK_OPCODE = (31u << OPCODE_SHIFT | 718u << 1), 677 678 // Icache and dcache related instructions 679 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1), 680 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1), 681 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1), 682 DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1), 683 684 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1), 685 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1), 686 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1), 687 688 // Instruction synchronization 689 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1), 690 // Memory barriers 691 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1), 692 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1), 693 694 // Wait instructions for polling. 695 WAIT_OPCODE = (31u << OPCODE_SHIFT | 62u << 1), 696 697 // Trap instructions 698 TDI_OPCODE = (2u << OPCODE_SHIFT), 699 TWI_OPCODE = (3u << OPCODE_SHIFT), 700 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1), 701 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1), 702 703 // Atomics. 704 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1), 705 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1), 706 LQARX_OPCODE = (31u << OPCODE_SHIFT | 276u << 1), 707 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1), 708 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1), 709 STQCX_OPCODE = (31u << OPCODE_SHIFT | 182u << 1) 710 711 }; 712 713 // Trap instructions TO bits 714 enum trap_to_bits { 715 // single bits 716 traptoLessThanSigned = 1 << 4, // 0, left end 717 traptoGreaterThanSigned = 1 << 3, 718 traptoEqual = 1 << 2, 719 traptoLessThanUnsigned = 1 << 1, 720 traptoGreaterThanUnsigned = 1 << 0, // 4, right end 721 722 // compound ones 723 traptoUnconditional = (traptoLessThanSigned | 724 traptoGreaterThanSigned | 725 traptoEqual | 726 traptoLessThanUnsigned | 727 traptoGreaterThanUnsigned) 728 }; 729 730 // Branch hints BH field 731 enum branch_hint_bh { 732 // bclr cases: 733 bhintbhBCLRisReturn = 0, 734 bhintbhBCLRisNotReturnButSame = 1, 735 bhintbhBCLRisNotPredictable = 3, 736 737 // bcctr cases: 738 bhintbhBCCTRisNotReturnButSame = 0, 739 bhintbhBCCTRisNotPredictable = 3 740 }; 741 742 // Branch prediction hints AT field 743 enum branch_hint_at { 744 bhintatNoHint = 0, // at=00 745 bhintatIsNotTaken = 2, // at=10 746 bhintatIsTaken = 3 // at=11 747 }; 748 749 // Branch prediction hints 750 enum branch_hint_concept { 751 // Use the same encoding as branch_hint_at to simply code. 752 bhintNoHint = bhintatNoHint, 753 bhintIsNotTaken = bhintatIsNotTaken, 754 bhintIsTaken = bhintatIsTaken 755 }; 756 757 // Used in BO field of branch instruction. 758 enum branch_condition { 759 bcondCRbiIs0 = 4, // bo=001at 760 bcondCRbiIs1 = 12, // bo=011at 761 bcondAlways = 20 // bo=10100 762 }; 763 764 // Branch condition with combined prediction hints. 765 enum branch_condition_with_hint { 766 bcondCRbiIs0_bhintNoHint = bcondCRbiIs0 | bhintatNoHint, 767 bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken, 768 bcondCRbiIs0_bhintIsTaken = bcondCRbiIs0 | bhintatIsTaken, 769 bcondCRbiIs1_bhintNoHint = bcondCRbiIs1 | bhintatNoHint, 770 bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken, 771 bcondCRbiIs1_bhintIsTaken = bcondCRbiIs1 | bhintatIsTaken, 772 }; 773 774 // Elemental Memory Barriers (>=Power 8) 775 enum Elemental_Membar_mask_bits { 776 StoreStore = 1 << 0, 777 StoreLoad = 1 << 1, 778 LoadStore = 1 << 2, 779 LoadLoad = 1 << 3 780 }; 781 782 // Branch prediction hints. 783 inline static int add_bhint_to_boint(const int bhint, const int boint) { 784 switch (boint) { 785 case bcondCRbiIs0: 786 case bcondCRbiIs1: 787 // branch_hint and branch_hint_at have same encodings 788 assert( (int)bhintNoHint == (int)bhintatNoHint 789 && (int)bhintIsNotTaken == (int)bhintatIsNotTaken 790 && (int)bhintIsTaken == (int)bhintatIsTaken, 791 "wrong encodings"); 792 assert((bhint & 0x03) == bhint, "wrong encodings"); 793 return (boint & ~0x03) | bhint; 794 case bcondAlways: 795 // no branch_hint 796 return boint; 797 default: 798 ShouldNotReachHere(); 799 return 0; 800 } 801 } 802 803 // Extract bcond from boint. 804 inline static int inv_boint_bcond(const int boint) { 805 int r_bcond = boint & ~0x03; 806 assert(r_bcond == bcondCRbiIs0 || 807 r_bcond == bcondCRbiIs1 || 808 r_bcond == bcondAlways, 809 "bad branch condition"); 810 return r_bcond; 811 } 812 813 // Extract bhint from boint. 814 inline static int inv_boint_bhint(const int boint) { 815 int r_bhint = boint & 0x03; 816 assert(r_bhint == bhintatNoHint || 817 r_bhint == bhintatIsNotTaken || 818 r_bhint == bhintatIsTaken, 819 "bad branch hint"); 820 return r_bhint; 821 } 822 823 // Calculate opposite of given bcond. 824 inline static int opposite_bcond(const int bcond) { 825 switch (bcond) { 826 case bcondCRbiIs0: 827 return bcondCRbiIs1; 828 case bcondCRbiIs1: 829 return bcondCRbiIs0; 830 default: 831 ShouldNotReachHere(); 832 return 0; 833 } 834 } 835 836 // Calculate opposite of given bhint. 837 inline static int opposite_bhint(const int bhint) { 838 switch (bhint) { 839 case bhintatNoHint: 840 return bhintatNoHint; 841 case bhintatIsNotTaken: 842 return bhintatIsTaken; 843 case bhintatIsTaken: 844 return bhintatIsNotTaken; 845 default: 846 ShouldNotReachHere(); 847 return 0; 848 } 849 } 850 851 // PPC branch instructions 852 enum ppcops { 853 b_op = 18, 854 bc_op = 16, 855 bcr_op = 19 856 }; 857 858 enum Condition { 859 negative = 0, 860 less = 0, 861 positive = 1, 862 greater = 1, 863 zero = 2, 864 equal = 2, 865 summary_overflow = 3, 866 }; 867 868 public: 869 // Helper functions for groups of instructions 870 871 enum Predict { pt = 1, pn = 0 }; // pt = predict taken 872 873 // Instruction must start at passed address. 874 static int instr_len(unsigned char *instr) { return BytesPerInstWord; } 875 876 // longest instructions 877 static int instr_maxlen() { return BytesPerInstWord; } 878 879 // Test if x is within signed immediate range for nbits. 880 static bool is_simm(int x, unsigned int nbits) { 881 assert(0 < nbits && nbits < 32, "out of bounds"); 882 const int min = -(((int)1) << nbits-1); 883 const int maxplus1 = (((int)1) << nbits-1); 884 return min <= x && x < maxplus1; 885 } 886 887 static bool is_simm(jlong x, unsigned int nbits) { 888 assert(0 < nbits && nbits < 64, "out of bounds"); 889 const jlong min = -(((jlong)1) << nbits-1); 890 const jlong maxplus1 = (((jlong)1) << nbits-1); 891 return min <= x && x < maxplus1; 892 } 893 894 // Test if x is within unsigned immediate range for nbits. 895 static bool is_uimm(int x, unsigned int nbits) { 896 assert(0 < nbits && nbits < 32, "out of bounds"); 897 const unsigned int maxplus1 = (((unsigned int)1) << nbits); 898 return (unsigned int)x < maxplus1; 899 } 900 901 static bool is_uimm(jlong x, unsigned int nbits) { 902 assert(0 < nbits && nbits < 64, "out of bounds"); 903 const julong maxplus1 = (((julong)1) << nbits); 904 return (julong)x < maxplus1; 905 } 906 907 protected: 908 // helpers 909 910 // X is supposed to fit in a field "nbits" wide 911 // and be sign-extended. Check the range. 912 static void assert_signed_range(intptr_t x, int nbits) { 913 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)), 914 "value out of range"); 915 } 916 917 static void assert_signed_word_disp_range(intptr_t x, int nbits) { 918 assert((x & 3) == 0, "not word aligned"); 919 assert_signed_range(x, nbits + 2); 920 } 921 922 static void assert_unsigned_const(int x, int nbits) { 923 assert(juint(x) < juint(1 << nbits), "unsigned constant out of range"); 924 } 925 926 static int fmask(juint hi_bit, juint lo_bit) { 927 assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits"); 928 return (1 << ( hi_bit-lo_bit + 1 )) - 1; 929 } 930 931 // inverse of u_field 932 static int inv_u_field(int x, int hi_bit, int lo_bit) { 933 juint r = juint(x) >> lo_bit; 934 r &= fmask(hi_bit, lo_bit); 935 return int(r); 936 } 937 938 // signed version: extract from field and sign-extend 939 static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) { 940 x = x << (31-hi_bit); 941 x = x >> (31-hi_bit+lo_bit); 942 return x; 943 } 944 945 static int u_field(int x, int hi_bit, int lo_bit) { 946 assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range"); 947 int r = x << lo_bit; 948 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); 949 return r; 950 } 951 952 // Same as u_field for signed values 953 static int s_field(int x, int hi_bit, int lo_bit) { 954 int nbits = hi_bit - lo_bit + 1; 955 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)), 956 "value out of range"); 957 x &= fmask(hi_bit, lo_bit); 958 int r = x << lo_bit; 959 return r; 960 } 961 962 // inv_op for ppc instructions 963 static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); } 964 965 // Determine target address from li, bd field of branch instruction. 966 static intptr_t inv_li_field(int x) { 967 intptr_t r = inv_s_field_ppc(x, 25, 2); 968 r = (r << 2); 969 return r; 970 } 971 static intptr_t inv_bd_field(int x, intptr_t pos) { 972 intptr_t r = inv_s_field_ppc(x, 15, 2); 973 r = (r << 2) + pos; 974 return r; 975 } 976 977 #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit)) 978 #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit)) 979 // Extract instruction fields from instruction words. 980 public: 981 static int inv_ra_field(int x) { return inv_opp_u_field(x, 15, 11); } 982 static int inv_rb_field(int x) { return inv_opp_u_field(x, 20, 16); } 983 static int inv_rt_field(int x) { return inv_opp_u_field(x, 10, 6); } 984 static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); } 985 static int inv_rs_field(int x) { return inv_opp_u_field(x, 10, 6); } 986 // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0. 987 // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0. 988 static int inv_ds_field(int x) { return inv_opp_s_field(x, 29, 16) << 2; } 989 static int inv_d1_field(int x) { return inv_opp_s_field(x, 31, 16); } 990 static int inv_si_field(int x) { return inv_opp_s_field(x, 31, 16); } 991 static int inv_to_field(int x) { return inv_opp_u_field(x, 10, 6); } 992 static int inv_lk_field(int x) { return inv_opp_u_field(x, 31, 31); } 993 static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); } 994 static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); } 995 996 #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit)) 997 #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit)) 998 999 // instruction fields 1000 static int aa( int x) { return opp_u_field(x, 30, 30); } 1001 static int ba( int x) { return opp_u_field(x, 15, 11); } 1002 static int bb( int x) { return opp_u_field(x, 20, 16); } 1003 static int bc( int x) { return opp_u_field(x, 25, 21); } 1004 static int bd( int x) { return opp_s_field(x, 29, 16); } 1005 static int bf( ConditionRegister cr) { return bf(cr->encoding()); } 1006 static int bf( int x) { return opp_u_field(x, 8, 6); } 1007 static int bfa(ConditionRegister cr) { return bfa(cr->encoding()); } 1008 static int bfa( int x) { return opp_u_field(x, 13, 11); } 1009 static int bh( int x) { return opp_u_field(x, 20, 19); } 1010 static int bi( int x) { return opp_u_field(x, 15, 11); } 1011 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; } 1012 static int bo( int x) { return opp_u_field(x, 10, 6); } 1013 static int bt( int x) { return opp_u_field(x, 10, 6); } 1014 static int d1( int x) { return opp_s_field(x, 31, 16); } 1015 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); } 1016 static int eh( int x) { return opp_u_field(x, 31, 31); } 1017 static int flm( int x) { return opp_u_field(x, 14, 7); } 1018 static int fra( FloatRegister r) { return fra(r->encoding());} 1019 static int frb( FloatRegister r) { return frb(r->encoding());} 1020 static int frc( FloatRegister r) { return frc(r->encoding());} 1021 static int frs( FloatRegister r) { return frs(r->encoding());} 1022 static int frt( FloatRegister r) { return frt(r->encoding());} 1023 static int fra( int x) { return opp_u_field(x, 15, 11); } 1024 static int frb( int x) { return opp_u_field(x, 20, 16); } 1025 static int frc( int x) { return opp_u_field(x, 25, 21); } 1026 static int frs( int x) { return opp_u_field(x, 10, 6); } 1027 static int frt( int x) { return opp_u_field(x, 10, 6); } 1028 static int fxm( int x) { return opp_u_field(x, 19, 12); } 1029 static int l10( int x) { return opp_u_field(x, 10, 10); } 1030 static int l15( int x) { return opp_u_field(x, 15, 15); } 1031 static int l910( int x) { return opp_u_field(x, 10, 9); } 1032 static int e1215( int x) { return opp_u_field(x, 15, 12); } 1033 static int lev( int x) { return opp_u_field(x, 26, 20); } 1034 static int li( int x) { return opp_s_field(x, 29, 6); } 1035 static int lk( int x) { return opp_u_field(x, 31, 31); } 1036 static int mb2125( int x) { return opp_u_field(x, 25, 21); } 1037 static int me2630( int x) { return opp_u_field(x, 30, 26); } 1038 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); } 1039 static int me2126( int x) { return mb2126(x); } 1040 static int nb( int x) { return opp_u_field(x, 20, 16); } 1041 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes 1042 static int oe( int x) { return opp_u_field(x, 21, 21); } 1043 static int ra( Register r) { return ra(r->encoding()); } 1044 static int ra( int x) { return opp_u_field(x, 15, 11); } 1045 static int rb( Register r) { return rb(r->encoding()); } 1046 static int rb( int x) { return opp_u_field(x, 20, 16); } 1047 static int rc( int x) { return opp_u_field(x, 31, 31); } 1048 static int rs( Register r) { return rs(r->encoding()); } 1049 static int rs( int x) { return opp_u_field(x, 10, 6); } 1050 // we don't want to use R0 in memory accesses, because it has value `0' then 1051 static int ra0mem( Register r) { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); } 1052 static int ra0mem( int x) { assert(x != 0, "cannot use register 0 in memory access"); return ra(x); } 1053 1054 // register r is target 1055 static int rt( Register r) { return rs(r); } 1056 static int rt( int x) { return rs(x); } 1057 static int rta( Register r) { return ra(r); } 1058 static int rta0mem( Register r) { rta(r); return ra0mem(r); } 1059 1060 static int sh1620( int x) { return opp_u_field(x, 20, 16); } 1061 static int sh30( int x) { return opp_u_field(x, 30, 30); } 1062 static int sh162030( int x) { return sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); } 1063 static int si( int x) { return opp_s_field(x, 31, 16); } 1064 static int spr( int x) { return opp_u_field(x, 20, 11); } 1065 static int sr( int x) { return opp_u_field(x, 15, 12); } 1066 static int tbr( int x) { return opp_u_field(x, 20, 11); } 1067 static int th( int x) { return opp_u_field(x, 10, 7); } 1068 static int thct( int x) { assert((x&8) == 0, "must be valid cache specification"); return th(x); } 1069 static int thds( int x) { assert((x&8) == 8, "must be valid stream specification"); return th(x); } 1070 static int to( int x) { return opp_u_field(x, 10, 6); } 1071 static int u( int x) { return opp_u_field(x, 19, 16); } 1072 static int ui( int x) { return opp_u_field(x, 31, 16); } 1073 1074 // Support vector instructions for >= Power6. 1075 static int vra( int x) { return opp_u_field(x, 15, 11); } 1076 static int vrb( int x) { return opp_u_field(x, 20, 16); } 1077 static int vrc( int x) { return opp_u_field(x, 25, 21); } 1078 static int vrs( int x) { return opp_u_field(x, 10, 6); } 1079 static int vrt( int x) { return opp_u_field(x, 10, 6); } 1080 1081 static int vra( VectorRegister r) { return vra(r->encoding());} 1082 static int vrb( VectorRegister r) { return vrb(r->encoding());} 1083 static int vrc( VectorRegister r) { return vrc(r->encoding());} 1084 static int vrs( VectorRegister r) { return vrs(r->encoding());} 1085 static int vrt( VectorRegister r) { return vrt(r->encoding());} 1086 1087 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions 1088 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions 1089 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction 1090 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions 1091 1092 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes 1093 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes 1094 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes 1095 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes 1096 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes 1097 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes 1098 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes 1099 1100 protected: 1101 // Compute relative address for branch. 1102 static intptr_t disp(intptr_t x, intptr_t off) { 1103 int xx = x - off; 1104 xx = xx >> 2; 1105 return xx; 1106 } 1107 1108 public: 1109 // signed immediate, in low bits, nbits long 1110 static int simm(int x, int nbits) { 1111 assert_signed_range(x, nbits); 1112 return x & ((1 << nbits) - 1); 1113 } 1114 1115 // unsigned immediate, in low bits, nbits long 1116 static int uimm(int x, int nbits) { 1117 assert_unsigned_const(x, nbits); 1118 return x & ((1 << nbits) - 1); 1119 } 1120 1121 static void set_imm(int* instr, short s) { 1122 // imm is always in the lower 16 bits of the instruction, 1123 // so this is endian-neutral. Same for the get_imm below. 1124 uint32_t w = *(uint32_t *)instr; 1125 *instr = (int)((w & ~0x0000FFFF) | (s & 0x0000FFFF)); 1126 } 1127 1128 static int get_imm(address a, int instruction_number) { 1129 return (short)((int *)a)[instruction_number]; 1130 } 1131 1132 static inline int hi16_signed( int x) { return (int)(int16_t)(x >> 16); } 1133 static inline int lo16_unsigned(int x) { return x & 0xffff; } 1134 1135 protected: 1136 1137 // Extract the top 32 bits in a 64 bit word. 1138 static int32_t hi32(int64_t x) { 1139 int32_t r = int32_t((uint64_t)x >> 32); 1140 return r; 1141 } 1142 1143 public: 1144 1145 static inline unsigned int align_addr(unsigned int addr, unsigned int a) { 1146 return ((addr + (a - 1)) & ~(a - 1)); 1147 } 1148 1149 static inline bool is_aligned(unsigned int addr, unsigned int a) { 1150 return (0 == addr % a); 1151 } 1152 1153 void flush() { 1154 AbstractAssembler::flush(); 1155 } 1156 1157 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32 1158 inline void emit_data(int); 1159 inline void emit_data(int, RelocationHolder const&); 1160 inline void emit_data(int, relocInfo::relocType rtype); 1161 1162 // Emit an address. 1163 inline address emit_addr(const address addr = NULL); 1164 1165#if !defined(ABI_ELFv2) 1166 // Emit a function descriptor with the specified entry point, TOC, 1167 // and ENV. If the entry point is NULL, the descriptor will point 1168 // just past the descriptor. 1169 // Use values from friend functions as defaults. 1170 inline address emit_fd(address entry = NULL, 1171 address toc = (address) FunctionDescriptor::friend_toc, 1172 address env = (address) FunctionDescriptor::friend_env); 1173#endif 1174 1175 ///////////////////////////////////////////////////////////////////////////////////// 1176 // PPC instructions 1177 ///////////////////////////////////////////////////////////////////////////////////// 1178 1179 // Memory instructions use r0 as hard coded 0, e.g. to simulate loading 1180 // immediates. The normal instruction encoders enforce that r0 is not 1181 // passed to them. Use either extended mnemonics encoders or the special ra0 1182 // versions. 1183 1184 // Issue an illegal instruction. 1185 inline void illtrap(); 1186 static inline bool is_illtrap(int x); 1187 1188 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions 1189 inline void addi( Register d, Register a, int si16); 1190 inline void addis(Register d, Register a, int si16); 1191 private: 1192 inline void addi_r0ok( Register d, Register a, int si16); 1193 inline void addis_r0ok(Register d, Register a, int si16); 1194 public: 1195 inline void addic_( Register d, Register a, int si16); 1196 inline void subfic( Register d, Register a, int si16); 1197 inline void add( Register d, Register a, Register b); 1198 inline void add_( Register d, Register a, Register b); 1199 inline void subf( Register d, Register a, Register b); // d = b - a "Sub_from", as in ppc spec. 1200 inline void sub( Register d, Register a, Register b); // d = a - b Swap operands of subf for readability. 1201 inline void subf_( Register d, Register a, Register b); 1202 inline void addc( Register d, Register a, Register b); 1203 inline void addc_( Register d, Register a, Register b); 1204 inline void subfc( Register d, Register a, Register b); 1205 inline void subfc_( Register d, Register a, Register b); 1206 inline void adde( Register d, Register a, Register b); 1207 inline void adde_( Register d, Register a, Register b); 1208 inline void subfe( Register d, Register a, Register b); 1209 inline void subfe_( Register d, Register a, Register b); 1210 inline void addme( Register d, Register a); 1211 inline void addme_( Register d, Register a); 1212 inline void subfme( Register d, Register a); 1213 inline void subfme_(Register d, Register a); 1214 inline void addze( Register d, Register a); 1215 inline void addze_( Register d, Register a); 1216 inline void subfze( Register d, Register a); 1217 inline void subfze_(Register d, Register a); 1218 inline void neg( Register d, Register a); 1219 inline void neg_( Register d, Register a); 1220 inline void mulli( Register d, Register a, int si16); 1221 inline void mulld( Register d, Register a, Register b); 1222 inline void mulld_( Register d, Register a, Register b); 1223 inline void mullw( Register d, Register a, Register b); 1224 inline void mullw_( Register d, Register a, Register b); 1225 inline void mulhw( Register d, Register a, Register b); 1226 inline void mulhw_( Register d, Register a, Register b); 1227 inline void mulhd( Register d, Register a, Register b); 1228 inline void mulhd_( Register d, Register a, Register b); 1229 inline void mulhdu( Register d, Register a, Register b); 1230 inline void mulhdu_(Register d, Register a, Register b); 1231 inline void divd( Register d, Register a, Register b); 1232 inline void divd_( Register d, Register a, Register b); 1233 inline void divw( Register d, Register a, Register b); 1234 inline void divw_( Register d, Register a, Register b); 1235 1236 // Fixed-Point Arithmetic Instructions with Overflow detection 1237 inline void addo( Register d, Register a, Register b); 1238 inline void addo_( Register d, Register a, Register b); 1239 inline void subfo( Register d, Register a, Register b); 1240 inline void subfo_( Register d, Register a, Register b); 1241 inline void addco( Register d, Register a, Register b); 1242 inline void addco_( Register d, Register a, Register b); 1243 inline void subfco( Register d, Register a, Register b); 1244 inline void subfco_( Register d, Register a, Register b); 1245 inline void addeo( Register d, Register a, Register b); 1246 inline void addeo_( Register d, Register a, Register b); 1247 inline void subfeo( Register d, Register a, Register b); 1248 inline void subfeo_( Register d, Register a, Register b); 1249 inline void addmeo( Register d, Register a); 1250 inline void addmeo_( Register d, Register a); 1251 inline void subfmeo( Register d, Register a); 1252 inline void subfmeo_(Register d, Register a); 1253 inline void addzeo( Register d, Register a); 1254 inline void addzeo_( Register d, Register a); 1255 inline void subfzeo( Register d, Register a); 1256 inline void subfzeo_(Register d, Register a); 1257 inline void nego( Register d, Register a); 1258 inline void nego_( Register d, Register a); 1259 inline void mulldo( Register d, Register a, Register b); 1260 inline void mulldo_( Register d, Register a, Register b); 1261 inline void mullwo( Register d, Register a, Register b); 1262 inline void mullwo_( Register d, Register a, Register b); 1263 inline void divdo( Register d, Register a, Register b); 1264 inline void divdo_( Register d, Register a, Register b); 1265 inline void divwo( Register d, Register a, Register b); 1266 inline void divwo_( Register d, Register a, Register b); 1267 1268 // extended mnemonics 1269 inline void li( Register d, int si16); 1270 inline void lis( Register d, int si16); 1271 inline void addir(Register d, int si16, Register a); 1272 1273 static bool is_addi(int x) { 1274 return ADDI_OPCODE == (x & ADDI_OPCODE_MASK); 1275 } 1276 static bool is_addis(int x) { 1277 return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK); 1278 } 1279 static bool is_bxx(int x) { 1280 return BXX_OPCODE == (x & BXX_OPCODE_MASK); 1281 } 1282 static bool is_b(int x) { 1283 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0; 1284 } 1285 static bool is_bl(int x) { 1286 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1; 1287 } 1288 static bool is_bcxx(int x) { 1289 return BCXX_OPCODE == (x & BCXX_OPCODE_MASK); 1290 } 1291 static bool is_bxx_or_bcxx(int x) { 1292 return is_bxx(x) || is_bcxx(x); 1293 } 1294 static bool is_bctrl(int x) { 1295 return x == 0x4e800421; 1296 } 1297 static bool is_bctr(int x) { 1298 return x == 0x4e800420; 1299 } 1300 static bool is_bclr(int x) { 1301 return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK); 1302 } 1303 static bool is_li(int x) { 1304 return is_addi(x) && inv_ra_field(x)==0; 1305 } 1306 static bool is_lis(int x) { 1307 return is_addis(x) && inv_ra_field(x)==0; 1308 } 1309 static bool is_mtctr(int x) { 1310 return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK); 1311 } 1312 static bool is_ld(int x) { 1313 return LD_OPCODE == (x & LD_OPCODE_MASK); 1314 } 1315 static bool is_std(int x) { 1316 return STD_OPCODE == (x & STD_OPCODE_MASK); 1317 } 1318 static bool is_stdu(int x) { 1319 return STDU_OPCODE == (x & STDU_OPCODE_MASK); 1320 } 1321 static bool is_stdx(int x) { 1322 return STDX_OPCODE == (x & STDX_OPCODE_MASK); 1323 } 1324 static bool is_stdux(int x) { 1325 return STDUX_OPCODE == (x & STDUX_OPCODE_MASK); 1326 } 1327 static bool is_stwx(int x) { 1328 return STWX_OPCODE == (x & STWX_OPCODE_MASK); 1329 } 1330 static bool is_stwux(int x) { 1331 return STWUX_OPCODE == (x & STWUX_OPCODE_MASK); 1332 } 1333 static bool is_stw(int x) { 1334 return STW_OPCODE == (x & STW_OPCODE_MASK); 1335 } 1336 static bool is_stwu(int x) { 1337 return STWU_OPCODE == (x & STWU_OPCODE_MASK); 1338 } 1339 static bool is_ori(int x) { 1340 return ORI_OPCODE == (x & ORI_OPCODE_MASK); 1341 }; 1342 static bool is_oris(int x) { 1343 return ORIS_OPCODE == (x & ORIS_OPCODE_MASK); 1344 }; 1345 static bool is_rldicr(int x) { 1346 return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK)); 1347 }; 1348 static bool is_nop(int x) { 1349 return x == 0x60000000; 1350 } 1351 // endgroup opcode for Power6 1352 static bool is_endgroup(int x) { 1353 return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0; 1354 } 1355 1356 1357 private: 1358 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions 1359 inline void cmpi( ConditionRegister bf, int l, Register a, int si16); 1360 inline void cmp( ConditionRegister bf, int l, Register a, Register b); 1361 inline void cmpli(ConditionRegister bf, int l, Register a, int ui16); 1362 inline void cmpl( ConditionRegister bf, int l, Register a, Register b); 1363 1364 public: 1365 // extended mnemonics of Compare Instructions 1366 inline void cmpwi( ConditionRegister crx, Register a, int si16); 1367 inline void cmpdi( ConditionRegister crx, Register a, int si16); 1368 inline void cmpw( ConditionRegister crx, Register a, Register b); 1369 inline void cmpd( ConditionRegister crx, Register a, Register b); 1370 inline void cmplwi(ConditionRegister crx, Register a, int ui16); 1371 inline void cmpldi(ConditionRegister crx, Register a, int ui16); 1372 inline void cmplw( ConditionRegister crx, Register a, Register b); 1373 inline void cmpld( ConditionRegister crx, Register a, Register b); 1374 1375 inline void isel( Register d, Register a, Register b, int bc); 1376 // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value. 1377 inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg); 1378 // Set d = 0 if (cr.cc) equals 1, otherwise b. 1379 inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg); 1380 1381 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions 1382 void andi( Register a, Register s, long ui16); // optimized version 1383 inline void andi_( Register a, Register s, int ui16); 1384 inline void andis_( Register a, Register s, int ui16); 1385 inline void ori( Register a, Register s, int ui16); 1386 inline void oris( Register a, Register s, int ui16); 1387 inline void xori( Register a, Register s, int ui16); 1388 inline void xoris( Register a, Register s, int ui16); 1389 inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword 1390 inline void and_( Register a, Register s, Register b); 1391 // Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a 1392 // SMT-priority change instruction (see SMT instructions below). 1393 inline void or_unchecked(Register a, Register s, Register b); 1394 inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword 1395 inline void or_( Register a, Register s, Register b); 1396 inline void xorr( Register a, Register s, Register b); // suffixed by 'r' as 'xor' is C++ keyword 1397 inline void xor_( Register a, Register s, Register b); 1398 inline void nand( Register a, Register s, Register b); 1399 inline void nand_( Register a, Register s, Register b); 1400 inline void nor( Register a, Register s, Register b); 1401 inline void nor_( Register a, Register s, Register b); 1402 inline void andc( Register a, Register s, Register b); 1403 inline void andc_( Register a, Register s, Register b); 1404 inline void orc( Register a, Register s, Register b); 1405 inline void orc_( Register a, Register s, Register b); 1406 inline void extsb( Register a, Register s); 1407 inline void extsb_( Register a, Register s); 1408 inline void extsh( Register a, Register s); 1409 inline void extsh_( Register a, Register s); 1410 inline void extsw( Register a, Register s); 1411 inline void extsw_( Register a, Register s); 1412 1413 // extended mnemonics 1414 inline void nop(); 1415 // NOP for FP and BR units (different versions to allow them to be in one group) 1416 inline void fpnop0(); 1417 inline void fpnop1(); 1418 inline void brnop0(); 1419 inline void brnop1(); 1420 inline void brnop2(); 1421 1422 inline void mr( Register d, Register s); 1423 inline void ori_opt( Register d, int ui16); 1424 inline void oris_opt(Register d, int ui16); 1425 1426 // endgroup opcode for Power6 1427 inline void endgroup(); 1428 1429 // count instructions 1430 inline void cntlzw( Register a, Register s); 1431 inline void cntlzw_( Register a, Register s); 1432 inline void cntlzd( Register a, Register s); 1433 inline void cntlzd_( Register a, Register s); 1434 1435 // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions 1436 inline void sld( Register a, Register s, Register b); 1437 inline void sld_( Register a, Register s, Register b); 1438 inline void slw( Register a, Register s, Register b); 1439 inline void slw_( Register a, Register s, Register b); 1440 inline void srd( Register a, Register s, Register b); 1441 inline void srd_( Register a, Register s, Register b); 1442 inline void srw( Register a, Register s, Register b); 1443 inline void srw_( Register a, Register s, Register b); 1444 inline void srad( Register a, Register s, Register b); 1445 inline void srad_( Register a, Register s, Register b); 1446 inline void sraw( Register a, Register s, Register b); 1447 inline void sraw_( Register a, Register s, Register b); 1448 inline void sradi( Register a, Register s, int sh6); 1449 inline void sradi_( Register a, Register s, int sh6); 1450 inline void srawi( Register a, Register s, int sh5); 1451 inline void srawi_( Register a, Register s, int sh5); 1452 1453 // extended mnemonics for Shift Instructions 1454 inline void sldi( Register a, Register s, int sh6); 1455 inline void sldi_( Register a, Register s, int sh6); 1456 inline void slwi( Register a, Register s, int sh5); 1457 inline void slwi_( Register a, Register s, int sh5); 1458 inline void srdi( Register a, Register s, int sh6); 1459 inline void srdi_( Register a, Register s, int sh6); 1460 inline void srwi( Register a, Register s, int sh5); 1461 inline void srwi_( Register a, Register s, int sh5); 1462 1463 inline void clrrdi( Register a, Register s, int ui6); 1464 inline void clrrdi_( Register a, Register s, int ui6); 1465 inline void clrldi( Register a, Register s, int ui6); 1466 inline void clrldi_( Register a, Register s, int ui6); 1467 inline void clrlsldi(Register a, Register s, int clrl6, int shl6); 1468 inline void clrlsldi_(Register a, Register s, int clrl6, int shl6); 1469 inline void extrdi( Register a, Register s, int n, int b); 1470 // testbit with condition register 1471 inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6); 1472 1473 // rotate instructions 1474 inline void rotldi( Register a, Register s, int n); 1475 inline void rotrdi( Register a, Register s, int n); 1476 inline void rotlwi( Register a, Register s, int n); 1477 inline void rotrwi( Register a, Register s, int n); 1478 1479 // Rotate Instructions 1480 inline void rldic( Register a, Register s, int sh6, int mb6); 1481 inline void rldic_( Register a, Register s, int sh6, int mb6); 1482 inline void rldicr( Register a, Register s, int sh6, int mb6); 1483 inline void rldicr_( Register a, Register s, int sh6, int mb6); 1484 inline void rldicl( Register a, Register s, int sh6, int mb6); 1485 inline void rldicl_( Register a, Register s, int sh6, int mb6); 1486 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5); 1487 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5); 1488 inline void rldimi( Register a, Register s, int sh6, int mb6); 1489 inline void rldimi_( Register a, Register s, int sh6, int mb6); 1490 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5); 1491 inline void insrdi( Register a, Register s, int n, int b); 1492 inline void insrwi( Register a, Register s, int n, int b); 1493 1494 // PPC 1, section 3.3.2 Fixed-Point Load Instructions 1495 // 4 bytes 1496 inline void lwzx( Register d, Register s1, Register s2); 1497 inline void lwz( Register d, int si16, Register s1); 1498 inline void lwzu( Register d, int si16, Register s1); 1499 1500 // 4 bytes 1501 inline void lwax( Register d, Register s1, Register s2); 1502 inline void lwa( Register d, int si16, Register s1); 1503 1504 // 4 bytes reversed 1505 inline void lwbrx( Register d, Register s1, Register s2); 1506 1507 // 2 bytes 1508 inline void lhzx( Register d, Register s1, Register s2); 1509 inline void lhz( Register d, int si16, Register s1); 1510 inline void lhzu( Register d, int si16, Register s1); 1511 1512 // 2 bytes reversed 1513 inline void lhbrx( Register d, Register s1, Register s2); 1514 1515 // 2 bytes 1516 inline void lhax( Register d, Register s1, Register s2); 1517 inline void lha( Register d, int si16, Register s1); 1518 inline void lhau( Register d, int si16, Register s1); 1519 1520 // 1 byte 1521 inline void lbzx( Register d, Register s1, Register s2); 1522 inline void lbz( Register d, int si16, Register s1); 1523 inline void lbzu( Register d, int si16, Register s1); 1524 1525 // 8 bytes 1526 inline void ldx( Register d, Register s1, Register s2); 1527 inline void ld( Register d, int si16, Register s1); 1528 inline void ldu( Register d, int si16, Register s1); 1529 1530 // PPC 1, section 3.3.3 Fixed-Point Store Instructions 1531 inline void stwx( Register d, Register s1, Register s2); 1532 inline void stw( Register d, int si16, Register s1); 1533 inline void stwu( Register d, int si16, Register s1); 1534 1535 inline void sthx( Register d, Register s1, Register s2); 1536 inline void sth( Register d, int si16, Register s1); 1537 inline void sthu( Register d, int si16, Register s1); 1538 1539 inline void stbx( Register d, Register s1, Register s2); 1540 inline void stb( Register d, int si16, Register s1); 1541 inline void stbu( Register d, int si16, Register s1); 1542 1543 inline void stdx( Register d, Register s1, Register s2); 1544 inline void std( Register d, int si16, Register s1); 1545 inline void stdu( Register d, int si16, Register s1); 1546 inline void stdux(Register s, Register a, Register b); 1547 1548 // PPC 1, section 3.3.13 Move To/From System Register Instructions 1549 inline void mtlr( Register s1); 1550 inline void mflr( Register d); 1551 inline void mtctr(Register s1); 1552 inline void mfctr(Register d); 1553 inline void mtcrf(int fxm, Register s); 1554 inline void mfcr( Register d); 1555 inline void mcrf( ConditionRegister crd, ConditionRegister cra); 1556 inline void mtcr( Register s); 1557 1558 // Special purpose registers 1559 // Exception Register 1560 inline void mtxer(Register s1); 1561 inline void mfxer(Register d); 1562 // Vector Register Save Register 1563 inline void mtvrsave(Register s1); 1564 inline void mfvrsave(Register d); 1565 // Timebase 1566 inline void mftb(Register d); 1567 // Introduced with Power 8: 1568 // Data Stream Control Register 1569 inline void mtdscr(Register s1); 1570 inline void mfdscr(Register d ); 1571 // Transactional Memory Registers 1572 inline void mftfhar(Register d); 1573 inline void mftfiar(Register d); 1574 inline void mftexasr(Register d); 1575 inline void mftexasru(Register d); 1576 1577 // TEXASR bit description 1578 enum transaction_failure_reason { 1579 // Upper half (TEXASRU): 1580 tm_failure_persistent = 7, // The failure is likely to recur on each execution. 1581 tm_disallowed = 8, // The instruction is not permitted. 1582 tm_nesting_of = 9, // The maximum transaction level was exceeded. 1583 tm_footprint_of = 10, // The tracking limit for transactional storage accesses was exceeded. 1584 tm_self_induced_cf = 11, // A self-induced conflict occurred in Suspended state. 1585 tm_non_trans_cf = 12, // A conflict occurred with a non-transactional access by another processor. 1586 tm_trans_cf = 13, // A conflict occurred with another transaction. 1587 tm_translation_cf = 14, // A conflict occurred with a TLB invalidation. 1588 tm_inst_fetch_cf = 16, // An instruction fetch was performed from a block that was previously written transactionally. 1589 tm_tabort = 31, // Termination was caused by the execution of an abort instruction. 1590 // Lower half: 1591 tm_suspended = 32, // Failure was recorded in Suspended state. 1592 tm_failure_summary = 36, // Failure has been detected and recorded. 1593 tm_tfiar_exact = 37, // Value in the TFIAR is exact. 1594 tm_rot = 38, // Rollback-only transaction. 1595 }; 1596 1597 // PPC 1, section 2.4.1 Branch Instructions 1598 inline void b( address a, relocInfo::relocType rt = relocInfo::none); 1599 inline void b( Label& L); 1600 inline void bl( address a, relocInfo::relocType rt = relocInfo::none); 1601 inline void bl( Label& L); 1602 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none); 1603 inline void bc( int boint, int biint, Label& L); 1604 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none); 1605 inline void bcl(int boint, int biint, Label& L); 1606 1607 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none); 1608 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none); 1609 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame, 1610 relocInfo::relocType rt = relocInfo::none); 1611 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn, 1612 relocInfo::relocType rt = relocInfo::none); 1613 1614 // helper function for b, bcxx 1615 inline bool is_within_range_of_b(address a, address pc); 1616 inline bool is_within_range_of_bcxx(address a, address pc); 1617 1618 // get the destination of a bxx branch (b, bl, ba, bla) 1619 static inline address bxx_destination(address baddr); 1620 static inline address bxx_destination(int instr, address pc); 1621 static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos); 1622 1623 // extended mnemonics for branch instructions 1624 inline void blt(ConditionRegister crx, Label& L); 1625 inline void bgt(ConditionRegister crx, Label& L); 1626 inline void beq(ConditionRegister crx, Label& L); 1627 inline void bso(ConditionRegister crx, Label& L); 1628 inline void bge(ConditionRegister crx, Label& L); 1629 inline void ble(ConditionRegister crx, Label& L); 1630 inline void bne(ConditionRegister crx, Label& L); 1631 inline void bns(ConditionRegister crx, Label& L); 1632 1633 // Branch instructions with static prediction hints. 1634 inline void blt_predict_taken( ConditionRegister crx, Label& L); 1635 inline void bgt_predict_taken( ConditionRegister crx, Label& L); 1636 inline void beq_predict_taken( ConditionRegister crx, Label& L); 1637 inline void bso_predict_taken( ConditionRegister crx, Label& L); 1638 inline void bge_predict_taken( ConditionRegister crx, Label& L); 1639 inline void ble_predict_taken( ConditionRegister crx, Label& L); 1640 inline void bne_predict_taken( ConditionRegister crx, Label& L); 1641 inline void bns_predict_taken( ConditionRegister crx, Label& L); 1642 inline void blt_predict_not_taken(ConditionRegister crx, Label& L); 1643 inline void bgt_predict_not_taken(ConditionRegister crx, Label& L); 1644 inline void beq_predict_not_taken(ConditionRegister crx, Label& L); 1645 inline void bso_predict_not_taken(ConditionRegister crx, Label& L); 1646 inline void bge_predict_not_taken(ConditionRegister crx, Label& L); 1647 inline void ble_predict_not_taken(ConditionRegister crx, Label& L); 1648 inline void bne_predict_not_taken(ConditionRegister crx, Label& L); 1649 inline void bns_predict_not_taken(ConditionRegister crx, Label& L); 1650 1651 // for use in conjunction with testbitdi: 1652 inline void btrue( ConditionRegister crx, Label& L); 1653 inline void bfalse(ConditionRegister crx, Label& L); 1654 1655 inline void bltl(ConditionRegister crx, Label& L); 1656 inline void bgtl(ConditionRegister crx, Label& L); 1657 inline void beql(ConditionRegister crx, Label& L); 1658 inline void bsol(ConditionRegister crx, Label& L); 1659 inline void bgel(ConditionRegister crx, Label& L); 1660 inline void blel(ConditionRegister crx, Label& L); 1661 inline void bnel(ConditionRegister crx, Label& L); 1662 inline void bnsl(ConditionRegister crx, Label& L); 1663 1664 // extended mnemonics for Branch Instructions via LR 1665 // We use `blr' for returns. 1666 inline void blr(relocInfo::relocType rt = relocInfo::none); 1667 1668 // extended mnemonics for Branch Instructions with CTR 1669 // bdnz means `decrement CTR and jump to L if CTR is not zero' 1670 inline void bdnz(Label& L); 1671 // Decrement and branch if result is zero. 1672 inline void bdz(Label& L); 1673 // we use `bctr[l]' for jumps/calls in function descriptor glue 1674 // code, e.g. calls to runtime functions 1675 inline void bctr( relocInfo::relocType rt = relocInfo::none); 1676 inline void bctrl(relocInfo::relocType rt = relocInfo::none); 1677 // conditional jumps/branches via CTR 1678 inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1679 inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1680 inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1681 inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1682 1683 // condition register logic instructions 1684 // NOTE: There's a preferred form: d and s2 should point into the same condition register. 1685 inline void crand( int d, int s1, int s2); 1686 inline void crnand(int d, int s1, int s2); 1687 inline void cror( int d, int s1, int s2); 1688 inline void crxor( int d, int s1, int s2); 1689 inline void crnor( int d, int s1, int s2); 1690 inline void creqv( int d, int s1, int s2); 1691 inline void crandc(int d, int s1, int s2); 1692 inline void crorc( int d, int s1, int s2); 1693 1694 // More convenient version. 1695 int condition_register_bit(ConditionRegister cr, Condition c) { 1696 return 4 * (int)(intptr_t)cr + c; 1697 } 1698 void crand( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1699 void crnand(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1700 void cror( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1701 void crxor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1702 void crnor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1703 void creqv( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1704 void crandc(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1705 void crorc( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1706 1707 // icache and dcache related instructions 1708 inline void icbi( Register s1, Register s2); 1709 //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only. 1710 inline void dcbz( Register s1, Register s2); 1711 inline void dcbst( Register s1, Register s2); 1712 inline void dcbf( Register s1, Register s2); 1713 1714 enum ct_cache_specification { 1715 ct_primary_cache = 0, 1716 ct_secondary_cache = 2 1717 }; 1718 // dcache read hint 1719 inline void dcbt( Register s1, Register s2); 1720 inline void dcbtct( Register s1, Register s2, int ct); 1721 inline void dcbtds( Register s1, Register s2, int ds); 1722 // dcache write hint 1723 inline void dcbtst( Register s1, Register s2); 1724 inline void dcbtstct(Register s1, Register s2, int ct); 1725 1726 // machine barrier instructions: 1727 // 1728 // - sync two-way memory barrier, aka fence 1729 // - lwsync orders Store|Store, 1730 // Load|Store, 1731 // Load|Load, 1732 // but not Store|Load 1733 // - eieio orders memory accesses for device memory (only) 1734 // - isync invalidates speculatively executed instructions 1735 // From the Power ISA 2.06 documentation: 1736 // "[...] an isync instruction prevents the execution of 1737 // instructions following the isync until instructions 1738 // preceding the isync have completed, [...]" 1739 // From IBM's AIX assembler reference: 1740 // "The isync [...] instructions causes the processor to 1741 // refetch any instructions that might have been fetched 1742 // prior to the isync instruction. The instruction isync 1743 // causes the processor to wait for all previous instructions 1744 // to complete. Then any instructions already fetched are 1745 // discarded and instruction processing continues in the 1746 // environment established by the previous instructions." 1747 // 1748 // semantic barrier instructions: 1749 // (as defined in orderAccess.hpp) 1750 // 1751 // - release orders Store|Store, (maps to lwsync) 1752 // Load|Store 1753 // - acquire orders Load|Store, (maps to lwsync) 1754 // Load|Load 1755 // - fence orders Store|Store, (maps to sync) 1756 // Load|Store, 1757 // Load|Load, 1758 // Store|Load 1759 // 1760 private: 1761 inline void sync(int l); 1762 public: 1763 inline void sync(); 1764 inline void lwsync(); 1765 inline void ptesync(); 1766 inline void eieio(); 1767 inline void isync(); 1768 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8) 1769 1770 // Wait instructions for polling. Attention: May result in SIGILL. 1771 inline void wait(); 1772 inline void waitrsv(); // >=Power7 1773 1774 // atomics 1775 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0); 1776 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0); 1777 inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0); 1778 inline bool lxarx_hint_exclusive_access(); 1779 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1780 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1781 inline void lqarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1782 inline void stwcx_( Register s, Register a, Register b); 1783 inline void stdcx_( Register s, Register a, Register b); 1784 inline void stqcx_( Register s, Register a, Register b); 1785 1786 // Instructions for adjusting thread priority for simultaneous 1787 // multithreading (SMT) on Power5. 1788 private: 1789 inline void smt_prio_very_low(); 1790 inline void smt_prio_medium_high(); 1791 inline void smt_prio_high(); 1792 1793 public: 1794 inline void smt_prio_low(); 1795 inline void smt_prio_medium_low(); 1796 inline void smt_prio_medium(); 1797 // >= Power7 1798 inline void smt_yield(); 1799 inline void smt_mdoio(); 1800 inline void smt_mdoom(); 1801 // >= Power8 1802 inline void smt_miso(); 1803 1804 // trap instructions 1805 inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur) 1806 // NOT FOR DIRECT USE!! 1807 protected: 1808 inline void tdi_unchecked(int tobits, Register a, int si16); 1809 inline void twi_unchecked(int tobits, Register a, int si16); 1810 inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP 1811 inline void twi( int tobits, Register a, int si16); // asserts UseSIGTRAP 1812 inline void td( int tobits, Register a, Register b); // asserts UseSIGTRAP 1813 inline void tw( int tobits, Register a, Register b); // asserts UseSIGTRAP 1814 1815 static bool is_tdi(int x, int tobits, int ra, int si16) { 1816 return (TDI_OPCODE == (x & TDI_OPCODE_MASK)) 1817 && (tobits == inv_to_field(x)) 1818 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1819 && (si16 == inv_si_field(x)); 1820 } 1821 1822 static bool is_twi(int x, int tobits, int ra, int si16) { 1823 return (TWI_OPCODE == (x & TWI_OPCODE_MASK)) 1824 && (tobits == inv_to_field(x)) 1825 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1826 && (si16 == inv_si_field(x)); 1827 } 1828 1829 static bool is_twi(int x, int tobits, int ra) { 1830 return (TWI_OPCODE == (x & TWI_OPCODE_MASK)) 1831 && (tobits == inv_to_field(x)) 1832 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)); 1833 } 1834 1835 static bool is_td(int x, int tobits, int ra, int rb) { 1836 return (TD_OPCODE == (x & TD_OPCODE_MASK)) 1837 && (tobits == inv_to_field(x)) 1838 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1839 && (rb == -1/*any reg*/ || rb == inv_rb_field(x)); 1840 } 1841 1842 static bool is_tw(int x, int tobits, int ra, int rb) { 1843 return (TW_OPCODE == (x & TW_OPCODE_MASK)) 1844 && (tobits == inv_to_field(x)) 1845 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1846 && (rb == -1/*any reg*/ || rb == inv_rb_field(x)); 1847 } 1848 1849 public: 1850 // PPC floating point instructions 1851 // PPC 1, section 4.6.2 Floating-Point Load Instructions 1852 inline void lfs( FloatRegister d, int si16, Register a); 1853 inline void lfsu( FloatRegister d, int si16, Register a); 1854 inline void lfsx( FloatRegister d, Register a, Register b); 1855 inline void lfd( FloatRegister d, int si16, Register a); 1856 inline void lfdu( FloatRegister d, int si16, Register a); 1857 inline void lfdx( FloatRegister d, Register a, Register b); 1858 1859 // PPC 1, section 4.6.3 Floating-Point Store Instructions 1860 inline void stfs( FloatRegister s, int si16, Register a); 1861 inline void stfsu( FloatRegister s, int si16, Register a); 1862 inline void stfsx( FloatRegister s, Register a, Register b); 1863 inline void stfd( FloatRegister s, int si16, Register a); 1864 inline void stfdu( FloatRegister s, int si16, Register a); 1865 inline void stfdx( FloatRegister s, Register a, Register b); 1866 1867 // PPC 1, section 4.6.4 Floating-Point Move Instructions 1868 inline void fmr( FloatRegister d, FloatRegister b); 1869 inline void fmr_( FloatRegister d, FloatRegister b); 1870 1871 // inline void mffgpr( FloatRegister d, Register b); 1872 // inline void mftgpr( Register d, FloatRegister b); 1873 inline void cmpb( Register a, Register s, Register b); 1874 inline void popcntb(Register a, Register s); 1875 inline void popcntw(Register a, Register s); 1876 inline void popcntd(Register a, Register s); 1877 1878 inline void fneg( FloatRegister d, FloatRegister b); 1879 inline void fneg_( FloatRegister d, FloatRegister b); 1880 inline void fabs( FloatRegister d, FloatRegister b); 1881 inline void fabs_( FloatRegister d, FloatRegister b); 1882 inline void fnabs( FloatRegister d, FloatRegister b); 1883 inline void fnabs_(FloatRegister d, FloatRegister b); 1884 1885 // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions 1886 inline void fadd( FloatRegister d, FloatRegister a, FloatRegister b); 1887 inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b); 1888 inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b); 1889 inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b); 1890 inline void fsub( FloatRegister d, FloatRegister a, FloatRegister b); 1891 inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b); 1892 inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b); 1893 inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b); 1894 inline void fmul( FloatRegister d, FloatRegister a, FloatRegister c); 1895 inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c); 1896 inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c); 1897 inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c); 1898 inline void fdiv( FloatRegister d, FloatRegister a, FloatRegister b); 1899 inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b); 1900 inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b); 1901 inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b); 1902 1903 // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions 1904 inline void frsp( FloatRegister d, FloatRegister b); 1905 inline void fctid( FloatRegister d, FloatRegister b); 1906 inline void fctidz(FloatRegister d, FloatRegister b); 1907 inline void fctiw( FloatRegister d, FloatRegister b); 1908 inline void fctiwz(FloatRegister d, FloatRegister b); 1909 inline void fcfid( FloatRegister d, FloatRegister b); 1910 inline void fcfids(FloatRegister d, FloatRegister b); 1911 1912 // PPC 1, section 4.6.7 Floating-Point Compare Instructions 1913 inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b); 1914 1915 inline void fsqrt( FloatRegister d, FloatRegister b); 1916 inline void fsqrts(FloatRegister d, FloatRegister b); 1917 1918 // Vector instructions for >= Power6. 1919 inline void lvebx( VectorRegister d, Register s1, Register s2); 1920 inline void lvehx( VectorRegister d, Register s1, Register s2); 1921 inline void lvewx( VectorRegister d, Register s1, Register s2); 1922 inline void lvx( VectorRegister d, Register s1, Register s2); 1923 inline void lvxl( VectorRegister d, Register s1, Register s2); 1924 inline void stvebx( VectorRegister d, Register s1, Register s2); 1925 inline void stvehx( VectorRegister d, Register s1, Register s2); 1926 inline void stvewx( VectorRegister d, Register s1, Register s2); 1927 inline void stvx( VectorRegister d, Register s1, Register s2); 1928 inline void stvxl( VectorRegister d, Register s1, Register s2); 1929 inline void lvsl( VectorRegister d, Register s1, Register s2); 1930 inline void lvsr( VectorRegister d, Register s1, Register s2); 1931 inline void vpkpx( VectorRegister d, VectorRegister a, VectorRegister b); 1932 inline void vpkshss( VectorRegister d, VectorRegister a, VectorRegister b); 1933 inline void vpkswss( VectorRegister d, VectorRegister a, VectorRegister b); 1934 inline void vpkshus( VectorRegister d, VectorRegister a, VectorRegister b); 1935 inline void vpkswus( VectorRegister d, VectorRegister a, VectorRegister b); 1936 inline void vpkuhum( VectorRegister d, VectorRegister a, VectorRegister b); 1937 inline void vpkuwum( VectorRegister d, VectorRegister a, VectorRegister b); 1938 inline void vpkuhus( VectorRegister d, VectorRegister a, VectorRegister b); 1939 inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b); 1940 inline void vupkhpx( VectorRegister d, VectorRegister b); 1941 inline void vupkhsb( VectorRegister d, VectorRegister b); 1942 inline void vupkhsh( VectorRegister d, VectorRegister b); 1943 inline void vupklpx( VectorRegister d, VectorRegister b); 1944 inline void vupklsb( VectorRegister d, VectorRegister b); 1945 inline void vupklsh( VectorRegister d, VectorRegister b); 1946 inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b); 1947 inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b); 1948 inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b); 1949 inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b); 1950 inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b); 1951 inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b); 1952 inline void vsplt( VectorRegister d, int ui4, VectorRegister b); 1953 inline void vsplth( VectorRegister d, int ui3, VectorRegister b); 1954 inline void vspltw( VectorRegister d, int ui2, VectorRegister b); 1955 inline void vspltisb( VectorRegister d, int si5); 1956 inline void vspltish( VectorRegister d, int si5); 1957 inline void vspltisw( VectorRegister d, int si5); 1958 inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1959 inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1960 inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b); 1961 inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int si4); 1962 inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b); 1963 inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b); 1964 inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b); 1965 inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b); 1966 inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b); 1967 inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b); 1968 inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b); 1969 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b); 1970 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b); 1971 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b); 1972 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b); 1973 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b); 1974 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b); 1975 inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b); 1976 inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b); 1977 inline void vsubsbs( VectorRegister d, VectorRegister a, VectorRegister b); 1978 inline void vsubsws( VectorRegister d, VectorRegister a, VectorRegister b); 1979 inline void vsububm( VectorRegister d, VectorRegister a, VectorRegister b); 1980 inline void vsubuwm( VectorRegister d, VectorRegister a, VectorRegister b); 1981 inline void vsubuhm( VectorRegister d, VectorRegister a, VectorRegister b); 1982 inline void vsububs( VectorRegister d, VectorRegister a, VectorRegister b); 1983 inline void vsubuws( VectorRegister d, VectorRegister a, VectorRegister b); 1984 inline void vsubuhs( VectorRegister d, VectorRegister a, VectorRegister b); 1985 inline void vmulesb( VectorRegister d, VectorRegister a, VectorRegister b); 1986 inline void vmuleub( VectorRegister d, VectorRegister a, VectorRegister b); 1987 inline void vmulesh( VectorRegister d, VectorRegister a, VectorRegister b); 1988 inline void vmuleuh( VectorRegister d, VectorRegister a, VectorRegister b); 1989 inline void vmulosb( VectorRegister d, VectorRegister a, VectorRegister b); 1990 inline void vmuloub( VectorRegister d, VectorRegister a, VectorRegister b); 1991 inline void vmulosh( VectorRegister d, VectorRegister a, VectorRegister b); 1992 inline void vmulouh( VectorRegister d, VectorRegister a, VectorRegister b); 1993 inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1994 inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c); 1995 inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1996 inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1997 inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1998 inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1999 inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2000 inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2001 inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2002 inline void vsumsws( VectorRegister d, VectorRegister a, VectorRegister b); 2003 inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b); 2004 inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b); 2005 inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b); 2006 inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b); 2007 inline void vavgsb( VectorRegister d, VectorRegister a, VectorRegister b); 2008 inline void vavgsw( VectorRegister d, VectorRegister a, VectorRegister b); 2009 inline void vavgsh( VectorRegister d, VectorRegister a, VectorRegister b); 2010 inline void vavgub( VectorRegister d, VectorRegister a, VectorRegister b); 2011 inline void vavguw( VectorRegister d, VectorRegister a, VectorRegister b); 2012 inline void vavguh( VectorRegister d, VectorRegister a, VectorRegister b); 2013 inline void vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b); 2014 inline void vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b); 2015 inline void vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b); 2016 inline void vmaxub( VectorRegister d, VectorRegister a, VectorRegister b); 2017 inline void vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b); 2018 inline void vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b); 2019 inline void vminsb( VectorRegister d, VectorRegister a, VectorRegister b); 2020 inline void vminsw( VectorRegister d, VectorRegister a, VectorRegister b); 2021 inline void vminsh( VectorRegister d, VectorRegister a, VectorRegister b); 2022 inline void vminub( VectorRegister d, VectorRegister a, VectorRegister b); 2023 inline void vminuw( VectorRegister d, VectorRegister a, VectorRegister b); 2024 inline void vminuh( VectorRegister d, VectorRegister a, VectorRegister b); 2025 inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b); 2026 inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b); 2027 inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b); 2028 inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b); 2029 inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b); 2030 inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b); 2031 inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b); 2032 inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b); 2033 inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b); 2034 inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b); 2035 inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b); 2036 inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b); 2037 inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b); 2038 inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b); 2039 inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b); 2040 inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b); 2041 inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b); 2042 inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b); 2043 inline void vand( VectorRegister d, VectorRegister a, VectorRegister b); 2044 inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b); 2045 inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b); 2046 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b); 2047 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b); 2048 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b); 2049 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b); 2050 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b); 2051 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b); 2052 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b); 2053 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b); 2054 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b); 2055 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b); 2056 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b); 2057 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b); 2058 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b); 2059 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b); 2060 // Vector Floating-Point not implemented yet 2061 inline void mtvscr( VectorRegister b); 2062 inline void mfvscr( VectorRegister d); 2063 2064 // AES (introduced with Power 8) 2065 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b); 2066 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b); 2067 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b); 2068 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b); 2069 inline void vsbox( VectorRegister d, VectorRegister a); 2070 2071 // SHA (introduced with Power 8) 2072 // Not yet implemented. 2073 2074 // Vector Binary Polynomial Multiplication (introduced with Power 8) 2075 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b); 2076 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b); 2077 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b); 2078 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b); 2079 2080 // Vector Permute and Xor (introduced with Power 8) 2081 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2082 2083 // Transactional Memory instructions (introduced with Power 8) 2084 inline void tbegin_(); // R=0 2085 inline void tbeginrot_(); // R=1 Rollback-Only Transaction 2086 inline void tend_(); // A=0 2087 inline void tendall_(); // A=1 2088 inline void tabort_(); 2089 inline void tabort_(Register a); 2090 inline void tabortwc_(int t, Register a, Register b); 2091 inline void tabortwci_(int t, Register a, int si); 2092 inline void tabortdc_(int t, Register a, Register b); 2093 inline void tabortdci_(int t, Register a, int si); 2094 inline void tsuspend_(); // tsr with L=0 2095 inline void tresume_(); // tsr with L=1 2096 inline void tcheck(int f); 2097 2098 static bool is_tbegin(int x) { 2099 return TBEGIN_OPCODE == (x & (0x3f << OPCODE_SHIFT | 0x3ff << 1)); 2100 } 2101 2102 // The following encoders use r0 as second operand. These instructions 2103 // read r0 as '0'. 2104 inline void lwzx( Register d, Register s2); 2105 inline void lwz( Register d, int si16); 2106 inline void lwax( Register d, Register s2); 2107 inline void lwa( Register d, int si16); 2108 inline void lwbrx(Register d, Register s2); 2109 inline void lhzx( Register d, Register s2); 2110 inline void lhz( Register d, int si16); 2111 inline void lhax( Register d, Register s2); 2112 inline void lha( Register d, int si16); 2113 inline void lhbrx(Register d, Register s2); 2114 inline void lbzx( Register d, Register s2); 2115 inline void lbz( Register d, int si16); 2116 inline void ldx( Register d, Register s2); 2117 inline void ld( Register d, int si16); 2118 inline void stwx( Register d, Register s2); 2119 inline void stw( Register d, int si16); 2120 inline void sthx( Register d, Register s2); 2121 inline void sth( Register d, int si16); 2122 inline void stbx( Register d, Register s2); 2123 inline void stb( Register d, int si16); 2124 inline void stdx( Register d, Register s2); 2125 inline void std( Register d, int si16); 2126 2127 // PPC 2, section 3.2.1 Instruction Cache Instructions 2128 inline void icbi( Register s2); 2129 // PPC 2, section 3.2.2 Data Cache Instructions 2130 //inlinevoid dcba( Register s2); // Instruction for embedded processor only. 2131 inline void dcbz( Register s2); 2132 inline void dcbst( Register s2); 2133 inline void dcbf( Register s2); 2134 // dcache read hint 2135 inline void dcbt( Register s2); 2136 inline void dcbtct( Register s2, int ct); 2137 inline void dcbtds( Register s2, int ds); 2138 // dcache write hint 2139 inline void dcbtst( Register s2); 2140 inline void dcbtstct(Register s2, int ct); 2141 2142 // Atomics: use ra0mem to disallow R0 as base. 2143 inline void lwarx_unchecked(Register d, Register b, int eh1); 2144 inline void ldarx_unchecked(Register d, Register b, int eh1); 2145 inline void lqarx_unchecked(Register d, Register b, int eh1); 2146 inline void lwarx( Register d, Register b, bool hint_exclusive_access); 2147 inline void ldarx( Register d, Register b, bool hint_exclusive_access); 2148 inline void lqarx( Register d, Register b, bool hint_exclusive_access); 2149 inline void stwcx_(Register s, Register b); 2150 inline void stdcx_(Register s, Register b); 2151 inline void stqcx_(Register s, Register b); 2152 inline void lfs( FloatRegister d, int si16); 2153 inline void lfsx( FloatRegister d, Register b); 2154 inline void lfd( FloatRegister d, int si16); 2155 inline void lfdx( FloatRegister d, Register b); 2156 inline void stfs( FloatRegister s, int si16); 2157 inline void stfsx( FloatRegister s, Register b); 2158 inline void stfd( FloatRegister s, int si16); 2159 inline void stfdx( FloatRegister s, Register b); 2160 inline void lvebx( VectorRegister d, Register s2); 2161 inline void lvehx( VectorRegister d, Register s2); 2162 inline void lvewx( VectorRegister d, Register s2); 2163 inline void lvx( VectorRegister d, Register s2); 2164 inline void lvxl( VectorRegister d, Register s2); 2165 inline void stvebx(VectorRegister d, Register s2); 2166 inline void stvehx(VectorRegister d, Register s2); 2167 inline void stvewx(VectorRegister d, Register s2); 2168 inline void stvx( VectorRegister d, Register s2); 2169 inline void stvxl( VectorRegister d, Register s2); 2170 inline void lvsl( VectorRegister d, Register s2); 2171 inline void lvsr( VectorRegister d, Register s2); 2172 2173 // RegisterOrConstant versions. 2174 // These emitters choose between the versions using two registers and 2175 // those with register and immediate, depending on the content of roc. 2176 // If the constant is not encodable as immediate, instructions to 2177 // load the constant are emitted beforehand. Store instructions need a 2178 // tmp reg if the constant is not encodable as immediate. 2179 // Size unpredictable. 2180 void ld( Register d, RegisterOrConstant roc, Register s1 = noreg); 2181 void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg); 2182 void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2183 void lha( Register d, RegisterOrConstant roc, Register s1 = noreg); 2184 void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2185 void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2186 void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2187 void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2188 void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2189 void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2190 void add( Register d, RegisterOrConstant roc, Register s1); 2191 void subf(Register d, RegisterOrConstant roc, Register s1); 2192 void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1); 2193 2194 2195 // Emit several instructions to load a 64 bit constant. This issues a fixed 2196 // instruction pattern so that the constant can be patched later on. 2197 enum { 2198 load_const_size = 5 * BytesPerInstWord 2199 }; 2200 void load_const(Register d, long a, Register tmp = noreg); 2201 inline void load_const(Register d, void* a, Register tmp = noreg); 2202 inline void load_const(Register d, Label& L, Register tmp = noreg); 2203 inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg); 2204 inline void load_const32(Register d, int i); // load signed int (patchable) 2205 2206 // Load a 64 bit constant, optimized, not identifyable. 2207 // Tmp can be used to increase ILP. Set return_simm16_rest = true to get a 2208 // 16 bit immediate offset. This is useful if the offset can be encoded in 2209 // a succeeding instruction. 2210 int load_const_optimized(Register d, long a, Register tmp = noreg, bool return_simm16_rest = false); 2211 inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) { 2212 return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest); 2213 } 2214 2215 // If return_simm16_rest, the return value needs to get added afterwards. 2216 int add_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false); 2217 inline int add_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) { 2218 return add_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest); 2219 } 2220 2221 // If return_simm16_rest, the return value needs to get added afterwards. 2222 inline int sub_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false) { 2223 return add_const_optimized(d, s, -x, tmp, return_simm16_rest); 2224 } 2225 inline int sub_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) { 2226 return sub_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest); 2227 } 2228 2229 // Creation 2230 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 2231#ifdef CHECK_DELAY 2232 delay_state = no_delay; 2233#endif 2234 } 2235 2236 // Testing 2237#ifndef PRODUCT 2238 void test_asm(); 2239#endif 2240}; 2241 2242 2243#endif // CPU_PPC_VM_ASSEMBLER_PPC_HPP 2244