assembler_ppc.hpp revision 11540:84d6afe30a53
1/* 2 * Copyright (c) 2002, 2016, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2016 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26#ifndef CPU_PPC_VM_ASSEMBLER_PPC_HPP 27#define CPU_PPC_VM_ASSEMBLER_PPC_HPP 28 29#include "asm/register.hpp" 30 31// Address is an abstraction used to represent a memory location 32// as used in assembler instructions. 33// PPC instructions grok either baseReg + indexReg or baseReg + disp. 34class Address VALUE_OBJ_CLASS_SPEC { 35 private: 36 Register _base; // Base register. 37 Register _index; // Index register. 38 intptr_t _disp; // Displacement. 39 40 public: 41 Address(Register b, Register i, address d = 0) 42 : _base(b), _index(i), _disp((intptr_t)d) { 43 assert(i == noreg || d == 0, "can't have both"); 44 } 45 46 Address(Register b, address d = 0) 47 : _base(b), _index(noreg), _disp((intptr_t)d) {} 48 49 Address(Register b, intptr_t d) 50 : _base(b), _index(noreg), _disp(d) {} 51 52 Address(Register b, RegisterOrConstant roc) 53 : _base(b), _index(noreg), _disp(0) { 54 if (roc.is_constant()) _disp = roc.as_constant(); else _index = roc.as_register(); 55 } 56 57 Address() 58 : _base(noreg), _index(noreg), _disp(0) {} 59 60 // accessors 61 Register base() const { return _base; } 62 Register index() const { return _index; } 63 int disp() const { return (int)_disp; } 64 bool is_const() const { return _base == noreg && _index == noreg; } 65}; 66 67class AddressLiteral VALUE_OBJ_CLASS_SPEC { 68 private: 69 address _address; 70 RelocationHolder _rspec; 71 72 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { 73 switch (rtype) { 74 case relocInfo::external_word_type: 75 return external_word_Relocation::spec(addr); 76 case relocInfo::internal_word_type: 77 return internal_word_Relocation::spec(addr); 78 case relocInfo::opt_virtual_call_type: 79 return opt_virtual_call_Relocation::spec(); 80 case relocInfo::static_call_type: 81 return static_call_Relocation::spec(); 82 case relocInfo::runtime_call_type: 83 return runtime_call_Relocation::spec(); 84 case relocInfo::none: 85 return RelocationHolder(); 86 default: 87 ShouldNotReachHere(); 88 return RelocationHolder(); 89 } 90 } 91 92 protected: 93 // creation 94 AddressLiteral() : _address(NULL), _rspec(NULL) {} 95 96 public: 97 AddressLiteral(address addr, RelocationHolder const& rspec) 98 : _address(addr), 99 _rspec(rspec) {} 100 101 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) 102 : _address((address) addr), 103 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 104 105 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none) 106 : _address((address) addr), 107 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 108 109 intptr_t value() const { return (intptr_t) _address; } 110 111 const RelocationHolder& rspec() const { return _rspec; } 112}; 113 114// Argument is an abstraction used to represent an outgoing 115// actual argument or an incoming formal parameter, whether 116// it resides in memory or in a register, in a manner consistent 117// with the PPC Application Binary Interface, or ABI. This is 118// often referred to as the native or C calling convention. 119 120class Argument VALUE_OBJ_CLASS_SPEC { 121 private: 122 int _number; // The number of the argument. 123 public: 124 enum { 125 // Only 8 registers may contain integer parameters. 126 n_register_parameters = 8, 127 // Can have up to 8 floating registers. 128 n_float_register_parameters = 8, 129 130 // PPC C calling conventions. 131 // The first eight arguments are passed in int regs if they are int. 132 n_int_register_parameters_c = 8, 133 // The first thirteen float arguments are passed in float regs. 134 n_float_register_parameters_c = 13, 135 // Only the first 8 parameters are not placed on the stack. Aix disassembly 136 // shows that xlC places all float args after argument 8 on the stack AND 137 // in a register. This is not documented, but we follow this convention, too. 138 n_regs_not_on_stack_c = 8, 139 }; 140 // creation 141 Argument(int number) : _number(number) {} 142 143 int number() const { return _number; } 144 145 // Locating register-based arguments: 146 bool is_register() const { return _number < n_register_parameters; } 147 148 Register as_register() const { 149 assert(is_register(), "must be a register argument"); 150 return as_Register(number() + R3_ARG1->encoding()); 151 } 152}; 153 154#if !defined(ABI_ELFv2) 155// A ppc64 function descriptor. 156struct FunctionDescriptor VALUE_OBJ_CLASS_SPEC { 157 private: 158 address _entry; 159 address _toc; 160 address _env; 161 162 public: 163 inline address entry() const { return _entry; } 164 inline address toc() const { return _toc; } 165 inline address env() const { return _env; } 166 167 inline void set_entry(address entry) { _entry = entry; } 168 inline void set_toc( address toc) { _toc = toc; } 169 inline void set_env( address env) { _env = env; } 170 171 inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); } 172 inline static ByteSize toc_offset() { return byte_offset_of(FunctionDescriptor, _toc); } 173 inline static ByteSize env_offset() { return byte_offset_of(FunctionDescriptor, _env); } 174 175 // Friend functions can be called without loading toc and env. 176 enum { 177 friend_toc = 0xcafe, 178 friend_env = 0xc0de 179 }; 180 181 inline bool is_friend_function() const { 182 return (toc() == (address) friend_toc) && (env() == (address) friend_env); 183 } 184 185 // Constructor for stack-allocated instances. 186 FunctionDescriptor() { 187 _entry = (address) 0xbad; 188 _toc = (address) 0xbad; 189 _env = (address) 0xbad; 190 } 191}; 192#endif 193 194 195// The PPC Assembler: Pure assembler doing NO optimizations on the 196// instruction level; i.e., what you write is what you get. The 197// Assembler is generating code into a CodeBuffer. 198 199class Assembler : public AbstractAssembler { 200 protected: 201 // Displacement routines 202 static int patched_branch(int dest_pos, int inst, int inst_pos); 203 static int branch_destination(int inst, int pos); 204 205 friend class AbstractAssembler; 206 207 // Code patchers need various routines like inv_wdisp() 208 friend class NativeInstruction; 209 friend class NativeGeneralJump; 210 friend class Relocation; 211 212 public: 213 214 enum shifts { 215 XO_21_29_SHIFT = 2, 216 XO_21_30_SHIFT = 1, 217 XO_27_29_SHIFT = 2, 218 XO_30_31_SHIFT = 0, 219 SPR_5_9_SHIFT = 11u, // SPR_5_9 field in bits 11 -- 15 220 SPR_0_4_SHIFT = 16u, // SPR_0_4 field in bits 16 -- 20 221 RS_SHIFT = 21u, // RS field in bits 21 -- 25 222 OPCODE_SHIFT = 26u, // opcode in bits 26 -- 31 223 }; 224 225 enum opcdxos_masks { 226 XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 227 ADDI_OPCODE_MASK = (63u << OPCODE_SHIFT), 228 ADDIS_OPCODE_MASK = (63u << OPCODE_SHIFT), 229 BXX_OPCODE_MASK = (63u << OPCODE_SHIFT), 230 BCXX_OPCODE_MASK = (63u << OPCODE_SHIFT), 231 // trap instructions 232 TDI_OPCODE_MASK = (63u << OPCODE_SHIFT), 233 TWI_OPCODE_MASK = (63u << OPCODE_SHIFT), 234 TD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 235 TW_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 236 LD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM 237 STD_OPCODE_MASK = LD_OPCODE_MASK, 238 STDU_OPCODE_MASK = STD_OPCODE_MASK, 239 STDX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 240 STDUX_OPCODE_MASK = STDX_OPCODE_MASK, 241 STW_OPCODE_MASK = (63u << OPCODE_SHIFT), 242 STWU_OPCODE_MASK = STW_OPCODE_MASK, 243 STWX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 244 STWUX_OPCODE_MASK = STWX_OPCODE_MASK, 245 MTCTR_OPCODE_MASK = ~(31u << RS_SHIFT), 246 ORI_OPCODE_MASK = (63u << OPCODE_SHIFT), 247 ORIS_OPCODE_MASK = (63u << OPCODE_SHIFT), 248 RLDICR_OPCODE_MASK = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT) 249 }; 250 251 enum opcdxos { 252 ADD_OPCODE = (31u << OPCODE_SHIFT | 266u << 1), 253 ADDC_OPCODE = (31u << OPCODE_SHIFT | 10u << 1), 254 ADDI_OPCODE = (14u << OPCODE_SHIFT), 255 ADDIS_OPCODE = (15u << OPCODE_SHIFT), 256 ADDIC__OPCODE = (13u << OPCODE_SHIFT), 257 ADDE_OPCODE = (31u << OPCODE_SHIFT | 138u << 1), 258 ADDME_OPCODE = (31u << OPCODE_SHIFT | 234u << 1), 259 ADDZE_OPCODE = (31u << OPCODE_SHIFT | 202u << 1), 260 SUBF_OPCODE = (31u << OPCODE_SHIFT | 40u << 1), 261 SUBFC_OPCODE = (31u << OPCODE_SHIFT | 8u << 1), 262 SUBFE_OPCODE = (31u << OPCODE_SHIFT | 136u << 1), 263 SUBFIC_OPCODE = (8u << OPCODE_SHIFT), 264 SUBFME_OPCODE = (31u << OPCODE_SHIFT | 232u << 1), 265 SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1), 266 DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1), 267 MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1), 268 MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1), 269 MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1), 270 MULLI_OPCODE = (7u << OPCODE_SHIFT), 271 AND_OPCODE = (31u << OPCODE_SHIFT | 28u << 1), 272 ANDI_OPCODE = (28u << OPCODE_SHIFT), 273 ANDIS_OPCODE = (29u << OPCODE_SHIFT), 274 ANDC_OPCODE = (31u << OPCODE_SHIFT | 60u << 1), 275 ORC_OPCODE = (31u << OPCODE_SHIFT | 412u << 1), 276 OR_OPCODE = (31u << OPCODE_SHIFT | 444u << 1), 277 ORI_OPCODE = (24u << OPCODE_SHIFT), 278 ORIS_OPCODE = (25u << OPCODE_SHIFT), 279 XOR_OPCODE = (31u << OPCODE_SHIFT | 316u << 1), 280 XORI_OPCODE = (26u << OPCODE_SHIFT), 281 XORIS_OPCODE = (27u << OPCODE_SHIFT), 282 283 NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1), 284 285 RLWINM_OPCODE = (21u << OPCODE_SHIFT), 286 CLRRWI_OPCODE = RLWINM_OPCODE, 287 CLRLWI_OPCODE = RLWINM_OPCODE, 288 289 RLWIMI_OPCODE = (20u << OPCODE_SHIFT), 290 291 SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1), 292 SLWI_OPCODE = RLWINM_OPCODE, 293 SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1), 294 SRWI_OPCODE = RLWINM_OPCODE, 295 SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1), 296 SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1), 297 298 CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1), 299 CMPI_OPCODE = (11u << OPCODE_SHIFT), 300 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1), 301 CMPLI_OPCODE = (10u << OPCODE_SHIFT), 302 303 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1), 304 305 // Special purpose registers 306 MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1), 307 MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1), 308 309 MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT), 310 MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT), 311 312 MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT), 313 MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT), 314 315 MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT), 316 MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT), 317 318 MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT), 319 MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT), 320 321 // Attention: Higher and lower half are inserted in reversed order. 322 MTTFHAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 323 MFTFHAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 324 MTTFIAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT), 325 MFTFIAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT), 326 MTTEXASR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT), 327 MFTEXASR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT), 328 MTTEXASRU_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT), 329 MFTEXASRU_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT), 330 331 MTVRSAVE_OPCODE = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 332 MFVRSAVE_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 333 334 MFTB_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT), 335 336 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1), 337 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1), 338 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1), 339 340 // condition register logic instructions 341 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1), 342 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1), 343 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1), 344 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1), 345 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1), 346 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1), 347 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1), 348 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1), 349 350 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1), 351 BXX_OPCODE = (18u << OPCODE_SHIFT), 352 BCXX_OPCODE = (16u << OPCODE_SHIFT), 353 354 // CTR-related opcodes 355 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1), 356 357 LWZ_OPCODE = (32u << OPCODE_SHIFT), 358 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1), 359 LWZU_OPCODE = (33u << OPCODE_SHIFT), 360 LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1), 361 362 LHA_OPCODE = (42u << OPCODE_SHIFT), 363 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1), 364 LHAU_OPCODE = (43u << OPCODE_SHIFT), 365 366 LHZ_OPCODE = (40u << OPCODE_SHIFT), 367 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1), 368 LHZU_OPCODE = (41u << OPCODE_SHIFT), 369 LHBRX_OPCODE = (31u << OPCODE_SHIFT | 790 << 1), 370 371 LBZ_OPCODE = (34u << OPCODE_SHIFT), 372 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1), 373 LBZU_OPCODE = (35u << OPCODE_SHIFT), 374 375 STW_OPCODE = (36u << OPCODE_SHIFT), 376 STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1), 377 STWU_OPCODE = (37u << OPCODE_SHIFT), 378 STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1), 379 380 STH_OPCODE = (44u << OPCODE_SHIFT), 381 STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1), 382 STHU_OPCODE = (45u << OPCODE_SHIFT), 383 384 STB_OPCODE = (38u << OPCODE_SHIFT), 385 STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1), 386 STBU_OPCODE = (39u << OPCODE_SHIFT), 387 388 EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1), 389 EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1), 390 EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1), // X-FORM 391 392 // 32 bit opcode encodings 393 394 LWA_OPCODE = (58u << OPCODE_SHIFT | 2u << XO_30_31_SHIFT), // DS-FORM 395 LWAX_OPCODE = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM 396 397 CNTLZW_OPCODE = (31u << OPCODE_SHIFT | 26u << XO_21_30_SHIFT), // X-FORM 398 399 // 64 bit opcode encodings 400 401 LD_OPCODE = (58u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM 402 LDU_OPCODE = (58u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM 403 LDX_OPCODE = (31u << OPCODE_SHIFT | 21u << XO_21_30_SHIFT), // X-FORM 404 405 STD_OPCODE = (62u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM 406 STDU_OPCODE = (62u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM 407 STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM 408 STDX_OPCODE = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM 409 410 RLDICR_OPCODE = (30u << OPCODE_SHIFT | 1u << XO_27_29_SHIFT), // MD-FORM 411 RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM 412 RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM 413 RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM 414 415 SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM 416 417 SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM 418 SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM 419 SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM 420 421 MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM 422 MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM 423 MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM 424 DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM 425 426 CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM 427 NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM 428 NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM 429 430 431 // opcodes only used for floating arithmetic 432 FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1), 433 FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1), 434 FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1), 435 FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1), 436 FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1), 437 FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1), 438 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx" 439 // on Power7. Do not use. 440 // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1), 441 // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1), 442 CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1), 443 POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1), 444 POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1), 445 POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1), 446 FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1), 447 FNABS_OPCODE = (63u << OPCODE_SHIFT | 136u << 1), 448 FMUL_OPCODE = (63u << OPCODE_SHIFT | 25u << 1), 449 FMULS_OPCODE = (59u << OPCODE_SHIFT | 25u << 1), 450 FNEG_OPCODE = (63u << OPCODE_SHIFT | 40u << 1), 451 FSUB_OPCODE = (63u << OPCODE_SHIFT | 20u << 1), 452 FSUBS_OPCODE = (59u << OPCODE_SHIFT | 20u << 1), 453 454 // PPC64-internal FPU conversion opcodes 455 FCFID_OPCODE = (63u << OPCODE_SHIFT | 846u << 1), 456 FCFIDS_OPCODE = (59u << OPCODE_SHIFT | 846u << 1), 457 FCTID_OPCODE = (63u << OPCODE_SHIFT | 814u << 1), 458 FCTIDZ_OPCODE = (63u << OPCODE_SHIFT | 815u << 1), 459 FCTIW_OPCODE = (63u << OPCODE_SHIFT | 14u << 1), 460 FCTIWZ_OPCODE = (63u << OPCODE_SHIFT | 15u << 1), 461 FRSP_OPCODE = (63u << OPCODE_SHIFT | 12u << 1), 462 463 // WARNING: using fmadd results in a non-compliant vm. Some floating 464 // point tck tests will fail. 465 FMADD_OPCODE = (59u << OPCODE_SHIFT | 29u << 1), 466 DMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1), 467 FMSUB_OPCODE = (59u << OPCODE_SHIFT | 28u << 1), 468 DMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1), 469 FNMADD_OPCODE = (59u << OPCODE_SHIFT | 31u << 1), 470 DNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1), 471 FNMSUB_OPCODE = (59u << OPCODE_SHIFT | 30u << 1), 472 DNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1), 473 474 LFD_OPCODE = (50u << OPCODE_SHIFT | 00u << 1), 475 LFDU_OPCODE = (51u << OPCODE_SHIFT | 00u << 1), 476 LFDX_OPCODE = (31u << OPCODE_SHIFT | 599u << 1), 477 LFS_OPCODE = (48u << OPCODE_SHIFT | 00u << 1), 478 LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1), 479 LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1), 480 481 STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1), 482 STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1), 483 STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1), 484 STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1), 485 STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1), 486 STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1), 487 488 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM 489 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM 490 491 // Vector instruction support for >= Power6 492 // Vector Storage Access 493 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1), 494 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1), 495 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1), 496 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1), 497 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1), 498 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1), 499 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1), 500 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1), 501 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1), 502 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1), 503 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1), 504 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1), 505 506 // Vector-Scalar (VSX) instruction support. 507 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1), 508 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1), 509 510 // Vector Permute and Formatting 511 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ), 512 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ), 513 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ), 514 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ), 515 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ), 516 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ), 517 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ), 518 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ), 519 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ), 520 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ), 521 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ), 522 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ), 523 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ), 524 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ), 525 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ), 526 527 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ), 528 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ), 529 VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ), 530 VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ), 531 VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ), 532 VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ), 533 534 VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ), 535 VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ), 536 VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ), 537 VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ), 538 VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ), 539 VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ), 540 541 VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ), 542 VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ), 543 544 VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ), 545 VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ), 546 VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ), 547 VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ), 548 VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ), 549 550 // Vector Integer 551 VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ), 552 VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ), 553 VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ), 554 VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ), 555 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ), 556 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ), 557 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ), 558 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ), 559 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ), 560 VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ), 561 VSUBCUW_OPCODE = (4u << OPCODE_SHIFT | 1408u ), 562 VSUBSHS_OPCODE = (4u << OPCODE_SHIFT | 1856u ), 563 VSUBSBS_OPCODE = (4u << OPCODE_SHIFT | 1792u ), 564 VSUBSWS_OPCODE = (4u << OPCODE_SHIFT | 1920u ), 565 VSUBUBM_OPCODE = (4u << OPCODE_SHIFT | 1024u ), 566 VSUBUWM_OPCODE = (4u << OPCODE_SHIFT | 1152u ), 567 VSUBUHM_OPCODE = (4u << OPCODE_SHIFT | 1088u ), 568 VSUBUBS_OPCODE = (4u << OPCODE_SHIFT | 1536u ), 569 VSUBUWS_OPCODE = (4u << OPCODE_SHIFT | 1664u ), 570 VSUBUHS_OPCODE = (4u << OPCODE_SHIFT | 1600u ), 571 572 VMULESB_OPCODE = (4u << OPCODE_SHIFT | 776u ), 573 VMULEUB_OPCODE = (4u << OPCODE_SHIFT | 520u ), 574 VMULESH_OPCODE = (4u << OPCODE_SHIFT | 840u ), 575 VMULEUH_OPCODE = (4u << OPCODE_SHIFT | 584u ), 576 VMULOSB_OPCODE = (4u << OPCODE_SHIFT | 264u ), 577 VMULOUB_OPCODE = (4u << OPCODE_SHIFT | 8u ), 578 VMULOSH_OPCODE = (4u << OPCODE_SHIFT | 328u ), 579 VMULOUH_OPCODE = (4u << OPCODE_SHIFT | 72u ), 580 VMHADDSHS_OPCODE=(4u << OPCODE_SHIFT | 32u ), 581 VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT | 33u ), 582 VMLADDUHM_OPCODE=(4u << OPCODE_SHIFT | 34u ), 583 VMSUBUHM_OPCODE= (4u << OPCODE_SHIFT | 36u ), 584 VMSUMMBM_OPCODE= (4u << OPCODE_SHIFT | 37u ), 585 VMSUMSHM_OPCODE= (4u << OPCODE_SHIFT | 40u ), 586 VMSUMSHS_OPCODE= (4u << OPCODE_SHIFT | 41u ), 587 VMSUMUHM_OPCODE= (4u << OPCODE_SHIFT | 38u ), 588 VMSUMUHS_OPCODE= (4u << OPCODE_SHIFT | 39u ), 589 590 VSUMSWS_OPCODE = (4u << OPCODE_SHIFT | 1928u ), 591 VSUM2SWS_OPCODE= (4u << OPCODE_SHIFT | 1672u ), 592 VSUM4SBS_OPCODE= (4u << OPCODE_SHIFT | 1800u ), 593 VSUM4UBS_OPCODE= (4u << OPCODE_SHIFT | 1544u ), 594 VSUM4SHS_OPCODE= (4u << OPCODE_SHIFT | 1608u ), 595 596 VAVGSB_OPCODE = (4u << OPCODE_SHIFT | 1282u ), 597 VAVGSW_OPCODE = (4u << OPCODE_SHIFT | 1410u ), 598 VAVGSH_OPCODE = (4u << OPCODE_SHIFT | 1346u ), 599 VAVGUB_OPCODE = (4u << OPCODE_SHIFT | 1026u ), 600 VAVGUW_OPCODE = (4u << OPCODE_SHIFT | 1154u ), 601 VAVGUH_OPCODE = (4u << OPCODE_SHIFT | 1090u ), 602 603 VMAXSB_OPCODE = (4u << OPCODE_SHIFT | 258u ), 604 VMAXSW_OPCODE = (4u << OPCODE_SHIFT | 386u ), 605 VMAXSH_OPCODE = (4u << OPCODE_SHIFT | 322u ), 606 VMAXUB_OPCODE = (4u << OPCODE_SHIFT | 2u ), 607 VMAXUW_OPCODE = (4u << OPCODE_SHIFT | 130u ), 608 VMAXUH_OPCODE = (4u << OPCODE_SHIFT | 66u ), 609 VMINSB_OPCODE = (4u << OPCODE_SHIFT | 770u ), 610 VMINSW_OPCODE = (4u << OPCODE_SHIFT | 898u ), 611 VMINSH_OPCODE = (4u << OPCODE_SHIFT | 834u ), 612 VMINUB_OPCODE = (4u << OPCODE_SHIFT | 514u ), 613 VMINUW_OPCODE = (4u << OPCODE_SHIFT | 642u ), 614 VMINUH_OPCODE = (4u << OPCODE_SHIFT | 578u ), 615 616 VCMPEQUB_OPCODE= (4u << OPCODE_SHIFT | 6u ), 617 VCMPEQUH_OPCODE= (4u << OPCODE_SHIFT | 70u ), 618 VCMPEQUW_OPCODE= (4u << OPCODE_SHIFT | 134u ), 619 VCMPGTSH_OPCODE= (4u << OPCODE_SHIFT | 838u ), 620 VCMPGTSB_OPCODE= (4u << OPCODE_SHIFT | 774u ), 621 VCMPGTSW_OPCODE= (4u << OPCODE_SHIFT | 902u ), 622 VCMPGTUB_OPCODE= (4u << OPCODE_SHIFT | 518u ), 623 VCMPGTUH_OPCODE= (4u << OPCODE_SHIFT | 582u ), 624 VCMPGTUW_OPCODE= (4u << OPCODE_SHIFT | 646u ), 625 626 VAND_OPCODE = (4u << OPCODE_SHIFT | 1028u ), 627 VANDC_OPCODE = (4u << OPCODE_SHIFT | 1092u ), 628 VNOR_OPCODE = (4u << OPCODE_SHIFT | 1284u ), 629 VOR_OPCODE = (4u << OPCODE_SHIFT | 1156u ), 630 VXOR_OPCODE = (4u << OPCODE_SHIFT | 1220u ), 631 VRLD_OPCODE = (4u << OPCODE_SHIFT | 196u ), 632 VRLB_OPCODE = (4u << OPCODE_SHIFT | 4u ), 633 VRLW_OPCODE = (4u << OPCODE_SHIFT | 132u ), 634 VRLH_OPCODE = (4u << OPCODE_SHIFT | 68u ), 635 VSLB_OPCODE = (4u << OPCODE_SHIFT | 260u ), 636 VSKW_OPCODE = (4u << OPCODE_SHIFT | 388u ), 637 VSLH_OPCODE = (4u << OPCODE_SHIFT | 324u ), 638 VSRB_OPCODE = (4u << OPCODE_SHIFT | 516u ), 639 VSRW_OPCODE = (4u << OPCODE_SHIFT | 644u ), 640 VSRH_OPCODE = (4u << OPCODE_SHIFT | 580u ), 641 VSRAB_OPCODE = (4u << OPCODE_SHIFT | 772u ), 642 VSRAW_OPCODE = (4u << OPCODE_SHIFT | 900u ), 643 VSRAH_OPCODE = (4u << OPCODE_SHIFT | 836u ), 644 645 // Vector Floating-Point 646 // not implemented yet 647 648 // Vector Status and Control 649 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ), 650 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ), 651 652 // AES (introduced with Power 8) 653 VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u), 654 VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u), 655 VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u), 656 VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u), 657 VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u), 658 659 // SHA (introduced with Power 8) 660 VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u), 661 VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u), 662 663 // Vector Binary Polynomial Multiplication (introduced with Power 8) 664 VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u), 665 VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u), 666 VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u), 667 VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u), 668 669 // Vector Permute and Xor (introduced with Power 8) 670 VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u), 671 672 // Transactional Memory instructions (introduced with Power 8) 673 TBEGIN_OPCODE = (31u << OPCODE_SHIFT | 654u << 1), 674 TEND_OPCODE = (31u << OPCODE_SHIFT | 686u << 1), 675 TABORT_OPCODE = (31u << OPCODE_SHIFT | 910u << 1), 676 TABORTWC_OPCODE = (31u << OPCODE_SHIFT | 782u << 1), 677 TABORTWCI_OPCODE = (31u << OPCODE_SHIFT | 846u << 1), 678 TABORTDC_OPCODE = (31u << OPCODE_SHIFT | 814u << 1), 679 TABORTDCI_OPCODE = (31u << OPCODE_SHIFT | 878u << 1), 680 TSR_OPCODE = (31u << OPCODE_SHIFT | 750u << 1), 681 TCHECK_OPCODE = (31u << OPCODE_SHIFT | 718u << 1), 682 683 // Icache and dcache related instructions 684 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1), 685 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1), 686 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1), 687 DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1), 688 689 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1), 690 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1), 691 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1), 692 693 // Instruction synchronization 694 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1), 695 // Memory barriers 696 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1), 697 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1), 698 699 // Wait instructions for polling. 700 WAIT_OPCODE = (31u << OPCODE_SHIFT | 62u << 1), 701 702 // Trap instructions 703 TDI_OPCODE = (2u << OPCODE_SHIFT), 704 TWI_OPCODE = (3u << OPCODE_SHIFT), 705 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1), 706 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1), 707 708 // Atomics. 709 LBARX_OPCODE = (31u << OPCODE_SHIFT | 52u << 1), 710 LHARX_OPCODE = (31u << OPCODE_SHIFT | 116u << 1), 711 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1), 712 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1), 713 LQARX_OPCODE = (31u << OPCODE_SHIFT | 276u << 1), 714 STBCX_OPCODE = (31u << OPCODE_SHIFT | 694u << 1), 715 STHCX_OPCODE = (31u << OPCODE_SHIFT | 726u << 1), 716 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1), 717 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1), 718 STQCX_OPCODE = (31u << OPCODE_SHIFT | 182u << 1) 719 720 }; 721 722 // Trap instructions TO bits 723 enum trap_to_bits { 724 // single bits 725 traptoLessThanSigned = 1 << 4, // 0, left end 726 traptoGreaterThanSigned = 1 << 3, 727 traptoEqual = 1 << 2, 728 traptoLessThanUnsigned = 1 << 1, 729 traptoGreaterThanUnsigned = 1 << 0, // 4, right end 730 731 // compound ones 732 traptoUnconditional = (traptoLessThanSigned | 733 traptoGreaterThanSigned | 734 traptoEqual | 735 traptoLessThanUnsigned | 736 traptoGreaterThanUnsigned) 737 }; 738 739 // Branch hints BH field 740 enum branch_hint_bh { 741 // bclr cases: 742 bhintbhBCLRisReturn = 0, 743 bhintbhBCLRisNotReturnButSame = 1, 744 bhintbhBCLRisNotPredictable = 3, 745 746 // bcctr cases: 747 bhintbhBCCTRisNotReturnButSame = 0, 748 bhintbhBCCTRisNotPredictable = 3 749 }; 750 751 // Branch prediction hints AT field 752 enum branch_hint_at { 753 bhintatNoHint = 0, // at=00 754 bhintatIsNotTaken = 2, // at=10 755 bhintatIsTaken = 3 // at=11 756 }; 757 758 // Branch prediction hints 759 enum branch_hint_concept { 760 // Use the same encoding as branch_hint_at to simply code. 761 bhintNoHint = bhintatNoHint, 762 bhintIsNotTaken = bhintatIsNotTaken, 763 bhintIsTaken = bhintatIsTaken 764 }; 765 766 // Used in BO field of branch instruction. 767 enum branch_condition { 768 bcondCRbiIs0 = 4, // bo=001at 769 bcondCRbiIs1 = 12, // bo=011at 770 bcondAlways = 20 // bo=10100 771 }; 772 773 // Branch condition with combined prediction hints. 774 enum branch_condition_with_hint { 775 bcondCRbiIs0_bhintNoHint = bcondCRbiIs0 | bhintatNoHint, 776 bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken, 777 bcondCRbiIs0_bhintIsTaken = bcondCRbiIs0 | bhintatIsTaken, 778 bcondCRbiIs1_bhintNoHint = bcondCRbiIs1 | bhintatNoHint, 779 bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken, 780 bcondCRbiIs1_bhintIsTaken = bcondCRbiIs1 | bhintatIsTaken, 781 }; 782 783 // Elemental Memory Barriers (>=Power 8) 784 enum Elemental_Membar_mask_bits { 785 StoreStore = 1 << 0, 786 StoreLoad = 1 << 1, 787 LoadStore = 1 << 2, 788 LoadLoad = 1 << 3 789 }; 790 791 // Branch prediction hints. 792 inline static int add_bhint_to_boint(const int bhint, const int boint) { 793 switch (boint) { 794 case bcondCRbiIs0: 795 case bcondCRbiIs1: 796 // branch_hint and branch_hint_at have same encodings 797 assert( (int)bhintNoHint == (int)bhintatNoHint 798 && (int)bhintIsNotTaken == (int)bhintatIsNotTaken 799 && (int)bhintIsTaken == (int)bhintatIsTaken, 800 "wrong encodings"); 801 assert((bhint & 0x03) == bhint, "wrong encodings"); 802 return (boint & ~0x03) | bhint; 803 case bcondAlways: 804 // no branch_hint 805 return boint; 806 default: 807 ShouldNotReachHere(); 808 return 0; 809 } 810 } 811 812 // Extract bcond from boint. 813 inline static int inv_boint_bcond(const int boint) { 814 int r_bcond = boint & ~0x03; 815 assert(r_bcond == bcondCRbiIs0 || 816 r_bcond == bcondCRbiIs1 || 817 r_bcond == bcondAlways, 818 "bad branch condition"); 819 return r_bcond; 820 } 821 822 // Extract bhint from boint. 823 inline static int inv_boint_bhint(const int boint) { 824 int r_bhint = boint & 0x03; 825 assert(r_bhint == bhintatNoHint || 826 r_bhint == bhintatIsNotTaken || 827 r_bhint == bhintatIsTaken, 828 "bad branch hint"); 829 return r_bhint; 830 } 831 832 // Calculate opposite of given bcond. 833 inline static int opposite_bcond(const int bcond) { 834 switch (bcond) { 835 case bcondCRbiIs0: 836 return bcondCRbiIs1; 837 case bcondCRbiIs1: 838 return bcondCRbiIs0; 839 default: 840 ShouldNotReachHere(); 841 return 0; 842 } 843 } 844 845 // Calculate opposite of given bhint. 846 inline static int opposite_bhint(const int bhint) { 847 switch (bhint) { 848 case bhintatNoHint: 849 return bhintatNoHint; 850 case bhintatIsNotTaken: 851 return bhintatIsTaken; 852 case bhintatIsTaken: 853 return bhintatIsNotTaken; 854 default: 855 ShouldNotReachHere(); 856 return 0; 857 } 858 } 859 860 // PPC branch instructions 861 enum ppcops { 862 b_op = 18, 863 bc_op = 16, 864 bcr_op = 19 865 }; 866 867 enum Condition { 868 negative = 0, 869 less = 0, 870 positive = 1, 871 greater = 1, 872 zero = 2, 873 equal = 2, 874 summary_overflow = 3, 875 }; 876 877 public: 878 // Helper functions for groups of instructions 879 880 enum Predict { pt = 1, pn = 0 }; // pt = predict taken 881 882 // Instruction must start at passed address. 883 static int instr_len(unsigned char *instr) { return BytesPerInstWord; } 884 885 // longest instructions 886 static int instr_maxlen() { return BytesPerInstWord; } 887 888 // Test if x is within signed immediate range for nbits. 889 static bool is_simm(int x, unsigned int nbits) { 890 assert(0 < nbits && nbits < 32, "out of bounds"); 891 const int min = -(((int)1) << nbits-1); 892 const int maxplus1 = (((int)1) << nbits-1); 893 return min <= x && x < maxplus1; 894 } 895 896 static bool is_simm(jlong x, unsigned int nbits) { 897 assert(0 < nbits && nbits < 64, "out of bounds"); 898 const jlong min = -(((jlong)1) << nbits-1); 899 const jlong maxplus1 = (((jlong)1) << nbits-1); 900 return min <= x && x < maxplus1; 901 } 902 903 // Test if x is within unsigned immediate range for nbits. 904 static bool is_uimm(int x, unsigned int nbits) { 905 assert(0 < nbits && nbits < 32, "out of bounds"); 906 const unsigned int maxplus1 = (((unsigned int)1) << nbits); 907 return (unsigned int)x < maxplus1; 908 } 909 910 static bool is_uimm(jlong x, unsigned int nbits) { 911 assert(0 < nbits && nbits < 64, "out of bounds"); 912 const julong maxplus1 = (((julong)1) << nbits); 913 return (julong)x < maxplus1; 914 } 915 916 protected: 917 // helpers 918 919 // X is supposed to fit in a field "nbits" wide 920 // and be sign-extended. Check the range. 921 static void assert_signed_range(intptr_t x, int nbits) { 922 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)), 923 "value out of range"); 924 } 925 926 static void assert_signed_word_disp_range(intptr_t x, int nbits) { 927 assert((x & 3) == 0, "not word aligned"); 928 assert_signed_range(x, nbits + 2); 929 } 930 931 static void assert_unsigned_const(int x, int nbits) { 932 assert(juint(x) < juint(1 << nbits), "unsigned constant out of range"); 933 } 934 935 static int fmask(juint hi_bit, juint lo_bit) { 936 assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits"); 937 return (1 << ( hi_bit-lo_bit + 1 )) - 1; 938 } 939 940 // inverse of u_field 941 static int inv_u_field(int x, int hi_bit, int lo_bit) { 942 juint r = juint(x) >> lo_bit; 943 r &= fmask(hi_bit, lo_bit); 944 return int(r); 945 } 946 947 // signed version: extract from field and sign-extend 948 static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) { 949 x = x << (31-hi_bit); 950 x = x >> (31-hi_bit+lo_bit); 951 return x; 952 } 953 954 static int u_field(int x, int hi_bit, int lo_bit) { 955 assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range"); 956 int r = x << lo_bit; 957 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); 958 return r; 959 } 960 961 // Same as u_field for signed values 962 static int s_field(int x, int hi_bit, int lo_bit) { 963 int nbits = hi_bit - lo_bit + 1; 964 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)), 965 "value out of range"); 966 x &= fmask(hi_bit, lo_bit); 967 int r = x << lo_bit; 968 return r; 969 } 970 971 // inv_op for ppc instructions 972 static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); } 973 974 // Determine target address from li, bd field of branch instruction. 975 static intptr_t inv_li_field(int x) { 976 intptr_t r = inv_s_field_ppc(x, 25, 2); 977 r = (r << 2); 978 return r; 979 } 980 static intptr_t inv_bd_field(int x, intptr_t pos) { 981 intptr_t r = inv_s_field_ppc(x, 15, 2); 982 r = (r << 2) + pos; 983 return r; 984 } 985 986 #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit)) 987 #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit)) 988 // Extract instruction fields from instruction words. 989 public: 990 static int inv_ra_field(int x) { return inv_opp_u_field(x, 15, 11); } 991 static int inv_rb_field(int x) { return inv_opp_u_field(x, 20, 16); } 992 static int inv_rt_field(int x) { return inv_opp_u_field(x, 10, 6); } 993 static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); } 994 static int inv_rs_field(int x) { return inv_opp_u_field(x, 10, 6); } 995 // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0. 996 // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0. 997 static int inv_ds_field(int x) { return inv_opp_s_field(x, 29, 16) << 2; } 998 static int inv_d1_field(int x) { return inv_opp_s_field(x, 31, 16); } 999 static int inv_si_field(int x) { return inv_opp_s_field(x, 31, 16); } 1000 static int inv_to_field(int x) { return inv_opp_u_field(x, 10, 6); } 1001 static int inv_lk_field(int x) { return inv_opp_u_field(x, 31, 31); } 1002 static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); } 1003 static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); } 1004 1005 #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit)) 1006 #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit)) 1007 1008 // instruction fields 1009 static int aa( int x) { return opp_u_field(x, 30, 30); } 1010 static int ba( int x) { return opp_u_field(x, 15, 11); } 1011 static int bb( int x) { return opp_u_field(x, 20, 16); } 1012 static int bc( int x) { return opp_u_field(x, 25, 21); } 1013 static int bd( int x) { return opp_s_field(x, 29, 16); } 1014 static int bf( ConditionRegister cr) { return bf(cr->encoding()); } 1015 static int bf( int x) { return opp_u_field(x, 8, 6); } 1016 static int bfa(ConditionRegister cr) { return bfa(cr->encoding()); } 1017 static int bfa( int x) { return opp_u_field(x, 13, 11); } 1018 static int bh( int x) { return opp_u_field(x, 20, 19); } 1019 static int bi( int x) { return opp_u_field(x, 15, 11); } 1020 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; } 1021 static int bo( int x) { return opp_u_field(x, 10, 6); } 1022 static int bt( int x) { return opp_u_field(x, 10, 6); } 1023 static int d1( int x) { return opp_s_field(x, 31, 16); } 1024 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); } 1025 static int eh( int x) { return opp_u_field(x, 31, 31); } 1026 static int flm( int x) { return opp_u_field(x, 14, 7); } 1027 static int fra( FloatRegister r) { return fra(r->encoding());} 1028 static int frb( FloatRegister r) { return frb(r->encoding());} 1029 static int frc( FloatRegister r) { return frc(r->encoding());} 1030 static int frs( FloatRegister r) { return frs(r->encoding());} 1031 static int frt( FloatRegister r) { return frt(r->encoding());} 1032 static int fra( int x) { return opp_u_field(x, 15, 11); } 1033 static int frb( int x) { return opp_u_field(x, 20, 16); } 1034 static int frc( int x) { return opp_u_field(x, 25, 21); } 1035 static int frs( int x) { return opp_u_field(x, 10, 6); } 1036 static int frt( int x) { return opp_u_field(x, 10, 6); } 1037 static int fxm( int x) { return opp_u_field(x, 19, 12); } 1038 static int l10( int x) { return opp_u_field(x, 10, 10); } 1039 static int l15( int x) { return opp_u_field(x, 15, 15); } 1040 static int l910( int x) { return opp_u_field(x, 10, 9); } 1041 static int e1215( int x) { return opp_u_field(x, 15, 12); } 1042 static int lev( int x) { return opp_u_field(x, 26, 20); } 1043 static int li( int x) { return opp_s_field(x, 29, 6); } 1044 static int lk( int x) { return opp_u_field(x, 31, 31); } 1045 static int mb2125( int x) { return opp_u_field(x, 25, 21); } 1046 static int me2630( int x) { return opp_u_field(x, 30, 26); } 1047 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); } 1048 static int me2126( int x) { return mb2126(x); } 1049 static int nb( int x) { return opp_u_field(x, 20, 16); } 1050 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes 1051 static int oe( int x) { return opp_u_field(x, 21, 21); } 1052 static int ra( Register r) { return ra(r->encoding()); } 1053 static int ra( int x) { return opp_u_field(x, 15, 11); } 1054 static int rb( Register r) { return rb(r->encoding()); } 1055 static int rb( int x) { return opp_u_field(x, 20, 16); } 1056 static int rc( int x) { return opp_u_field(x, 31, 31); } 1057 static int rs( Register r) { return rs(r->encoding()); } 1058 static int rs( int x) { return opp_u_field(x, 10, 6); } 1059 // we don't want to use R0 in memory accesses, because it has value `0' then 1060 static int ra0mem( Register r) { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); } 1061 static int ra0mem( int x) { assert(x != 0, "cannot use register 0 in memory access"); return ra(x); } 1062 1063 // register r is target 1064 static int rt( Register r) { return rs(r); } 1065 static int rt( int x) { return rs(x); } 1066 static int rta( Register r) { return ra(r); } 1067 static int rta0mem( Register r) { rta(r); return ra0mem(r); } 1068 1069 static int sh1620( int x) { return opp_u_field(x, 20, 16); } 1070 static int sh30( int x) { return opp_u_field(x, 30, 30); } 1071 static int sh162030( int x) { return sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); } 1072 static int si( int x) { return opp_s_field(x, 31, 16); } 1073 static int spr( int x) { return opp_u_field(x, 20, 11); } 1074 static int sr( int x) { return opp_u_field(x, 15, 12); } 1075 static int tbr( int x) { return opp_u_field(x, 20, 11); } 1076 static int th( int x) { return opp_u_field(x, 10, 7); } 1077 static int thct( int x) { assert((x&8) == 0, "must be valid cache specification"); return th(x); } 1078 static int thds( int x) { assert((x&8) == 8, "must be valid stream specification"); return th(x); } 1079 static int to( int x) { return opp_u_field(x, 10, 6); } 1080 static int u( int x) { return opp_u_field(x, 19, 16); } 1081 static int ui( int x) { return opp_u_field(x, 31, 16); } 1082 1083 // Support vector instructions for >= Power6. 1084 static int vra( int x) { return opp_u_field(x, 15, 11); } 1085 static int vrb( int x) { return opp_u_field(x, 20, 16); } 1086 static int vrc( int x) { return opp_u_field(x, 25, 21); } 1087 static int vrs( int x) { return opp_u_field(x, 10, 6); } 1088 static int vrt( int x) { return opp_u_field(x, 10, 6); } 1089 1090 static int vra( VectorRegister r) { return vra(r->encoding());} 1091 static int vrb( VectorRegister r) { return vrb(r->encoding());} 1092 static int vrc( VectorRegister r) { return vrc(r->encoding());} 1093 static int vrs( VectorRegister r) { return vrs(r->encoding());} 1094 static int vrt( VectorRegister r) { return vrt(r->encoding());} 1095 1096 // Support Vector-Scalar (VSX) instructions. 1097 static int vsra( int x) { return opp_u_field(x, 15, 11); } 1098 static int vsrb( int x) { return opp_u_field(x, 20, 16); } 1099 static int vsrc( int x) { return opp_u_field(x, 25, 21); } 1100 static int vsrs( int x) { return opp_u_field(x, 10, 6); } 1101 static int vsrt( int x) { return opp_u_field(x, 10, 6); } 1102 1103 static int vsra( VectorSRegister r) { return vsra(r->encoding());} 1104 static int vsrb( VectorSRegister r) { return vsrb(r->encoding());} 1105 static int vsrc( VectorSRegister r) { return vsrc(r->encoding());} 1106 static int vsrs( VectorSRegister r) { return vsrs(r->encoding());} 1107 static int vsrt( VectorSRegister r) { return vsrt(r->encoding());} 1108 1109 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions 1110 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions 1111 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction 1112 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions 1113 1114 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes 1115 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes 1116 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes 1117 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes 1118 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes 1119 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes 1120 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes 1121 1122 protected: 1123 // Compute relative address for branch. 1124 static intptr_t disp(intptr_t x, intptr_t off) { 1125 int xx = x - off; 1126 xx = xx >> 2; 1127 return xx; 1128 } 1129 1130 public: 1131 // signed immediate, in low bits, nbits long 1132 static int simm(int x, int nbits) { 1133 assert_signed_range(x, nbits); 1134 return x & ((1 << nbits) - 1); 1135 } 1136 1137 // unsigned immediate, in low bits, nbits long 1138 static int uimm(int x, int nbits) { 1139 assert_unsigned_const(x, nbits); 1140 return x & ((1 << nbits) - 1); 1141 } 1142 1143 static void set_imm(int* instr, short s) { 1144 // imm is always in the lower 16 bits of the instruction, 1145 // so this is endian-neutral. Same for the get_imm below. 1146 uint32_t w = *(uint32_t *)instr; 1147 *instr = (int)((w & ~0x0000FFFF) | (s & 0x0000FFFF)); 1148 } 1149 1150 static int get_imm(address a, int instruction_number) { 1151 return (short)((int *)a)[instruction_number]; 1152 } 1153 1154 static inline int hi16_signed( int x) { return (int)(int16_t)(x >> 16); } 1155 static inline int lo16_unsigned(int x) { return x & 0xffff; } 1156 1157 protected: 1158 1159 // Extract the top 32 bits in a 64 bit word. 1160 static int32_t hi32(int64_t x) { 1161 int32_t r = int32_t((uint64_t)x >> 32); 1162 return r; 1163 } 1164 1165 public: 1166 1167 static inline unsigned int align_addr(unsigned int addr, unsigned int a) { 1168 return ((addr + (a - 1)) & ~(a - 1)); 1169 } 1170 1171 static inline bool is_aligned(unsigned int addr, unsigned int a) { 1172 return (0 == addr % a); 1173 } 1174 1175 void flush() { 1176 AbstractAssembler::flush(); 1177 } 1178 1179 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32 1180 inline void emit_data(int); 1181 inline void emit_data(int, RelocationHolder const&); 1182 inline void emit_data(int, relocInfo::relocType rtype); 1183 1184 // Emit an address. 1185 inline address emit_addr(const address addr = NULL); 1186 1187#if !defined(ABI_ELFv2) 1188 // Emit a function descriptor with the specified entry point, TOC, 1189 // and ENV. If the entry point is NULL, the descriptor will point 1190 // just past the descriptor. 1191 // Use values from friend functions as defaults. 1192 inline address emit_fd(address entry = NULL, 1193 address toc = (address) FunctionDescriptor::friend_toc, 1194 address env = (address) FunctionDescriptor::friend_env); 1195#endif 1196 1197 ///////////////////////////////////////////////////////////////////////////////////// 1198 // PPC instructions 1199 ///////////////////////////////////////////////////////////////////////////////////// 1200 1201 // Memory instructions use r0 as hard coded 0, e.g. to simulate loading 1202 // immediates. The normal instruction encoders enforce that r0 is not 1203 // passed to them. Use either extended mnemonics encoders or the special ra0 1204 // versions. 1205 1206 // Issue an illegal instruction. 1207 inline void illtrap(); 1208 static inline bool is_illtrap(int x); 1209 1210 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions 1211 inline void addi( Register d, Register a, int si16); 1212 inline void addis(Register d, Register a, int si16); 1213 private: 1214 inline void addi_r0ok( Register d, Register a, int si16); 1215 inline void addis_r0ok(Register d, Register a, int si16); 1216 public: 1217 inline void addic_( Register d, Register a, int si16); 1218 inline void subfic( Register d, Register a, int si16); 1219 inline void add( Register d, Register a, Register b); 1220 inline void add_( Register d, Register a, Register b); 1221 inline void subf( Register d, Register a, Register b); // d = b - a "Sub_from", as in ppc spec. 1222 inline void sub( Register d, Register a, Register b); // d = a - b Swap operands of subf for readability. 1223 inline void subf_( Register d, Register a, Register b); 1224 inline void addc( Register d, Register a, Register b); 1225 inline void addc_( Register d, Register a, Register b); 1226 inline void subfc( Register d, Register a, Register b); 1227 inline void subfc_( Register d, Register a, Register b); 1228 inline void adde( Register d, Register a, Register b); 1229 inline void adde_( Register d, Register a, Register b); 1230 inline void subfe( Register d, Register a, Register b); 1231 inline void subfe_( Register d, Register a, Register b); 1232 inline void addme( Register d, Register a); 1233 inline void addme_( Register d, Register a); 1234 inline void subfme( Register d, Register a); 1235 inline void subfme_(Register d, Register a); 1236 inline void addze( Register d, Register a); 1237 inline void addze_( Register d, Register a); 1238 inline void subfze( Register d, Register a); 1239 inline void subfze_(Register d, Register a); 1240 inline void neg( Register d, Register a); 1241 inline void neg_( Register d, Register a); 1242 inline void mulli( Register d, Register a, int si16); 1243 inline void mulld( Register d, Register a, Register b); 1244 inline void mulld_( Register d, Register a, Register b); 1245 inline void mullw( Register d, Register a, Register b); 1246 inline void mullw_( Register d, Register a, Register b); 1247 inline void mulhw( Register d, Register a, Register b); 1248 inline void mulhw_( Register d, Register a, Register b); 1249 inline void mulhwu( Register d, Register a, Register b); 1250 inline void mulhwu_(Register d, Register a, Register b); 1251 inline void mulhd( Register d, Register a, Register b); 1252 inline void mulhd_( Register d, Register a, Register b); 1253 inline void mulhdu( Register d, Register a, Register b); 1254 inline void mulhdu_(Register d, Register a, Register b); 1255 inline void divd( Register d, Register a, Register b); 1256 inline void divd_( Register d, Register a, Register b); 1257 inline void divw( Register d, Register a, Register b); 1258 inline void divw_( Register d, Register a, Register b); 1259 1260 // Fixed-Point Arithmetic Instructions with Overflow detection 1261 inline void addo( Register d, Register a, Register b); 1262 inline void addo_( Register d, Register a, Register b); 1263 inline void subfo( Register d, Register a, Register b); 1264 inline void subfo_( Register d, Register a, Register b); 1265 inline void addco( Register d, Register a, Register b); 1266 inline void addco_( Register d, Register a, Register b); 1267 inline void subfco( Register d, Register a, Register b); 1268 inline void subfco_( Register d, Register a, Register b); 1269 inline void addeo( Register d, Register a, Register b); 1270 inline void addeo_( Register d, Register a, Register b); 1271 inline void subfeo( Register d, Register a, Register b); 1272 inline void subfeo_( Register d, Register a, Register b); 1273 inline void addmeo( Register d, Register a); 1274 inline void addmeo_( Register d, Register a); 1275 inline void subfmeo( Register d, Register a); 1276 inline void subfmeo_(Register d, Register a); 1277 inline void addzeo( Register d, Register a); 1278 inline void addzeo_( Register d, Register a); 1279 inline void subfzeo( Register d, Register a); 1280 inline void subfzeo_(Register d, Register a); 1281 inline void nego( Register d, Register a); 1282 inline void nego_( Register d, Register a); 1283 inline void mulldo( Register d, Register a, Register b); 1284 inline void mulldo_( Register d, Register a, Register b); 1285 inline void mullwo( Register d, Register a, Register b); 1286 inline void mullwo_( Register d, Register a, Register b); 1287 inline void divdo( Register d, Register a, Register b); 1288 inline void divdo_( Register d, Register a, Register b); 1289 inline void divwo( Register d, Register a, Register b); 1290 inline void divwo_( Register d, Register a, Register b); 1291 1292 // extended mnemonics 1293 inline void li( Register d, int si16); 1294 inline void lis( Register d, int si16); 1295 inline void addir(Register d, int si16, Register a); 1296 1297 static bool is_addi(int x) { 1298 return ADDI_OPCODE == (x & ADDI_OPCODE_MASK); 1299 } 1300 static bool is_addis(int x) { 1301 return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK); 1302 } 1303 static bool is_bxx(int x) { 1304 return BXX_OPCODE == (x & BXX_OPCODE_MASK); 1305 } 1306 static bool is_b(int x) { 1307 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0; 1308 } 1309 static bool is_bl(int x) { 1310 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1; 1311 } 1312 static bool is_bcxx(int x) { 1313 return BCXX_OPCODE == (x & BCXX_OPCODE_MASK); 1314 } 1315 static bool is_bxx_or_bcxx(int x) { 1316 return is_bxx(x) || is_bcxx(x); 1317 } 1318 static bool is_bctrl(int x) { 1319 return x == 0x4e800421; 1320 } 1321 static bool is_bctr(int x) { 1322 return x == 0x4e800420; 1323 } 1324 static bool is_bclr(int x) { 1325 return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK); 1326 } 1327 static bool is_li(int x) { 1328 return is_addi(x) && inv_ra_field(x)==0; 1329 } 1330 static bool is_lis(int x) { 1331 return is_addis(x) && inv_ra_field(x)==0; 1332 } 1333 static bool is_mtctr(int x) { 1334 return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK); 1335 } 1336 static bool is_ld(int x) { 1337 return LD_OPCODE == (x & LD_OPCODE_MASK); 1338 } 1339 static bool is_std(int x) { 1340 return STD_OPCODE == (x & STD_OPCODE_MASK); 1341 } 1342 static bool is_stdu(int x) { 1343 return STDU_OPCODE == (x & STDU_OPCODE_MASK); 1344 } 1345 static bool is_stdx(int x) { 1346 return STDX_OPCODE == (x & STDX_OPCODE_MASK); 1347 } 1348 static bool is_stdux(int x) { 1349 return STDUX_OPCODE == (x & STDUX_OPCODE_MASK); 1350 } 1351 static bool is_stwx(int x) { 1352 return STWX_OPCODE == (x & STWX_OPCODE_MASK); 1353 } 1354 static bool is_stwux(int x) { 1355 return STWUX_OPCODE == (x & STWUX_OPCODE_MASK); 1356 } 1357 static bool is_stw(int x) { 1358 return STW_OPCODE == (x & STW_OPCODE_MASK); 1359 } 1360 static bool is_stwu(int x) { 1361 return STWU_OPCODE == (x & STWU_OPCODE_MASK); 1362 } 1363 static bool is_ori(int x) { 1364 return ORI_OPCODE == (x & ORI_OPCODE_MASK); 1365 }; 1366 static bool is_oris(int x) { 1367 return ORIS_OPCODE == (x & ORIS_OPCODE_MASK); 1368 }; 1369 static bool is_rldicr(int x) { 1370 return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK)); 1371 }; 1372 static bool is_nop(int x) { 1373 return x == 0x60000000; 1374 } 1375 // endgroup opcode for Power6 1376 static bool is_endgroup(int x) { 1377 return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0; 1378 } 1379 1380 1381 private: 1382 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions 1383 inline void cmpi( ConditionRegister bf, int l, Register a, int si16); 1384 inline void cmp( ConditionRegister bf, int l, Register a, Register b); 1385 inline void cmpli(ConditionRegister bf, int l, Register a, int ui16); 1386 inline void cmpl( ConditionRegister bf, int l, Register a, Register b); 1387 1388 public: 1389 // extended mnemonics of Compare Instructions 1390 inline void cmpwi( ConditionRegister crx, Register a, int si16); 1391 inline void cmpdi( ConditionRegister crx, Register a, int si16); 1392 inline void cmpw( ConditionRegister crx, Register a, Register b); 1393 inline void cmpd( ConditionRegister crx, Register a, Register b); 1394 inline void cmplwi(ConditionRegister crx, Register a, int ui16); 1395 inline void cmpldi(ConditionRegister crx, Register a, int ui16); 1396 inline void cmplw( ConditionRegister crx, Register a, Register b); 1397 inline void cmpld( ConditionRegister crx, Register a, Register b); 1398 1399 inline void isel( Register d, Register a, Register b, int bc); 1400 // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value. 1401 inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg); 1402 // Set d = 0 if (cr.cc) equals 1, otherwise b. 1403 inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg); 1404 1405 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions 1406 void andi( Register a, Register s, long ui16); // optimized version 1407 inline void andi_( Register a, Register s, int ui16); 1408 inline void andis_( Register a, Register s, int ui16); 1409 inline void ori( Register a, Register s, int ui16); 1410 inline void oris( Register a, Register s, int ui16); 1411 inline void xori( Register a, Register s, int ui16); 1412 inline void xoris( Register a, Register s, int ui16); 1413 inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword 1414 inline void and_( Register a, Register s, Register b); 1415 // Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a 1416 // SMT-priority change instruction (see SMT instructions below). 1417 inline void or_unchecked(Register a, Register s, Register b); 1418 inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword 1419 inline void or_( Register a, Register s, Register b); 1420 inline void xorr( Register a, Register s, Register b); // suffixed by 'r' as 'xor' is C++ keyword 1421 inline void xor_( Register a, Register s, Register b); 1422 inline void nand( Register a, Register s, Register b); 1423 inline void nand_( Register a, Register s, Register b); 1424 inline void nor( Register a, Register s, Register b); 1425 inline void nor_( Register a, Register s, Register b); 1426 inline void andc( Register a, Register s, Register b); 1427 inline void andc_( Register a, Register s, Register b); 1428 inline void orc( Register a, Register s, Register b); 1429 inline void orc_( Register a, Register s, Register b); 1430 inline void extsb( Register a, Register s); 1431 inline void extsb_( Register a, Register s); 1432 inline void extsh( Register a, Register s); 1433 inline void extsh_( Register a, Register s); 1434 inline void extsw( Register a, Register s); 1435 inline void extsw_( Register a, Register s); 1436 1437 // extended mnemonics 1438 inline void nop(); 1439 // NOP for FP and BR units (different versions to allow them to be in one group) 1440 inline void fpnop0(); 1441 inline void fpnop1(); 1442 inline void brnop0(); 1443 inline void brnop1(); 1444 inline void brnop2(); 1445 1446 inline void mr( Register d, Register s); 1447 inline void ori_opt( Register d, int ui16); 1448 inline void oris_opt(Register d, int ui16); 1449 1450 // endgroup opcode for Power6 1451 inline void endgroup(); 1452 1453 // count instructions 1454 inline void cntlzw( Register a, Register s); 1455 inline void cntlzw_( Register a, Register s); 1456 inline void cntlzd( Register a, Register s); 1457 inline void cntlzd_( Register a, Register s); 1458 1459 // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions 1460 inline void sld( Register a, Register s, Register b); 1461 inline void sld_( Register a, Register s, Register b); 1462 inline void slw( Register a, Register s, Register b); 1463 inline void slw_( Register a, Register s, Register b); 1464 inline void srd( Register a, Register s, Register b); 1465 inline void srd_( Register a, Register s, Register b); 1466 inline void srw( Register a, Register s, Register b); 1467 inline void srw_( Register a, Register s, Register b); 1468 inline void srad( Register a, Register s, Register b); 1469 inline void srad_( Register a, Register s, Register b); 1470 inline void sraw( Register a, Register s, Register b); 1471 inline void sraw_( Register a, Register s, Register b); 1472 inline void sradi( Register a, Register s, int sh6); 1473 inline void sradi_( Register a, Register s, int sh6); 1474 inline void srawi( Register a, Register s, int sh5); 1475 inline void srawi_( Register a, Register s, int sh5); 1476 1477 // extended mnemonics for Shift Instructions 1478 inline void sldi( Register a, Register s, int sh6); 1479 inline void sldi_( Register a, Register s, int sh6); 1480 inline void slwi( Register a, Register s, int sh5); 1481 inline void slwi_( Register a, Register s, int sh5); 1482 inline void srdi( Register a, Register s, int sh6); 1483 inline void srdi_( Register a, Register s, int sh6); 1484 inline void srwi( Register a, Register s, int sh5); 1485 inline void srwi_( Register a, Register s, int sh5); 1486 1487 inline void clrrdi( Register a, Register s, int ui6); 1488 inline void clrrdi_( Register a, Register s, int ui6); 1489 inline void clrldi( Register a, Register s, int ui6); 1490 inline void clrldi_( Register a, Register s, int ui6); 1491 inline void clrlsldi(Register a, Register s, int clrl6, int shl6); 1492 inline void clrlsldi_(Register a, Register s, int clrl6, int shl6); 1493 inline void extrdi( Register a, Register s, int n, int b); 1494 // testbit with condition register 1495 inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6); 1496 1497 // rotate instructions 1498 inline void rotldi( Register a, Register s, int n); 1499 inline void rotrdi( Register a, Register s, int n); 1500 inline void rotlwi( Register a, Register s, int n); 1501 inline void rotrwi( Register a, Register s, int n); 1502 1503 // Rotate Instructions 1504 inline void rldic( Register a, Register s, int sh6, int mb6); 1505 inline void rldic_( Register a, Register s, int sh6, int mb6); 1506 inline void rldicr( Register a, Register s, int sh6, int mb6); 1507 inline void rldicr_( Register a, Register s, int sh6, int mb6); 1508 inline void rldicl( Register a, Register s, int sh6, int mb6); 1509 inline void rldicl_( Register a, Register s, int sh6, int mb6); 1510 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5); 1511 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5); 1512 inline void rldimi( Register a, Register s, int sh6, int mb6); 1513 inline void rldimi_( Register a, Register s, int sh6, int mb6); 1514 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5); 1515 inline void insrdi( Register a, Register s, int n, int b); 1516 inline void insrwi( Register a, Register s, int n, int b); 1517 1518 // PPC 1, section 3.3.2 Fixed-Point Load Instructions 1519 // 4 bytes 1520 inline void lwzx( Register d, Register s1, Register s2); 1521 inline void lwz( Register d, int si16, Register s1); 1522 inline void lwzu( Register d, int si16, Register s1); 1523 1524 // 4 bytes 1525 inline void lwax( Register d, Register s1, Register s2); 1526 inline void lwa( Register d, int si16, Register s1); 1527 1528 // 4 bytes reversed 1529 inline void lwbrx( Register d, Register s1, Register s2); 1530 1531 // 2 bytes 1532 inline void lhzx( Register d, Register s1, Register s2); 1533 inline void lhz( Register d, int si16, Register s1); 1534 inline void lhzu( Register d, int si16, Register s1); 1535 1536 // 2 bytes reversed 1537 inline void lhbrx( Register d, Register s1, Register s2); 1538 1539 // 2 bytes 1540 inline void lhax( Register d, Register s1, Register s2); 1541 inline void lha( Register d, int si16, Register s1); 1542 inline void lhau( Register d, int si16, Register s1); 1543 1544 // 1 byte 1545 inline void lbzx( Register d, Register s1, Register s2); 1546 inline void lbz( Register d, int si16, Register s1); 1547 inline void lbzu( Register d, int si16, Register s1); 1548 1549 // 8 bytes 1550 inline void ldx( Register d, Register s1, Register s2); 1551 inline void ld( Register d, int si16, Register s1); 1552 inline void ldu( Register d, int si16, Register s1); 1553 1554 // For convenience. Load pointer into d from b+s1. 1555 inline void ld_ptr(Register d, int b, Register s1); 1556 DEBUG_ONLY(inline void ld_ptr(Register d, ByteSize b, Register s1);) 1557 1558 // PPC 1, section 3.3.3 Fixed-Point Store Instructions 1559 inline void stwx( Register d, Register s1, Register s2); 1560 inline void stw( Register d, int si16, Register s1); 1561 inline void stwu( Register d, int si16, Register s1); 1562 1563 inline void sthx( Register d, Register s1, Register s2); 1564 inline void sth( Register d, int si16, Register s1); 1565 inline void sthu( Register d, int si16, Register s1); 1566 1567 inline void stbx( Register d, Register s1, Register s2); 1568 inline void stb( Register d, int si16, Register s1); 1569 inline void stbu( Register d, int si16, Register s1); 1570 1571 inline void stdx( Register d, Register s1, Register s2); 1572 inline void std( Register d, int si16, Register s1); 1573 inline void stdu( Register d, int si16, Register s1); 1574 inline void stdux(Register s, Register a, Register b); 1575 1576 // PPC 1, section 3.3.13 Move To/From System Register Instructions 1577 inline void mtlr( Register s1); 1578 inline void mflr( Register d); 1579 inline void mtctr(Register s1); 1580 inline void mfctr(Register d); 1581 inline void mtcrf(int fxm, Register s); 1582 inline void mfcr( Register d); 1583 inline void mcrf( ConditionRegister crd, ConditionRegister cra); 1584 inline void mtcr( Register s); 1585 1586 // Special purpose registers 1587 // Exception Register 1588 inline void mtxer(Register s1); 1589 inline void mfxer(Register d); 1590 // Vector Register Save Register 1591 inline void mtvrsave(Register s1); 1592 inline void mfvrsave(Register d); 1593 // Timebase 1594 inline void mftb(Register d); 1595 // Introduced with Power 8: 1596 // Data Stream Control Register 1597 inline void mtdscr(Register s1); 1598 inline void mfdscr(Register d ); 1599 // Transactional Memory Registers 1600 inline void mftfhar(Register d); 1601 inline void mftfiar(Register d); 1602 inline void mftexasr(Register d); 1603 inline void mftexasru(Register d); 1604 1605 // TEXASR bit description 1606 enum transaction_failure_reason { 1607 // Upper half (TEXASRU): 1608 tm_failure_persistent = 7, // The failure is likely to recur on each execution. 1609 tm_disallowed = 8, // The instruction is not permitted. 1610 tm_nesting_of = 9, // The maximum transaction level was exceeded. 1611 tm_footprint_of = 10, // The tracking limit for transactional storage accesses was exceeded. 1612 tm_self_induced_cf = 11, // A self-induced conflict occurred in Suspended state. 1613 tm_non_trans_cf = 12, // A conflict occurred with a non-transactional access by another processor. 1614 tm_trans_cf = 13, // A conflict occurred with another transaction. 1615 tm_translation_cf = 14, // A conflict occurred with a TLB invalidation. 1616 tm_inst_fetch_cf = 16, // An instruction fetch was performed from a block that was previously written transactionally. 1617 tm_tabort = 31, // Termination was caused by the execution of an abort instruction. 1618 // Lower half: 1619 tm_suspended = 32, // Failure was recorded in Suspended state. 1620 tm_failure_summary = 36, // Failure has been detected and recorded. 1621 tm_tfiar_exact = 37, // Value in the TFIAR is exact. 1622 tm_rot = 38, // Rollback-only transaction. 1623 }; 1624 1625 // PPC 1, section 2.4.1 Branch Instructions 1626 inline void b( address a, relocInfo::relocType rt = relocInfo::none); 1627 inline void b( Label& L); 1628 inline void bl( address a, relocInfo::relocType rt = relocInfo::none); 1629 inline void bl( Label& L); 1630 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none); 1631 inline void bc( int boint, int biint, Label& L); 1632 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none); 1633 inline void bcl(int boint, int biint, Label& L); 1634 1635 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none); 1636 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none); 1637 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame, 1638 relocInfo::relocType rt = relocInfo::none); 1639 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn, 1640 relocInfo::relocType rt = relocInfo::none); 1641 1642 // helper function for b, bcxx 1643 inline bool is_within_range_of_b(address a, address pc); 1644 inline bool is_within_range_of_bcxx(address a, address pc); 1645 1646 // get the destination of a bxx branch (b, bl, ba, bla) 1647 static inline address bxx_destination(address baddr); 1648 static inline address bxx_destination(int instr, address pc); 1649 static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos); 1650 1651 // extended mnemonics for branch instructions 1652 inline void blt(ConditionRegister crx, Label& L); 1653 inline void bgt(ConditionRegister crx, Label& L); 1654 inline void beq(ConditionRegister crx, Label& L); 1655 inline void bso(ConditionRegister crx, Label& L); 1656 inline void bge(ConditionRegister crx, Label& L); 1657 inline void ble(ConditionRegister crx, Label& L); 1658 inline void bne(ConditionRegister crx, Label& L); 1659 inline void bns(ConditionRegister crx, Label& L); 1660 1661 // Branch instructions with static prediction hints. 1662 inline void blt_predict_taken( ConditionRegister crx, Label& L); 1663 inline void bgt_predict_taken( ConditionRegister crx, Label& L); 1664 inline void beq_predict_taken( ConditionRegister crx, Label& L); 1665 inline void bso_predict_taken( ConditionRegister crx, Label& L); 1666 inline void bge_predict_taken( ConditionRegister crx, Label& L); 1667 inline void ble_predict_taken( ConditionRegister crx, Label& L); 1668 inline void bne_predict_taken( ConditionRegister crx, Label& L); 1669 inline void bns_predict_taken( ConditionRegister crx, Label& L); 1670 inline void blt_predict_not_taken(ConditionRegister crx, Label& L); 1671 inline void bgt_predict_not_taken(ConditionRegister crx, Label& L); 1672 inline void beq_predict_not_taken(ConditionRegister crx, Label& L); 1673 inline void bso_predict_not_taken(ConditionRegister crx, Label& L); 1674 inline void bge_predict_not_taken(ConditionRegister crx, Label& L); 1675 inline void ble_predict_not_taken(ConditionRegister crx, Label& L); 1676 inline void bne_predict_not_taken(ConditionRegister crx, Label& L); 1677 inline void bns_predict_not_taken(ConditionRegister crx, Label& L); 1678 1679 // for use in conjunction with testbitdi: 1680 inline void btrue( ConditionRegister crx, Label& L); 1681 inline void bfalse(ConditionRegister crx, Label& L); 1682 1683 inline void bltl(ConditionRegister crx, Label& L); 1684 inline void bgtl(ConditionRegister crx, Label& L); 1685 inline void beql(ConditionRegister crx, Label& L); 1686 inline void bsol(ConditionRegister crx, Label& L); 1687 inline void bgel(ConditionRegister crx, Label& L); 1688 inline void blel(ConditionRegister crx, Label& L); 1689 inline void bnel(ConditionRegister crx, Label& L); 1690 inline void bnsl(ConditionRegister crx, Label& L); 1691 1692 // extended mnemonics for Branch Instructions via LR 1693 // We use `blr' for returns. 1694 inline void blr(relocInfo::relocType rt = relocInfo::none); 1695 1696 // extended mnemonics for Branch Instructions with CTR 1697 // bdnz means `decrement CTR and jump to L if CTR is not zero' 1698 inline void bdnz(Label& L); 1699 // Decrement and branch if result is zero. 1700 inline void bdz(Label& L); 1701 // we use `bctr[l]' for jumps/calls in function descriptor glue 1702 // code, e.g. calls to runtime functions 1703 inline void bctr( relocInfo::relocType rt = relocInfo::none); 1704 inline void bctrl(relocInfo::relocType rt = relocInfo::none); 1705 // conditional jumps/branches via CTR 1706 inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1707 inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1708 inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1709 inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1710 1711 // condition register logic instructions 1712 // NOTE: There's a preferred form: d and s2 should point into the same condition register. 1713 inline void crand( int d, int s1, int s2); 1714 inline void crnand(int d, int s1, int s2); 1715 inline void cror( int d, int s1, int s2); 1716 inline void crxor( int d, int s1, int s2); 1717 inline void crnor( int d, int s1, int s2); 1718 inline void creqv( int d, int s1, int s2); 1719 inline void crandc(int d, int s1, int s2); 1720 inline void crorc( int d, int s1, int s2); 1721 1722 // More convenient version. 1723 int condition_register_bit(ConditionRegister cr, Condition c) { 1724 return 4 * (int)(intptr_t)cr + c; 1725 } 1726 void crand( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1727 void crnand(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1728 void cror( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1729 void crxor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1730 void crnor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1731 void creqv( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1732 void crandc(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1733 void crorc( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1734 1735 // icache and dcache related instructions 1736 inline void icbi( Register s1, Register s2); 1737 //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only. 1738 inline void dcbz( Register s1, Register s2); 1739 inline void dcbst( Register s1, Register s2); 1740 inline void dcbf( Register s1, Register s2); 1741 1742 enum ct_cache_specification { 1743 ct_primary_cache = 0, 1744 ct_secondary_cache = 2 1745 }; 1746 // dcache read hint 1747 inline void dcbt( Register s1, Register s2); 1748 inline void dcbtct( Register s1, Register s2, int ct); 1749 inline void dcbtds( Register s1, Register s2, int ds); 1750 // dcache write hint 1751 inline void dcbtst( Register s1, Register s2); 1752 inline void dcbtstct(Register s1, Register s2, int ct); 1753 1754 // machine barrier instructions: 1755 // 1756 // - sync two-way memory barrier, aka fence 1757 // - lwsync orders Store|Store, 1758 // Load|Store, 1759 // Load|Load, 1760 // but not Store|Load 1761 // - eieio orders memory accesses for device memory (only) 1762 // - isync invalidates speculatively executed instructions 1763 // From the Power ISA 2.06 documentation: 1764 // "[...] an isync instruction prevents the execution of 1765 // instructions following the isync until instructions 1766 // preceding the isync have completed, [...]" 1767 // From IBM's AIX assembler reference: 1768 // "The isync [...] instructions causes the processor to 1769 // refetch any instructions that might have been fetched 1770 // prior to the isync instruction. The instruction isync 1771 // causes the processor to wait for all previous instructions 1772 // to complete. Then any instructions already fetched are 1773 // discarded and instruction processing continues in the 1774 // environment established by the previous instructions." 1775 // 1776 // semantic barrier instructions: 1777 // (as defined in orderAccess.hpp) 1778 // 1779 // - release orders Store|Store, (maps to lwsync) 1780 // Load|Store 1781 // - acquire orders Load|Store, (maps to lwsync) 1782 // Load|Load 1783 // - fence orders Store|Store, (maps to sync) 1784 // Load|Store, 1785 // Load|Load, 1786 // Store|Load 1787 // 1788 private: 1789 inline void sync(int l); 1790 public: 1791 inline void sync(); 1792 inline void lwsync(); 1793 inline void ptesync(); 1794 inline void eieio(); 1795 inline void isync(); 1796 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8) 1797 1798 // Wait instructions for polling. Attention: May result in SIGILL. 1799 inline void wait(); 1800 inline void waitrsv(); // >=Power7 1801 1802 // atomics 1803 inline void lbarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8 1804 inline void lharx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8 1805 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0); 1806 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0); 1807 inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8 1808 inline bool lxarx_hint_exclusive_access(); 1809 inline void lbarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1810 inline void lharx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1811 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1812 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1813 inline void lqarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1814 inline void stbcx_( Register s, Register a, Register b); 1815 inline void sthcx_( Register s, Register a, Register b); 1816 inline void stwcx_( Register s, Register a, Register b); 1817 inline void stdcx_( Register s, Register a, Register b); 1818 inline void stqcx_( Register s, Register a, Register b); 1819 1820 // Instructions for adjusting thread priority for simultaneous 1821 // multithreading (SMT) on Power5. 1822 private: 1823 inline void smt_prio_very_low(); 1824 inline void smt_prio_medium_high(); 1825 inline void smt_prio_high(); 1826 1827 public: 1828 inline void smt_prio_low(); 1829 inline void smt_prio_medium_low(); 1830 inline void smt_prio_medium(); 1831 // >= Power7 1832 inline void smt_yield(); 1833 inline void smt_mdoio(); 1834 inline void smt_mdoom(); 1835 // >= Power8 1836 inline void smt_miso(); 1837 1838 // trap instructions 1839 inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur) 1840 // NOT FOR DIRECT USE!! 1841 protected: 1842 inline void tdi_unchecked(int tobits, Register a, int si16); 1843 inline void twi_unchecked(int tobits, Register a, int si16); 1844 inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP 1845 inline void twi( int tobits, Register a, int si16); // asserts UseSIGTRAP 1846 inline void td( int tobits, Register a, Register b); // asserts UseSIGTRAP 1847 inline void tw( int tobits, Register a, Register b); // asserts UseSIGTRAP 1848 1849 static bool is_tdi(int x, int tobits, int ra, int si16) { 1850 return (TDI_OPCODE == (x & TDI_OPCODE_MASK)) 1851 && (tobits == inv_to_field(x)) 1852 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1853 && (si16 == inv_si_field(x)); 1854 } 1855 1856 static bool is_twi(int x, int tobits, int ra, int si16) { 1857 return (TWI_OPCODE == (x & TWI_OPCODE_MASK)) 1858 && (tobits == inv_to_field(x)) 1859 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1860 && (si16 == inv_si_field(x)); 1861 } 1862 1863 static bool is_twi(int x, int tobits, int ra) { 1864 return (TWI_OPCODE == (x & TWI_OPCODE_MASK)) 1865 && (tobits == inv_to_field(x)) 1866 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)); 1867 } 1868 1869 static bool is_td(int x, int tobits, int ra, int rb) { 1870 return (TD_OPCODE == (x & TD_OPCODE_MASK)) 1871 && (tobits == inv_to_field(x)) 1872 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1873 && (rb == -1/*any reg*/ || rb == inv_rb_field(x)); 1874 } 1875 1876 static bool is_tw(int x, int tobits, int ra, int rb) { 1877 return (TW_OPCODE == (x & TW_OPCODE_MASK)) 1878 && (tobits == inv_to_field(x)) 1879 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1880 && (rb == -1/*any reg*/ || rb == inv_rb_field(x)); 1881 } 1882 1883 public: 1884 // PPC floating point instructions 1885 // PPC 1, section 4.6.2 Floating-Point Load Instructions 1886 inline void lfs( FloatRegister d, int si16, Register a); 1887 inline void lfsu( FloatRegister d, int si16, Register a); 1888 inline void lfsx( FloatRegister d, Register a, Register b); 1889 inline void lfd( FloatRegister d, int si16, Register a); 1890 inline void lfdu( FloatRegister d, int si16, Register a); 1891 inline void lfdx( FloatRegister d, Register a, Register b); 1892 1893 // PPC 1, section 4.6.3 Floating-Point Store Instructions 1894 inline void stfs( FloatRegister s, int si16, Register a); 1895 inline void stfsu( FloatRegister s, int si16, Register a); 1896 inline void stfsx( FloatRegister s, Register a, Register b); 1897 inline void stfd( FloatRegister s, int si16, Register a); 1898 inline void stfdu( FloatRegister s, int si16, Register a); 1899 inline void stfdx( FloatRegister s, Register a, Register b); 1900 1901 // PPC 1, section 4.6.4 Floating-Point Move Instructions 1902 inline void fmr( FloatRegister d, FloatRegister b); 1903 inline void fmr_( FloatRegister d, FloatRegister b); 1904 1905 // inline void mffgpr( FloatRegister d, Register b); 1906 // inline void mftgpr( Register d, FloatRegister b); 1907 inline void cmpb( Register a, Register s, Register b); 1908 inline void popcntb(Register a, Register s); 1909 inline void popcntw(Register a, Register s); 1910 inline void popcntd(Register a, Register s); 1911 1912 inline void fneg( FloatRegister d, FloatRegister b); 1913 inline void fneg_( FloatRegister d, FloatRegister b); 1914 inline void fabs( FloatRegister d, FloatRegister b); 1915 inline void fabs_( FloatRegister d, FloatRegister b); 1916 inline void fnabs( FloatRegister d, FloatRegister b); 1917 inline void fnabs_(FloatRegister d, FloatRegister b); 1918 1919 // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions 1920 inline void fadd( FloatRegister d, FloatRegister a, FloatRegister b); 1921 inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b); 1922 inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b); 1923 inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b); 1924 inline void fsub( FloatRegister d, FloatRegister a, FloatRegister b); 1925 inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b); 1926 inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b); 1927 inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b); 1928 inline void fmul( FloatRegister d, FloatRegister a, FloatRegister c); 1929 inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c); 1930 inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c); 1931 inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c); 1932 inline void fdiv( FloatRegister d, FloatRegister a, FloatRegister b); 1933 inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b); 1934 inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b); 1935 inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b); 1936 1937 // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions 1938 inline void frsp( FloatRegister d, FloatRegister b); 1939 inline void fctid( FloatRegister d, FloatRegister b); 1940 inline void fctidz(FloatRegister d, FloatRegister b); 1941 inline void fctiw( FloatRegister d, FloatRegister b); 1942 inline void fctiwz(FloatRegister d, FloatRegister b); 1943 inline void fcfid( FloatRegister d, FloatRegister b); 1944 inline void fcfids(FloatRegister d, FloatRegister b); 1945 1946 // PPC 1, section 4.6.7 Floating-Point Compare Instructions 1947 inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b); 1948 1949 inline void fsqrt( FloatRegister d, FloatRegister b); 1950 inline void fsqrts(FloatRegister d, FloatRegister b); 1951 1952 // Vector instructions for >= Power6. 1953 inline void lvebx( VectorRegister d, Register s1, Register s2); 1954 inline void lvehx( VectorRegister d, Register s1, Register s2); 1955 inline void lvewx( VectorRegister d, Register s1, Register s2); 1956 inline void lvx( VectorRegister d, Register s1, Register s2); 1957 inline void lvxl( VectorRegister d, Register s1, Register s2); 1958 inline void stvebx( VectorRegister d, Register s1, Register s2); 1959 inline void stvehx( VectorRegister d, Register s1, Register s2); 1960 inline void stvewx( VectorRegister d, Register s1, Register s2); 1961 inline void stvx( VectorRegister d, Register s1, Register s2); 1962 inline void stvxl( VectorRegister d, Register s1, Register s2); 1963 inline void lvsl( VectorRegister d, Register s1, Register s2); 1964 inline void lvsr( VectorRegister d, Register s1, Register s2); 1965 inline void vpkpx( VectorRegister d, VectorRegister a, VectorRegister b); 1966 inline void vpkshss( VectorRegister d, VectorRegister a, VectorRegister b); 1967 inline void vpkswss( VectorRegister d, VectorRegister a, VectorRegister b); 1968 inline void vpkshus( VectorRegister d, VectorRegister a, VectorRegister b); 1969 inline void vpkswus( VectorRegister d, VectorRegister a, VectorRegister b); 1970 inline void vpkuhum( VectorRegister d, VectorRegister a, VectorRegister b); 1971 inline void vpkuwum( VectorRegister d, VectorRegister a, VectorRegister b); 1972 inline void vpkuhus( VectorRegister d, VectorRegister a, VectorRegister b); 1973 inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b); 1974 inline void vupkhpx( VectorRegister d, VectorRegister b); 1975 inline void vupkhsb( VectorRegister d, VectorRegister b); 1976 inline void vupkhsh( VectorRegister d, VectorRegister b); 1977 inline void vupklpx( VectorRegister d, VectorRegister b); 1978 inline void vupklsb( VectorRegister d, VectorRegister b); 1979 inline void vupklsh( VectorRegister d, VectorRegister b); 1980 inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b); 1981 inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b); 1982 inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b); 1983 inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b); 1984 inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b); 1985 inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b); 1986 inline void vsplt( VectorRegister d, int ui4, VectorRegister b); 1987 inline void vsplth( VectorRegister d, int ui3, VectorRegister b); 1988 inline void vspltw( VectorRegister d, int ui2, VectorRegister b); 1989 inline void vspltisb( VectorRegister d, int si5); 1990 inline void vspltish( VectorRegister d, int si5); 1991 inline void vspltisw( VectorRegister d, int si5); 1992 inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1993 inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 1994 inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b); 1995 inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int si4); 1996 inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b); 1997 inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b); 1998 inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b); 1999 inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b); 2000 inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b); 2001 inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b); 2002 inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b); 2003 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b); 2004 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b); 2005 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b); 2006 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b); 2007 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b); 2008 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b); 2009 inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b); 2010 inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b); 2011 inline void vsubsbs( VectorRegister d, VectorRegister a, VectorRegister b); 2012 inline void vsubsws( VectorRegister d, VectorRegister a, VectorRegister b); 2013 inline void vsububm( VectorRegister d, VectorRegister a, VectorRegister b); 2014 inline void vsubuwm( VectorRegister d, VectorRegister a, VectorRegister b); 2015 inline void vsubuhm( VectorRegister d, VectorRegister a, VectorRegister b); 2016 inline void vsububs( VectorRegister d, VectorRegister a, VectorRegister b); 2017 inline void vsubuws( VectorRegister d, VectorRegister a, VectorRegister b); 2018 inline void vsubuhs( VectorRegister d, VectorRegister a, VectorRegister b); 2019 inline void vmulesb( VectorRegister d, VectorRegister a, VectorRegister b); 2020 inline void vmuleub( VectorRegister d, VectorRegister a, VectorRegister b); 2021 inline void vmulesh( VectorRegister d, VectorRegister a, VectorRegister b); 2022 inline void vmuleuh( VectorRegister d, VectorRegister a, VectorRegister b); 2023 inline void vmulosb( VectorRegister d, VectorRegister a, VectorRegister b); 2024 inline void vmuloub( VectorRegister d, VectorRegister a, VectorRegister b); 2025 inline void vmulosh( VectorRegister d, VectorRegister a, VectorRegister b); 2026 inline void vmulouh( VectorRegister d, VectorRegister a, VectorRegister b); 2027 inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2028 inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c); 2029 inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2030 inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2031 inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2032 inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2033 inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2034 inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2035 inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2036 inline void vsumsws( VectorRegister d, VectorRegister a, VectorRegister b); 2037 inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b); 2038 inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b); 2039 inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b); 2040 inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b); 2041 inline void vavgsb( VectorRegister d, VectorRegister a, VectorRegister b); 2042 inline void vavgsw( VectorRegister d, VectorRegister a, VectorRegister b); 2043 inline void vavgsh( VectorRegister d, VectorRegister a, VectorRegister b); 2044 inline void vavgub( VectorRegister d, VectorRegister a, VectorRegister b); 2045 inline void vavguw( VectorRegister d, VectorRegister a, VectorRegister b); 2046 inline void vavguh( VectorRegister d, VectorRegister a, VectorRegister b); 2047 inline void vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b); 2048 inline void vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b); 2049 inline void vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b); 2050 inline void vmaxub( VectorRegister d, VectorRegister a, VectorRegister b); 2051 inline void vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b); 2052 inline void vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b); 2053 inline void vminsb( VectorRegister d, VectorRegister a, VectorRegister b); 2054 inline void vminsw( VectorRegister d, VectorRegister a, VectorRegister b); 2055 inline void vminsh( VectorRegister d, VectorRegister a, VectorRegister b); 2056 inline void vminub( VectorRegister d, VectorRegister a, VectorRegister b); 2057 inline void vminuw( VectorRegister d, VectorRegister a, VectorRegister b); 2058 inline void vminuh( VectorRegister d, VectorRegister a, VectorRegister b); 2059 inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b); 2060 inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b); 2061 inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b); 2062 inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b); 2063 inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b); 2064 inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b); 2065 inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b); 2066 inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b); 2067 inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b); 2068 inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b); 2069 inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b); 2070 inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b); 2071 inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b); 2072 inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b); 2073 inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b); 2074 inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b); 2075 inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b); 2076 inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b); 2077 inline void vand( VectorRegister d, VectorRegister a, VectorRegister b); 2078 inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b); 2079 inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b); 2080 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b); 2081 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b); 2082 inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b); 2083 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b); 2084 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b); 2085 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b); 2086 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b); 2087 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b); 2088 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b); 2089 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b); 2090 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b); 2091 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b); 2092 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b); 2093 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b); 2094 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b); 2095 // Vector Floating-Point not implemented yet 2096 inline void mtvscr( VectorRegister b); 2097 inline void mfvscr( VectorRegister d); 2098 2099 // Vector-Scalar (VSX) instructions. 2100 inline void lxvd2x( VectorSRegister d, Register a, Register b); 2101 inline void stxvd2x( VectorSRegister d, Register a, Register b); 2102 2103 // AES (introduced with Power 8) 2104 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b); 2105 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b); 2106 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b); 2107 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b); 2108 inline void vsbox( VectorRegister d, VectorRegister a); 2109 2110 // SHA (introduced with Power 8) 2111 // Not yet implemented. 2112 2113 // Vector Binary Polynomial Multiplication (introduced with Power 8) 2114 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b); 2115 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b); 2116 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b); 2117 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b); 2118 2119 // Vector Permute and Xor (introduced with Power 8) 2120 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2121 2122 // Transactional Memory instructions (introduced with Power 8) 2123 inline void tbegin_(); // R=0 2124 inline void tbeginrot_(); // R=1 Rollback-Only Transaction 2125 inline void tend_(); // A=0 2126 inline void tendall_(); // A=1 2127 inline void tabort_(); 2128 inline void tabort_(Register a); 2129 inline void tabortwc_(int t, Register a, Register b); 2130 inline void tabortwci_(int t, Register a, int si); 2131 inline void tabortdc_(int t, Register a, Register b); 2132 inline void tabortdci_(int t, Register a, int si); 2133 inline void tsuspend_(); // tsr with L=0 2134 inline void tresume_(); // tsr with L=1 2135 inline void tcheck(int f); 2136 2137 static bool is_tbegin(int x) { 2138 return TBEGIN_OPCODE == (x & (0x3f << OPCODE_SHIFT | 0x3ff << 1)); 2139 } 2140 2141 // The following encoders use r0 as second operand. These instructions 2142 // read r0 as '0'. 2143 inline void lwzx( Register d, Register s2); 2144 inline void lwz( Register d, int si16); 2145 inline void lwax( Register d, Register s2); 2146 inline void lwa( Register d, int si16); 2147 inline void lwbrx(Register d, Register s2); 2148 inline void lhzx( Register d, Register s2); 2149 inline void lhz( Register d, int si16); 2150 inline void lhax( Register d, Register s2); 2151 inline void lha( Register d, int si16); 2152 inline void lhbrx(Register d, Register s2); 2153 inline void lbzx( Register d, Register s2); 2154 inline void lbz( Register d, int si16); 2155 inline void ldx( Register d, Register s2); 2156 inline void ld( Register d, int si16); 2157 inline void stwx( Register d, Register s2); 2158 inline void stw( Register d, int si16); 2159 inline void sthx( Register d, Register s2); 2160 inline void sth( Register d, int si16); 2161 inline void stbx( Register d, Register s2); 2162 inline void stb( Register d, int si16); 2163 inline void stdx( Register d, Register s2); 2164 inline void std( Register d, int si16); 2165 2166 // PPC 2, section 3.2.1 Instruction Cache Instructions 2167 inline void icbi( Register s2); 2168 // PPC 2, section 3.2.2 Data Cache Instructions 2169 //inlinevoid dcba( Register s2); // Instruction for embedded processor only. 2170 inline void dcbz( Register s2); 2171 inline void dcbst( Register s2); 2172 inline void dcbf( Register s2); 2173 // dcache read hint 2174 inline void dcbt( Register s2); 2175 inline void dcbtct( Register s2, int ct); 2176 inline void dcbtds( Register s2, int ds); 2177 // dcache write hint 2178 inline void dcbtst( Register s2); 2179 inline void dcbtstct(Register s2, int ct); 2180 2181 // Atomics: use ra0mem to disallow R0 as base. 2182 inline void lbarx_unchecked(Register d, Register b, int eh1); 2183 inline void lharx_unchecked(Register d, Register b, int eh1); 2184 inline void lwarx_unchecked(Register d, Register b, int eh1); 2185 inline void ldarx_unchecked(Register d, Register b, int eh1); 2186 inline void lqarx_unchecked(Register d, Register b, int eh1); 2187 inline void lbarx( Register d, Register b, bool hint_exclusive_access); 2188 inline void lharx( Register d, Register b, bool hint_exclusive_access); 2189 inline void lwarx( Register d, Register b, bool hint_exclusive_access); 2190 inline void ldarx( Register d, Register b, bool hint_exclusive_access); 2191 inline void lqarx( Register d, Register b, bool hint_exclusive_access); 2192 inline void stbcx_(Register s, Register b); 2193 inline void sthcx_(Register s, Register b); 2194 inline void stwcx_(Register s, Register b); 2195 inline void stdcx_(Register s, Register b); 2196 inline void stqcx_(Register s, Register b); 2197 inline void lfs( FloatRegister d, int si16); 2198 inline void lfsx( FloatRegister d, Register b); 2199 inline void lfd( FloatRegister d, int si16); 2200 inline void lfdx( FloatRegister d, Register b); 2201 inline void stfs( FloatRegister s, int si16); 2202 inline void stfsx( FloatRegister s, Register b); 2203 inline void stfd( FloatRegister s, int si16); 2204 inline void stfdx( FloatRegister s, Register b); 2205 inline void lvebx( VectorRegister d, Register s2); 2206 inline void lvehx( VectorRegister d, Register s2); 2207 inline void lvewx( VectorRegister d, Register s2); 2208 inline void lvx( VectorRegister d, Register s2); 2209 inline void lvxl( VectorRegister d, Register s2); 2210 inline void stvebx(VectorRegister d, Register s2); 2211 inline void stvehx(VectorRegister d, Register s2); 2212 inline void stvewx(VectorRegister d, Register s2); 2213 inline void stvx( VectorRegister d, Register s2); 2214 inline void stvxl( VectorRegister d, Register s2); 2215 inline void lvsl( VectorRegister d, Register s2); 2216 inline void lvsr( VectorRegister d, Register s2); 2217 2218 // RegisterOrConstant versions. 2219 // These emitters choose between the versions using two registers and 2220 // those with register and immediate, depending on the content of roc. 2221 // If the constant is not encodable as immediate, instructions to 2222 // load the constant are emitted beforehand. Store instructions need a 2223 // tmp reg if the constant is not encodable as immediate. 2224 // Size unpredictable. 2225 void ld( Register d, RegisterOrConstant roc, Register s1 = noreg); 2226 void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg); 2227 void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2228 void lha( Register d, RegisterOrConstant roc, Register s1 = noreg); 2229 void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2230 void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2231 void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2232 void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2233 void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2234 void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2235 void add( Register d, RegisterOrConstant roc, Register s1); 2236 void subf(Register d, RegisterOrConstant roc, Register s1); 2237 void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1); 2238 // Load pointer d from s1+roc. 2239 void ld_ptr(Register d, RegisterOrConstant roc, Register s1 = noreg) { ld(d, roc, s1); } 2240 2241 // Emit several instructions to load a 64 bit constant. This issues a fixed 2242 // instruction pattern so that the constant can be patched later on. 2243 enum { 2244 load_const_size = 5 * BytesPerInstWord 2245 }; 2246 void load_const(Register d, long a, Register tmp = noreg); 2247 inline void load_const(Register d, void* a, Register tmp = noreg); 2248 inline void load_const(Register d, Label& L, Register tmp = noreg); 2249 inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg); 2250 inline void load_const32(Register d, int i); // load signed int (patchable) 2251 2252 // Load a 64 bit constant, optimized, not identifyable. 2253 // Tmp can be used to increase ILP. Set return_simm16_rest = true to get a 2254 // 16 bit immediate offset. This is useful if the offset can be encoded in 2255 // a succeeding instruction. 2256 int load_const_optimized(Register d, long a, Register tmp = noreg, bool return_simm16_rest = false); 2257 inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) { 2258 return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest); 2259 } 2260 2261 // If return_simm16_rest, the return value needs to get added afterwards. 2262 int add_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false); 2263 inline int add_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) { 2264 return add_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest); 2265 } 2266 2267 // If return_simm16_rest, the return value needs to get added afterwards. 2268 inline int sub_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false) { 2269 return add_const_optimized(d, s, -x, tmp, return_simm16_rest); 2270 } 2271 inline int sub_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) { 2272 return sub_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest); 2273 } 2274 2275 // Creation 2276 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 2277#ifdef CHECK_DELAY 2278 delay_state = no_delay; 2279#endif 2280 } 2281 2282 // Testing 2283#ifndef PRODUCT 2284 void test_asm(); 2285#endif 2286}; 2287 2288 2289#endif // CPU_PPC_VM_ASSEMBLER_PPC_HPP 2290