vm_version_aarch64.hpp revision 11857:d0fbf661cc16 
1/*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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8 * published by the Free Software Foundation.
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10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
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25
26#ifndef CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP
27#define CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP
28
29#include "runtime/globals_extension.hpp"
30#include "runtime/vm_version.hpp"
31#include "utilities/sizes.hpp"
32
33class VM_Version : public Abstract_VM_Version {
34  friend class JVMCIVMStructs;
35
36protected:
37  static int _cpu;
38  static int _model;
39  static int _model2;
40  static int _variant;
41  static int _revision;
42  static int _stepping;
43
44  struct PsrInfo {
45    uint32_t dczid_el0;
46    uint32_t ctr_el0;
47  };
48  static PsrInfo _psr_info;
49  static void get_processor_features();
50
51public:
52  // Initialization
53  static void initialize();
54
55  // Asserts
56  static void assert_is_initialized() {
57  }
58
59  enum Family {
60    CPU_ARM       = 'A',
61    CPU_BROADCOM  = 'B',
62    CPU_CAVIUM    = 'C',
63    CPU_DEC       = 'D',
64    CPU_INFINEON  = 'I',
65    CPU_MOTOROLA  = 'M',
66    CPU_NVIDIA    = 'N',
67    CPU_AMCC      = 'P',
68    CPU_QUALCOM   = 'Q',
69    CPU_MARVELL   = 'V',
70    CPU_INTEL     = 'i',
71  };
72
73  enum Feature_Flag {
74    CPU_FP           = (1<<0),
75    CPU_ASIMD        = (1<<1),
76    CPU_EVTSTRM      = (1<<2),
77    CPU_AES          = (1<<3),
78    CPU_PMULL        = (1<<4),
79    CPU_SHA1         = (1<<5),
80    CPU_SHA2         = (1<<6),
81    CPU_CRC32        = (1<<7),
82    CPU_LSE          = (1<<8),
83    CPU_STXR_PREFETCH= (1 << 29),
84    CPU_A53MAC       = (1 << 30),
85    CPU_DMB_ATOMICS  = (1 << 31),
86  };
87
88  static int cpu_family()                     { return _cpu; }
89  static int cpu_model()                      { return _model; }
90  static int cpu_model2()                     { return _model2; }
91  static int cpu_variant()                    { return _variant; }
92  static int cpu_revision()                   { return _revision; }
93  static ByteSize dczid_el0_offset() { return byte_offset_of(PsrInfo, dczid_el0); }
94  static ByteSize ctr_el0_offset()   { return byte_offset_of(PsrInfo, ctr_el0); }
95  static bool is_zva_enabled() {
96    // Check the DZP bit (bit 4) of dczid_el0 is zero
97    // and block size (bit 0~3) is not zero.
98    return ((_psr_info.dczid_el0 & 0x10) == 0 &&
99            (_psr_info.dczid_el0 & 0xf) != 0);
100  }
101  static int zva_length() {
102    assert(is_zva_enabled(), "ZVA not available");
103    return 4 << (_psr_info.dczid_el0 & 0xf);
104  }
105  static int icache_line_size() {
106    return (1 << (_psr_info.ctr_el0 & 0x0f)) * 4;
107  }
108  static int dcache_line_size() {
109    return (1 << ((_psr_info.ctr_el0 >> 16) & 0x0f)) * 4;
110  }
111};
112
113#endif // CPU_AARCH64_VM_VM_VERSION_AARCH64_HPP
114