1/* $OpenBSD: if_rsureg.h,v 1.4 2020/11/30 16:09:33 krw Exp $ */ 2 3/*- 4 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19/* Maximum number of pipes is 11. */ 20#define R92S_MAX_EP 11 21 22/* USB Requests. */ 23#define R92S_REQ_REGS 0x05 24 25/* 26 * MAC registers. 27 */ 28#define R92S_SYSCFG 0x0000 29#define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000) 30#define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002) 31#define R92S_PMC_FSM (R92S_SYSCFG + 0x004) 32#define R92S_SYS_CLKR (R92S_SYSCFG + 0x008) 33#define R92S_EE_9346CR (R92S_SYSCFG + 0x00a) 34#define R92S_AFE_MISC (R92S_SYSCFG + 0x010) 35#define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011) 36#define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018) 37#define R92S_RF_CTRL (R92S_SYSCFG + 0x01f) 38#define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020) 39#define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021) 40#define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026) 41#define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028) 42#define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030) 43#define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034) 44#define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8) 45 46#define R92S_CMDCTRL 0x0040 47#define R92S_CR (R92S_CMDCTRL + 0x000) 48#define R92S_TCR (R92S_CMDCTRL + 0x004) 49#define R92S_RCR (R92S_CMDCTRL + 0x008) 50 51#define R92S_MACIDSETTING 0x0050 52#define R92S_MACID (R92S_MACIDSETTING + 0x000) 53 54#define R92S_GP 0x01e0 55#define R92S_GPIO_CTRL (R92S_GP + 0x00c) 56#define R92S_GPIO_IO_SEL (R92S_GP + 0x00e) 57#define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011) 58 59#define R92S_IOCMD_CTRL 0x0370 60#define R92S_IOCMD_DATA 0x0374 61 62#define R92S_USB_HRPWM 0xfe58 63 64/* Bits for R92S_SYS_FUNC_EN. */ 65#define R92S_FEN_CPUEN 0x0400 66 67/* Bits for R92S_PMC_FSM. */ 68#define R92S_PMC_FSM_CUT_M 0x000f8000 69#define R92S_PMC_FSM_CUT_S 15 70 71/* Bits for R92S_SYS_CLKR. */ 72#define R92S_SYS_CLKSEL 0x0001 73#define R92S_SYS_PS_CLKSEL 0x0002 74#define R92S_SYS_CPU_CLKSEL 0x0004 75#define R92S_MAC_CLK_EN 0x0800 76#define R92S_SYS_CLK_EN 0x1000 77#define R92S_SWHW_SEL 0x4000 78#define R92S_FWHW_SEL 0x8000 79 80/* Bits for R92S_EE_9346CR. */ 81#define R92S_9356SEL 0x10 82#define R92S_EEPROM_EN 0x20 83 84/* Bits for R92S_AFE_MISC. */ 85#define R92S_AFE_MISC_BGEN 0x01 86#define R92S_AFE_MISC_MBEN 0x02 87#define R92S_AFE_MISC_I32_EN 0x08 88 89/* Bits for R92S_SPS1_CTRL. */ 90#define R92S_SPS1_LDEN 0x01 91#define R92S_SPS1_SWEN 0x02 92 93/* Bits for R92S_LDOA15_CTRL. */ 94#define R92S_LDA15_EN 0x01 95 96/* Bits for R92S_LDOV12D_CTRL. */ 97#define R92S_LDV12_EN 0x01 98 99/* Bits for R92C_EFUSE_CTRL. */ 100#define R92S_EFUSE_CTRL_DATA_M 0x000000ff 101#define R92S_EFUSE_CTRL_DATA_S 0 102#define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00 103#define R92S_EFUSE_CTRL_ADDR_S 8 104#define R92S_EFUSE_CTRL_VALID 0x80000000 105 106/* Bits for R92S_CR. */ 107#define R92S_CR_TXDMA_EN 0x10 108 109/* Bits for R92S_TCR. */ 110#define R92S_TCR_IMEM_CODE_DONE 0x01 111#define R92S_TCR_IMEM_CHK_RPT 0x02 112#define R92S_TCR_EMEM_CODE_DONE 0x04 113#define R92S_TCR_EMEM_CHK_RPT 0x08 114#define R92S_TCR_DMEM_CODE_DONE 0x10 115#define R92S_TCR_IMEM_RDY 0x20 116#define R92S_TCR_FWRDY 0x80 117 118/* Bits for R92S_GPIO_IO_SEL. */ 119#define R92S_GPIO_WPS 0x10 120 121/* Bits for R92S_MAC_PINMUX_CTRL. */ 122#define R92S_GPIOSEL_GPIO_M 0x03 123#define R92S_GPIOSEL_GPIO_S 0 124#define R92S_GPIOSEL_GPIO_JTAG 0 125#define R92S_GPIOSEL_GPIO_PHYDBG 1 126#define R92S_GPIOSEL_GPIO_BT 2 127#define R92S_GPIOSEL_GPIO_WLANDBG 3 128#define R92S_GPIOMUX_EN 0x08 129 130/* Bits for R92S_IOCMD_CTRL. */ 131#define R92S_IOCMD_CLASS_M 0xff000000 132#define R92S_IOCMD_CLASS_S 24 133#define R92S_IOCMD_CLASS_BB_RF 0xf0 134#define R92S_IOCMD_VALUE_M 0x00ffff00 135#define R92S_IOCMD_VALUE_S 8 136#define R92S_IOCMD_INDEX_M 0x000000ff 137#define R92S_IOCMD_INDEX_S 0 138#define R92S_IOCMD_INDEX_BB_READ 0 139#define R92S_IOCMD_INDEX_BB_WRITE 1 140#define R92S_IOCMD_INDEX_RF_READ 2 141#define R92S_IOCMD_INDEX_RF_WRITE 3 142 143/* Bits for R92S_USB_HRPWM. */ 144#define R92S_USB_HRPWM_PS_ALL_ON 0x04 145#define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08 146 147/* 148 * Macros to access subfields in registers. 149 */ 150/* Mask and Shift (getter). */ 151#define MS(val, field) \ 152 (((val) & field##_M) >> field##_S) 153 154/* Shift and Mask (setter). */ 155#define SM(field, val) \ 156 (((val) << field##_S) & field##_M) 157 158/* Rewrite. */ 159#define RW(var, field, val) \ 160 (((var) & ~field##_M) | SM(field, val)) 161 162/* 163 * Firmware image header. 164 */ 165struct r92s_fw_priv { 166 /* QWORD0 */ 167 uint16_t signature; 168 uint8_t hci_sel; 169#define R92S_HCI_SEL_PCIE 0x01 170#define R92S_HCI_SEL_USB 0x02 171#define R92S_HCI_SEL_SDIO 0x04 172#define R92S_HCI_SEL_8172 0x10 173#define R92S_HCI_SEL_AP 0x80 174 175 uint8_t chip_version; 176 uint16_t custid; 177 uint8_t rf_config; 178 uint8_t nendpoints; 179 /* QWORD1 */ 180 uint32_t regulatory; 181 uint8_t rfintfs; 182 uint8_t def_nettype; 183 uint8_t turbo_mode; 184 uint8_t lowpower_mode; 185 /* QWORD2 */ 186 uint8_t lbk_mode; 187 uint8_t mp_mode; 188 uint8_t vcs_type; 189#define R92S_VCS_TYPE_DISABLE 0 190#define R92S_VCS_TYPE_ENABLE 1 191#define R92S_VCS_TYPE_AUTO 2 192 193 uint8_t vcs_mode; 194#define R92S_VCS_MODE_NONE 0 195#define R92S_VCS_MODE_RTS_CTS 1 196#define R92S_VCS_MODE_CTS2SELF 2 197 198 uint32_t reserved1; 199 /* QWORD3 */ 200 uint8_t qos_en; 201 uint8_t bw40_en; 202 uint8_t amsdu2ampdu_en; 203 uint8_t ampdu_en; 204 uint8_t rc_offload; 205 uint8_t agg_offload; 206 uint16_t reserved2; 207 /* QWORD4 */ 208 uint8_t beacon_offload; 209 uint8_t mlme_offload; 210 uint8_t hwpc_offload; 211 uint8_t tcpcsum_offload; 212 uint8_t tcp_offload; 213 uint8_t ps_offload; 214 uint8_t wwlan_offload; 215 uint8_t reserved3; 216 /* QWORD5 */ 217 uint16_t tcp_tx_len; 218 uint16_t tcp_rx_len; 219 uint32_t reserved4; 220} __packed; 221 222struct r92s_fw_hdr { 223 uint16_t signature; 224 uint16_t version; 225 uint32_t dmemsz; 226 uint32_t imemsz; 227 uint32_t sramsz; 228 uint32_t privsz; 229 uint16_t efuse_addr; 230 uint16_t h2c_resp_addr; 231 uint32_t svnrev; 232 uint8_t month; 233 uint8_t day; 234 uint8_t hour; 235 uint8_t minute; 236 struct r92s_fw_priv priv; 237} __packed; 238 239/* Structure for FW commands and FW events notifications. */ 240struct r92s_fw_cmd_hdr { 241 uint16_t len; 242 uint8_t code; 243 uint8_t seq; 244#define R92S_FW_CMD_MORE 0x80 245 246 uint32_t reserved; 247} __packed; 248 249/* FW commands codes. */ 250#define R92S_CMD_READ_MACREG 0 251#define R92S_CMD_WRITE_MACREG 1 252#define R92S_CMD_READ_BBREG 2 253#define R92S_CMD_WRITE_BBREG 3 254#define R92S_CMD_READ_RFREG 4 255#define R92S_CMD_WRITE_RFREG 5 256#define R92S_CMD_READ_EEPROM 6 257#define R92S_CMD_WRITE_EEPROM 7 258#define R92S_CMD_READ_EFUSE 8 259#define R92S_CMD_WRITE_EFUSE 9 260#define R92S_CMD_READ_CAM 10 261#define R92S_CMD_WRITE_CAM 11 262#define R92S_CMD_SET_BCNITV 12 263#define R92S_CMD_SET_MBIDCFG 13 264#define R92S_CMD_JOIN_BSS 14 265#define R92S_CMD_DISCONNECT 15 266#define R92S_CMD_CREATE_BSS 16 267#define R92S_CMD_SET_OPMODE 17 268#define R92S_CMD_SITE_SURVEY 18 269#define R92S_CMD_SET_AUTH 19 270#define R92S_CMD_SET_KEY 20 271#define R92S_CMD_SET_STA_KEY 21 272#define R92S_CMD_SET_ASSOC_STA 22 273#define R92S_CMD_DEL_ASSOC_STA 23 274#define R92S_CMD_SET_STAPWRSTATE 24 275#define R92S_CMD_SET_BASIC_RATE 25 276#define R92S_CMD_GET_BASIC_RATE 26 277#define R92S_CMD_SET_DATA_RATE 27 278#define R92S_CMD_GET_DATA_RATE 28 279#define R92S_CMD_SET_PHY_INFO 29 280#define R92S_CMD_GET_PHY_INFO 30 281#define R92S_CMD_SET_PHY 31 282#define R92S_CMD_GET_PHY 32 283#define R92S_CMD_READ_RSSI 33 284#define R92S_CMD_READ_GAIN 34 285#define R92S_CMD_SET_ATIM 35 286#define R92S_CMD_SET_PWR_MODE 36 287#define R92S_CMD_JOIN_BSS_RPT 37 288#define R92S_CMD_SET_RA_TABLE 38 289#define R92S_CMD_GET_RA_TABLE 39 290#define R92S_CMD_GET_CCX_REPORT 40 291#define R92S_CMD_GET_DTM_REPORT 41 292#define R92S_CMD_GET_TXRATE_STATS 42 293#define R92S_CMD_SET_USB_SUSPEND 43 294#define R92S_CMD_SET_H2C_LBK 44 295#define R92S_CMD_ADDBA_REQ 45 296#define R92S_CMD_SET_CHANNEL 46 297#define R92S_CMD_SET_TXPOWER 47 298#define R92S_CMD_SWITCH_ANTENNA 48 299#define R92S_CMD_SET_CRYSTAL_CAL 49 300#define R92S_CMD_SET_SINGLE_CARRIER_TX 50 301#define R92S_CMD_SET_SINGLE_TONE_TX 51 302#define R92S_CMD_SET_CARRIER_SUPPR_TX 52 303#define R92S_CMD_SET_CONTINUOUS_TX 53 304#define R92S_CMD_SWITCH_BANDWIDTH 54 305#define R92S_CMD_TX_BEACON 55 306#define R92S_CMD_SET_POWER_TRACKING 56 307#define R92S_CMD_AMSDU_TO_AMPDU 57 308#define R92S_CMD_SET_MAC_ADDRESS 58 309#define R92S_CMD_GET_H2C_LBK 59 310#define R92S_CMD_SET_PBREQ_IE 60 311#define R92S_CMD_SET_ASSOCREQ_IE 61 312#define R92S_CMD_SET_PBRESP_IE 62 313#define R92S_CMD_SET_ASSOCRESP_IE 63 314#define R92S_CMD_GET_CURDATARATE 64 315#define R92S_CMD_GET_TXRETRY_CNT 65 316#define R92S_CMD_GET_RXRETRY_CNT 66 317#define R92S_CMD_GET_BCNOK_CNT 67 318#define R92S_CMD_GET_BCNERR_CNT 68 319#define R92S_CMD_GET_CURTXPWR_LEVEL 69 320#define R92S_CMD_SET_DIG 70 321#define R92S_CMD_SET_RA 71 322#define R92S_CMD_SET_PT 72 323#define R92S_CMD_READ_TSSI 73 324 325/* FW events notifications codes. */ 326#define R92S_EVT_READ_MACREG 0 327#define R92S_EVT_READ_BBREG 1 328#define R92S_EVT_READ_RFREG 2 329#define R92S_EVT_READ_EEPROM 3 330#define R92S_EVT_READ_EFUSE 4 331#define R92S_EVT_READ_CAM 5 332#define R92S_EVT_GET_BASICRATE 6 333#define R92S_EVT_GET_DATARATE 7 334#define R92S_EVT_SURVEY 8 335#define R92S_EVT_SURVEY_DONE 9 336#define R92S_EVT_JOIN_BSS 10 337#define R92S_EVT_ADD_STA 11 338#define R92S_EVT_DEL_STA 12 339#define R92S_EVT_ATIM_DONE 13 340#define R92S_EVT_TX_REPORT 14 341#define R92S_EVT_CCX_REPORT 15 342#define R92S_EVT_DTM_REPORT 16 343#define R92S_EVT_TXRATE_STATS 17 344#define R92S_EVT_C2H_LBK 18 345#define R92S_EVT_FWDBG 19 346#define R92S_EVT_C2H_FEEDBACK 20 347#define R92S_EVT_ADDBA 21 348#define R92S_EVT_C2H_BCN 22 349#define R92S_EVT_PWR_STATE 23 350#define R92S_EVT_WPS_PBC 24 351#define R92S_EVT_ADDBA_REQ_REPORT 25 352 353/* Structure for R92S_CMD_SITE_SURVEY. */ 354struct r92s_fw_cmd_sitesurvey { 355 uint32_t active; 356 uint32_t limit; 357 uint32_t ssidlen; 358 uint8_t ssid[32 + 1]; 359} __packed; 360 361/* Structure for R92S_CMD_SET_AUTH. */ 362struct r92s_fw_cmd_auth { 363 uint8_t mode; 364#define R92S_AUTHMODE_OPEN 0 365#define R92S_AUTHMODE_SHARED 1 366#define R92S_AUTHMODE_WPA 2 367 368 uint8_t dot1x; 369} __packed; 370 371/* Structure for R92S_CMD_SET_KEY. */ 372struct r92s_fw_cmd_set_key { 373 uint8_t algo; 374#define R92S_KEY_ALGO_NONE 0 375#define R92S_KEY_ALGO_WEP40 1 376#define R92S_KEY_ALGO_TKIP 2 377#define R92S_KEY_ALGO_TKIP_MMIC 3 378#define R92S_KEY_ALGO_AES 4 379#define R92S_KEY_ALGO_WEP104 5 380 381 uint8_t id; 382 uint8_t grpkey; 383 uint8_t key[16]; 384} __packed; 385 386/* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */ 387/* NDIS_802_11_SSID. */ 388struct ndis_802_11_ssid { 389 uint32_t ssidlen; 390 uint8_t ssid[32]; 391} __packed; 392 393/* NDIS_802_11_CONFIGURATION_FH. */ 394struct ndis_802_11_configuration_fh { 395 uint32_t len; 396 uint32_t hoppattern; 397 uint32_t hopset; 398 uint32_t dwelltime; 399} __packed; 400 401/* NDIS_802_11_CONFIGURATION. */ 402struct ndis_802_11_configuration { 403 uint32_t len; 404 uint32_t bintval; 405 uint32_t atim; 406 uint32_t dsconfig; 407 struct ndis_802_11_configuration_fh fhconfig; 408} __packed; 409 410/* NDIS_WLAN_BSSID_EX. */ 411struct ndis_wlan_bssid_ex { 412 uint32_t len; 413 uint8_t macaddr[IEEE80211_ADDR_LEN]; 414 uint8_t reserved[2]; 415 struct ndis_802_11_ssid ssid; 416 uint32_t privacy; 417 int32_t rssi; 418 uint32_t networktype; 419#define NDIS802_11FH 0 420#define NDIS802_11DS 1 421#define NDIS802_11OFDM5 2 422#define NDIS802_11OFDM24 3 423#define NDIS802_11AUTOMODE 4 424 425 struct ndis_802_11_configuration config; 426 uint32_t inframode; 427#define NDIS802_11IBSS 0 428#define NDIS802_11INFRASTRUCTURE 1 429#define NDIS802_11AUTOUNKNOWN 2 430#define NDIS802_11MONITOR 3 431#define NDIS802_11APMODE 4 432 433 uint8_t supprates[16]; 434 uint32_t ieslen; 435 /* Followed by ``ieslen'' bytes. */ 436} __packed; 437 438/* NDIS_802_11_FIXED_IEs. */ 439struct ndis_802_11_fixed_ies { 440 uint8_t tstamp[8]; 441 uint16_t bintval; 442 uint16_t capabilities; 443} __packed; 444 445/* Structure for R92S_CMD_SET_PWR_MODE. */ 446struct r92s_set_pwr_mode { 447 uint8_t mode; 448#define R92S_PS_MODE_ACTIVE 0 449#define R92S_PS_MODE_MIN 1 450#define R92S_PS_MODE_MAX 2 451#define R92S_PS_MODE_DTIM 3 452#define R92S_PS_MODE_VOIP 4 453#define R92S_PS_MODE_UAPSD_WMM 5 454#define R92S_PS_MODE_UAPSD 6 455#define R92S_PS_MODE_IBSS 7 456#define R92S_PS_MODE_WWLAN 8 457#define R92S_PS_MODE_RADIOOFF 9 458#define R92S_PS_MODE_DISABLE 10 459 460 uint8_t low_traffic_en; 461 uint8_t lpnav_en; 462 uint8_t rf_low_snr_en; 463 uint8_t dps_en; 464 uint8_t bcn_rx_en; 465 uint8_t bcn_pass_cnt; 466 uint8_t bcn_to; 467 uint16_t bcn_itv; 468 uint8_t app_itv; 469 uint8_t awake_bcn_itv; 470 uint8_t smart_ps; 471 uint8_t bcn_pass_time; 472} __packed; 473 474/* Structure for event R92S_EVENT_JOIN_BSS. */ 475struct r92s_event_join_bss { 476 uint32_t next; 477 uint32_t prev; 478 uint32_t networktype; 479 uint32_t fixed; 480 uint32_t lastscanned; 481 uint32_t associd; 482 uint32_t join_res; 483 struct ndis_wlan_bssid_ex bss; 484} __packed; 485 486#define R92S_MACID_BSS 5 487 488/* Rx MAC descriptor. */ 489struct r92s_rx_stat { 490 uint32_t rxdw0; 491#define R92S_RXDW0_PKTLEN_M 0x00003fff 492#define R92S_RXDW0_PKTLEN_S 0 493#define R92S_RXDW0_CRCERR 0x00004000 494#define R92S_RXDW0_INFOSZ_M 0x000f0000 495#define R92S_RXDW0_INFOSZ_S 16 496#define R92S_RXDW0_QOS 0x00800000 497#define R92S_RXDW0_SHIFT_M 0x03000000 498#define R92S_RXDW0_SHIFT_S 24 499#define R92S_RXDW0_DECRYPTED 0x08000000 500 501 uint32_t rxdw1; 502#define R92S_RXDW1_MOREFRAG 0x08000000 503 504 uint32_t rxdw2; 505#define R92S_RXDW2_FRAG_M 0x0000f000 506#define R92S_RXDW2_FRAG_S 12 507#define R92S_RXDW2_PKTCNT_M 0x00ff0000 508#define R92S_RXDW2_PKTCNT_S 16 509 510 uint32_t rxdw3; 511#define R92S_RXDW3_RATE_M 0x0000003f 512#define R92S_RXDW3_RATE_S 0 513#define R92S_RXDW3_TCPCHKRPT 0x00000800 514#define R92S_RXDW3_IPCHKRPT 0x00001000 515#define R92S_RXDW3_TCPCHKVALID 0x00002000 516#define R92S_RXDW3_HTC 0x00004000 517 518 uint32_t rxdw4; 519 uint32_t rxdw5; 520} __packed __attribute__((aligned(4))); 521 522/* Rx PHY descriptor. */ 523struct r92s_rx_phystat { 524 uint32_t phydw0; 525 uint32_t phydw1; 526 uint32_t phydw2; 527 uint32_t phydw3; 528 uint32_t phydw4; 529 uint32_t phydw5; 530 uint32_t phydw6; 531 uint32_t phydw7; 532} __packed __attribute__((aligned(4))); 533 534/* Rx PHY CCK descriptor. */ 535struct r92s_rx_cck { 536 uint8_t adc_pwdb[4]; 537 uint8_t sq_rpt; 538 uint8_t agc_rpt; 539} __packed; 540 541/* Tx MAC descriptor. */ 542struct r92s_tx_desc { 543 uint32_t txdw0; 544#define R92S_TXDW0_PKTLEN_M 0x0000ffff 545#define R92S_TXDW0_PKTLEN_S 0 546#define R92S_TXDW0_OFFSET_M 0x00ff0000 547#define R92S_TXDW0_OFFSET_S 16 548#define R92S_TXDW0_TYPE_M 0x03000000 549#define R92S_TXDW0_TYPE_S 24 550#define R92S_TXDW0_LSG 0x04000000 551#define R92S_TXDW0_FSG 0x08000000 552#define R92S_TXDW0_LINIP 0x10000000 553#define R92S_TXDW0_OWN 0x80000000 554 555 uint32_t txdw1; 556#define R92S_TXDW1_MACID_M 0x0000001f 557#define R92S_TXDW1_MACID_S 0 558#define R92S_TXDW1_MOREDATA 0x00000020 559#define R92S_TXDW1_MOREFRAG 0x00000040 560#define R92S_TXDW1_QSEL_M 0x00001f00 561#define R92S_TXDW1_QSEL_S 8 562#define R92S_TXDW1_QSEL_BE 0x03 563#define R92S_TXDW1_QSEL_H2C 0x1f 564#define R92S_TXDW1_NONQOS 0x00010000 565#define R92S_TXDW1_KEYIDX_M 0x00060000 566#define R92S_TXDW1_KEYIDX_S 17 567#define R92S_TXDW1_CIPHER_M 0x00c00000 568#define R92S_TXDW1_CIPHER_S 22 569#define R92S_TXDW1_CIPHER_WEP 1 570#define R92S_TXDW1_CIPHER_TKIP 2 571#define R92S_TXDW1_CIPHER_AES 3 572#define R92S_TXDW1_HWPC 0x80000000 573 574 uint32_t txdw2; 575#define R92S_TXDW2_BMCAST 0x00000080 576#define R92S_TXDW2_AGGEN 0x20000000 577#define R92S_TXDW2_BK 0x40000000 578 579 uint32_t txdw3; 580#define R92S_TXDW3_SEQ_M 0x0fff0000 581#define R92S_TXDW3_SEQ_S 16 582#define R92S_TXDW3_FRAG_M 0xf0000000 583#define R92S_TXDW3_FRAG_S 28 584 585 uint32_t txdw4; 586#define R92S_TXDW4_TXBW 0x00040000 587 588 uint32_t txdw5; 589#define R92S_TXDW5_DISFB 0x00008000 590 591 uint16_t ipchksum; 592 uint16_t tcpchksum; 593 594 uint16_t txbufsize; 595 uint16_t reserved1; 596} __packed __attribute__((aligned(4))); 597 598 599/* 600 * Driver definitions. 601 */ 602#define RSU_RX_LIST_COUNT 1 603#define RSU_TX_LIST_COUNT (8 + 1) /* NB: +1 for FW commands. */ 604 605#define RSU_HOST_CMD_RING_COUNT 32 606 607#define RSU_RXBUFSZ (8 * 1024) 608#define RSU_TXBUFSZ \ 609 ((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3) 610 611#define RSU_TX_TIMEOUT 5000 /* ms */ 612#define RSU_CMD_TIMEOUT 2000 /* ms */ 613 614/* Queue ids (used by soft only). */ 615#define RSU_QID_BCN 0 616#define RSU_QID_MGT 1 617#define RSU_QID_BMC 2 618#define RSU_QID_VO 3 619#define RSU_QID_VI 4 620#define RSU_QID_BE 5 621#define RSU_QID_BK 6 622#define RSU_QID_RXOFF 7 623#define RSU_QID_H2C 8 624#define RSU_QID_C2H 9 625 626/* Map AC to queue id. */ 627static const uint8_t rsu_ac2qid[EDCA_NUM_AC] = { 628 RSU_QID_BE, 629 RSU_QID_BK, 630 RSU_QID_VI, 631 RSU_QID_VO 632}; 633 634/* Pipe index to endpoint address mapping. */ 635static const uint8_t r92s_epaddr[] = 636 { 0x83, 0x04, 0x06, 0x0d, 637 0x05, 0x07, 638 0x89, 0x0a, 0x0b, 0x0c }; 639 640/* Queue id to pipe index mapping for 4 endpoints configurations. */ 641static const uint8_t rsu_qid2idx_4ep[] = 642 { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 }; 643 644/* Queue id to pipe index mapping for 6 endpoints configurations. */ 645static const uint8_t rsu_qid2idx_6ep[] = 646 { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 }; 647 648/* Queue id to pipe index mapping for 11 endpoints configurations. */ 649static const uint8_t rsu_qid2idx_11ep[] = 650 { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 }; 651 652struct rsu_rx_radiotap_header { 653 struct ieee80211_radiotap_header wr_ihdr; 654 uint8_t wr_flags; 655 uint8_t wr_rate; 656 uint16_t wr_chan_freq; 657 uint16_t wr_chan_flags; 658 uint8_t wr_dbm_antsignal; 659} __packed; 660 661#define RSU_RX_RADIOTAP_PRESENT \ 662 (1 << IEEE80211_RADIOTAP_FLAGS | \ 663 1 << IEEE80211_RADIOTAP_RATE | \ 664 1 << IEEE80211_RADIOTAP_CHANNEL | \ 665 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 666 667struct rsu_tx_radiotap_header { 668 struct ieee80211_radiotap_header wt_ihdr; 669 uint8_t wt_flags; 670 uint16_t wt_chan_freq; 671 uint16_t wt_chan_flags; 672} __packed; 673 674#define RSU_TX_RADIOTAP_PRESENT \ 675 (1 << IEEE80211_RADIOTAP_FLAGS | \ 676 1 << IEEE80211_RADIOTAP_CHANNEL) 677 678struct rsu_softc; 679 680struct rsu_rx_data { 681 struct rsu_softc *sc; 682 struct usbd_pipe *pipe; 683 struct usbd_xfer *xfer; 684 uint8_t *buf; 685}; 686 687struct rsu_tx_data { 688 struct rsu_softc *sc; 689 struct usbd_pipe *pipe; 690 struct usbd_xfer *xfer; 691 uint8_t *buf; 692 TAILQ_ENTRY(rsu_tx_data) next; 693}; 694 695struct rsu_host_cmd { 696 void (*cb)(struct rsu_softc *, void *); 697 uint8_t data[256]; 698}; 699 700struct rsu_cmd_newstate { 701 enum ieee80211_state state; 702 int arg; 703}; 704 705struct rsu_cmd_key { 706 struct ieee80211_key key; 707 struct ieee80211_node *ni; 708}; 709 710struct rsu_host_cmd_ring { 711 struct rsu_host_cmd cmd[RSU_HOST_CMD_RING_COUNT]; 712 int cur; 713 int next; 714 int queued; 715}; 716 717struct rsu_softc { 718 struct device sc_dev; 719 struct ieee80211com sc_ic; 720 int (*sc_newstate)(struct ieee80211com *, 721 enum ieee80211_state, int); 722 struct usbd_device *sc_udev; 723 struct usbd_interface *sc_iface; 724 struct usb_task sc_task; 725 struct timeout calib_to; 726 struct usbd_pipe *pipe[R92S_MAX_EP]; 727 int npipes; 728 const uint8_t *qid2idx; 729 730 u_int cut; 731 int scan_pass; 732 int sc_tx_timer; 733 struct rsu_host_cmd_ring cmdq; 734 struct rsu_rx_data rx_data[RSU_RX_LIST_COUNT]; 735 struct rsu_tx_data tx_data[RSU_TX_LIST_COUNT]; 736 struct rsu_tx_data *fwcmd_data; 737 uint8_t cmd_seq; 738 TAILQ_HEAD(, rsu_tx_data) tx_free_list; 739 uint8_t rom[128]; 740 741#if NBPFILTER > 0 742 caddr_t sc_drvbpf; 743 744 union { 745 struct rsu_rx_radiotap_header th; 746 uint8_t pad[64]; 747 } sc_rxtapu; 748#define sc_rxtap sc_rxtapu.th 749 int sc_rxtap_len; 750 751 union { 752 struct rsu_tx_radiotap_header th; 753 uint8_t pad[64]; 754 } sc_txtapu; 755#define sc_txtap sc_txtapu.th 756 int sc_txtap_len; 757#endif 758 int sc_key_tasks; 759}; 760