1/* $OpenBSD: dwc2_hw.h,v 1.5 2023/08/15 08:27:30 miod Exp $ */ 2/* $NetBSD: dwc2_hw.h,v 1.2 2013/09/25 06:19:22 skrll Exp $ */ 3 4/* 5 * hw.h - DesignWare HS OTG Controller hardware definitions 6 * 7 * Copyright 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40#ifndef __DWC2_HW_H__ 41#define __DWC2_HW_H__ 42 43#define HSOTG_REG(x) (x) 44 45#define GOTGCTL HSOTG_REG(0x000) 46#define GOTGCTL_CHIRPEN (1 << 27) 47#define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22) 48#define GOTGCTL_MULT_VALID_BC_SHIFT 22 49#define GOTGCTL_CURMODE_HOST (1 << 21) 50#define GOTGCTL_OTGVER (1 << 20) 51#define GOTGCTL_BSESVLD (1 << 19) 52#define GOTGCTL_ASESVLD (1 << 18) 53#define GOTGCTL_DBNC_SHORT (1 << 17) 54#define GOTGCTL_CONID_B (1 << 16) 55#define GOTGCTL_DBNCE_FLTR_BYPASS (1 << 15) 56#define GOTGCTL_DEVHNPEN (1 << 11) 57#define GOTGCTL_HSTSETHNPEN (1 << 10) 58#define GOTGCTL_HNPREQ (1 << 9) 59#define GOTGCTL_HSTNEGSCS (1 << 8) 60#define GOTGCTL_BVALOVAL (1 << 7) 61#define GOTGCTL_BVALOEN (1 << 6) 62#define GOTGCTL_AVALOVAL (1 << 5) 63#define GOTGCTL_AVALOEN (1 << 4) 64#define GOTGCTL_VBVALOVAL (1 << 3) 65#define GOTGCTL_VBVALOEN (1 << 2) 66#define GOTGCTL_SESREQ (1 << 1) 67#define GOTGCTL_SESREQSCS (1 << 0) 68 69#define GOTGINT HSOTG_REG(0x004) 70#define GOTGINT_DBNCE_DONE (1 << 19) 71#define GOTGINT_A_DEV_TOUT_CHG (1 << 18) 72#define GOTGINT_HST_NEG_DET (1 << 17) 73#define GOTGINT_HST_NEG_SUC_STS_CHNG (1 << 9) 74#define GOTGINT_SES_REQ_SUC_STS_CHNG (1 << 8) 75#define GOTGINT_SES_END_DET (1 << 2) 76 77#define GAHBCFG HSOTG_REG(0x008) 78#define GAHBCFG_AHB_SINGLE (1 << 23) 79#define GAHBCFG_NOTI_ALL_DMA_WRIT (1 << 22) 80#define GAHBCFG_REM_MEM_SUPP (1 << 21) 81#define GAHBCFG_P_TXF_EMP_LVL (1 << 8) 82#define GAHBCFG_NP_TXF_EMP_LVL (1 << 7) 83#define GAHBCFG_DMA_EN (1 << 5) 84#define GAHBCFG_HBSTLEN_MASK (0xf << 1) 85#define GAHBCFG_HBSTLEN_SHIFT 1 86#define GAHBCFG_HBSTLEN_SINGLE 0 87#define GAHBCFG_HBSTLEN_INCR 1 88#define GAHBCFG_HBSTLEN_INCR4 3 89#define GAHBCFG_HBSTLEN_INCR8 5 90#define GAHBCFG_HBSTLEN_INCR16 7 91#define GAHBCFG_GLBL_INTR_EN (1 << 0) 92#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \ 93 GAHBCFG_NP_TXF_EMP_LVL | \ 94 GAHBCFG_DMA_EN | \ 95 GAHBCFG_GLBL_INTR_EN) 96 97#define GUSBCFG HSOTG_REG(0x00C) 98#define GUSBCFG_FORCEDEVMODE (1 << 30) 99#define GUSBCFG_FORCEHOSTMODE (1 << 29) 100#define GUSBCFG_TXENDDELAY (1 << 28) 101#define GUSBCFG_ICTRAFFICPULLREMOVE (1 << 27) 102#define GUSBCFG_ICUSBCAP (1 << 26) 103#define GUSBCFG_ULPI_INT_PROT_DIS (1 << 25) 104#define GUSBCFG_INDICATORPASSTHROUGH (1 << 24) 105#define GUSBCFG_INDICATORCOMPLEMENT (1 << 23) 106#define GUSBCFG_TERMSELDLPULSE (1 << 22) 107#define GUSBCFG_ULPI_INT_VBUS_IND (1 << 21) 108#define GUSBCFG_ULPI_EXT_VBUS_DRV (1 << 20) 109#define GUSBCFG_ULPI_CLK_SUSP_M (1 << 19) 110#define GUSBCFG_ULPI_AUTO_RES (1 << 18) 111#define GUSBCFG_ULPI_FS_LS (1 << 17) 112#define GUSBCFG_OTG_UTMI_FS_SEL (1 << 16) 113#define GUSBCFG_PHY_LP_CLK_SEL (1 << 15) 114#define GUSBCFG_USBTRDTIM_MASK (0xf << 10) 115#define GUSBCFG_USBTRDTIM_SHIFT 10 116#define GUSBCFG_HNPCAP (1 << 9) 117#define GUSBCFG_SRPCAP (1 << 8) 118#define GUSBCFG_DDRSEL (1 << 7) 119#define GUSBCFG_PHYSEL (1 << 6) 120#define GUSBCFG_FSINTF (1 << 5) 121#define GUSBCFG_ULPI_UTMI_SEL (1 << 4) 122#define GUSBCFG_PHYIF16 (1 << 3) 123#define GUSBCFG_PHYIF8 (0 << 3) 124#define GUSBCFG_TOUTCAL_MASK (0x7 << 0) 125#define GUSBCFG_TOUTCAL_SHIFT 0 126#define GUSBCFG_TOUTCAL_LIMIT 0x7 127#define GUSBCFG_TOUTCAL(_x) ((_x) << 0) 128 129#define GRSTCTL HSOTG_REG(0x010) 130#define GRSTCTL_AHBIDLE (1U << 31) 131#define GRSTCTL_DMAREQ (1 << 30) 132#define GRSTCTL_CSFTRST_DONE (1 << 29) 133#define GRSTCTL_TXFNUM_MASK (0x1f << 6) 134#define GRSTCTL_TXFNUM_SHIFT 6 135#define GRSTCTL_TXFNUM_LIMIT 0x1f 136#define GRSTCTL_TXFNUM(_x) ((_x) << 6) 137#define GRSTCTL_TXFFLSH (1 << 5) 138#define GRSTCTL_RXFFLSH (1 << 4) 139#define GRSTCTL_IN_TKNQ_FLSH (1 << 3) 140#define GRSTCTL_FRMCNTRRST (1 << 2) 141#define GRSTCTL_HSFTRST (1 << 1) 142#define GRSTCTL_CSFTRST (1 << 0) 143 144#define GINTSTS HSOTG_REG(0x014) 145#define GINTMSK HSOTG_REG(0x018) 146#define GINTSTS_WKUPINT (1U << 31) 147#define GINTSTS_SESSREQINT (1 << 30) 148#define GINTSTS_DISCONNINT (1 << 29) 149#define GINTSTS_CONIDSTSCHNG (1 << 28) 150#define GINTSTS_LPMTRANRCVD (1 << 27) 151#define GINTSTS_PTXFEMP (1 << 26) 152#define GINTSTS_HCHINT (1 << 25) 153#define GINTSTS_PRTINT (1 << 24) 154#define GINTSTS_RESETDET (1 << 23) 155#define GINTSTS_FET_SUSP (1 << 22) 156#define GINTSTS_INCOMPL_IP (1 << 21) 157#define GINTSTS_INCOMPL_SOOUT (1 << 21) 158#define GINTSTS_INCOMPL_SOIN (1 << 20) 159#define GINTSTS_OEPINT (1 << 19) 160#define GINTSTS_IEPINT (1 << 18) 161#define GINTSTS_EPMIS (1 << 17) 162#define GINTSTS_RESTOREDONE (1 << 16) 163#define GINTSTS_EOPF (1 << 15) 164#define GINTSTS_ISOUTDROP (1 << 14) 165#define GINTSTS_ENUMDONE (1 << 13) 166#define GINTSTS_USBRST (1 << 12) 167#define GINTSTS_USBSUSP (1 << 11) 168#define GINTSTS_ERLYSUSP (1 << 10) 169#define GINTSTS_I2CINT (1 << 9) 170#define GINTSTS_ULPI_CK_INT (1 << 8) 171#define GINTSTS_GOUTNAKEFF (1 << 7) 172#define GINTSTS_GINNAKEFF (1 << 6) 173#define GINTSTS_NPTXFEMP (1 << 5) 174#define GINTSTS_RXFLVL (1 << 4) 175#define GINTSTS_SOF (1 << 3) 176#define GINTSTS_OTGINT (1 << 2) 177#define GINTSTS_MODEMIS (1 << 1) 178#define GINTSTS_CURMODE_HOST (1 << 0) 179 180#define GRXSTSR HSOTG_REG(0x01C) 181#define GRXSTSP HSOTG_REG(0x020) 182#define GRXSTS_FN_MASK (0x7f << 25) 183#define GRXSTS_FN_SHIFT 25 184#define GRXSTS_PKTSTS_MASK (0xf << 17) 185#define GRXSTS_PKTSTS_SHIFT 17 186#define GRXSTS_PKTSTS_GLOBALOUTNAK 1 187#define GRXSTS_PKTSTS_OUTRX 2 188#define GRXSTS_PKTSTS_HCHIN 2 189#define GRXSTS_PKTSTS_OUTDONE 3 190#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3 191#define GRXSTS_PKTSTS_SETUPDONE 4 192#define GRXSTS_PKTSTS_DATATOGGLEERR 5 193#define GRXSTS_PKTSTS_SETUPRX 6 194#define GRXSTS_PKTSTS_HCHHALTED 7 195#define GRXSTS_HCHNUM_MASK (0xf << 0) 196#define GRXSTS_HCHNUM_SHIFT 0 197#define GRXSTS_DPID_MASK (0x3 << 15) 198#define GRXSTS_DPID_SHIFT 15 199#define GRXSTS_BYTECNT_MASK (0x7ff << 4) 200#define GRXSTS_BYTECNT_SHIFT 4 201#define GRXSTS_EPNUM_MASK (0xf << 0) 202#define GRXSTS_EPNUM_SHIFT 0 203 204#define GRXFSIZ HSOTG_REG(0x024) 205#define GRXFSIZ_DEPTH_MASK (0xffff << 0) 206#define GRXFSIZ_DEPTH_SHIFT 0 207 208#define GNPTXFSIZ HSOTG_REG(0x028) 209/* Use FIFOSIZE_* constants to access this register */ 210 211#define GNPTXSTS HSOTG_REG(0x02C) 212#define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24) 213#define GNPTXSTS_NP_TXQ_TOP_SHIFT 24 214#define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16) 215#define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16 216#define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff) 217#define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0) 218#define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0 219#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff) 220 221#define GI2CCTL HSOTG_REG(0x0030) 222#define GI2CCTL_BSYDNE (1U << 31) 223#define GI2CCTL_RW (1 << 30) 224#define GI2CCTL_I2CDATSE0 (1 << 28) 225#define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26) 226#define GI2CCTL_I2CDEVADDR_SHIFT 26 227#define GI2CCTL_I2CSUSPCTL (1 << 25) 228#define GI2CCTL_ACK (1 << 24) 229#define GI2CCTL_I2CEN (1 << 23) 230#define GI2CCTL_ADDR_MASK (0x7f << 16) 231#define GI2CCTL_ADDR_SHIFT 16 232#define GI2CCTL_REGADDR_MASK (0xff << 8) 233#define GI2CCTL_REGADDR_SHIFT 8 234#define GI2CCTL_RWDATA_MASK (0xff << 0) 235#define GI2CCTL_RWDATA_SHIFT 0 236 237#define GPVNDCTL HSOTG_REG(0x0034) 238#define GGPIO HSOTG_REG(0x0038) 239#define GGPIO_STM32_OTG_GCCFG_PWRDWN (1 << 16) 240#define GGPIO_STM32_OTG_GCCFG_VBDEN (1 << 21) 241#define GGPIO_STM32_OTG_GCCFG_IDEN (1 << 22) 242 243#define GUID HSOTG_REG(0x003c) 244#define GSNPSID HSOTG_REG(0x0040) 245#define GHWCFG1 HSOTG_REG(0x0044) 246#define GSNPSID_ID_MASK 0xffff0000 247 248#define GHWCFG2 HSOTG_REG(0x0048) 249#define GHWCFG2_OTG_ENABLE_IC_USB (1U << 31) 250#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26) 251#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26 252#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24) 253#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24 254#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22) 255#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22 256#define GHWCFG2_MULTI_PROC_INT (1 << 20) 257#define GHWCFG2_DYNAMIC_FIFO (1 << 19) 258#define GHWCFG2_PERIO_EP_SUPPORTED (1 << 18) 259#define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14) 260#define GHWCFG2_NUM_HOST_CHAN_SHIFT 14 261#define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10) 262#define GHWCFG2_NUM_DEV_EP_SHIFT 10 263#define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8) 264#define GHWCFG2_FS_PHY_TYPE_SHIFT 8 265#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0 266#define GHWCFG2_FS_PHY_TYPE_DEDICATED 1 267#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2 268#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3 269#define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6) 270#define GHWCFG2_HS_PHY_TYPE_SHIFT 6 271#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 272#define GHWCFG2_HS_PHY_TYPE_UTMI 1 273#define GHWCFG2_HS_PHY_TYPE_ULPI 2 274#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 275#define GHWCFG2_POINT2POINT (1 << 5) 276#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3) 277#define GHWCFG2_ARCHITECTURE_SHIFT 3 278#define GHWCFG2_SLAVE_ONLY_ARCH 0 279#define GHWCFG2_EXT_DMA_ARCH 1 280#define GHWCFG2_INT_DMA_ARCH 2 281#define GHWCFG2_OP_MODE_MASK (0x7 << 0) 282#define GHWCFG2_OP_MODE_SHIFT 0 283#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0 284#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1 285#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2 286#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 287#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 288#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 289#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 290#define GHWCFG2_OP_MODE_UNDEFINED 7 291 292#define GHWCFG3 HSOTG_REG(0x004c) 293#define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16) 294#define GHWCFG3_DFIFO_DEPTH_SHIFT 16 295#define GHWCFG3_OTG_LPM_EN (1 << 15) 296#define GHWCFG3_BC_SUPPORT (1 << 14) 297#define GHWCFG3_OTG_ENABLE_HSIC (1 << 13) 298#define GHWCFG3_ADP_SUPP (1 << 12) 299#define GHWCFG3_SYNCH_RESET_TYPE (1 << 11) 300#define GHWCFG3_OPTIONAL_FEATURES (1 << 10) 301#define GHWCFG3_VENDOR_CTRL_IF (1 << 9) 302#define GHWCFG3_I2C (1 << 8) 303#define GHWCFG3_OTG_FUNC (1 << 7) 304#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4) 305#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4 306#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0) 307#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0 308 309#define GHWCFG4 HSOTG_REG(0x0050) 310#define GHWCFG4_DESC_DMA_DYN (1U << 31) 311#define GHWCFG4_DESC_DMA (1 << 30) 312#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26) 313#define GHWCFG4_NUM_IN_EPS_SHIFT 26 314#define GHWCFG4_DED_FIFO_EN (1 << 25) 315#define GHWCFG4_DED_FIFO_SHIFT 25 316#define GHWCFG4_SESSION_END_FILT_EN (1 << 24) 317#define GHWCFG4_B_VALID_FILT_EN (1 << 23) 318#define GHWCFG4_A_VALID_FILT_EN (1 << 22) 319#define GHWCFG4_VBUS_VALID_FILT_EN (1 << 21) 320#define GHWCFG4_IDDIG_FILT_EN (1 << 20) 321#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16) 322#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16 323#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) 324#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14 325#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 326#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 327#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 328#define GHWCFG4_ACG_SUPPORTED (1 << 12) 329#define GHWCFG4_IPG_ISOC_SUPPORTED (1 << 11) 330#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED (1 << 10) 331#define GHWCFG4_XHIBER (1 << 7) 332#define GHWCFG4_HIBER (1 << 6) 333#define GHWCFG4_MIN_AHB_FREQ (1 << 5) 334#define GHWCFG4_POWER_OPTIMIZ (1 << 4) 335#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0) 336#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0 337 338#define GLPMCFG HSOTG_REG(0x0054) 339#define GLPMCFG_INVSELHSIC (1U << 31) 340#define GLPMCFG_HSICCON (1 << 30) 341#define GLPMCFG_RSTRSLPSTS (1 << 29) 342#define GLPMCFG_ENBESL (1 << 28) 343#define GLPMCFG_RETRY_COUNT_STS_MASK (0x7 << 25) 344#define GLPMCFG_RETRY_COUNT_STS_SHIFT 25 345#define GLPMCFG_SNDLPM (1 << 24) 346#define GLPMCFG_RETRY_CNT_MASK (0x7 << 21) 347#define GLPMCFG_RETRY_CNT_SHIFT 21 348#define GLPMCFG_LPM_REJECT_CTRL_CONTROL (1 << 21) 349#define GLPMCFG_LPM_ACCEPT_CTRL_ISOC (1 << 22) 350#define GLPMCFG_LPM_CHAN_INDEX_MASK (0xf << 17) 351#define GLPMCFG_LPM_CHAN_INDEX_SHIFT 17 352#define GLPMCFG_L1RESUMEOK (1 << 16) 353#define GLPMCFG_SLPSTS (1 << 15) 354#define GLPMCFG_COREL1RES_MASK (0x3 << 13) 355#define GLPMCFG_COREL1RES_SHIFT 13 356#define GLPMCFG_HIRD_THRES_MASK (0x1f << 8) 357#define GLPMCFG_HIRD_THRES_SHIFT 8 358#define GLPMCFG_HIRD_THRES_EN (0x10 << 8) 359#define GLPMCFG_ENBLSLPM (1 << 7) 360#define GLPMCFG_BREMOTEWAKE (1 << 6) 361#define GLPMCFG_HIRD_MASK (0xf << 2) 362#define GLPMCFG_HIRD_SHIFT 2 363#define GLPMCFG_APPL1RES (1 << 1) 364#define GLPMCFG_LPMCAP (1 << 0) 365 366#define GPWRDN HSOTG_REG(0x0058) 367#define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24) 368#define GPWRDN_MULT_VAL_ID_BC_SHIFT 24 369#define GPWRDN_ADP_INT (1 << 23) 370#define GPWRDN_BSESSVLD (1 << 22) 371#define GPWRDN_IDSTS (1 << 21) 372#define GPWRDN_LINESTATE_MASK (0x3 << 19) 373#define GPWRDN_LINESTATE_SHIFT 19 374#define GPWRDN_STS_CHGINT_MSK (1 << 18) 375#define GPWRDN_STS_CHGINT (1 << 17) 376#define GPWRDN_SRP_DET_MSK (1 << 16) 377#define GPWRDN_SRP_DET (1 << 15) 378#define GPWRDN_CONNECT_DET_MSK (1 << 14) 379#define GPWRDN_CONNECT_DET (1 << 13) 380#define GPWRDN_DISCONN_DET_MSK (1 << 12) 381#define GPWRDN_DISCONN_DET (1 << 11) 382#define GPWRDN_RST_DET_MSK (1 << 10) 383#define GPWRDN_RST_DET (1 << 9) 384#define GPWRDN_LNSTSCHG_MSK (1 << 8) 385#define GPWRDN_LNSTSCHG (1 << 7) 386#define GPWRDN_DIS_VBUS (1 << 6) 387#define GPWRDN_PWRDNSWTCH (1 << 5) 388#define GPWRDN_PWRDNRSTN (1 << 4) 389#define GPWRDN_PWRDNCLMP (1 << 3) 390#define GPWRDN_RESTORE (1 << 2) 391#define GPWRDN_PMUACTV (1 << 1) 392#define GPWRDN_PMUINTSEL (1 << 0) 393 394#define GDFIFOCFG HSOTG_REG(0x005c) 395#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16) 396#define GDFIFOCFG_EPINFOBASE_SHIFT 16 397#define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0) 398#define GDFIFOCFG_GDFIFOCFG_SHIFT 0 399 400#define ADPCTL HSOTG_REG(0x0060) 401#define ADPCTL_AR_MASK (0x3 << 27) 402#define ADPCTL_AR_SHIFT 27 403#define ADPCTL_ADP_TMOUT_INT_MSK (1 << 26) 404#define ADPCTL_ADP_SNS_INT_MSK (1 << 25) 405#define ADPCTL_ADP_PRB_INT_MSK (1 << 24) 406#define ADPCTL_ADP_TMOUT_INT (1 << 23) 407#define ADPCTL_ADP_SNS_INT (1 << 22) 408#define ADPCTL_ADP_PRB_INT (1 << 21) 409#define ADPCTL_ADPENA (1 << 20) 410#define ADPCTL_ADPRES (1 << 19) 411#define ADPCTL_ENASNS (1 << 18) 412#define ADPCTL_ENAPRB (1 << 17) 413#define ADPCTL_RTIM_MASK (0x7ff << 6) 414#define ADPCTL_RTIM_SHIFT 6 415#define ADPCTL_PRB_PER_MASK (0x3 << 4) 416#define ADPCTL_PRB_PER_SHIFT 4 417#define ADPCTL_PRB_DELTA_MASK (0x3 << 2) 418#define ADPCTL_PRB_DELTA_SHIFT 2 419#define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0) 420#define ADPCTL_PRB_DSCHRG_SHIFT 0 421 422#define GREFCLK HSOTG_REG(0x0064) 423#define GREFCLK_REFCLKPER_MASK (0x1ffff << 15) 424#define GREFCLK_REFCLKPER_SHIFT 15 425#define GREFCLK_REF_CLK_MODE (1 << 14) 426#define GREFCLK_SOF_CNT_WKUP_ALERT_MASK (0x3ff) 427#define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT 0 428 429#define GINTMSK2 HSOTG_REG(0x0068) 430#define GINTMSK2_WKUP_ALERT_INT_MSK (1 << 0) 431 432#define GINTSTS2 HSOTG_REG(0x006c) 433#define GINTSTS2_WKUP_ALERT_INT (1 << 0) 434 435#define HPTXFSIZ HSOTG_REG(0x100) 436/* Use FIFOSIZE_* constants to access this register */ 437 438#define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4)) 439/* Use FIFOSIZE_* constants to access this register */ 440 441/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */ 442#define FIFOSIZE_DEPTH_MASK (0xffff << 16) 443#define FIFOSIZE_DEPTH_SHIFT 16 444#define FIFOSIZE_STARTADDR_MASK (0xffff << 0) 445#define FIFOSIZE_STARTADDR_SHIFT 0 446#define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff) 447 448/* Device mode registers */ 449 450#define DCFG HSOTG_REG(0x800) 451#define DCFG_DESCDMA_EN (1 << 23) 452#define DCFG_EPMISCNT_MASK (0x1f << 18) 453#define DCFG_EPMISCNT_SHIFT 18 454#define DCFG_EPMISCNT_LIMIT 0x1f 455#define DCFG_EPMISCNT(_x) ((_x) << 18) 456#define DCFG_IPG_ISOC_SUPPORDED (1 << 17) 457#define DCFG_PERFRINT_MASK (0x3 << 11) 458#define DCFG_PERFRINT_SHIFT 11 459#define DCFG_PERFRINT_LIMIT 0x3 460#define DCFG_PERFRINT(_x) ((_x) << 11) 461#define DCFG_DEVADDR_MASK (0x7f << 4) 462#define DCFG_DEVADDR_SHIFT 4 463#define DCFG_DEVADDR_LIMIT 0x7f 464#define DCFG_DEVADDR(_x) ((_x) << 4) 465#define DCFG_NZ_STS_OUT_HSHK (1 << 2) 466#define DCFG_DEVSPD_MASK (0x3 << 0) 467#define DCFG_DEVSPD_SHIFT 0 468#define DCFG_DEVSPD_HS 0 469#define DCFG_DEVSPD_FS 1 470#define DCFG_DEVSPD_LS 2 471#define DCFG_DEVSPD_FS48 3 472 473#define DCTL HSOTG_REG(0x804) 474#define DCTL_SERVICE_INTERVAL_SUPPORTED (1 << 19) 475#define DCTL_PWRONPRGDONE (1 << 11) 476#define DCTL_CGOUTNAK (1 << 10) 477#define DCTL_SGOUTNAK (1 << 9) 478#define DCTL_CGNPINNAK (1 << 8) 479#define DCTL_SGNPINNAK (1 << 7) 480#define DCTL_TSTCTL_MASK (0x7 << 4) 481#define DCTL_TSTCTL_SHIFT 4 482#define DCTL_GOUTNAKSTS (1 << 3) 483#define DCTL_GNPINNAKSTS (1 << 2) 484#define DCTL_SFTDISCON (1 << 1) 485#define DCTL_RMTWKUPSIG (1 << 0) 486 487#define DSTS HSOTG_REG(0x808) 488#define DSTS_SOFFN_MASK (0x3fff << 8) 489#define DSTS_SOFFN_SHIFT 8 490#define DSTS_SOFFN_LIMIT 0x3fff 491#define DSTS_SOFFN(_x) ((_x) << 8) 492#define DSTS_ERRATICERR (1 << 3) 493#define DSTS_ENUMSPD_MASK (0x3 << 1) 494#define DSTS_ENUMSPD_SHIFT 1 495#define DSTS_ENUMSPD_HS 0 496#define DSTS_ENUMSPD_FS 1 497#define DSTS_ENUMSPD_LS 2 498#define DSTS_ENUMSPD_FS48 3 499#define DSTS_SUSPSTS (1 << 0) 500 501#define DIEPMSK HSOTG_REG(0x810) 502#define DIEPMSK_NAKMSK (1 << 13) 503#define DIEPMSK_BNAININTRMSK (1 << 9) 504#define DIEPMSK_TXFIFOUNDRNMSK (1 << 8) 505#define DIEPMSK_TXFIFOEMPTY (1 << 7) 506#define DIEPMSK_INEPNAKEFFMSK (1 << 6) 507#define DIEPMSK_INTKNEPMISMSK (1 << 5) 508#define DIEPMSK_INTKNTXFEMPMSK (1 << 4) 509#define DIEPMSK_TIMEOUTMSK (1 << 3) 510#define DIEPMSK_AHBERRMSK (1 << 2) 511#define DIEPMSK_EPDISBLDMSK (1 << 1) 512#define DIEPMSK_XFERCOMPLMSK (1 << 0) 513 514#define DOEPMSK HSOTG_REG(0x814) 515#define DOEPMSK_BNAMSK (1 << 9) 516#define DOEPMSK_BACK2BACKSETUP (1 << 6) 517#define DOEPMSK_STSPHSERCVDMSK (1 << 5) 518#define DOEPMSK_OUTTKNEPDISMSK (1 << 4) 519#define DOEPMSK_SETUPMSK (1 << 3) 520#define DOEPMSK_AHBERRMSK (1 << 2) 521#define DOEPMSK_EPDISBLDMSK (1 << 1) 522#define DOEPMSK_XFERCOMPLMSK (1 << 0) 523 524#define DAINT HSOTG_REG(0x818) 525#define DAINTMSK HSOTG_REG(0x81C) 526#define DAINT_OUTEP_SHIFT 16 527#define DAINT_OUTEP(_x) (1 << ((_x) + 16)) 528#define DAINT_INEP(_x) (1 << (_x)) 529 530#define DTKNQR1 HSOTG_REG(0x820) 531#define DTKNQR2 HSOTG_REG(0x824) 532#define DTKNQR3 HSOTG_REG(0x830) 533#define DTKNQR4 HSOTG_REG(0x834) 534#define DIEPEMPMSK HSOTG_REG(0x834) 535 536#define DVBUSDIS HSOTG_REG(0x828) 537#define DVBUSPULSE HSOTG_REG(0x82C) 538 539#define DIEPCTL0 HSOTG_REG(0x900) 540#define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20)) 541 542#define DOEPCTL0 HSOTG_REG(0xB00) 543#define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20)) 544 545/* EP0 specialness: 546 * bits[29..28] - reserved (no SetD0PID, SetD1PID) 547 * bits[25..22] - should always be zero, this isn't a periodic endpoint 548 * bits[10..0] - MPS setting different for EP0 549 */ 550#define D0EPCTL_MPS_MASK (0x3 << 0) 551#define D0EPCTL_MPS_SHIFT 0 552#define D0EPCTL_MPS_64 0 553#define D0EPCTL_MPS_32 1 554#define D0EPCTL_MPS_16 2 555#define D0EPCTL_MPS_8 3 556 557#define DXEPCTL_EPENA (1U << 31) 558#define DXEPCTL_EPDIS (1 << 30) 559#define DXEPCTL_SETD1PID (1 << 29) 560#define DXEPCTL_SETODDFR (1 << 29) 561#define DXEPCTL_SETD0PID (1 << 28) 562#define DXEPCTL_SETEVENFR (1 << 28) 563#define DXEPCTL_SNAK (1 << 27) 564#define DXEPCTL_CNAK (1 << 26) 565#define DXEPCTL_TXFNUM_MASK (0xf << 22) 566#define DXEPCTL_TXFNUM_SHIFT 22 567#define DXEPCTL_TXFNUM_LIMIT 0xf 568#define DXEPCTL_TXFNUM(_x) ((_x) << 22) 569#define DXEPCTL_STALL (1 << 21) 570#define DXEPCTL_SNP (1 << 20) 571#define DXEPCTL_EPTYPE_MASK (0x3 << 18) 572#define DXEPCTL_EPTYPE_CONTROL (0x0 << 18) 573#define DXEPCTL_EPTYPE_ISO (0x1 << 18) 574#define DXEPCTL_EPTYPE_BULK (0x2 << 18) 575#define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18) 576 577#define DXEPCTL_NAKSTS (1 << 17) 578#define DXEPCTL_DPID (1 << 16) 579#define DXEPCTL_EOFRNUM (1 << 16) 580#define DXEPCTL_USBACTEP (1 << 15) 581#define DXEPCTL_NEXTEP_MASK (0xf << 11) 582#define DXEPCTL_NEXTEP_SHIFT 11 583#define DXEPCTL_NEXTEP_LIMIT 0xf 584#define DXEPCTL_NEXTEP(_x) ((_x) << 11) 585#define DXEPCTL_MPS_MASK (0x7ff << 0) 586#define DXEPCTL_MPS_SHIFT 0 587#define DXEPCTL_MPS_LIMIT 0x7ff 588#define DXEPCTL_MPS(_x) ((_x) << 0) 589 590#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20)) 591#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20)) 592#define DXEPINT_SETUP_RCVD (1 << 15) 593#define DXEPINT_NYETINTRPT (1 << 14) 594#define DXEPINT_NAKINTRPT (1 << 13) 595#define DXEPINT_BBLEERRINTRPT (1 << 12) 596#define DXEPINT_PKTDRPSTS (1 << 11) 597#define DXEPINT_BNAINTR (1 << 9) 598#define DXEPINT_TXFIFOUNDRN (1 << 8) 599#define DXEPINT_OUTPKTERR (1 << 8) 600#define DXEPINT_TXFEMP (1 << 7) 601#define DXEPINT_INEPNAKEFF (1 << 6) 602#define DXEPINT_BACK2BACKSETUP (1 << 6) 603#define DXEPINT_INTKNEPMIS (1 << 5) 604#define DXEPINT_STSPHSERCVD (1 << 5) 605#define DXEPINT_INTKNTXFEMP (1 << 4) 606#define DXEPINT_OUTTKNEPDIS (1 << 4) 607#define DXEPINT_TIMEOUT (1 << 3) 608#define DXEPINT_SETUP (1 << 3) 609#define DXEPINT_AHBERR (1 << 2) 610#define DXEPINT_EPDISBLD (1 << 1) 611#define DXEPINT_XFERCOMPL (1 << 0) 612 613#define DIEPTSIZ0 HSOTG_REG(0x910) 614#define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19) 615#define DIEPTSIZ0_PKTCNT_SHIFT 19 616#define DIEPTSIZ0_PKTCNT_LIMIT 0x3 617#define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19) 618#define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0) 619#define DIEPTSIZ0_XFERSIZE_SHIFT 0 620#define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f 621#define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0) 622 623#define DOEPTSIZ0 HSOTG_REG(0xB10) 624#define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29) 625#define DOEPTSIZ0_SUPCNT_SHIFT 29 626#define DOEPTSIZ0_SUPCNT_LIMIT 0x3 627#define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29) 628#define DOEPTSIZ0_PKTCNT (1 << 19) 629#define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0) 630#define DOEPTSIZ0_XFERSIZE_SHIFT 0 631 632#define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20)) 633#define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20)) 634#define DXEPTSIZ_MC_MASK (0x3 << 29) 635#define DXEPTSIZ_MC_SHIFT 29 636#define DXEPTSIZ_MC_LIMIT 0x3 637#define DXEPTSIZ_MC(_x) ((_x) << 29) 638#define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19) 639#define DXEPTSIZ_PKTCNT_SHIFT 19 640#define DXEPTSIZ_PKTCNT_LIMIT 0x3ff 641#define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff) 642#define DXEPTSIZ_PKTCNT(_x) ((_x) << 19) 643#define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0) 644#define DXEPTSIZ_XFERSIZE_SHIFT 0 645#define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff 646#define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff) 647#define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0) 648 649#define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20)) 650#define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20)) 651 652#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20)) 653 654#define PCGCTL HSOTG_REG(0x0e00) 655#define PCGCTL_IF_DEV_MODE (1U << 31) 656#define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29) 657#define PCGCTL_P2HD_PRT_SPD_SHIFT 29 658#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27) 659#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27 660#define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20) 661#define PCGCTL_MAC_DEV_ADDR_SHIFT 20 662#define PCGCTL_MAX_TERMSEL (1 << 19) 663#define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17) 664#define PCGCTL_MAX_XCVRSELECT_SHIFT 17 665#define PCGCTL_PORT_POWER (1 << 16) 666#define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14) 667#define PCGCTL_PRT_CLK_SEL_SHIFT 14 668#define PCGCTL_ESS_REG_RESTORED (1 << 13) 669#define PCGCTL_EXTND_HIBER_SWITCH (1 << 12) 670#define PCGCTL_EXTND_HIBER_PWRCLMP (1 << 11) 671#define PCGCTL_ENBL_EXTND_HIBER (1 << 10) 672#define PCGCTL_RESTOREMODE (1 << 9) 673#define PCGCTL_RESETAFTSUSP (1 << 8) 674#define PCGCTL_DEEP_SLEEP (1 << 7) 675#define PCGCTL_PHY_IN_SLEEP (1 << 6) 676#define PCGCTL_ENBL_SLEEP_GATING (1 << 5) 677#define PCGCTL_RSTPDWNMODULE (1 << 3) 678#define PCGCTL_PWRCLMP (1 << 2) 679#define PCGCTL_GATEHCLK (1 << 1) 680#define PCGCTL_STOPPCLK (1 << 0) 681 682#define PCGCCTL1 HSOTG_REG(0xe04) 683#define PCGCCTL1_TIMER (0x3 << 1) 684#define PCGCCTL1_GATEEN (1 << 0) 685 686#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000)) 687 688/* Host Mode Registers */ 689 690#define HCFG HSOTG_REG(0x0400) 691#define HCFG_MODECHTIMEN (1U << 31) 692#define HCFG_PERSCHEDENA (1 << 26) 693#define HCFG_FRLISTEN_MASK (0x3 << 24) 694#define HCFG_FRLISTEN_SHIFT 24 695#define HCFG_FRLISTEN_8 (0 << 24) 696#define FRLISTEN_8_SIZE 8 697#define HCFG_FRLISTEN_16 (1 << 24) 698#define FRLISTEN_16_SIZE 16 699#define HCFG_FRLISTEN_32 (2 << 24) 700#define FRLISTEN_32_SIZE 32 701#define HCFG_FRLISTEN_64 (3 << 24) 702#define FRLISTEN_64_SIZE 64 703#define HCFG_DESCDMA (1 << 23) 704#define HCFG_RESVALID_MASK (0xff << 8) 705#define HCFG_RESVALID_SHIFT 8 706#define HCFG_ENA32KHZ (1 << 7) 707#define HCFG_FSLSSUPP (1 << 2) 708#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0) 709#define HCFG_FSLSPCLKSEL_SHIFT 0 710#define HCFG_FSLSPCLKSEL_30_60_MHZ 0 711#define HCFG_FSLSPCLKSEL_48_MHZ 1 712#define HCFG_FSLSPCLKSEL_6_MHZ 2 713 714#define HFIR HSOTG_REG(0x0404) 715#define HFIR_FRINT_MASK (0xffff << 0) 716#define HFIR_FRINT_SHIFT 0 717#define HFIR_RLDCTRL (1 << 16) 718 719#define HFNUM HSOTG_REG(0x0408) 720#define HFNUM_FRREM_MASK (0xffff << 16) 721#define HFNUM_FRREM_SHIFT 16 722#define HFNUM_FRNUM_MASK (0xffff << 0) 723#define HFNUM_FRNUM_SHIFT 0 724#define HFNUM_MAX_FRNUM 0x3fff 725 726#define HPTXSTS HSOTG_REG(0x0410) 727#define TXSTS_QTOP_ODD (1U << 31) 728#define TXSTS_QTOP_CHNEP_MASK (0xf << 27) 729#define TXSTS_QTOP_CHNEP_SHIFT 27 730#define TXSTS_QTOP_TOKEN_MASK (0x3 << 25) 731#define TXSTS_QTOP_TOKEN_SHIFT 25 732#define TXSTS_QTOP_TERMINATE (1 << 24) 733#define TXSTS_QSPCAVAIL_MASK (0xff << 16) 734#define TXSTS_QSPCAVAIL_SHIFT 16 735#define TXSTS_FSPCAVAIL_MASK (0xffff << 0) 736#define TXSTS_FSPCAVAIL_SHIFT 0 737 738#define HAINT HSOTG_REG(0x0414) 739#define HAINTMSK HSOTG_REG(0x0418) 740#define HFLBADDR HSOTG_REG(0x041c) 741 742#define HPRT0 HSOTG_REG(0x0440) 743#define HPRT0_SPD_MASK (0x3 << 17) 744#define HPRT0_SPD_SHIFT 17 745#define HPRT0_SPD_HIGH_SPEED 0 746#define HPRT0_SPD_FULL_SPEED 1 747#define HPRT0_SPD_LOW_SPEED 2 748#define HPRT0_TSTCTL_MASK (0xf << 13) 749#define HPRT0_TSTCTL_SHIFT 13 750#define HPRT0_PWR (1 << 12) 751#define HPRT0_LNSTS_MASK (0x3 << 10) 752#define HPRT0_LNSTS_SHIFT 10 753#define HPRT0_RST (1 << 8) 754#define HPRT0_SUSP (1 << 7) 755#define HPRT0_RES (1 << 6) 756#define HPRT0_OVRCURRCHG (1 << 5) 757#define HPRT0_OVRCURRACT (1 << 4) 758#define HPRT0_ENACHG (1 << 3) 759#define HPRT0_ENA (1 << 2) 760#define HPRT0_CONNDET (1 << 1) 761#define HPRT0_CONNSTS (1 << 0) 762 763#define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch)) 764#define HCCHAR_CHENA (1U << 31) 765#define HCCHAR_CHDIS (1 << 30) 766#define HCCHAR_ODDFRM (1 << 29) 767#define HCCHAR_DEVADDR_MASK (0x7f << 22) 768#define HCCHAR_DEVADDR_SHIFT 22 769#define HCCHAR_MULTICNT_MASK (0x3 << 20) 770#define HCCHAR_MULTICNT_SHIFT 20 771#define HCCHAR_EPTYPE_MASK (0x3 << 18) 772#define HCCHAR_EPTYPE_SHIFT 18 773#define HCCHAR_LSPDDEV (1 << 17) 774#define HCCHAR_EPDIR (1 << 15) 775#define HCCHAR_EPNUM_MASK (0xf << 11) 776#define HCCHAR_EPNUM_SHIFT 11 777#define HCCHAR_MPS_MASK (0x7ff << 0) 778#define HCCHAR_MPS_SHIFT 0 779 780#define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch)) 781#define HCSPLT_SPLTENA (1U << 31) 782#define HCSPLT_COMPSPLT (1 << 16) 783#define HCSPLT_XACTPOS_MASK (0x3 << 14) 784#define HCSPLT_XACTPOS_SHIFT 14 785#define HCSPLT_XACTPOS_MID 0 786#define HCSPLT_XACTPOS_END 1 787#define HCSPLT_XACTPOS_BEGIN 2 788#define HCSPLT_XACTPOS_ALL 3 789#define HCSPLT_HUBADDR_MASK (0x7f << 7) 790#define HCSPLT_HUBADDR_SHIFT 7 791#define HCSPLT_PRTADDR_MASK (0x7f << 0) 792#define HCSPLT_PRTADDR_SHIFT 0 793 794#define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch)) 795#define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch)) 796#define HCINTMSK_RESERVED14_31 (0x3ffff << 14) 797#define HCINTMSK_FRM_LIST_ROLL (1 << 13) 798#define HCINTMSK_XCS_XACT (1 << 12) 799#define HCINTMSK_BNA (1 << 11) 800#define HCINTMSK_DATATGLERR (1 << 10) 801#define HCINTMSK_FRMOVRUN (1 << 9) 802#define HCINTMSK_BBLERR (1 << 8) 803#define HCINTMSK_XACTERR (1 << 7) 804#define HCINTMSK_NYET (1 << 6) 805#define HCINTMSK_ACK (1 << 5) 806#define HCINTMSK_NAK (1 << 4) 807#define HCINTMSK_STALL (1 << 3) 808#define HCINTMSK_AHBERR (1 << 2) 809#define HCINTMSK_CHHLTD (1 << 1) 810#define HCINTMSK_XFERCOMPL (1 << 0) 811 812#define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch)) 813#define TSIZ_DOPNG (1U << 31) 814#define TSIZ_SC_MC_PID_MASK (0x3 << 29) 815#define TSIZ_SC_MC_PID_SHIFT 29 816#define TSIZ_SC_MC_PID_DATA0 0 817#define TSIZ_SC_MC_PID_DATA2 1 818#define TSIZ_SC_MC_PID_DATA1 2 819#define TSIZ_SC_MC_PID_MDATA 3 820#define TSIZ_SC_MC_PID_SETUP 3 821#define TSIZ_PKTCNT_MASK (0x3ff << 19) 822#define TSIZ_PKTCNT_SHIFT 19 823#define TSIZ_NTD_MASK (0xff << 8) 824#define TSIZ_NTD_SHIFT 8 825#define TSIZ_SCHINFO_MASK (0xff << 0) 826#define TSIZ_SCHINFO_SHIFT 0 827#define TSIZ_XFERSIZE_MASK (0x7ffff << 0) 828#define TSIZ_XFERSIZE_SHIFT 0 829 830#define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch)) 831 832#define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch)) 833 834#define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch)) 835 836/** 837 * struct dwc2_dma_desc - DMA descriptor structure, 838 * used for both host and gadget modes 839 * 840 * @status: DMA descriptor status quadlet 841 * @buf: DMA descriptor data buffer pointer 842 * 843 * DMA Descriptor structure contains two quadlets: 844 * Status quadlet and Data buffer pointer. 845 */ 846struct dwc2_dma_desc { 847 u32 status; 848 u32 buf; 849} __packed; 850 851/* Host Mode DMA descriptor status quadlet */ 852 853#define HOST_DMA_A (1U << 31) 854#define HOST_DMA_STS_MASK (0x3 << 28) 855#define HOST_DMA_STS_SHIFT 28 856#define HOST_DMA_STS_PKTERR (1 << 28) 857#define HOST_DMA_EOL (1 << 26) 858#define HOST_DMA_IOC (1 << 25) 859#define HOST_DMA_SUP (1 << 24) 860#define HOST_DMA_ALT_QTD (1 << 23) 861#define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17) 862#define HOST_DMA_QTD_OFFSET_SHIFT 17 863#define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0) 864#define HOST_DMA_ISOC_NBYTES_SHIFT 0 865#define HOST_DMA_NBYTES_MASK (0x1ffff << 0) 866#define HOST_DMA_NBYTES_SHIFT 0 867#define HOST_DMA_NBYTES_LIMIT 131071 868 869/* Device Mode DMA descriptor status quadlet */ 870 871#define DEV_DMA_BUFF_STS_MASK (0x3 << 30) 872#define DEV_DMA_BUFF_STS_SHIFT 30 873#define DEV_DMA_BUFF_STS_HREADY 0 874#define DEV_DMA_BUFF_STS_DMABUSY 1 875#define DEV_DMA_BUFF_STS_DMADONE 2 876#define DEV_DMA_BUFF_STS_HBUSY 3 877#define DEV_DMA_STS_MASK (0x3 << 28) 878#define DEV_DMA_STS_SHIFT 28 879#define DEV_DMA_STS_SUCC 0 880#define DEV_DMA_STS_BUFF_FLUSH 1 881#define DEV_DMA_STS_BUFF_ERR 3 882#define DEV_DMA_L (1 << 27) 883#define DEV_DMA_SHORT (1 << 26) 884#define DEV_DMA_IOC (1 << 25) 885#define DEV_DMA_SR (1 << 24) 886#define DEV_DMA_MTRF (1 << 23) 887#define DEV_DMA_ISOC_PID_MASK (0x3 << 23) 888#define DEV_DMA_ISOC_PID_SHIFT 23 889#define DEV_DMA_ISOC_PID_DATA0 0 890#define DEV_DMA_ISOC_PID_DATA2 1 891#define DEV_DMA_ISOC_PID_DATA1 2 892#define DEV_DMA_ISOC_PID_MDATA 3 893#define DEV_DMA_ISOC_FRNUM_MASK (0x7ff << 12) 894#define DEV_DMA_ISOC_FRNUM_SHIFT 12 895#define DEV_DMA_ISOC_TX_NBYTES_MASK (0xfff << 0) 896#define DEV_DMA_ISOC_TX_NBYTES_LIMIT 0xfff 897#define DEV_DMA_ISOC_RX_NBYTES_MASK (0x7ff << 0) 898#define DEV_DMA_ISOC_RX_NBYTES_LIMIT 0x7ff 899#define DEV_DMA_ISOC_NBYTES_SHIFT 0 900#define DEV_DMA_NBYTES_MASK (0xffff << 0) 901#define DEV_DMA_NBYTES_SHIFT 0 902#define DEV_DMA_NBYTES_LIMIT 0xffff 903 904#define MAX_DMA_DESC_NUM_GENERIC 64 905#define MAX_DMA_DESC_NUM_HS_ISOC 256 906 907#endif /* __DWC2_HW_H__ */ 908