dwc2_hcdqueue.c revision 1.7
1/* $OpenBSD: dwc2_hcdqueue.c,v 1.7 2015/06/28 11:48:18 jmatthew Exp $ */ 2/* $NetBSD: dwc2_hcdqueue.c,v 1.11 2014/09/03 10:00:08 skrll Exp $ */ 3 4/* 5 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines 6 * 7 * Copyright (C) 2004-2013 Synopsys, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions, and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The names of the above-listed copyright holders may not be used 19 * to endorse or promote products derived from this software without 20 * specific prior written permission. 21 * 22 * ALTERNATIVELY, this software may be distributed under the terms of the 23 * GNU General Public License ("GPL") as published by the Free Software 24 * Foundation; either version 2 of the License, or (at your option) any 25 * later version. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40/* 41 * This file contains the functions to manage Queue Heads and Queue 42 * Transfer Descriptors for Host mode 43 */ 44 45#if 0 46#include <sys/cdefs.h> 47__KERNEL_RCSID(0, "$NetBSD: dwc2_hcdqueue.c,v 1.11 2014/09/03 10:00:08 skrll Exp $"); 48#endif 49 50#include <sys/param.h> 51#include <sys/systm.h> 52#include <sys/types.h> 53#include <sys/malloc.h> 54#include <sys/pool.h> 55 56#include <machine/bus.h> 57 58#include <dev/usb/usb.h> 59#include <dev/usb/usbdi.h> 60#include <dev/usb/usbdivar.h> 61#include <dev/usb/usb_mem.h> 62 63#include <dev/usb/dwc2/dwc2.h> 64#include <dev/usb/dwc2/dwc2var.h> 65 66#include <dev/usb/dwc2/dwc2_core.h> 67#include <dev/usb/dwc2/dwc2_hcd.h> 68 69STATIC u32 dwc2_calc_bus_time(struct dwc2_hsotg *, int, int, int, int); 70 71/** 72 * dwc2_qh_init() - Initializes a QH structure 73 * 74 * @hsotg: The HCD state structure for the DWC OTG controller 75 * @qh: The QH to init 76 * @urb: Holds the information about the device/endpoint needed to initialize 77 * the QH 78 */ 79#define SCHEDULE_SLOP 10 80STATIC void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 81 struct dwc2_hcd_urb *urb) 82{ 83 int dev_speed, hub_addr, hub_port; 84 85 dev_vdbg(hsotg->dev, "%s()\n", __func__); 86 87 /* Initialize QH */ 88 qh->ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info); 89 qh->ep_is_in = dwc2_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0; 90 91 qh->data_toggle = DWC2_HC_PID_DATA0; 92 qh->maxp = dwc2_hcd_get_mps(&urb->pipe_info); 93 TAILQ_INIT(&qh->qtd_list); 94 qh->linked = 0; 95 96 /* FS/LS Endpoint on HS Hub, NOT virtual root hub */ 97 dev_speed = dwc2_host_get_speed(hsotg, urb->priv); 98 99 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port); 100 qh->nak_frame = 0xffff; 101 102 if ((dev_speed == USB_SPEED_LOW || dev_speed == USB_SPEED_FULL) && 103 hub_addr != 0 && hub_addr != 1) { 104 dev_vdbg(hsotg->dev, 105 "QH init: EP %d: TT found at hub addr %d, for port %d\n", 106 dwc2_hcd_get_ep_num(&urb->pipe_info), hub_addr, 107 hub_port); 108 qh->do_split = 1; 109 } 110 111 if (qh->ep_type == USB_ENDPOINT_XFER_INT || 112 qh->ep_type == USB_ENDPOINT_XFER_ISOC) { 113 /* Compute scheduling parameters once and save them */ 114 u32 hprt, prtspd; 115 116 /* Todo: Account for split transfers in the bus time */ 117 int bytecount = 118 dwc2_hb_mult(qh->maxp) * dwc2_max_packet(qh->maxp); 119 120 qh->usecs = dwc2_calc_bus_time(hsotg, qh->do_split ? 121 USB_SPEED_HIGH : dev_speed, qh->ep_is_in, 122 qh->ep_type == USB_ENDPOINT_XFER_ISOC, 123 bytecount); 124 /* Start in a slightly future (micro)frame */ 125 qh->sched_frame = dwc2_frame_num_inc(hsotg->frame_number, 126 SCHEDULE_SLOP); 127 qh->interval = urb->interval; 128#if 0 129 /* Increase interrupt polling rate for debugging */ 130 if (qh->ep_type == USB_ENDPOINT_XFER_INT) 131 qh->interval = 8; 132#endif 133 hprt = DWC2_READ_4(hsotg, HPRT0); 134 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; 135 if (prtspd == HPRT0_SPD_HIGH_SPEED && 136 (dev_speed == USB_SPEED_LOW || 137 dev_speed == USB_SPEED_FULL)) { 138 qh->interval *= 8; 139 qh->sched_frame |= 0x7; 140 qh->start_split_frame = qh->sched_frame; 141 } 142 dev_dbg(hsotg->dev, "interval=%d\n", qh->interval); 143 } 144 145 dev_vdbg(hsotg->dev, "DWC OTG HCD QH Initialized\n"); 146 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - qh = %p\n", qh); 147 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Device Address = %d\n", 148 dwc2_hcd_get_dev_addr(&urb->pipe_info)); 149 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Endpoint %d, %s\n", 150 dwc2_hcd_get_ep_num(&urb->pipe_info), 151 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); 152 153 qh->dev_speed = dev_speed; 154 155#ifdef DWC2_DEBUG 156 const char *speed, *type; 157 switch (dev_speed) { 158 case USB_SPEED_LOW: 159 speed = "low"; 160 break; 161 case USB_SPEED_FULL: 162 speed = "full"; 163 break; 164 case USB_SPEED_HIGH: 165 speed = "high"; 166 break; 167 default: 168 speed = "?"; 169 break; 170 } 171 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Speed = %s\n", speed); 172 173 switch (qh->ep_type) { 174 case USB_ENDPOINT_XFER_ISOC: 175 type = "isochronous"; 176 break; 177 case USB_ENDPOINT_XFER_INT: 178 type = "interrupt"; 179 break; 180 case USB_ENDPOINT_XFER_CONTROL: 181 type = "control"; 182 break; 183 case USB_ENDPOINT_XFER_BULK: 184 type = "bulk"; 185 break; 186 default: 187 type = "?"; 188 break; 189 } 190 191 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - Type = %s\n", type); 192#endif 193 194 if (qh->ep_type == USB_ENDPOINT_XFER_INT) { 195 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - usecs = %d\n", 196 qh->usecs); 197 dev_vdbg(hsotg->dev, "DWC OTG HCD QH - interval = %d\n", 198 qh->interval); 199 } 200} 201 202/** 203 * dwc2_hcd_qh_create() - Allocates and initializes a QH 204 * 205 * @hsotg: The HCD state structure for the DWC OTG controller 206 * @urb: Holds the information about the device/endpoint needed 207 * to initialize the QH 208 * @mem_flags: Flag to do atomic allocation if needed 209 * 210 * Return: Pointer to the newly allocated QH, or NULL on error 211 */ 212STATIC struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg, 213 struct dwc2_hcd_urb *urb, 214 gfp_t mem_flags) 215{ 216 struct dwc2_softc *sc = hsotg->hsotg_sc; 217 struct dwc2_qh *qh; 218 219 if (!urb->priv) 220 return NULL; 221 222 /* Allocate memory */ 223 qh = pool_get(&sc->sc_qhpool, PR_NOWAIT); 224 if (!qh) 225 return NULL; 226 227 memset(qh, 0, sizeof(*qh)); 228 dwc2_qh_init(hsotg, qh, urb); 229 230 if (hsotg->core_params->dma_desc_enable > 0 && 231 dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) { 232 dwc2_hcd_qh_free(hsotg, qh); 233 return NULL; 234 } 235 236 return qh; 237} 238 239/** 240 * dwc2_hcd_qh_free() - Frees the QH 241 * 242 * @hsotg: HCD instance 243 * @qh: The QH to free 244 * 245 * QH should already be removed from the list. QTD list should already be empty 246 * if called from URB Dequeue. 247 * 248 * Must NOT be called with interrupt disabled or spinlock held 249 */ 250void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 251{ 252 struct dwc2_softc *sc = hsotg->hsotg_sc; 253 254 if (hsotg->core_params->dma_desc_enable > 0) { 255 dwc2_hcd_qh_free_ddma(hsotg, qh); 256 } else if (qh->dw_align_buf) { 257 /* XXXNH */ 258 usb_freemem(&hsotg->hsotg_sc->sc_bus, &qh->dw_align_buf_usbdma); 259 } 260 261 pool_put(&sc->sc_qhpool, qh); 262} 263 264/** 265 * dwc2_periodic_channel_available() - Checks that a channel is available for a 266 * periodic transfer 267 * 268 * @hsotg: The HCD state structure for the DWC OTG controller 269 * 270 * Return: 0 if successful, negative error code otherwise 271 */ 272STATIC int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg) 273{ 274 /* 275 * Currently assuming that there is a dedicated host channel for 276 * each periodic transaction plus at least one host channel for 277 * non-periodic transactions 278 */ 279 int status; 280 int num_channels; 281 282 num_channels = hsotg->core_params->host_channels; 283 if (hsotg->periodic_channels + hsotg->non_periodic_channels < 284 num_channels 285 && hsotg->periodic_channels < num_channels - 1) { 286 status = 0; 287 } else { 288 dev_dbg(hsotg->dev, 289 "%s: Total channels: %d, Periodic: %d, " 290 "Non-periodic: %d\n", __func__, num_channels, 291 hsotg->periodic_channels, hsotg->non_periodic_channels); 292 status = -ENOSPC; 293 } 294 295 return status; 296} 297 298/** 299 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth 300 * for the specified QH in the periodic schedule 301 * 302 * @hsotg: The HCD state structure for the DWC OTG controller 303 * @qh: QH containing periodic bandwidth required 304 * 305 * Return: 0 if successful, negative error code otherwise 306 * 307 * For simplicity, this calculation assumes that all the transfers in the 308 * periodic schedule may occur in the same (micro)frame 309 */ 310STATIC int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg, 311 struct dwc2_qh *qh) 312{ 313 int status; 314 s16 max_claimed_usecs; 315 316 status = 0; 317 318 if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) { 319 /* 320 * High speed mode 321 * Max periodic usecs is 80% x 125 usec = 100 usec 322 */ 323 max_claimed_usecs = 100 - qh->usecs; 324 } else { 325 /* 326 * Full speed mode 327 * Max periodic usecs is 90% x 1000 usec = 900 usec 328 */ 329 max_claimed_usecs = 900 - qh->usecs; 330 } 331 332 if (hsotg->periodic_usecs > max_claimed_usecs) { 333 dev_err(hsotg->dev, 334 "%s: already claimed usecs %d, required usecs %d\n", 335 __func__, hsotg->periodic_usecs, qh->usecs); 336 status = -ENOSPC; 337 } 338 339 return status; 340} 341 342/** 343 * Microframe scheduler 344 * track the total use in hsotg->frame_usecs 345 * keep each qh use in qh->frame_usecs 346 * when surrendering the qh then donate the time back 347 */ 348STATIC const unsigned short max_uframe_usecs[] = { 349 100, 100, 100, 100, 100, 100, 30, 0 350}; 351 352void dwc2_hcd_init_usecs(struct dwc2_hsotg *hsotg) 353{ 354 int i; 355 356 for (i = 0; i < 8; i++) 357 hsotg->frame_usecs[i] = max_uframe_usecs[i]; 358} 359 360STATIC int dwc2_find_single_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 361{ 362 unsigned short utime = qh->usecs; 363 int i; 364 365 for (i = 0; i < 8; i++) { 366 /* At the start hsotg->frame_usecs[i] = max_uframe_usecs[i] */ 367 if (utime <= hsotg->frame_usecs[i]) { 368 hsotg->frame_usecs[i] -= utime; 369 qh->frame_usecs[i] += utime; 370 return i; 371 } 372 } 373 return -ENOSPC; 374} 375 376/* 377 * use this for FS apps that can span multiple uframes 378 */ 379STATIC int dwc2_find_multi_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 380{ 381 unsigned short utime = qh->usecs; 382 unsigned short xtime; 383 int t_left; 384 int i; 385 int j; 386 int k; 387 388 for (i = 0; i < 8; i++) { 389 if (hsotg->frame_usecs[i] <= 0) 390 continue; 391 392 /* 393 * we need n consecutive slots so use j as a start slot 394 * j plus j+1 must be enough time (for now) 395 */ 396 xtime = hsotg->frame_usecs[i]; 397 for (j = i + 1; j < 8; j++) { 398 /* 399 * if we add this frame remaining time to xtime we may 400 * be OK, if not we need to test j for a complete frame 401 */ 402 if (xtime + hsotg->frame_usecs[j] < utime) { 403 if (hsotg->frame_usecs[j] < 404 max_uframe_usecs[j]) 405 continue; 406 } 407 if (xtime >= utime) { 408 t_left = utime; 409 for (k = i; k < 8; k++) { 410 t_left -= hsotg->frame_usecs[k]; 411 if (t_left <= 0) { 412 qh->frame_usecs[k] += 413 hsotg->frame_usecs[k] 414 + t_left; 415 hsotg->frame_usecs[k] = -t_left; 416 return i; 417 } else { 418 qh->frame_usecs[k] += 419 hsotg->frame_usecs[k]; 420 hsotg->frame_usecs[k] = 0; 421 } 422 } 423 } 424 /* add the frame time to x time */ 425 xtime += hsotg->frame_usecs[j]; 426 /* we must have a fully available next frame or break */ 427 if (xtime < utime && 428 hsotg->frame_usecs[j] == max_uframe_usecs[j]) 429 continue; 430 } 431 } 432 return -ENOSPC; 433} 434 435STATIC int dwc2_find_uframe(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 436{ 437 int ret; 438 439 if (qh->dev_speed == USB_SPEED_HIGH) { 440 /* if this is a hs transaction we need a full frame */ 441 ret = dwc2_find_single_uframe(hsotg, qh); 442 } else { 443 /* 444 * if this is a fs transaction we may need a sequence 445 * of frames 446 */ 447 ret = dwc2_find_multi_uframe(hsotg, qh); 448 } 449 return ret; 450} 451 452/** 453 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a 454 * host channel is large enough to handle the maximum data transfer in a single 455 * (micro)frame for a periodic transfer 456 * 457 * @hsotg: The HCD state structure for the DWC OTG controller 458 * @qh: QH for a periodic endpoint 459 * 460 * Return: 0 if successful, negative error code otherwise 461 */ 462STATIC int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg, 463 struct dwc2_qh *qh) 464{ 465 u32 max_xfer_size; 466 u32 max_channel_xfer_size; 467 int status = 0; 468 469 max_xfer_size = dwc2_max_packet(qh->maxp) * dwc2_hb_mult(qh->maxp); 470 max_channel_xfer_size = hsotg->core_params->max_transfer_size; 471 472 if (max_xfer_size > max_channel_xfer_size) { 473 dev_err(hsotg->dev, 474 "%s: Periodic xfer length %d > max xfer length for channel %d\n", 475 __func__, max_xfer_size, max_channel_xfer_size); 476 status = -ENOSPC; 477 } 478 479 return status; 480} 481 482/** 483 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in 484 * the periodic schedule 485 * 486 * @hsotg: The HCD state structure for the DWC OTG controller 487 * @qh: QH for the periodic transfer. The QH should already contain the 488 * scheduling information. 489 * 490 * Return: 0 if successful, negative error code otherwise 491 */ 492STATIC int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 493{ 494 int status; 495 496 if (hsotg->core_params->uframe_sched > 0) { 497 int frame = -1; 498 499 status = dwc2_find_uframe(hsotg, qh); 500 if (status == 0) 501 frame = 7; 502 else if (status > 0) 503 frame = status - 1; 504 505 /* Set the new frame up */ 506 if (frame >= 0) { 507 qh->sched_frame &= ~0x7; 508 qh->sched_frame |= (frame & 7); 509 } 510 511 if (status > 0) 512 status = 0; 513 } else { 514 status = dwc2_periodic_channel_available(hsotg); 515 if (status) { 516 dev_info(hsotg->dev, 517 "%s: No host channel available for periodic transfer\n", 518 __func__); 519 return status; 520 } 521 522 status = dwc2_check_periodic_bandwidth(hsotg, qh); 523 } 524 525 if (status) { 526 dev_dbg(hsotg->dev, 527 "%s: Insufficient periodic bandwidth for periodic transfer\n", 528 __func__); 529 return status; 530 } 531 532 status = dwc2_check_max_xfer_size(hsotg, qh); 533 if (status) { 534 dev_dbg(hsotg->dev, 535 "%s: Channel max transfer size too small for periodic transfer\n", 536 __func__); 537 return status; 538 } 539 540 if (hsotg->core_params->dma_desc_enable > 0) 541 /* Don't rely on SOF and start in ready schedule */ 542 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_ready, qh, qh_list_entry); 543 else 544 /* Always start in inactive schedule */ 545 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_inactive, qh, qh_list_entry); 546 qh->linked = 1; 547 548 if (hsotg->core_params->uframe_sched <= 0) 549 /* Reserve periodic channel */ 550 hsotg->periodic_channels++; 551 552 /* Update claimed usecs per (micro)frame */ 553 hsotg->periodic_usecs += qh->usecs; 554 555 return status; 556} 557 558/** 559 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer 560 * from the periodic schedule 561 * 562 * @hsotg: The HCD state structure for the DWC OTG controller 563 * @qh: QH for the periodic transfer 564 */ 565STATIC void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg, 566 struct dwc2_qh *qh) 567{ 568 int i; 569 570 qh->linked = 0; 571 572 /* Update claimed usecs per (micro)frame */ 573 hsotg->periodic_usecs -= qh->usecs; 574 575 if (hsotg->core_params->uframe_sched > 0) { 576 for (i = 0; i < 8; i++) { 577 hsotg->frame_usecs[i] += qh->frame_usecs[i]; 578 qh->frame_usecs[i] = 0; 579 } 580 } else { 581 /* Release periodic channel reservation */ 582 hsotg->periodic_channels--; 583 } 584} 585 586/** 587 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic 588 * schedule if it is not already in the schedule. If the QH is already in 589 * the schedule, no action is taken. 590 * 591 * @hsotg: The HCD state structure for the DWC OTG controller 592 * @qh: The QH to add 593 * 594 * Return: 0 if successful, negative error code otherwise 595 */ 596int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 597{ 598 int status; 599 u32 intr_mask; 600 601 if (dbg_qh(qh)) 602 dev_vdbg(hsotg->dev, "%s()\n", __func__); 603 604 if (qh->linked != 0) { 605 /* QH already in a schedule */ 606 return 0; 607 } 608 609 /* Add the new QH to the appropriate schedule */ 610 if (dwc2_qh_is_non_per(qh)) { 611 /* Always start in inactive schedule */ 612 TAILQ_INSERT_TAIL(&hsotg->non_periodic_sched_inactive, qh, qh_list_entry); 613 qh->linked = 1; 614 return 0; 615 } 616 status = dwc2_schedule_periodic(hsotg, qh); 617 if (status) 618 return status; 619 if (!hsotg->periodic_qh_count) { 620 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 621 intr_mask |= GINTSTS_SOF; 622 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); 623 } 624 hsotg->periodic_qh_count++; 625 626 return 0; 627} 628 629/** 630 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic 631 * schedule. Memory is not freed. 632 * 633 * @hsotg: The HCD state structure 634 * @qh: QH to remove from schedule 635 */ 636void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh) 637{ 638 u32 intr_mask; 639 640 dev_vdbg(hsotg->dev, "%s()\n", __func__); 641 642 if (qh->linked == 0) { 643 /* QH is not in a schedule */ 644 return; 645 } 646 647 if (dwc2_qh_is_non_per(qh)) { 648 if (hsotg->non_periodic_qh_ptr == qh) { 649 hsotg->non_periodic_qh_ptr = 650 TAILQ_NEXT(qh, qh_list_entry); 651 } 652 653 if (qh->channel) { 654 TAILQ_REMOVE(&hsotg->non_periodic_sched_active, qh, qh_list_entry); 655 } else { 656 TAILQ_REMOVE(&hsotg->non_periodic_sched_inactive, qh, qh_list_entry); 657 } 658 qh->linked = 0; 659 660 if (hsotg->non_periodic_qh_ptr == NULL) 661 hsotg->non_periodic_qh_ptr = TAILQ_FIRST(&hsotg->non_periodic_sched_active); 662 return; 663 } 664 dwc2_deschedule_periodic(hsotg, qh); 665 hsotg->periodic_qh_count--; 666 if (!hsotg->periodic_qh_count) { 667 intr_mask = DWC2_READ_4(hsotg, GINTMSK); 668 intr_mask &= ~GINTSTS_SOF; 669 DWC2_WRITE_4(hsotg, GINTMSK, intr_mask); 670 } 671} 672 673/* 674 * Schedule the next continuing periodic split transfer 675 */ 676STATIC void dwc2_sched_periodic_split(struct dwc2_hsotg *hsotg, 677 struct dwc2_qh *qh, u16 frame_number, 678 int sched_next_periodic_split) 679{ 680 u16 incr; 681 682 if (sched_next_periodic_split) { 683 qh->sched_frame = frame_number; 684 incr = dwc2_frame_num_inc(qh->start_split_frame, 1); 685 if (dwc2_frame_num_le(frame_number, incr)) { 686 /* 687 * Allow one frame to elapse after start split 688 * microframe before scheduling complete split, but 689 * DON'T if we are doing the next start split in the 690 * same frame for an ISOC out 691 */ 692 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC || 693 qh->ep_is_in != 0) { 694 qh->sched_frame = 695 dwc2_frame_num_inc(qh->sched_frame, 1); 696 } 697 } 698 } else { 699 qh->sched_frame = dwc2_frame_num_inc(qh->start_split_frame, 700 qh->interval); 701 if (dwc2_frame_num_le(qh->sched_frame, frame_number)) 702 qh->sched_frame = frame_number; 703 qh->sched_frame |= 0x7; 704 qh->start_split_frame = qh->sched_frame; 705 } 706} 707 708/* 709 * Deactivates a QH. For non-periodic QHs, removes the QH from the active 710 * non-periodic schedule. The QH is added to the inactive non-periodic 711 * schedule if any QTDs are still attached to the QH. 712 * 713 * For periodic QHs, the QH is removed from the periodic queued schedule. If 714 * there are any QTDs still attached to the QH, the QH is added to either the 715 * periodic inactive schedule or the periodic ready schedule and its next 716 * scheduled frame is calculated. The QH is placed in the ready schedule if 717 * the scheduled frame has been reached already. Otherwise it's placed in the 718 * inactive schedule. If there are no QTDs attached to the QH, the QH is 719 * completely removed from the periodic schedule. 720 */ 721void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh, 722 int sched_next_periodic_split) 723{ 724 u16 frame_number; 725 726 if (dbg_qh(qh)) 727 dev_vdbg(hsotg->dev, "%s()\n", __func__); 728 729 if (dwc2_qh_is_non_per(qh)) { 730 dwc2_hcd_qh_unlink(hsotg, qh); 731 if (!TAILQ_EMPTY(&qh->qtd_list)) 732 /* Add back to inactive non-periodic schedule */ 733 dwc2_hcd_qh_add(hsotg, qh); 734 return; 735 } 736 737 frame_number = dwc2_hcd_get_frame_number(hsotg); 738 739 if (qh->do_split) { 740 dwc2_sched_periodic_split(hsotg, qh, frame_number, 741 sched_next_periodic_split); 742 } else { 743 qh->sched_frame = dwc2_frame_num_inc(qh->sched_frame, 744 qh->interval); 745 if (dwc2_frame_num_le(qh->sched_frame, frame_number)) 746 qh->sched_frame = frame_number; 747 } 748 749 if (TAILQ_EMPTY(&qh->qtd_list)) { 750 dwc2_hcd_qh_unlink(hsotg, qh); 751 return; 752 } 753 /* 754 * Remove from periodic_sched_queued and move to 755 * appropriate queue 756 */ 757 TAILQ_REMOVE(&hsotg->periodic_sched_queued, qh, qh_list_entry); 758 if ((hsotg->core_params->uframe_sched > 0 && 759 dwc2_frame_num_le(qh->sched_frame, frame_number)) || 760 (hsotg->core_params->uframe_sched <= 0 && 761 qh->sched_frame == frame_number)) { 762 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_ready, qh, qh_list_entry); 763 } else { 764 TAILQ_INSERT_TAIL(&hsotg->periodic_sched_inactive, qh, qh_list_entry); 765 } 766} 767 768/** 769 * dwc2_hcd_qtd_init() - Initializes a QTD structure 770 * 771 * @qtd: The QTD to initialize 772 * @urb: The associated URB 773 */ 774void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb) 775{ 776 qtd->urb = urb; 777 if (dwc2_hcd_get_pipe_type(&urb->pipe_info) == 778 USB_ENDPOINT_XFER_CONTROL) { 779 /* 780 * The only time the QTD data toggle is used is on the data 781 * phase of control transfers. This phase always starts with 782 * DATA1. 783 */ 784 qtd->data_toggle = DWC2_HC_PID_DATA1; 785 qtd->control_phase = DWC2_CONTROL_SETUP; 786 } 787 788 /* Start split */ 789 qtd->complete_split = 0; 790 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL; 791 qtd->isoc_split_offset = 0; 792 qtd->in_process = 0; 793 794 /* Store the qtd ptr in the urb to reference the QTD */ 795 urb->qtd = qtd; 796} 797 798/** 799 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH 800 * 801 * @hsotg: The DWC HCD structure 802 * @qtd: The QTD to add 803 * @qh: Out parameter to return queue head 804 * @mem_flags: Flag to do atomic alloc if needed 805 * 806 * Return: 0 if successful, negative error code otherwise 807 * 808 * Finds the correct QH to place the QTD into. If it does not find a QH, it 809 * will create a new QH. If the QH to which the QTD is added is not currently 810 * scheduled, it is placed into the proper schedule based on its EP type. 811 * 812 * HCD lock must be held and interrupts must be disabled on entry 813 */ 814int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd, 815 struct dwc2_qh **qh, gfp_t mem_flags) 816{ 817 struct dwc2_hcd_urb *urb = qtd->urb; 818 int allocated = 0; 819 int retval; 820 821 /* 822 * Get the QH which holds the QTD-list to insert to. Create QH if it 823 * doesn't exist. 824 */ 825 if (*qh == NULL) { 826 *qh = dwc2_hcd_qh_create(hsotg, urb, mem_flags); 827 if (*qh == NULL) 828 return -ENOMEM; 829 allocated = 1; 830 } 831 832 retval = dwc2_hcd_qh_add(hsotg, *qh); 833 if (retval) 834 goto fail; 835 836 qtd->qh = *qh; 837 TAILQ_INSERT_TAIL(&(*qh)->qtd_list, qtd, qtd_list_entry); 838 839 return 0; 840 841fail: 842 if (allocated) { 843 struct dwc2_qtd *qtd2, *qtd2_tmp; 844 struct dwc2_qh *qh_tmp = *qh; 845 846 *qh = NULL; 847 dwc2_hcd_qh_unlink(hsotg, qh_tmp); 848 849 /* Free each QTD in the QH's QTD list */ 850 TAILQ_FOREACH_SAFE(qtd2, &qh_tmp->qtd_list, qtd_list_entry, qtd2_tmp) 851 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh_tmp); 852 853 dwc2_hcd_qh_free(hsotg, qh_tmp); 854 } 855 856 return retval; 857} 858 859void dwc2_hcd_qtd_unlink_and_free(struct dwc2_hsotg *hsotg, 860 struct dwc2_qtd *qtd, 861 struct dwc2_qh *qh) 862{ 863 struct dwc2_softc *sc = hsotg->hsotg_sc; 864 865 TAILQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); 866 pool_put(&sc->sc_qtdpool, qtd); 867} 868 869#define BITSTUFFTIME(bytecount) ((8 * 7 * (bytecount)) / 6) 870#define HS_HOST_DELAY 5 /* nanoseconds */ 871#define FS_LS_HOST_DELAY 1000 /* nanoseconds */ 872#define HUB_LS_SETUP 333 /* nanoseconds */ 873 874STATIC u32 dwc2_calc_bus_time(struct dwc2_hsotg *hsotg, int speed, int is_in, 875 int is_isoc, int bytecount) 876{ 877 unsigned long retval; 878 879 switch (speed) { 880 case USB_SPEED_HIGH: 881 if (is_isoc) 882 retval = 883 ((38 * 8 * 2083) + 884 (2083 * (3 + BITSTUFFTIME(bytecount)))) / 1000 + 885 HS_HOST_DELAY; 886 else 887 retval = 888 ((55 * 8 * 2083) + 889 (2083 * (3 + BITSTUFFTIME(bytecount)))) / 1000 + 890 HS_HOST_DELAY; 891 break; 892 case USB_SPEED_FULL: 893 if (is_isoc) { 894 retval = 895 (8354 * (31 + 10 * BITSTUFFTIME(bytecount))) / 1000; 896 if (is_in) 897 retval = 7268 + FS_LS_HOST_DELAY + retval; 898 else 899 retval = 6265 + FS_LS_HOST_DELAY + retval; 900 } else { 901 retval = 902 (8354 * (31 + 10 * BITSTUFFTIME(bytecount))) / 1000; 903 retval = 9107 + FS_LS_HOST_DELAY + retval; 904 } 905 break; 906 case USB_SPEED_LOW: 907 if (is_in) { 908 retval = 909 (67667 * (31 + 10 * BITSTUFFTIME(bytecount))) / 910 1000; 911 retval = 912 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + 913 retval; 914 } else { 915 retval = 916 (66700 * (31 + 10 * BITSTUFFTIME(bytecount))) / 917 1000; 918 retval = 919 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + 920 retval; 921 } 922 break; 923 default: 924 dev_warn(hsotg->dev, "Unknown device speed\n"); 925 retval = -1; 926 } 927 928 return NS_TO_US(retval); 929} 930