1/*	$OpenBSD: dwc2_hcdqueue.c,v 1.15 2022/09/09 21:16:54 mglocker Exp $	*/
2/*	$NetBSD: dwc2_hcdqueue.c,v 1.11 2014/09/03 10:00:08 skrll Exp $	*/
3
4/*
5 * hcd_queue.c - DesignWare HS OTG Controller host queuing routines
6 *
7 * Copyright (C) 2004-2013 Synopsys, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions, and the following disclaimer,
14 *    without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 *    to endorse or promote products derived from this software without
20 *    specific prior written permission.
21 *
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") as published by the Free Software
24 * Foundation; either version 2 of the License, or (at your option) any
25 * later version.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40/*
41 * This file contains the functions to manage Queue Heads and Queue
42 * Transfer Descriptors for Host mode
43 */
44#include <sys/param.h>
45#include <sys/systm.h>
46#include <sys/malloc.h>
47#include <sys/pool.h>
48
49#include <machine/bus.h>
50
51#include <dev/usb/usb.h>
52#include <dev/usb/usbdi.h>
53#include <dev/usb/usbdivar.h>
54#include <dev/usb/usb_mem.h>
55
56#include <dev/usb/dwc2/dwc2.h>
57#include <dev/usb/dwc2/dwc2var.h>
58
59#include <dev/usb/dwc2/dwc2_core.h>
60#include <dev/usb/dwc2/dwc2_hcd.h>
61
62#include <dev/usb/dwc2/gcd.h>
63#include <dev/usb/dwc2/bitmap.h>
64
65STATIC void dwc2_wait_timer_fn(void *);
66
67/* Wait this long before releasing periodic reservation */
68#define DWC2_UNRESERVE_DELAY (msecs_to_jiffies(5))
69
70/* If we get a NAK, wait this long before retrying */
71#define DWC2_RETRY_WAIT_DELAY 1	/* msec */
72
73/**
74 * dwc2_periodic_channel_available() - Checks that a channel is available for a
75 * periodic transfer
76 *
77 * @hsotg: The HCD state structure for the DWC OTG controller
78 *
79 * Return: 0 if successful, negative error code otherwise
80 */
81STATIC int dwc2_periodic_channel_available(struct dwc2_hsotg *hsotg)
82{
83	/*
84	 * Currently assuming that there is a dedicated host channel for
85	 * each periodic transaction plus at least one host channel for
86	 * non-periodic transactions
87	 */
88	int status;
89	int num_channels;
90
91	num_channels = hsotg->params.host_channels;
92	if ((hsotg->periodic_channels + hsotg->non_periodic_channels <
93	     num_channels) && (hsotg->periodic_channels < num_channels - 1)) {
94		status = 0;
95	} else {
96		dev_dbg(hsotg->dev,
97			"%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
98			__func__, num_channels,
99			hsotg->periodic_channels, hsotg->non_periodic_channels);
100		status = -ENOSPC;
101	}
102
103	return status;
104}
105
106/**
107 * dwc2_check_periodic_bandwidth() - Checks that there is sufficient bandwidth
108 * for the specified QH in the periodic schedule
109 *
110 * @hsotg: The HCD state structure for the DWC OTG controller
111 * @qh:    QH containing periodic bandwidth required
112 *
113 * Return: 0 if successful, negative error code otherwise
114 *
115 * For simplicity, this calculation assumes that all the transfers in the
116 * periodic schedule may occur in the same (micro)frame
117 */
118STATIC int dwc2_check_periodic_bandwidth(struct dwc2_hsotg *hsotg,
119					 struct dwc2_qh *qh)
120{
121	int status;
122	s16 max_claimed_usecs;
123
124	status = 0;
125
126	if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
127		/*
128		 * High speed mode
129		 * Max periodic usecs is 80% x 125 usec = 100 usec
130		 */
131		max_claimed_usecs = 100 - qh->host_us;
132	} else {
133		/*
134		 * Full speed mode
135		 * Max periodic usecs is 90% x 1000 usec = 900 usec
136		 */
137		max_claimed_usecs = 900 - qh->host_us;
138	}
139
140	if (hsotg->periodic_usecs > max_claimed_usecs) {
141		dev_err(hsotg->dev,
142			"%s: already claimed usecs %d, required usecs %d\n",
143			__func__, hsotg->periodic_usecs, qh->host_us);
144		status = -ENOSPC;
145	}
146
147	return status;
148}
149
150/**
151 * pmap_schedule() - Schedule time in a periodic bitmap (pmap).
152 *
153 * @map:             The bitmap representing the schedule; will be updated
154 *                   upon success.
155 * @bits_per_period: The schedule represents several periods.  This is how many
156 *                   bits are in each period.  It's assumed that the beginning
157 *                   of the schedule will repeat after its end.
158 * @periods_in_map:  The number of periods in the schedule.
159 * @num_bits:        The number of bits we need per period we want to reserve
160 *                   in this function call.
161 * @interval:        How often we need to be scheduled for the reservation this
162 *                   time.  1 means every period.  2 means every other period.
163 *                   ...you get the picture?
164 * @start:           The bit number to start at.  Normally 0.  Must be within
165 *                   the interval or we return failure right away.
166 * @only_one_period: Normally we'll allow picking a start anywhere within the
167 *                   first interval, since we can still make all repetition
168 *                   requirements by doing that.  However, if you pass true
169 *                   here then we'll return failure if we can't fit within
170 *                   the period that "start" is in.
171 *
172 * The idea here is that we want to schedule time for repeating events that all
173 * want the same resource.  The resource is divided into fixed-sized periods
174 * and the events want to repeat every "interval" periods.  The schedule
175 * granularity is one bit.
176 *
177 * To keep things "simple", we'll represent our schedule with a bitmap that
178 * contains a fixed number of periods.  This gets rid of a lot of complexity
179 * but does mean that we need to handle things specially (and non-ideally) if
180 * the number of the periods in the schedule doesn't match well with the
181 * intervals that we're trying to schedule.
182 *
183 * Here's an explanation of the scheme we'll implement, assuming 8 periods.
184 * - If interval is 1, we need to take up space in each of the 8
185 *   periods we're scheduling.  Easy.
186 * - If interval is 2, we need to take up space in half of the
187 *   periods.  Again, easy.
188 * - If interval is 3, we actually need to fall back to interval 1.
189 *   Why?  Because we might need time in any period.  AKA for the
190 *   first 8 periods, we'll be in slot 0, 3, 6.  Then we'll be
191 *   in slot 1, 4, 7.  Then we'll be in 2, 5.  Then we'll be back to
192 *   0, 3, and 6.  Since we could be in any frame we need to reserve
193 *   for all of them.  Sucks, but that's what you gotta do.  Note that
194 *   if we were instead scheduling 8 * 3 = 24 we'd do much better, but
195 *   then we need more memory and time to do scheduling.
196 * - If interval is 4, easy.
197 * - If interval is 5, we again need interval 1.  The schedule will be
198 *   0, 5, 2, 7, 4, 1, 6, 3, 0
199 * - If interval is 6, we need interval 2.  0, 6, 4, 2.
200 * - If interval is 7, we need interval 1.
201 * - If interval is 8, we need interval 8.
202 *
203 * If you do the math, you'll see that we need to pretend that interval is
204 * equal to the greatest_common_divisor(interval, periods_in_map).
205 *
206 * Note that at the moment this function tends to front-pack the schedule.
207 * In some cases that's really non-ideal (it's hard to schedule things that
208 * need to repeat every period).  In other cases it's perfect (you can easily
209 * schedule bigger, less often repeating things).
210 *
211 * Here's the algorithm in action (8 periods, 5 bits per period):
212 *  |**   |     |**   |     |**   |     |**   |     |   OK 2 bits, intv 2 at 0
213 *  |*****|  ***|*****|  ***|*****|  ***|*****|  ***|   OK 3 bits, intv 3 at 2
214 *  |*****|* ***|*****|  ***|*****|* ***|*****|  ***|   OK 1 bits, intv 4 at 5
215 *  |**   |*    |**   |     |**   |*    |**   |     | Remv 3 bits, intv 3 at 2
216 *  |***  |*    |***  |     |***  |*    |***  |     |   OK 1 bits, intv 6 at 2
217 *  |**** |*  * |**** |   * |**** |*  * |**** |   * |   OK 1 bits, intv 1 at 3
218 *  |**** |**** |**** | *** |**** |**** |**** | *** |   OK 2 bits, intv 2 at 6
219 *  |*****|*****|*****| ****|*****|*****|*****| ****|   OK 1 bits, intv 1 at 4
220 *  |*****|*****|*****| ****|*****|*****|*****| ****| FAIL 1 bits, intv 1
221 *  |  ***|*****|  ***| ****|  ***|*****|  ***| ****| Remv 2 bits, intv 2 at 0
222 *  |  ***| ****|  ***| ****|  ***| ****|  ***| ****| Remv 1 bits, intv 4 at 5
223 *  |   **| ****|   **| ****|   **| ****|   **| ****| Remv 1 bits, intv 6 at 2
224 *  |    *| ** *|    *| ** *|    *| ** *|    *| ** *| Remv 1 bits, intv 1 at 3
225 *  |    *|    *|    *|    *|    *|    *|    *|    *| Remv 2 bits, intv 2 at 6
226 *  |     |     |     |     |     |     |     |     | Remv 1 bits, intv 1 at 4
227 *  |**   |     |**   |     |**   |     |**   |     |   OK 2 bits, intv 2 at 0
228 *  |***  |     |**   |     |***  |     |**   |     |   OK 1 bits, intv 4 at 2
229 *  |*****|     |** **|     |*****|     |** **|     |   OK 2 bits, intv 2 at 3
230 *  |*****|*    |** **|     |*****|*    |** **|     |   OK 1 bits, intv 4 at 5
231 *  |*****|***  |** **| **  |*****|***  |** **| **  |   OK 2 bits, intv 2 at 6
232 *  |*****|*****|** **| ****|*****|*****|** **| ****|   OK 2 bits, intv 2 at 8
233 *  |*****|*****|*****| ****|*****|*****|*****| ****|   OK 1 bits, intv 4 at 12
234 *
235 * This function is pretty generic and could be easily abstracted if anything
236 * needed similar scheduling.
237 *
238 * Returns either -ENOSPC or a >= 0 start bit which should be passed to the
239 * unschedule routine.  The map bitmap will be updated on a non-error result.
240 */
241static int pmap_schedule(unsigned long *map, int bits_per_period,
242			 int periods_in_map, int num_bits,
243			 int interval, int start, bool only_one_period)
244{
245	int interval_bits;
246	int to_reserve;
247	int first_end;
248	int i;
249
250	if (num_bits > bits_per_period)
251		return -ENOSPC;
252
253	/* Adjust interval as per description */
254	interval = gcd(interval, periods_in_map);
255
256	interval_bits = bits_per_period * interval;
257	to_reserve = periods_in_map / interval;
258
259	/* If start has gotten us past interval then we can't schedule */
260	if (start >= interval_bits)
261		return -ENOSPC;
262
263	if (only_one_period)
264		/* Must fit within same period as start; end at begin of next */
265		first_end = (start / bits_per_period + 1) * bits_per_period;
266	else
267		/* Can fit anywhere in the first interval */
268		first_end = interval_bits;
269
270	/*
271	 * We'll try to pick the first repetition, then see if that time
272	 * is free for each of the subsequent repetitions.  If it's not
273	 * we'll adjust the start time for the next search of the first
274	 * repetition.
275	 */
276	while (start + num_bits <= first_end) {
277		int end;
278
279		/* Need to stay within this period */
280		end = (start / bits_per_period + 1) * bits_per_period;
281
282		/* Look for num_bits us in this microframe starting at start */
283		start = bitmap_find_next_zero_area(map, end, start, num_bits,
284						   0);
285
286		/*
287		 * We should get start >= end if we fail.  We might be
288		 * able to check the next microframe depending on the
289		 * interval, so continue on (start already updated).
290		 */
291		if (start >= end) {
292			start = end;
293			continue;
294		}
295
296		/* At this point we have a valid point for first one */
297		for (i = 1; i < to_reserve; i++) {
298			int ith_start = start + interval_bits * i;
299			int ith_end = end + interval_bits * i;
300			int ret;
301
302			/* Use this as a dumb "check if bits are 0" */
303			ret = bitmap_find_next_zero_area(
304				map, ith_start + num_bits, ith_start, num_bits,
305				0);
306
307			/* We got the right place, continue checking */
308			if (ret == ith_start)
309				continue;
310
311			/* Move start up for next time and exit for loop */
312			ith_start = bitmap_find_next_zero_area(
313				map, ith_end, ith_start, num_bits, 0);
314			if (ith_start >= ith_end)
315				/* Need a while new period next time */
316				start = end;
317			else
318				start = ith_start - interval_bits * i;
319			break;
320		}
321
322		/* If didn't exit the for loop with a break, we have success */
323		if (i == to_reserve)
324			break;
325	}
326
327	if (start + num_bits > first_end)
328		return -ENOSPC;
329
330	for (i = 0; i < to_reserve; i++) {
331		int ith_start = start + interval_bits * i;
332
333		bitmap_set(map, ith_start, num_bits);
334	}
335
336	return start;
337}
338
339/**
340 * pmap_unschedule() - Undo work done by pmap_schedule()
341 *
342 * @map:             See pmap_schedule().
343 * @bits_per_period: See pmap_schedule().
344 * @periods_in_map:  See pmap_schedule().
345 * @num_bits:        The number of bits that was passed to schedule.
346 * @interval:        The interval that was passed to schedule.
347 * @start:           The return value from pmap_schedule().
348 */
349static void pmap_unschedule(unsigned long *map, int bits_per_period,
350			    int periods_in_map, int num_bits,
351			    int interval, int start)
352{
353	int interval_bits;
354	int to_release;
355	int i;
356
357	/* Adjust interval as per description in pmap_schedule() */
358	interval = gcd(interval, periods_in_map);
359
360	interval_bits = bits_per_period * interval;
361	to_release = periods_in_map / interval;
362
363	for (i = 0; i < to_release; i++) {
364		int ith_start = start + interval_bits * i;
365
366		bitmap_clear(map, ith_start, num_bits);
367	}
368}
369
370/**
371 * dwc2_get_ls_map() - Get the map used for the given qh
372 *
373 * @hsotg: The HCD state structure for the DWC OTG controller.
374 * @qh:    QH for the periodic transfer.
375 *
376 * We'll always get the periodic map out of our TT.  Note that even if we're
377 * running the host straight in low speed / full speed mode it appears as if
378 * a TT is allocated for us, so we'll use it.  If that ever changes we can
379 * add logic here to get a map out of "hsotg" if !qh->do_split.
380 *
381 * Returns: the map or NULL if a map couldn't be found.
382 */
383static unsigned long *dwc2_get_ls_map(struct dwc2_hsotg *hsotg,
384				      struct dwc2_qh *qh)
385{
386	unsigned long *map;
387
388	/* Don't expect to be missing a TT and be doing low speed scheduling */
389	if (WARN_ON(!qh->dwc_tt))
390		return NULL;
391
392	/* Get the map and adjust if this is a multi_tt hub */
393	map = qh->dwc_tt->periodic_bitmaps;
394	if (qh->dwc_tt->usb_tt->hub->multi)
395		map += DWC2_ELEMENTS_PER_LS_BITMAP * (qh->ttport - 1);
396
397	return map;
398}
399
400#ifdef DWC2_PRINT_SCHEDULE
401/*
402 * cat_printf() - A printf() + strcat() helper
403 *
404 * This is useful for concatenating a bunch of strings where each string is
405 * constructed using printf.
406 *
407 * @buf:   The destination buffer; will be updated to point after the printed
408 *         data.
409 * @size:  The number of bytes in the buffer (includes space for '\0').
410 * @fmt:   The format for printf.
411 * @...:   The args for printf.
412 */
413static __printf(3, 4)
414void cat_printf(char **buf, size_t *size, const char *fmt, ...)
415{
416	va_list args;
417	int i;
418
419	if (*size == 0)
420		return;
421
422	va_start(args, fmt);
423	i = vsnprintf(*buf, *size, fmt, args);
424	va_end(args);
425
426	if (i >= *size) {
427		(*buf)[*size - 1] = '\0';
428		*buf += *size;
429		*size = 0;
430	} else {
431		*buf += i;
432		*size -= i;
433	}
434}
435
436/*
437 * pmap_print() - Print the given periodic map
438 *
439 * Will attempt to print out the periodic schedule.
440 *
441 * @map:             See pmap_schedule().
442 * @bits_per_period: See pmap_schedule().
443 * @periods_in_map:  See pmap_schedule().
444 * @period_name:     The name of 1 period, like "uFrame"
445 * @units:           The name of the units, like "us".
446 * @print_fn:        The function to call for printing.
447 * @print_data:      Opaque data to pass to the print function.
448 */
449static void pmap_print(unsigned long *map, int bits_per_period,
450		       int periods_in_map, const char *period_name,
451		       const char *units,
452		       void (*print_fn)(const char *str, void *data),
453		       void *print_data)
454{
455	int period;
456
457	for (period = 0; period < periods_in_map; period++) {
458		char tmp[64];
459		char *buf = tmp;
460		size_t buf_size = sizeof(tmp);
461		int period_start = period * bits_per_period;
462		int period_end = period_start + bits_per_period;
463		int start = 0;
464		int count = 0;
465		bool printed = false;
466		int i;
467
468		for (i = period_start; i < period_end + 1; i++) {
469			/* Handle case when ith bit is set */
470			if (i < period_end &&
471			    bitmap_find_next_zero_area(map, i + 1,
472						       i, 1, 0) != i) {
473				if (count == 0)
474					start = i - period_start;
475				count++;
476				continue;
477			}
478
479			/* ith bit isn't set; don't care if count == 0 */
480			if (count == 0)
481				continue;
482
483			if (!printed)
484				cat_printf(&buf, &buf_size, "%s %d: ",
485					   period_name, period);
486			else
487				cat_printf(&buf, &buf_size, ", ");
488			printed = true;
489
490			cat_printf(&buf, &buf_size, "%d %s -%3d %s", start,
491				   units, start + count - 1, units);
492			count = 0;
493		}
494
495		if (printed)
496			print_fn(tmp, print_data);
497	}
498}
499
500struct dwc2_qh_print_data {
501	struct dwc2_hsotg *hsotg;
502	struct dwc2_qh *qh;
503};
504
505/**
506 * dwc2_qh_print() - Helper function for dwc2_qh_schedule_print()
507 *
508 * @str:  The string to print
509 * @data: A pointer to a struct dwc2_qh_print_data
510 */
511static void dwc2_qh_print(const char *str, void *data)
512{
513	struct dwc2_qh_print_data *print_data = data;
514
515	dwc2_sch_dbg(print_data->hsotg, "QH=%p ...%s\n", print_data->qh, str);
516}
517
518/**
519 * dwc2_qh_schedule_print() - Print the periodic schedule
520 *
521 * @hsotg: The HCD state structure for the DWC OTG controller.
522 * @qh:    QH to print.
523 */
524static void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
525				   struct dwc2_qh *qh)
526{
527	struct dwc2_qh_print_data print_data = { hsotg, qh };
528	int i;
529
530	/*
531	 * The printing functions are quite slow and inefficient.
532	 * If we don't have tracing turned on, don't run unless the special
533	 * define is turned on.
534	 */
535
536	if (qh->schedule_low_speed) {
537		unsigned long *map = dwc2_get_ls_map(hsotg, qh);
538
539		dwc2_sch_dbg(hsotg, "QH=%p LS/FS trans: %d=>%d us @ %d us",
540			     qh, qh->device_us,
541			     DWC2_ROUND_US_TO_SLICE(qh->device_us),
542			     DWC2_US_PER_SLICE * qh->ls_start_schedule_slice);
543
544		if (map) {
545			dwc2_sch_dbg(hsotg,
546				     "QH=%p Whole low/full speed map %p now:\n",
547				     qh, map);
548			pmap_print(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
549				   DWC2_LS_SCHEDULE_FRAMES, "Frame ", "slices",
550				   dwc2_qh_print, &print_data);
551		}
552	}
553
554	for (i = 0; i < qh->num_hs_transfers; i++) {
555		struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + i;
556		int uframe = trans_time->start_schedule_us /
557			     DWC2_HS_PERIODIC_US_PER_UFRAME;
558		int rel_us = trans_time->start_schedule_us %
559			     DWC2_HS_PERIODIC_US_PER_UFRAME;
560
561		dwc2_sch_dbg(hsotg,
562			     "QH=%p HS trans #%d: %d us @ uFrame %d + %d us\n",
563			     qh, i, trans_time->duration_us, uframe, rel_us);
564	}
565	if (qh->num_hs_transfers) {
566		dwc2_sch_dbg(hsotg, "QH=%p Whole high speed map now:\n", qh);
567		pmap_print(hsotg->hs_periodic_bitmap,
568			   DWC2_HS_PERIODIC_US_PER_UFRAME,
569			   DWC2_HS_SCHEDULE_UFRAMES, "uFrame", "us",
570			   dwc2_qh_print, &print_data);
571	}
572}
573#else
574static inline void dwc2_qh_schedule_print(struct dwc2_hsotg *hsotg,
575					  struct dwc2_qh *qh) {};
576#endif
577
578/**
579 * dwc2_ls_pmap_schedule() - Schedule a low speed QH
580 *
581 * @hsotg:        The HCD state structure for the DWC OTG controller.
582 * @qh:           QH for the periodic transfer.
583 * @search_slice: We'll start trying to schedule at the passed slice.
584 *                Remember that slices are the units of the low speed
585 *                schedule (think 25us or so).
586 *
587 * Wraps pmap_schedule() with the right parameters for low speed scheduling.
588 *
589 * Normally we schedule low speed devices on the map associated with the TT.
590 *
591 * Returns: 0 for success or an error code.
592 */
593static int dwc2_ls_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
594				 int search_slice)
595{
596	int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
597	unsigned long *map = dwc2_get_ls_map(hsotg, qh);
598	int slice;
599
600	if (!map)
601		return -EINVAL;
602
603	/*
604	 * Schedule on the proper low speed map with our low speed scheduling
605	 * parameters.  Note that we use the "device_interval" here since
606	 * we want the low speed interval and the only way we'd be in this
607	 * function is if the device is low speed.
608	 *
609	 * If we happen to be doing low speed and high speed scheduling for the
610	 * same transaction (AKA we have a split) we always do low speed first.
611	 * That means we can always pass "false" for only_one_period (that
612	 * parameters is only useful when we're trying to get one schedule to
613	 * match what we already planned in the other schedule).
614	 */
615	slice = pmap_schedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
616			      DWC2_LS_SCHEDULE_FRAMES, slices,
617			      qh->device_interval, search_slice, false);
618
619	if (slice < 0)
620		return slice;
621
622	qh->ls_start_schedule_slice = slice;
623	return 0;
624}
625
626/**
627 * dwc2_ls_pmap_unschedule() - Undo work done by dwc2_ls_pmap_schedule()
628 *
629 * @hsotg:       The HCD state structure for the DWC OTG controller.
630 * @qh:          QH for the periodic transfer.
631 */
632static void dwc2_ls_pmap_unschedule(struct dwc2_hsotg *hsotg,
633				    struct dwc2_qh *qh)
634{
635	int slices = DIV_ROUND_UP(qh->device_us, DWC2_US_PER_SLICE);
636	unsigned long *map = dwc2_get_ls_map(hsotg, qh);
637
638	/* Schedule should have failed, so no worries about no error code */
639	if (!map)
640		return;
641
642	pmap_unschedule(map, DWC2_LS_PERIODIC_SLICES_PER_FRAME,
643			DWC2_LS_SCHEDULE_FRAMES, slices, qh->device_interval,
644			qh->ls_start_schedule_slice);
645}
646
647/**
648 * dwc2_hs_pmap_schedule - Schedule in the main high speed schedule
649 *
650 * This will schedule something on the main dwc2 schedule.
651 *
652 * We'll start looking in qh->hs_transfers[index].start_schedule_us.  We'll
653 * update this with the result upon success.  We also use the duration from
654 * the same structure.
655 *
656 * @hsotg:           The HCD state structure for the DWC OTG controller.
657 * @qh:              QH for the periodic transfer.
658 * @only_one_period: If true we will limit ourselves to just looking at
659 *                   one period (aka one 100us chunk).  This is used if we have
660 *                   already scheduled something on the low speed schedule and
661 *                   need to find something that matches on the high speed one.
662 * @index:           The index into qh->hs_transfers that we're working with.
663 *
664 * Returns: 0 for success or an error code.  Upon success the
665 *          dwc2_hs_transfer_time specified by "index" will be updated.
666 */
667static int dwc2_hs_pmap_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
668				 bool only_one_period, int index)
669{
670	struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
671	int us;
672
673	us = pmap_schedule(hsotg->hs_periodic_bitmap,
674			   DWC2_HS_PERIODIC_US_PER_UFRAME,
675			   DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
676			   qh->host_interval, trans_time->start_schedule_us,
677			   only_one_period);
678
679	if (us < 0)
680		return us;
681
682	trans_time->start_schedule_us = us;
683	return 0;
684}
685
686/**
687 * dwc2_hs_pmap_unschedule() - Undo work done by dwc2_hs_pmap_schedule()
688 *
689 * @hsotg:       The HCD state structure for the DWC OTG controller.
690 * @qh:          QH for the periodic transfer.
691 * @index:       Transfer index
692 */
693static void dwc2_hs_pmap_unschedule(struct dwc2_hsotg *hsotg,
694				    struct dwc2_qh *qh, int index)
695{
696	struct dwc2_hs_transfer_time *trans_time = qh->hs_transfers + index;
697
698	pmap_unschedule(hsotg->hs_periodic_bitmap,
699			DWC2_HS_PERIODIC_US_PER_UFRAME,
700			DWC2_HS_SCHEDULE_UFRAMES, trans_time->duration_us,
701			qh->host_interval, trans_time->start_schedule_us);
702}
703
704/**
705 * dwc2_uframe_schedule_split - Schedule a QH for a periodic split xfer.
706 *
707 * This is the most complicated thing in USB.  We have to find matching time
708 * in both the global high speed schedule for the port and the low speed
709 * schedule for the TT associated with the given device.
710 *
711 * Being here means that the host must be running in high speed mode and the
712 * device is in low or full speed mode (and behind a hub).
713 *
714 * @hsotg:       The HCD state structure for the DWC OTG controller.
715 * @qh:          QH for the periodic transfer.
716 */
717static int dwc2_uframe_schedule_split(struct dwc2_hsotg *hsotg,
718				      struct dwc2_qh *qh)
719{
720	int bytecount = qh->maxp_mult * qh->maxp;
721	int ls_search_slice;
722	int err = 0;
723	int host_interval_in_sched;
724
725	/*
726	 * The interval (how often to repeat) in the actual host schedule.
727	 * See pmap_schedule() for gcd() explanation.
728	 */
729	host_interval_in_sched = gcd(qh->host_interval,
730				     DWC2_HS_SCHEDULE_UFRAMES);
731
732	/*
733	 * We always try to find space in the low speed schedule first, then
734	 * try to find high speed time that matches.  If we don't, we'll bump
735	 * up the place we start searching in the low speed schedule and try
736	 * again.  To start we'll look right at the beginning of the low speed
737	 * schedule.
738	 *
739	 * Note that this will tend to front-load the high speed schedule.
740	 * We may eventually want to try to avoid this by either considering
741	 * both schedules together or doing some sort of round robin.
742	 */
743	ls_search_slice = 0;
744
745	while (ls_search_slice < DWC2_LS_SCHEDULE_SLICES) {
746		int start_s_uframe;
747		int ssplit_s_uframe;
748		int second_s_uframe;
749		int rel_uframe;
750		int first_count;
751		int middle_count;
752		int end_count;
753		int first_data_bytes;
754		int other_data_bytes;
755		int i;
756
757		if (qh->schedule_low_speed) {
758			err = dwc2_ls_pmap_schedule(hsotg, qh, ls_search_slice);
759
760			/*
761			 * If we got an error here there's no other magic we
762			 * can do, so bail.  All the looping above is only
763			 * helpful to redo things if we got a low speed slot
764			 * and then couldn't find a matching high speed slot.
765			 */
766			if (err)
767				return err;
768		} else {
769			/* Must be missing the tt structure?  Why? */
770			WARN_ON_ONCE(1);
771		}
772
773		/*
774		 * This will give us a number 0 - 7 if
775		 * DWC2_LS_SCHEDULE_FRAMES == 1, or 0 - 15 if == 2, or ...
776		 */
777		start_s_uframe = qh->ls_start_schedule_slice /
778				 DWC2_SLICES_PER_UFRAME;
779
780		/* Get a number that's always 0 - 7 */
781		rel_uframe = (start_s_uframe % 8);
782
783		/*
784		 * If we were going to start in uframe 7 then we would need to
785		 * issue a start split in uframe 6, which spec says is not OK.
786		 * Move on to the next full frame (assuming there is one).
787		 *
788		 * See 11.18.4 Host Split Transaction Scheduling Requirements
789		 * bullet 1.
790		 */
791		if (rel_uframe == 7) {
792			if (qh->schedule_low_speed)
793				dwc2_ls_pmap_unschedule(hsotg, qh);
794			ls_search_slice =
795				(qh->ls_start_schedule_slice /
796				 DWC2_LS_PERIODIC_SLICES_PER_FRAME + 1) *
797				DWC2_LS_PERIODIC_SLICES_PER_FRAME;
798			continue;
799		}
800
801		/*
802		 * For ISOC in:
803		 * - start split            (frame -1)
804		 * - complete split w/ data (frame +1)
805		 * - complete split w/ data (frame +2)
806		 * - ...
807		 * - complete split w/ data (frame +num_data_packets)
808		 * - complete split w/ data (frame +num_data_packets+1)
809		 * - complete split w/ data (frame +num_data_packets+2, max 8)
810		 *   ...though if frame was "0" then max is 7...
811		 *
812		 * For ISOC out we might need to do:
813		 * - start split w/ data    (frame -1)
814		 * - start split w/ data    (frame +0)
815		 * - ...
816		 * - start split w/ data    (frame +num_data_packets-2)
817		 *
818		 * For INTERRUPT in we might need to do:
819		 * - start split            (frame -1)
820		 * - complete split w/ data (frame +1)
821		 * - complete split w/ data (frame +2)
822		 * - complete split w/ data (frame +3, max 8)
823		 *
824		 * For INTERRUPT out we might need to do:
825		 * - start split w/ data    (frame -1)
826		 * - complete split         (frame +1)
827		 * - complete split         (frame +2)
828		 * - complete split         (frame +3, max 8)
829		 *
830		 * Start adjusting!
831		 */
832		ssplit_s_uframe = (start_s_uframe +
833				   host_interval_in_sched - 1) %
834				  host_interval_in_sched;
835		if (qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in)
836			second_s_uframe = start_s_uframe;
837		else
838			second_s_uframe = start_s_uframe + 1;
839
840		/* First data transfer might not be all 188 bytes. */
841		first_data_bytes = 188 -
842			DIV_ROUND_UP(188 * (qh->ls_start_schedule_slice %
843					    DWC2_SLICES_PER_UFRAME),
844				     DWC2_SLICES_PER_UFRAME);
845		if (first_data_bytes > bytecount)
846			first_data_bytes = bytecount;
847		other_data_bytes = bytecount - first_data_bytes;
848
849		/*
850		 * For now, skip OUT xfers where first xfer is partial
851		 *
852		 * Main dwc2 code assumes:
853		 * - INT transfers never get split in two.
854		 * - ISOC transfers can always transfer 188 bytes the first
855		 *   time.
856		 *
857		 * Until that code is fixed, try again if the first transfer
858		 * couldn't transfer everything.
859		 *
860		 * This code can be removed if/when the rest of dwc2 handles
861		 * the above cases.  Until it's fixed we just won't be able
862		 * to schedule quite as tightly.
863		 */
864		if (!qh->ep_is_in &&
865		    (first_data_bytes != min_t(int, 188, bytecount))) {
866			dwc2_sch_dbg(hsotg,
867				     "QH=%p avoiding broken 1st xfer (%d, %d)\n",
868				     qh, first_data_bytes, bytecount);
869			if (qh->schedule_low_speed)
870				dwc2_ls_pmap_unschedule(hsotg, qh);
871			ls_search_slice = (start_s_uframe + 1) *
872				DWC2_SLICES_PER_UFRAME;
873			continue;
874		}
875
876		/* Start by assuming transfers for the bytes */
877		qh->num_hs_transfers = 1 + DIV_ROUND_UP(other_data_bytes, 188);
878
879		/*
880		 * Everything except ISOC OUT has extra transfers.  Rules are
881		 * complicated.  See 11.18.4 Host Split Transaction Scheduling
882		 * Requirements bullet 3.
883		 */
884		if (qh->ep_type == USB_ENDPOINT_XFER_INT) {
885			if (rel_uframe == 6)
886				qh->num_hs_transfers += 2;
887			else
888				qh->num_hs_transfers += 3;
889
890			if (qh->ep_is_in) {
891				/*
892				 * First is start split, middle/end is data.
893				 * Allocate full data bytes for all data.
894				 */
895				first_count = 4;
896				middle_count = bytecount;
897				end_count = bytecount;
898			} else {
899				/*
900				 * First is data, middle/end is complete.
901				 * First transfer and second can have data.
902				 * Rest should just have complete split.
903				 */
904				first_count = first_data_bytes;
905				middle_count = max_t(int, 4, other_data_bytes);
906				end_count = 4;
907			}
908		} else {
909			if (qh->ep_is_in) {
910				int last;
911
912				/* Account for the start split */
913				qh->num_hs_transfers++;
914
915				/* Calculate "L" value from spec */
916				last = rel_uframe + qh->num_hs_transfers + 1;
917
918				/* Start with basic case */
919				if (last <= 6)
920					qh->num_hs_transfers += 2;
921				else
922					qh->num_hs_transfers += 1;
923
924				/* Adjust downwards */
925				if (last >= 6 && rel_uframe == 0)
926					qh->num_hs_transfers--;
927
928				/* 1st = start; rest can contain data */
929				first_count = 4;
930				middle_count = min_t(int, 188, bytecount);
931				end_count = middle_count;
932			} else {
933				/* All contain data, last might be smaller */
934				first_count = first_data_bytes;
935				middle_count = min_t(int, 188,
936						     other_data_bytes);
937				end_count = other_data_bytes % 188;
938			}
939		}
940
941		/* Assign durations per uFrame */
942		qh->hs_transfers[0].duration_us = HS_USECS_ISO(first_count);
943		for (i = 1; i < qh->num_hs_transfers - 1; i++)
944			qh->hs_transfers[i].duration_us =
945				HS_USECS_ISO(middle_count);
946		if (qh->num_hs_transfers > 1)
947			qh->hs_transfers[qh->num_hs_transfers - 1].duration_us =
948				HS_USECS_ISO(end_count);
949
950		/*
951		 * Assign start us.  The call below to dwc2_hs_pmap_schedule()
952		 * will start with these numbers but may adjust within the same
953		 * microframe.
954		 */
955		qh->hs_transfers[0].start_schedule_us =
956			ssplit_s_uframe * DWC2_HS_PERIODIC_US_PER_UFRAME;
957		for (i = 1; i < qh->num_hs_transfers; i++)
958			qh->hs_transfers[i].start_schedule_us =
959				((second_s_uframe + i - 1) %
960				 DWC2_HS_SCHEDULE_UFRAMES) *
961				DWC2_HS_PERIODIC_US_PER_UFRAME;
962
963		/* Try to schedule with filled in hs_transfers above */
964		for (i = 0; i < qh->num_hs_transfers; i++) {
965			err = dwc2_hs_pmap_schedule(hsotg, qh, true, i);
966			if (err)
967				break;
968		}
969
970		/* If we scheduled all w/out breaking out then we're all good */
971		if (i == qh->num_hs_transfers)
972			break;
973
974		for (; i >= 0; i--)
975			dwc2_hs_pmap_unschedule(hsotg, qh, i);
976
977		if (qh->schedule_low_speed)
978			dwc2_ls_pmap_unschedule(hsotg, qh);
979
980		/* Try again starting in the next microframe */
981		ls_search_slice = (start_s_uframe + 1) * DWC2_SLICES_PER_UFRAME;
982	}
983
984	if (ls_search_slice >= DWC2_LS_SCHEDULE_SLICES)
985		return -ENOSPC;
986
987	return 0;
988}
989
990/**
991 * dwc2_uframe_schedule_hs - Schedule a QH for a periodic high speed xfer.
992 *
993 * Basically this just wraps dwc2_hs_pmap_schedule() to provide a clean
994 * interface.
995 *
996 * @hsotg:       The HCD state structure for the DWC OTG controller.
997 * @qh:          QH for the periodic transfer.
998 */
999static int dwc2_uframe_schedule_hs(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1000{
1001	/* In non-split host and device time are the same */
1002	WARN_ON(qh->host_us != qh->device_us);
1003	WARN_ON(qh->host_interval != qh->device_interval);
1004	WARN_ON(qh->num_hs_transfers != 1);
1005
1006	/* We'll have one transfer; init start to 0 before calling scheduler */
1007	qh->hs_transfers[0].start_schedule_us = 0;
1008	qh->hs_transfers[0].duration_us = qh->host_us;
1009
1010	return dwc2_hs_pmap_schedule(hsotg, qh, false, 0);
1011}
1012
1013/**
1014 * dwc2_uframe_schedule_ls - Schedule a QH for a periodic low/full speed xfer.
1015 *
1016 * Basically this just wraps dwc2_ls_pmap_schedule() to provide a clean
1017 * interface.
1018 *
1019 * @hsotg:       The HCD state structure for the DWC OTG controller.
1020 * @qh:          QH for the periodic transfer.
1021 */
1022static int dwc2_uframe_schedule_ls(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1023{
1024	/* In non-split host and device time are the same */
1025	WARN_ON(qh->host_us != qh->device_us);
1026	WARN_ON(qh->host_interval != qh->device_interval);
1027	WARN_ON(!qh->schedule_low_speed);
1028
1029	/* Run on the main low speed schedule (no split = no hub = no TT) */
1030	return dwc2_ls_pmap_schedule(hsotg, qh, 0);
1031}
1032
1033/**
1034 * dwc2_uframe_schedule - Schedule a QH for a periodic xfer.
1035 *
1036 * Calls one of the 3 sub-function depending on what type of transfer this QH
1037 * is for.  Also adds some printing.
1038 *
1039 * @hsotg:       The HCD state structure for the DWC OTG controller.
1040 * @qh:          QH for the periodic transfer.
1041 */
1042static int dwc2_uframe_schedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1043{
1044	int ret;
1045
1046	if (qh->dev_speed == USB_SPEED_HIGH)
1047		ret = dwc2_uframe_schedule_hs(hsotg, qh);
1048	else if (!qh->do_split)
1049		ret = dwc2_uframe_schedule_ls(hsotg, qh);
1050	else
1051		ret = dwc2_uframe_schedule_split(hsotg, qh);
1052
1053	if (ret)
1054		dwc2_sch_dbg(hsotg, "QH=%p Failed to schedule %d\n", qh, ret);
1055	else
1056		dwc2_qh_schedule_print(hsotg, qh);
1057
1058	return ret;
1059}
1060
1061/**
1062 * dwc2_uframe_unschedule - Undoes dwc2_uframe_schedule().
1063 *
1064 * @hsotg:       The HCD state structure for the DWC OTG controller.
1065 * @qh:          QH for the periodic transfer.
1066 */
1067static void dwc2_uframe_unschedule(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1068{
1069	int i;
1070
1071	for (i = 0; i < qh->num_hs_transfers; i++)
1072		dwc2_hs_pmap_unschedule(hsotg, qh, i);
1073
1074	if (qh->schedule_low_speed)
1075		dwc2_ls_pmap_unschedule(hsotg, qh);
1076
1077	dwc2_sch_dbg(hsotg, "QH=%p Unscheduled\n", qh);
1078}
1079
1080/**
1081 * dwc2_pick_first_frame() - Choose 1st frame for qh that's already scheduled
1082 *
1083 * Takes a qh that has already been scheduled (which means we know we have the
1084 * bandwdith reserved for us) and set the next_active_frame and the
1085 * start_active_frame.
1086 *
1087 * This is expected to be called on qh's that weren't previously actively
1088 * running.  It just picks the next frame that we can fit into without any
1089 * thought about the past.
1090 *
1091 * @hsotg: The HCD state structure for the DWC OTG controller
1092 * @qh:    QH for a periodic endpoint
1093 *
1094 */
1095static void dwc2_pick_first_frame(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1096{
1097	u16 frame_number;
1098	u16 earliest_frame;
1099	u16 next_active_frame;
1100	u16 relative_frame;
1101	u16 interval;
1102
1103	/*
1104	 * Use the real frame number rather than the cached value as of the
1105	 * last SOF to give us a little extra slop.
1106	 */
1107	frame_number = dwc2_hcd_get_frame_number(hsotg);
1108
1109	/*
1110	 * We wouldn't want to start any earlier than the next frame just in
1111	 * case the frame number ticks as we're doing this calculation.
1112	 *
1113	 * NOTE: if we could quantify how long till we actually get scheduled
1114	 * we might be able to avoid the "+ 1" by looking at the upper part of
1115	 * HFNUM (the FRREM field).  For now we'll just use the + 1 though.
1116	 */
1117	earliest_frame = dwc2_frame_num_inc(frame_number, 1);
1118	next_active_frame = earliest_frame;
1119
1120	/* Get the "no microframe schduler" out of the way... */
1121	if (!hsotg->params.uframe_sched) {
1122		if (qh->do_split)
1123			/* Splits are active at microframe 0 minus 1 */
1124			next_active_frame |= 0x7;
1125		goto exit;
1126	}
1127
1128	if (qh->dev_speed == USB_SPEED_HIGH || qh->do_split) {
1129		/*
1130		 * We're either at high speed or we're doing a split (which
1131		 * means we're talking high speed to a hub).  In any case
1132		 * the first frame should be based on when the first scheduled
1133		 * event is.
1134		 */
1135		WARN_ON(qh->num_hs_transfers < 1);
1136
1137		relative_frame = qh->hs_transfers[0].start_schedule_us /
1138				 DWC2_HS_PERIODIC_US_PER_UFRAME;
1139
1140		/* Adjust interval as per high speed schedule */
1141		interval = gcd(qh->host_interval, DWC2_HS_SCHEDULE_UFRAMES);
1142
1143	} else {
1144		/*
1145		 * Low or full speed directly on dwc2.  Just about the same
1146		 * as high speed but on a different schedule and with slightly
1147		 * different adjustments.  Note that this works because when
1148		 * the host and device are both low speed then frames in the
1149		 * controller tick at low speed.
1150		 */
1151		relative_frame = qh->ls_start_schedule_slice /
1152				 DWC2_LS_PERIODIC_SLICES_PER_FRAME;
1153		interval = gcd(qh->host_interval, DWC2_LS_SCHEDULE_FRAMES);
1154	}
1155
1156	/* Scheduler messed up if frame is past interval */
1157	WARN_ON(relative_frame >= interval);
1158
1159	/*
1160	 * We know interval must divide (HFNUM_MAX_FRNUM + 1) now that we've
1161	 * done the gcd(), so it's safe to move to the beginning of the current
1162	 * interval like this.
1163	 *
1164	 * After this we might be before earliest_frame, but don't worry,
1165	 * we'll fix it...
1166	 */
1167	next_active_frame = (next_active_frame / interval) * interval;
1168
1169	/*
1170	 * Actually choose to start at the frame number we've been
1171	 * scheduled for.
1172	 */
1173	next_active_frame = dwc2_frame_num_inc(next_active_frame,
1174					       relative_frame);
1175
1176	/*
1177	 * We actually need 1 frame before since the next_active_frame is
1178	 * the frame number we'll be put on the ready list and we won't be on
1179	 * the bus until 1 frame later.
1180	 */
1181	next_active_frame = dwc2_frame_num_dec(next_active_frame, 1);
1182
1183	/*
1184	 * By now we might actually be before the earliest_frame.  Let's move
1185	 * up intervals until we're not.
1186	 */
1187	while (dwc2_frame_num_gt(earliest_frame, next_active_frame))
1188		next_active_frame = dwc2_frame_num_inc(next_active_frame,
1189						       interval);
1190
1191exit:
1192	qh->next_active_frame = next_active_frame;
1193	qh->start_active_frame = next_active_frame;
1194
1195	dwc2_sch_vdbg(hsotg, "QH=%p First fn=%04x nxt=%04x\n",
1196		      qh, frame_number, qh->next_active_frame);
1197}
1198
1199/**
1200 * dwc2_do_reserve() - Make a periodic reservation
1201 *
1202 * Try to allocate space in the periodic schedule.  Depending on parameters
1203 * this might use the microframe scheduler or the dumb scheduler.
1204 *
1205 * @hsotg: The HCD state structure for the DWC OTG controller
1206 * @qh:    QH for the periodic transfer.
1207 *
1208 * Returns: 0 upon success; error upon failure.
1209 */
1210static int dwc2_do_reserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1211{
1212	int status;
1213
1214	if (hsotg->params.uframe_sched) {
1215		status = dwc2_uframe_schedule(hsotg, qh);
1216	} else {
1217		status = dwc2_periodic_channel_available(hsotg);
1218		if (status) {
1219			dev_info(hsotg->dev,
1220				 "%s: No host channel available for periodic transfer\n",
1221				 __func__);
1222			return status;
1223		}
1224
1225		status = dwc2_check_periodic_bandwidth(hsotg, qh);
1226	}
1227
1228	if (status) {
1229		dev_dbg(hsotg->dev,
1230			"%s: Insufficient periodic bandwidth for periodic transfer\n",
1231			__func__);
1232		return status;
1233	}
1234
1235	if (!hsotg->params.uframe_sched)
1236		/* Reserve periodic channel */
1237		hsotg->periodic_channels++;
1238
1239	/* Update claimed usecs per (micro)frame */
1240	hsotg->periodic_usecs += qh->host_us;
1241
1242	dwc2_pick_first_frame(hsotg, qh);
1243
1244	return 0;
1245}
1246
1247/**
1248 * dwc2_do_unreserve() - Actually release the periodic reservation
1249 *
1250 * This function actually releases the periodic bandwidth that was reserved
1251 * by the given qh.
1252 *
1253 * @hsotg: The HCD state structure for the DWC OTG controller
1254 * @qh:    QH for the periodic transfer.
1255 */
1256static void dwc2_do_unreserve(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1257{
1258	MUTEX_ASSERT_LOCKED(&hsotg->lock);
1259
1260	WARN_ON(!qh->unreserve_pending);
1261
1262	/* No more unreserve pending--we're doing it */
1263	qh->unreserve_pending = false;
1264
1265	if (WARN_ON(!list_empty(&qh->qh_list_entry)))
1266		list_del_init(&qh->qh_list_entry);
1267
1268	/* Update claimed usecs per (micro)frame */
1269	hsotg->periodic_usecs -= qh->host_us;
1270
1271	if (hsotg->params.uframe_sched) {
1272		dwc2_uframe_unschedule(hsotg, qh);
1273	} else {
1274		/* Release periodic channel reservation */
1275		hsotg->periodic_channels--;
1276	}
1277}
1278
1279/**
1280 * dwc2_unreserve_timer_fn() - Timer function to release periodic reservation
1281 *
1282 * According to the kernel doc for usb_submit_urb() (specifically the part about
1283 * "Reserved Bandwidth Transfers"), we need to keep a reservation active as
1284 * long as a device driver keeps submitting.  Since we're using HCD_BH to give
1285 * back the URB we need to give the driver a little bit of time before we
1286 * release the reservation.  This worker is called after the appropriate
1287 * delay.
1288 *
1289 * @t: Address to a qh unreserve_work.
1290 */
1291static void dwc2_unreserve_timer_fn(void *arg)
1292{
1293	struct dwc2_qh *qh = arg;
1294	struct dwc2_hsotg *hsotg = qh->hsotg;
1295	unsigned long flags;
1296
1297	/*
1298	 * Wait for the lock, or for us to be scheduled again.  We
1299	 * could be scheduled again if:
1300	 * - We started executing but didn't get the lock yet.
1301	 * - A new reservation came in, but cancel didn't take effect
1302	 *   because we already started executing.
1303	 * - The timer has been kicked again.
1304	 * In that case cancel and wait for the next call.
1305	 */
1306	while (!spin_trylock_irqsave(&hsotg->lock, flags)) {
1307		if (timeout_pending(&qh->unreserve_timer))
1308			return;
1309	}
1310
1311	/*
1312	 * Might be no more unreserve pending if:
1313	 * - We started executing but didn't get the lock yet.
1314	 * - A new reservation came in, but cancel didn't take effect
1315	 *   because we already started executing.
1316	 *
1317	 * We can't put this in the loop above because unreserve_pending needs
1318	 * to be accessed under lock, so we can only check it once we got the
1319	 * lock.
1320	 */
1321	if (qh->unreserve_pending)
1322		dwc2_do_unreserve(hsotg, qh);
1323
1324	spin_unlock_irqrestore(&hsotg->lock, flags);
1325}
1326
1327/**
1328 * dwc2_check_max_xfer_size() - Checks that the max transfer size allowed in a
1329 * host channel is large enough to handle the maximum data transfer in a single
1330 * (micro)frame for a periodic transfer
1331 *
1332 * @hsotg: The HCD state structure for the DWC OTG controller
1333 * @qh:    QH for a periodic endpoint
1334 *
1335 * Return: 0 if successful, negative error code otherwise
1336 */
1337STATIC int dwc2_check_max_xfer_size(struct dwc2_hsotg *hsotg,
1338				    struct dwc2_qh *qh)
1339{
1340	u32 max_xfer_size;
1341	u32 max_channel_xfer_size;
1342	int status = 0;
1343
1344	max_xfer_size = qh->maxp * qh->maxp_mult;
1345	max_channel_xfer_size = hsotg->params.max_transfer_size;
1346
1347	if (max_xfer_size > max_channel_xfer_size) {
1348		dev_err(hsotg->dev,
1349			"%s: Periodic xfer length %d > max xfer length for channel %d\n",
1350			__func__, max_xfer_size, max_channel_xfer_size);
1351		status = -ENOSPC;
1352	}
1353
1354	return status;
1355}
1356
1357/**
1358 * dwc2_schedule_periodic() - Schedules an interrupt or isochronous transfer in
1359 * the periodic schedule
1360 *
1361 * @hsotg: The HCD state structure for the DWC OTG controller
1362 * @qh:    QH for the periodic transfer. The QH should already contain the
1363 *         scheduling information.
1364 *
1365 * Return: 0 if successful, negative error code otherwise
1366 */
1367STATIC int dwc2_schedule_periodic(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1368{
1369	int status;
1370
1371	status = dwc2_check_max_xfer_size(hsotg, qh);
1372	if (status) {
1373		dev_dbg(hsotg->dev,
1374			"%s: Channel max transfer size too small for periodic transfer\n",
1375			__func__);
1376		return status;
1377	}
1378
1379	/* Cancel pending unreserve; if canceled OK, unreserve was pending */
1380	if (timeout_del(&qh->unreserve_timer))
1381		WARN_ON(!qh->unreserve_pending);
1382
1383	/*
1384	 * Only need to reserve if there's not an unreserve pending, since if an
1385	 * unreserve is pending then by definition our old reservation is still
1386	 * valid.  Unreserve might still be pending even if we didn't cancel if
1387	 * dwc2_unreserve_timer_fn() already started.  Code in the timer handles
1388	 * that case.
1389	 */
1390	if (!qh->unreserve_pending) {
1391		status = dwc2_do_reserve(hsotg, qh);
1392		if (status)
1393			return status;
1394	} else {
1395		/*
1396		 * It might have been a while, so make sure that frame_number
1397		 * is still good.  Note: we could also try to use the similar
1398		 * dwc2_next_periodic_start() but that schedules much more
1399		 * tightly and we might need to hurry and queue things up.
1400		 */
1401		if (dwc2_frame_num_le(qh->next_active_frame,
1402				      hsotg->frame_number))
1403			dwc2_pick_first_frame(hsotg, qh);
1404	}
1405
1406	qh->unreserve_pending = 0;
1407
1408	if (hsotg->params.dma_desc_enable)
1409		/* Don't rely on SOF and start in ready schedule */
1410		list_add_tail(&qh->qh_list_entry, &hsotg->periodic_sched_ready);
1411	else
1412		/* Always start in inactive schedule */
1413		list_add_tail(&qh->qh_list_entry,
1414			      &hsotg->periodic_sched_inactive);
1415
1416	return 0;
1417}
1418
1419/**
1420 * dwc2_deschedule_periodic() - Removes an interrupt or isochronous transfer
1421 * from the periodic schedule
1422 *
1423 * @hsotg: The HCD state structure for the DWC OTG controller
1424 * @qh:	   QH for the periodic transfer
1425 */
1426STATIC void dwc2_deschedule_periodic(struct dwc2_hsotg *hsotg,
1427				     struct dwc2_qh *qh)
1428{
1429	MUTEX_ASSERT_LOCKED(&hsotg->lock);
1430
1431	/*
1432	 * Schedule the unreserve to happen in a little bit.  Cases here:
1433	 * - Unreserve worker might be sitting there waiting to grab the lock.
1434	 *   In this case it will notice it's been schedule again and will
1435	 *   quit.
1436	 * - Unreserve worker might not be scheduled.
1437	 *
1438	 * We should never already be scheduled since dwc2_schedule_periodic()
1439	 * should have canceled the scheduled unreserve timer (hence the
1440	 * warning on did_modify).
1441	 *
1442	 * We add + 1 to the timer to guarantee that at least 1 jiffy has
1443	 * passed (otherwise if the jiffy counter might tick right after we
1444	 * read it and we'll get no delay).
1445	 */
1446	timeout_add(&qh->unreserve_timer, DWC2_UNRESERVE_DELAY + 1);
1447	qh->unreserve_pending = 1;
1448
1449	list_del_init(&qh->qh_list_entry);
1450}
1451
1452/**
1453 * dwc2_wait_timer_fn() - Timer function to re-queue after waiting
1454 *
1455 * As per the spec, a NAK indicates that "a function is temporarily unable to
1456 * transmit or receive data, but will eventually be able to do so without need
1457 * of host intervention".
1458 *
1459 * That means that when we encounter a NAK we're supposed to retry.
1460 *
1461 * ...but if we retry right away (from the interrupt handler that saw the NAK)
1462 * then we can end up with an interrupt storm (if the other side keeps NAKing
1463 * us) because on slow enough CPUs it could take us longer to get out of the
1464 * interrupt routine than it takes for the device to send another NAK.  That
1465 * leads to a constant stream of NAK interrupts and the CPU locks.
1466 *
1467 * ...so instead of retrying right away in the case of a NAK we'll set a timer
1468 * to retry some time later.  This function handles that timer and moves the
1469 * qh back to the "inactive" list, then queues transactions.
1470 *
1471 * @t: Pointer to wait_timer in a qh.
1472 *
1473 * Return: HRTIMER_NORESTART to not automatically restart this timer.
1474 */
1475STATIC void dwc2_wait_timer_fn(void *arg)
1476{
1477	struct dwc2_qh *qh = arg;
1478	struct dwc2_hsotg *hsotg = qh->hsotg;
1479	unsigned long flags;
1480
1481	spin_lock_irqsave(&hsotg->lock, flags);
1482
1483	/*
1484	 * We'll set wait_timer_cancel to true if we want to cancel this
1485	 * operation in dwc2_hcd_qh_unlink().
1486	 */
1487	if (!qh->wait_timer_cancel) {
1488		enum dwc2_transaction_type tr_type;
1489
1490		qh->want_wait = false;
1491
1492		list_move(&qh->qh_list_entry,
1493			  &hsotg->non_periodic_sched_inactive);
1494
1495		tr_type = dwc2_hcd_select_transactions(hsotg);
1496		if (tr_type != DWC2_TRANSACTION_NONE)
1497			dwc2_hcd_queue_transactions(hsotg, tr_type);
1498	}
1499
1500	spin_unlock_irqrestore(&hsotg->lock, flags);
1501}
1502
1503/**
1504 * dwc2_qh_init() - Initializes a QH structure
1505 *
1506 * @hsotg: The HCD state structure for the DWC OTG controller
1507 * @qh:    The QH to init
1508 * @urb:   Holds the information about the device/endpoint needed to initialize
1509 *         the QH
1510 * @mem_flags: Flags for allocating memory.
1511 */
1512STATIC void dwc2_qh_init(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1513			 struct dwc2_hcd_urb *urb, gfp_t mem_flags)
1514{
1515	int dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
1516	u8 ep_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1517	bool ep_is_in = !!dwc2_hcd_is_pipe_in(&urb->pipe_info);
1518	bool ep_is_isoc = (ep_type == USB_ENDPOINT_XFER_ISOC);
1519	bool ep_is_int = (ep_type == USB_ENDPOINT_XFER_INT);
1520	u32 hprt = dwc2_readl(hsotg, HPRT0);
1521	u32 prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1522	bool do_split = (prtspd == HPRT0_SPD_HIGH_SPEED &&
1523			 dev_speed != USB_SPEED_HIGH);
1524	int maxp = dwc2_hcd_get_maxp(&urb->pipe_info);
1525	int maxp_mult = dwc2_hcd_get_maxp_mult(&urb->pipe_info);
1526	int bytecount = maxp_mult * maxp;
1527	char *speed, *type;
1528
1529	/* Initialize QH */
1530	qh->hsotg = hsotg;
1531	timeout_set(&qh->unreserve_timer, dwc2_unreserve_timer_fn, qh);
1532	timeout_set(&qh->wait_timer, dwc2_wait_timer_fn, qh);
1533	qh->ep_type = ep_type;
1534	qh->ep_is_in = ep_is_in;
1535
1536	qh->data_toggle = DWC2_HC_PID_DATA0;
1537	qh->maxp = maxp;
1538	qh->maxp_mult = maxp_mult;
1539	INIT_LIST_HEAD(&qh->qtd_list);
1540	INIT_LIST_HEAD(&qh->qh_list_entry);
1541
1542	qh->do_split = do_split;
1543	qh->dev_speed = dev_speed;
1544
1545	if (ep_is_int || ep_is_isoc) {
1546		/* Compute scheduling parameters once and save them */
1547		int host_speed = do_split ? USB_SPEED_HIGH : dev_speed;
1548		struct dwc2_tt *dwc_tt = dwc2_host_get_tt_info(hsotg, urb->priv,
1549							       mem_flags,
1550							       &qh->ttport);
1551		int device_ns;
1552
1553		qh->dwc_tt = dwc_tt;
1554
1555		qh->host_us = NS_TO_US(dwc2_usb_calc_bus_time(host_speed,
1556				       ep_is_in, ep_is_isoc, bytecount));
1557		device_ns = dwc2_usb_calc_bus_time(dev_speed, ep_is_in,
1558						   ep_is_isoc, bytecount);
1559
1560		if (do_split && dwc_tt)
1561			device_ns += dwc2_ttthink_to_ns(hsotg, urb->priv,
1562			    dwc_tt->usb_tt->hub->ttthink);
1563		qh->device_us = NS_TO_US(device_ns);
1564
1565		qh->device_interval = urb->interval;
1566		qh->host_interval = urb->interval * (do_split ? 8 : 1);
1567
1568		/*
1569		 * Schedule low speed if we're running the host in low or
1570		 * full speed OR if we've got a "TT" to deal with to access this
1571		 * device.
1572		 */
1573		qh->schedule_low_speed = prtspd != HPRT0_SPD_HIGH_SPEED ||
1574					 dwc_tt;
1575
1576		if (do_split) {
1577			/* We won't know num transfers until we schedule */
1578			qh->num_hs_transfers = -1;
1579		} else if (dev_speed == USB_SPEED_HIGH) {
1580			qh->num_hs_transfers = 1;
1581		} else {
1582			qh->num_hs_transfers = 0;
1583		}
1584
1585		/* We'll schedule later when we have something to do */
1586	}
1587
1588	switch (dev_speed) {
1589	case USB_SPEED_LOW:
1590		speed = "low";
1591		break;
1592	case USB_SPEED_FULL:
1593		speed = "full";
1594		break;
1595	case USB_SPEED_HIGH:
1596		speed = "high";
1597		break;
1598	default:
1599		speed = "?";
1600		break;
1601	}
1602
1603	switch (qh->ep_type) {
1604	case USB_ENDPOINT_XFER_ISOC:
1605		type = "isochronous";
1606		break;
1607	case USB_ENDPOINT_XFER_INT:
1608		type = "interrupt";
1609		break;
1610	case USB_ENDPOINT_XFER_CONTROL:
1611		type = "control";
1612		break;
1613	case USB_ENDPOINT_XFER_BULK:
1614		type = "bulk";
1615		break;
1616	default:
1617		type = "?";
1618		break;
1619	}
1620
1621	dwc2_sch_dbg(hsotg, "QH=%p Init %s, %s speed, %d bytes:\n", qh, type,
1622		     speed, bytecount);
1623	dwc2_sch_dbg(hsotg, "QH=%p ...addr=%d, ep=%d, %s\n", qh,
1624		     dwc2_hcd_get_dev_addr(&urb->pipe_info),
1625		     dwc2_hcd_get_ep_num(&urb->pipe_info),
1626		     ep_is_in ? "IN" : "OUT");
1627	if (ep_is_int || ep_is_isoc) {
1628		dwc2_sch_dbg(hsotg,
1629			     "QH=%p ...duration: host=%d us, device=%d us\n",
1630			     qh, qh->host_us, qh->device_us);
1631		dwc2_sch_dbg(hsotg, "QH=%p ...interval: host=%d, device=%d\n",
1632			     qh, qh->host_interval, qh->device_interval);
1633		if (qh->schedule_low_speed)
1634			dwc2_sch_dbg(hsotg, "QH=%p ...low speed schedule=%p\n",
1635				     qh, dwc2_get_ls_map(hsotg, qh));
1636	}
1637}
1638
1639/**
1640 * dwc2_hcd_qh_create() - Allocates and initializes a QH
1641 *
1642 * @hsotg:        The HCD state structure for the DWC OTG controller
1643 * @urb:          Holds the information about the device/endpoint needed
1644 *                to initialize the QH
1645 * @mem_flags:   Flags for allocating memory.
1646 *
1647 * Return: Pointer to the newly allocated QH, or NULL on error
1648 */
1649struct dwc2_qh *dwc2_hcd_qh_create(struct dwc2_hsotg *hsotg,
1650				   struct dwc2_hcd_urb *urb,
1651					  gfp_t mem_flags)
1652{
1653	struct dwc2_softc *sc = hsotg->hsotg_sc;
1654	struct dwc2_qh *qh;
1655
1656	if (!urb->priv)
1657		return NULL;
1658
1659	/* Allocate memory */
1660	qh = pool_get(&sc->sc_qhpool, PR_NOWAIT | PR_ZERO);
1661	if (!qh)
1662		return NULL;
1663
1664	dwc2_qh_init(hsotg, qh, urb, mem_flags);
1665
1666	if (hsotg->params.dma_desc_enable &&
1667	    dwc2_hcd_qh_init_ddma(hsotg, qh, mem_flags) < 0) {
1668		dwc2_hcd_qh_free(hsotg, qh);
1669		return NULL;
1670	}
1671
1672	return qh;
1673}
1674
1675/**
1676 * dwc2_hcd_qh_free() - Frees the QH
1677 *
1678 * @hsotg: HCD instance
1679 * @qh:    The QH to free
1680 *
1681 * QH should already be removed from the list. QTD list should already be empty
1682 * if called from URB Dequeue.
1683 *
1684 * Must NOT be called with interrupt disabled or spinlock held
1685 */
1686void dwc2_hcd_qh_free(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1687{
1688	struct dwc2_softc *sc = hsotg->hsotg_sc;
1689
1690	/* Make sure any unreserve work is finished. */
1691	if (timeout_del(&qh->unreserve_timer)) {
1692		unsigned long flags;
1693
1694		spin_lock_irqsave(&hsotg->lock, flags);
1695		dwc2_do_unreserve(hsotg, qh);
1696		spin_unlock_irqrestore(&hsotg->lock, flags);
1697	}
1698
1699	/*
1700	 * We don't have the lock so we can safely wait until the wait timer
1701	 * finishes.  Of course, at this point in time we'd better have set
1702	 * wait_timer_active to false so if this timer was still pending it
1703	 * won't do anything anyway, but we want it to finish before we free
1704	 * memory.
1705	 */
1706	timeout_del(&qh->wait_timer);
1707
1708	dwc2_host_put_tt_info(hsotg, qh->dwc_tt);
1709
1710	if (qh->desc_list)
1711		dwc2_hcd_qh_free_ddma(hsotg, qh);
1712	else if (hsotg->unaligned_cache && qh->dw_align_buf) {
1713		usb_freemem(&sc->sc_bus, &qh->dw_align_buf_usbdma);
1714 		qh->dw_align_buf_dma = (dma_addr_t)0;
1715	}
1716
1717	pool_put(&sc->sc_qhpool, qh);
1718}
1719
1720/**
1721 * dwc2_hcd_qh_add() - Adds a QH to either the non periodic or periodic
1722 * schedule if it is not already in the schedule. If the QH is already in
1723 * the schedule, no action is taken.
1724 *
1725 * @hsotg: The HCD state structure for the DWC OTG controller
1726 * @qh:    The QH to add
1727 *
1728 * Return: 0 if successful, negative error code otherwise
1729 */
1730int dwc2_hcd_qh_add(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1731{
1732	int status;
1733	u32 intr_mask;
1734
1735	if (dbg_qh(qh))
1736		dev_vdbg(hsotg->dev, "%s()\n", __func__);
1737
1738	if (!list_empty(&qh->qh_list_entry))
1739		/* QH already in a schedule */
1740		return 0;
1741
1742	/* Add the new QH to the appropriate schedule */
1743	if (dwc2_qh_is_non_per(qh)) {
1744		/* Schedule right away */
1745		qh->start_active_frame = hsotg->frame_number;
1746		qh->next_active_frame = qh->start_active_frame;
1747
1748		if (qh->want_wait) {
1749			list_add_tail(&qh->qh_list_entry,
1750				      &hsotg->non_periodic_sched_waiting);
1751			qh->wait_timer_cancel = false;
1752			timeout_add_msec(&qh->wait_timer,
1753			    DWC2_RETRY_WAIT_DELAY);
1754		} else {
1755			list_add_tail(&qh->qh_list_entry,
1756				      &hsotg->non_periodic_sched_inactive);
1757		}
1758		return 0;
1759	}
1760
1761	status = dwc2_schedule_periodic(hsotg, qh);
1762	if (status)
1763		return status;
1764	if (!hsotg->periodic_qh_count) {
1765		intr_mask = dwc2_readl(hsotg, GINTMSK);
1766		intr_mask |= GINTSTS_SOF;
1767		dwc2_writel(hsotg, intr_mask, GINTMSK);
1768	}
1769	hsotg->periodic_qh_count++;
1770
1771	return 0;
1772}
1773
1774/**
1775 * dwc2_hcd_qh_unlink() - Removes a QH from either the non-periodic or periodic
1776 * schedule. Memory is not freed.
1777 *
1778 * @hsotg: The HCD state structure
1779 * @qh:    QH to remove from schedule
1780 */
1781void dwc2_hcd_qh_unlink(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
1782{
1783	u32 intr_mask;
1784
1785	dev_vdbg(hsotg->dev, "%s()\n", __func__);
1786
1787	/* If the wait_timer is pending, this will stop it from acting */
1788	qh->wait_timer_cancel = true;
1789
1790	if (list_empty(&qh->qh_list_entry))
1791		/* QH is not in a schedule */
1792		return;
1793
1794	if (dwc2_qh_is_non_per(qh)) {
1795		if (hsotg->non_periodic_qh_ptr == &qh->qh_list_entry)
1796			hsotg->non_periodic_qh_ptr =
1797					hsotg->non_periodic_qh_ptr->next;
1798		list_del_init(&qh->qh_list_entry);
1799		return;
1800	}
1801
1802	dwc2_deschedule_periodic(hsotg, qh);
1803	hsotg->periodic_qh_count--;
1804	if (!hsotg->periodic_qh_count &&
1805	    !hsotg->params.dma_desc_enable) {
1806		intr_mask = dwc2_readl(hsotg, GINTMSK);
1807		intr_mask &= ~GINTSTS_SOF;
1808		dwc2_writel(hsotg, intr_mask, GINTMSK);
1809	}
1810}
1811
1812/**
1813 * dwc2_next_for_periodic_split() - Set next_active_frame midway thru a split.
1814 *
1815 * This is called for setting next_active_frame for periodic splits for all but
1816 * the first packet of the split.  Confusing?  I thought so...
1817 *
1818 * Periodic splits are single low/full speed transfers that we end up splitting
1819 * up into several high speed transfers.  They always fit into one full (1 ms)
1820 * frame but might be split over several microframes (125 us each).  We to put
1821 * each of the parts on a very specific high speed frame.
1822 *
1823 * This function figures out where the next active uFrame needs to be.
1824 *
1825 * @hsotg:        The HCD state structure
1826 * @qh:           QH for the periodic transfer.
1827 * @frame_number: The current frame number.
1828 *
1829 * Return: number missed by (or 0 if we didn't miss).
1830 */
1831static int dwc2_next_for_periodic_split(struct dwc2_hsotg *hsotg,
1832					struct dwc2_qh *qh, u16 frame_number)
1833{
1834	u16 old_frame = qh->next_active_frame;
1835	u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
1836	int missed = 0;
1837	u16 incr;
1838
1839	/*
1840	 * See dwc2_uframe_schedule_split() for split scheduling.
1841	 *
1842	 * Basically: increment 1 normally, but 2 right after the start split
1843	 * (except for ISOC out).
1844	 */
1845	if (old_frame == qh->start_active_frame &&
1846	    !(qh->ep_type == USB_ENDPOINT_XFER_ISOC && !qh->ep_is_in))
1847		incr = 2;
1848	else
1849		incr = 1;
1850
1851	qh->next_active_frame = dwc2_frame_num_inc(old_frame, incr);
1852
1853	/*
1854	 * Note that it's OK for frame_number to be 1 frame past
1855	 * next_active_frame.  Remember that next_active_frame is supposed to
1856	 * be 1 frame _before_ when we want to be scheduled.  If we're 1 frame
1857	 * past it just means schedule ASAP.
1858	 *
1859	 * It's _not_ OK, however, if we're more than one frame past.
1860	 */
1861	if (dwc2_frame_num_gt(prev_frame_number, qh->next_active_frame)) {
1862		/*
1863		 * OOPS, we missed.  That's actually pretty bad since
1864		 * the hub will be unhappy; try ASAP I guess.
1865		 */
1866		missed = dwc2_frame_num_dec(prev_frame_number,
1867					    qh->next_active_frame);
1868		qh->next_active_frame = frame_number;
1869	}
1870
1871	return missed;
1872}
1873
1874/**
1875 * dwc2_next_periodic_start() - Set next_active_frame for next transfer start
1876 *
1877 * This is called for setting next_active_frame for a periodic transfer for
1878 * all cases other than midway through a periodic split.  This will also update
1879 * start_active_frame.
1880 *
1881 * Since we _always_ keep start_active_frame as the start of the previous
1882 * transfer this is normally pretty easy: we just add our interval to
1883 * start_active_frame and we've got our answer.
1884 *
1885 * The tricks come into play if we miss.  In that case we'll look for the next
1886 * slot we can fit into.
1887 *
1888 * @hsotg:        The HCD state structure
1889 * @qh:           QH for the periodic transfer.
1890 * @frame_number: The current frame number.
1891 *
1892 * Return: number missed by (or 0 if we didn't miss).
1893 */
1894static int dwc2_next_periodic_start(struct dwc2_hsotg *hsotg,
1895				    struct dwc2_qh *qh, u16 frame_number)
1896{
1897	int missed = 0;
1898	u16 interval = qh->host_interval;
1899	u16 prev_frame_number = dwc2_frame_num_dec(frame_number, 1);
1900
1901	qh->start_active_frame = dwc2_frame_num_inc(qh->start_active_frame,
1902						    interval);
1903
1904	/*
1905	 * The dwc2_frame_num_gt() function used below won't work terribly well
1906	 * with if we just incremented by a really large intervals since the
1907	 * frame counter only goes to 0x3fff.  It's terribly unlikely that we
1908	 * will have missed in this case anyway.  Just go to exit.  If we want
1909	 * to try to do better we'll need to keep track of a bigger counter
1910	 * somewhere in the driver and handle overflows.
1911	 */
1912	if (interval >= 0x1000)
1913		goto exit;
1914
1915	/*
1916	 * Test for misses, which is when it's too late to schedule.
1917	 *
1918	 * A few things to note:
1919	 * - We compare against prev_frame_number since start_active_frame
1920	 *   and next_active_frame are always 1 frame before we want things
1921	 *   to be active and we assume we can still get scheduled in the
1922	 *   current frame number.
1923	 * - It's possible for start_active_frame (now incremented) to be
1924	 *   next_active_frame if we got an EO MISS (even_odd miss) which
1925	 *   basically means that we detected there wasn't enough time for
1926	 *   the last packet and dwc2_hc_set_even_odd_frame() rescheduled us
1927	 *   at the last second.  We want to make sure we don't schedule
1928	 *   another transfer for the same frame.  My test webcam doesn't seem
1929	 *   terribly upset by missing a transfer but really doesn't like when
1930	 *   we do two transfers in the same frame.
1931	 * - Some misses are expected.  Specifically, in order to work
1932	 *   perfectly dwc2 really needs quite spectacular interrupt latency
1933	 *   requirements.  It needs to be able to handle its interrupts
1934	 *   completely within 125 us of them being asserted. That not only
1935	 *   means that the dwc2 interrupt handler needs to be fast but it
1936	 *   means that nothing else in the system has to block dwc2 for a long
1937	 *   time.  We can help with the dwc2 parts of this, but it's hard to
1938	 *   guarantee that a system will have interrupt latency < 125 us, so
1939	 *   we have to be robust to some misses.
1940	 */
1941	if (qh->start_active_frame == qh->next_active_frame ||
1942	    dwc2_frame_num_gt(prev_frame_number, qh->start_active_frame)) {
1943		u16 ideal_start = qh->start_active_frame;
1944		int periods_in_map;
1945
1946		/*
1947		 * Adjust interval as per gcd with map size.
1948		 * See pmap_schedule() for more details here.
1949		 */
1950		if (qh->do_split || qh->dev_speed == USB_SPEED_HIGH)
1951			periods_in_map = DWC2_HS_SCHEDULE_UFRAMES;
1952		else
1953			periods_in_map = DWC2_LS_SCHEDULE_FRAMES;
1954		interval = gcd(interval, periods_in_map);
1955
1956		do {
1957			qh->start_active_frame = dwc2_frame_num_inc(
1958				qh->start_active_frame, interval);
1959		} while (dwc2_frame_num_gt(prev_frame_number,
1960					   qh->start_active_frame));
1961
1962		missed = dwc2_frame_num_dec(qh->start_active_frame,
1963					    ideal_start);
1964	}
1965
1966exit:
1967	qh->next_active_frame = qh->start_active_frame;
1968
1969	return missed;
1970}
1971
1972/*
1973 * Deactivates a QH. For non-periodic QHs, removes the QH from the active
1974 * non-periodic schedule. The QH is added to the inactive non-periodic
1975 * schedule if any QTDs are still attached to the QH.
1976 *
1977 * For periodic QHs, the QH is removed from the periodic queued schedule. If
1978 * there are any QTDs still attached to the QH, the QH is added to either the
1979 * periodic inactive schedule or the periodic ready schedule and its next
1980 * scheduled frame is calculated. The QH is placed in the ready schedule if
1981 * the scheduled frame has been reached already. Otherwise it's placed in the
1982 * inactive schedule. If there are no QTDs attached to the QH, the QH is
1983 * completely removed from the periodic schedule.
1984 */
1985void dwc2_hcd_qh_deactivate(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
1986			    int sched_next_periodic_split)
1987{
1988#ifdef DWC2_DEBUG
1989	u16 old_frame = qh->next_active_frame;
1990#endif
1991	u16 frame_number;
1992	int missed;
1993
1994	if (dbg_qh(qh))
1995		dev_vdbg(hsotg->dev, "%s()\n", __func__);
1996
1997	if (dwc2_qh_is_non_per(qh)) {
1998		dwc2_hcd_qh_unlink(hsotg, qh);
1999		if (!list_empty(&qh->qtd_list))
2000			/* Add back to inactive/waiting non-periodic schedule */
2001			dwc2_hcd_qh_add(hsotg, qh);
2002		return;
2003	}
2004
2005	/*
2006	 * Use the real frame number rather than the cached value as of the
2007	 * last SOF just to get us a little closer to reality.  Note that
2008	 * means we don't actually know if we've already handled the SOF
2009	 * interrupt for this frame.
2010	 */
2011	frame_number = dwc2_hcd_get_frame_number(hsotg);
2012
2013	if (sched_next_periodic_split)
2014		missed = dwc2_next_for_periodic_split(hsotg, qh, frame_number);
2015	else
2016		missed = dwc2_next_periodic_start(hsotg, qh, frame_number);
2017
2018	dwc2_sch_vdbg(hsotg,
2019		      "QH=%p next(%d) fn=%04x, sch=%04x=>%04x (%+d) miss=%d %s\n",
2020		     qh, sched_next_periodic_split, frame_number, old_frame,
2021		     qh->next_active_frame,
2022		     dwc2_frame_num_dec(qh->next_active_frame, old_frame),
2023		missed, missed ? "MISS" : "");
2024
2025	if (list_empty(&qh->qtd_list)) {
2026		dwc2_hcd_qh_unlink(hsotg, qh);
2027		return;
2028	}
2029
2030	/*
2031	 * Remove from periodic_sched_queued and move to
2032	 * appropriate queue
2033	 *
2034	 * Note: we purposely use the frame_number from the "hsotg" structure
2035	 * since we know SOF interrupt will handle future frames.
2036	 */
2037	if (dwc2_frame_num_le(qh->next_active_frame, hsotg->frame_number))
2038		list_move_tail(&qh->qh_list_entry,
2039			       &hsotg->periodic_sched_ready);
2040	else
2041		list_move_tail(&qh->qh_list_entry,
2042			       &hsotg->periodic_sched_inactive);
2043}
2044
2045/**
2046 * dwc2_hcd_qtd_init() - Initializes a QTD structure
2047 *
2048 * @qtd: The QTD to initialize
2049 * @urb: The associated URB
2050 */
2051void dwc2_hcd_qtd_init(struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2052{
2053	qtd->urb = urb;
2054	if (dwc2_hcd_get_pipe_type(&urb->pipe_info) ==
2055			USB_ENDPOINT_XFER_CONTROL) {
2056		/*
2057		 * The only time the QTD data toggle is used is on the data
2058		 * phase of control transfers. This phase always starts with
2059		 * DATA1.
2060		 */
2061		qtd->data_toggle = DWC2_HC_PID_DATA1;
2062		qtd->control_phase = DWC2_CONTROL_SETUP;
2063	}
2064
2065	/* Start split */
2066	qtd->complete_split = 0;
2067	qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
2068	qtd->isoc_split_offset = 0;
2069	qtd->in_process = 0;
2070
2071	/* Store the qtd ptr in the urb to reference the QTD */
2072	urb->qtd = qtd;
2073}
2074
2075/**
2076 * dwc2_hcd_qtd_add() - Adds a QTD to the QTD-list of a QH
2077 *			Caller must hold driver lock.
2078 *
2079 * @hsotg:        The DWC HCD structure
2080 * @qtd:          The QTD to add
2081 * @qh:           Queue head to add qtd to
2082 *
2083 * Return: 0 if successful, negative error code otherwise
2084 *
2085 * If the QH to which the QTD is added is not currently scheduled, it is placed
2086 * into the proper schedule based on its EP type.
2087 */
2088int dwc2_hcd_qtd_add(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2089		     struct dwc2_qh *qh)
2090{
2091	int retval;
2092
2093	if (unlikely(!qh)) {
2094		dev_err(hsotg->dev, "%s: Invalid QH\n", __func__);
2095		retval = -EINVAL;
2096		goto fail;
2097	}
2098
2099	retval = dwc2_hcd_qh_add(hsotg, qh);
2100	if (retval)
2101		goto fail;
2102
2103	qtd->qh = qh;
2104	list_add_tail(&qtd->qtd_list_entry, &qh->qtd_list);
2105
2106	return 0;
2107fail:
2108	return retval;
2109}
2110
2111/*** XXX: Include following functions in to our USB stack?  *******************/
2112
2113#define BW_HUB_LS_SETUP	333L	/* nanoseconds */
2114#define BW_HOST_DELAY	1000L	/* nanoseconds */
2115
2116long
2117dwc2_usb_calc_bus_time(int speed, int is_input, int isoc, int bytecount)
2118{
2119	unsigned long   tmp;
2120
2121	switch (speed) {
2122	case USB_SPEED_LOW:     /* INTR only */
2123		if (is_input) {
2124			tmp = (67667L * (31L + 10L * BitTime (bytecount))) /
2125			    1000L;
2126			return 64060L + (2 * BW_HUB_LS_SETUP) + BW_HOST_DELAY +
2127			    tmp;
2128		} else {
2129			tmp = (66700L * (31L + 10L * BitTime (bytecount))) /
2130			    1000L;
2131			return 64107L + (2 * BW_HUB_LS_SETUP) + BW_HOST_DELAY +
2132			    tmp;
2133		}
2134	case USB_SPEED_FULL:	/* ISOC or INTR */
2135		if (isoc) {
2136			tmp = (8354L * (31L + 10L * BitTime (bytecount))) /
2137			    1000L;
2138			return ((is_input) ? 7268L : 6265L) + BW_HOST_DELAY +
2139			    tmp;
2140		} else {
2141			tmp = (8354L * (31L + 10L * BitTime (bytecount))) /
2142			    1000L;
2143			return 9107L + BW_HOST_DELAY + tmp;
2144		}
2145	case USB_SPEED_HIGH:    /* ISOC or INTR */
2146		/* FIXME adjust for input vs output */
2147		if (isoc)
2148			tmp = HS_NSECS_ISO (bytecount);
2149		else
2150			tmp = HS_NSECS (bytecount);
2151		return tmp;
2152	default:
2153		printf ("%s: bogus device speed!\n", __func__);
2154		return -1;
2155	}
2156}
2157
2158int
2159dwc2_ttthink_to_ns(struct dwc2_hsotg *hsotg, void *context, int ttthink)
2160{
2161	struct usbd_xfer *xfer = context;
2162	struct dwc2_pipe *dpipe = DWC2_XFER2DPIPE(xfer);
2163	struct usbd_device *dev = dpipe->pipe.device;
2164
2165	/* 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns */
2166	switch (ttthink) {
2167	case UHD_TT_THINK_8:
2168		if (dev->ddesc.bDeviceProtocol != 0)
2169			return 666;
2170		else
2171			return 0;
2172	case UHD_TT_THINK_16:
2173		return 666 * 2;
2174	case UHD_TT_THINK_24:
2175		return 666 * 3;
2176	case UHD_TT_THINK_32:
2177		return 666 * 4;
2178	default:
2179		dev_dbg(hsotg->dev, "%s: Invalid TT Think Time (0x%04x)!\n",
2180		    __func__, ttthink);
2181		break;
2182	}
2183
2184	return 0;
2185}
2186