qec.c revision 1.3
1/* $OpenBSD: qec.c,v 1.3 2002/03/14 01:27:02 millert Exp $ */ 2/* $NetBSD: qec.c,v 1.12 2000/12/04 20:12:55 fvdl Exp $ */ 3 4/*- 5 * Copyright (c) 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40#include <sys/types.h> 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/kernel.h> 44#include <sys/errno.h> 45#include <sys/device.h> 46#include <sys/malloc.h> 47 48#include <machine/bus.h> 49#include <machine/intr.h> 50#include <machine/autoconf.h> 51 52#include <dev/sbus/sbusvar.h> 53#include <dev/sbus/qecreg.h> 54#include <dev/sbus/qecvar.h> 55 56static int qecprint(void *, const char *); 57static int qecmatch(struct device *, void *, void *); 58static void qecattach(struct device *, struct device *, void *); 59void qec_init(struct qec_softc *); 60 61static int qec_bus_map( 62 bus_space_tag_t, 63 bus_type_t, /*slot*/ 64 bus_addr_t, /*offset*/ 65 bus_size_t, /*size*/ 66 int, /*flags*/ 67 vaddr_t, /*preferred virtual address */ 68 bus_space_handle_t *); 69static void *qec_intr_establish __P(( 70 bus_space_tag_t, 71 int, /*bus interrupt priority*/ 72 int, /*`device class' interrupt level*/ 73 int, /*flags*/ 74 int (*)(void *), /*handler*/ 75 void *)); /*arg*/ 76 77struct cfattach qec_ca = { 78 sizeof(struct qec_softc), qecmatch, qecattach 79}; 80 81struct cfdriver qec_cd = { 82 NULL, "qec", DV_DULL 83}; 84 85int 86qecprint(aux, busname) 87 void *aux; 88 const char *busname; 89{ 90 struct sbus_attach_args *sa = aux; 91 bus_space_tag_t t = sa->sa_bustag; 92 struct qec_softc *sc = t->cookie; 93 94 sa->sa_bustag = sc->sc_bustag; /* XXX */ 95 sbus_print(aux, busname); /* XXX */ 96 sa->sa_bustag = t; /* XXX */ 97 return (UNCONF); 98} 99 100int 101qecmatch(parent, vcf, aux) 102 struct device *parent; 103 void *vcf; 104 void *aux; 105{ 106 struct cfdata *cf = vcf; 107 struct sbus_attach_args *sa = aux; 108 109 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0); 110} 111 112/* 113 * Attach all the sub-devices we can find 114 */ 115void 116qecattach(parent, self, aux) 117 struct device *parent, *self; 118 void *aux; 119{ 120 struct sbus_attach_args *sa = aux; 121 struct qec_softc *sc = (void *)self; 122 int node; 123 int sbusburst; 124 bus_space_tag_t sbt; 125 bus_space_handle_t bh; 126 int error; 127 128 sc->sc_bustag = sa->sa_bustag; 129 sc->sc_dmatag = sa->sa_dmatag; 130 node = sa->sa_node; 131 132 if (sa->sa_nreg < 2) { 133 printf("%s: only %d register sets\n", 134 self->dv_xname, sa->sa_nreg); 135 return; 136 } 137 138 if (sbus_bus_map(sa->sa_bustag, 139 sa->sa_reg[0].sbr_slot, 140 sa->sa_reg[0].sbr_offset, 141 sa->sa_reg[0].sbr_size, 142 BUS_SPACE_MAP_LINEAR, 0, &sc->sc_regs) != 0) { 143 printf("%s: attach: cannot map registers\n", self->dv_xname); 144 return; 145 } 146 147 /* 148 * This device's "register space 1" is just a buffer where the 149 * Lance ring-buffers can be stored. Note the buffer's location 150 * and size, so the child driver can pick them up. 151 */ 152 if (sbus_bus_map(sa->sa_bustag, 153 sa->sa_reg[1].sbr_slot, 154 sa->sa_reg[1].sbr_offset, 155 sa->sa_reg[1].sbr_size, 156 BUS_SPACE_MAP_LINEAR, 0, &bh) != 0) { 157 printf("%s: attach: cannot map registers\n", self->dv_xname); 158 return; 159 } 160 sc->sc_buffer = (caddr_t)(u_long)bh; 161 sc->sc_bufsiz = (bus_size_t)sa->sa_reg[1].sbr_size; 162 163 /* Get number of on-board channels */ 164 sc->sc_nchannels = getpropint(node, "#channels", -1); 165 if (sc->sc_nchannels == -1) { 166 printf(": no channels\n"); 167 return; 168 } 169 170 /* 171 * Get transfer burst size from PROM 172 */ 173 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 174 if (sbusburst == 0) 175 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 176 177 sc->sc_burst = getpropint(node, "burst-sizes", -1); 178 if (sc->sc_burst == -1) 179 /* take SBus burst sizes */ 180 sc->sc_burst = sbusburst; 181 182 /* Clamp at parent's burst sizes */ 183 sc->sc_burst &= sbusburst; 184 185 sbus_establish(&sc->sc_sd, &sc->sc_dev); 186 187 /* 188 * Collect address translations from the OBP. 189 */ 190 error = getprop(node, "ranges", sizeof(struct sbus_range), 191 &sc->sc_nrange, (void **)&sc->sc_range); 192 switch (error) { 193 case 0: 194 break; 195 case ENOENT: 196 default: 197 panic("%s: error getting ranges property", self->dv_xname); 198 } 199 200 /* Allocate a bus tag */ 201 sbt = (bus_space_tag_t) 202 malloc(sizeof(struct sparc_bus_space_tag), M_DEVBUF, M_NOWAIT); 203 if (sbt == NULL) { 204 printf("%s: attach: out of memory\n", self->dv_xname); 205 return; 206 } 207 208 bzero(sbt, sizeof *sbt); 209 sbt->cookie = sc; 210 sbt->parent = sc->sc_bustag; 211 sbt->sparc_bus_map = qec_bus_map; 212 sbt->sparc_intr_establish = qec_intr_establish; 213 214 /* 215 * Save interrupt information for use in our qec_intr_establish() 216 * function below. Apparently, the intr level for the quad 217 * ethernet board (qe) is stored in the QEC node rather then 218 * separately in each of the QE nodes. 219 * 220 * XXX - qe.c should call bus_intr_establish() with `level = 0'.. 221 * XXX - maybe we should have our own attach args for all that. 222 */ 223 sc->sc_intr = sa->sa_intr; 224 225 printf(": %dK memory\n", sc->sc_bufsiz / 1024); 226 227 qec_init(sc); 228 229 /* search through children */ 230 for (node = firstchild(node); node; node = nextsibling(node)) { 231 struct sbus_attach_args sa; 232 233 sbus_setup_attach_args((struct sbus_softc *)parent, 234 sbt, sc->sc_dmatag, node, &sa); 235 (void)config_found(&sc->sc_dev, (void *)&sa, qecprint); 236 sbus_destroy_attach_args(&sa); 237 } 238} 239 240int 241qec_bus_map(t, btype, offset, size, flags, vaddr, hp) 242 bus_space_tag_t t; 243 bus_type_t btype; 244 bus_addr_t offset; 245 bus_size_t size; 246 int flags; 247 vaddr_t vaddr; 248 bus_space_handle_t *hp; 249{ 250 struct qec_softc *sc = t->cookie; 251 int slot = btype; 252 int i; 253 254 for (i = 0; i < sc->sc_nrange; i++) { 255 bus_addr_t paddr; 256 bus_type_t iospace; 257 258 if (sc->sc_range[i].cspace != slot) 259 continue; 260 261 /* We've found the connection to the parent bus */ 262 paddr = sc->sc_range[i].poffset + offset; 263 iospace = sc->sc_range[i].pspace; 264 return (bus_space_map2(sc->sc_bustag, iospace, paddr, 265 size, flags, vaddr, hp)); 266 } 267 268 return (EINVAL); 269} 270 271void * 272qec_intr_establish(t, pri, level, flags, handler, arg) 273 bus_space_tag_t t; 274 int pri; 275 int level; 276 int flags; 277 int (*handler)(void *); 278 void *arg; 279{ 280 struct qec_softc *sc = t->cookie; 281 282 if (pri == 0) { 283 /* 284 * qe.c calls bus_intr_establish() with `pri == 0' 285 * XXX - see also comment in qec_attach(). 286 */ 287 if (sc->sc_intr == NULL) { 288 printf("%s: warning: no interrupts\n", 289 sc->sc_dev.dv_xname); 290 return (NULL); 291 } 292 pri = sc->sc_intr->sbi_pri; 293 } 294 295 return (bus_intr_establish(t->parent, pri, level, flags, handler, arg)); 296} 297 298void 299qec_init(sc) 300 struct qec_softc *sc; 301{ 302 bus_space_tag_t t = sc->sc_bustag; 303 bus_space_handle_t qr = sc->sc_regs; 304 u_int32_t v, burst = 0, psize; 305 int i; 306 307 /* First, reset the controller */ 308 bus_space_write_4(t, qr, QEC_QRI_CTRL, QEC_CTRL_RESET); 309 for (i = 0; i < 1000; i++) { 310 DELAY(100); 311 v = bus_space_read_4(t, qr, QEC_QRI_CTRL); 312 if ((v & QEC_CTRL_RESET) == 0) 313 break; 314 } 315 316 /* 317 * Cut available buffer size into receive and transmit buffers. 318 * XXX - should probably be done in be & qe driver... 319 */ 320 v = sc->sc_msize = sc->sc_bufsiz / sc->sc_nchannels; 321 bus_space_write_4(t, qr, QEC_QRI_MSIZE, v); 322 323 v = sc->sc_rsize = sc->sc_bufsiz / (sc->sc_nchannels * 2); 324 bus_space_write_4(t, qr, QEC_QRI_RSIZE, v); 325 bus_space_write_4(t, qr, QEC_QRI_TSIZE, v); 326 327 psize = sc->sc_nchannels == 1 ? QEC_PSIZE_2048 : 0; 328 bus_space_write_4(t, qr, QEC_QRI_PSIZE, psize); 329 330 if (sc->sc_burst & SBUS_BURST_64) 331 burst = QEC_CTRL_B64; 332 else if (sc->sc_burst & SBUS_BURST_32) 333 burst = QEC_CTRL_B32; 334 else 335 burst = QEC_CTRL_B16; 336 337 v = bus_space_read_4(t, qr, QEC_QRI_CTRL); 338 v = (v & QEC_CTRL_MODEMASK) | burst; 339 bus_space_write_4(t, qr, QEC_QRI_CTRL, v); 340} 341 342/* 343 * Common routine to initialize the QEC packet ring buffer. 344 * Called from be & qe drivers. 345 */ 346void 347qec_meminit(qr, pktbufsz) 348 struct qec_ring *qr; 349 unsigned int pktbufsz; 350{ 351 bus_addr_t txbufdma, rxbufdma; 352 bus_addr_t dma; 353 caddr_t p; 354 unsigned int ntbuf, nrbuf, i; 355 356 p = qr->rb_membase; 357 dma = qr->rb_dmabase; 358 359 ntbuf = qr->rb_ntbuf; 360 nrbuf = qr->rb_nrbuf; 361 362 /* 363 * Allocate transmit descriptors 364 */ 365 qr->rb_txd = (struct qec_xd *)p; 366 qr->rb_txddma = dma; 367 p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 368 dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 369 370 /* 371 * Allocate receive descriptors 372 */ 373 qr->rb_rxd = (struct qec_xd *)p; 374 qr->rb_rxddma = dma; 375 p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 376 dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd); 377 378 379 /* 380 * Allocate transmit buffers 381 */ 382 qr->rb_txbuf = p; 383 txbufdma = dma; 384 p += ntbuf * pktbufsz; 385 dma += ntbuf * pktbufsz; 386 387 /* 388 * Allocate receive buffers 389 */ 390 qr->rb_rxbuf = p; 391 rxbufdma = dma; 392 p += nrbuf * pktbufsz; 393 dma += nrbuf * pktbufsz; 394 395 /* 396 * Initialize transmit buffer descriptors 397 */ 398 for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) { 399 qr->rb_txd[i].xd_addr = (u_int32_t) 400 (txbufdma + (i % ntbuf) * pktbufsz); 401 qr->rb_txd[i].xd_flags = 0; 402 } 403 404 /* 405 * Initialize receive buffer descriptors 406 */ 407 for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) { 408 qr->rb_rxd[i].xd_addr = (u_int32_t) 409 (rxbufdma + (i % nrbuf) * pktbufsz); 410 qr->rb_rxd[i].xd_flags = (i < nrbuf) 411 ? QEC_XD_OWN | (pktbufsz & QEC_XD_LENGTH) 412 : 0; 413 } 414 415 qr->rb_tdhead = qr->rb_tdtail = 0; 416 qr->rb_td_nbusy = 0; 417 qr->rb_rdtail = 0; 418} 419