esp_sbus.c revision 1.3
1/* $OpenBSD: esp_sbus.c,v 1.3 2001/09/25 23:58:15 jason Exp $ */ 2/* $NetBSD: esp_sbus.c,v 1.14 2001/04/25 17:53:37 bouyer Exp $ */ 3 4/*- 5 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 10 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41#include <sys/types.h> 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/device.h> 45#include <sys/buf.h> 46#include <sys/malloc.h> 47 48#include <scsi/scsi_all.h> 49#include <scsi/scsiconf.h> 50#include <scsi/scsi_message.h> 51 52#include <machine/bus.h> 53#include <machine/intr.h> 54#include <machine/autoconf.h> 55 56#include <dev/ic/lsi64854reg.h> 57#include <dev/ic/lsi64854var.h> 58 59#include <dev/ic/ncr53c9xreg.h> 60#include <dev/ic/ncr53c9xvar.h> 61 62#include <dev/sbus/sbusvar.h> 63 64struct scsi_adapter esp_switch = { 65 ncr53c9x_scsi_cmd, 66 minphys, /* no max at this level; handled by DMA code */ 67 NULL, 68 NULL, 69}; 70 71struct scsi_device esp_dev = { 72 NULL, /* Use default error handler */ 73 NULL, /* have a queue, served by this */ 74 NULL, /* have no async handler */ 75 NULL, /* Use default 'done' routine */ 76}; 77 78/* #define ESP_SBUS_DEBUG */ 79 80struct esp_softc { 81 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 82 struct sbusdev sc_sd; /* sbus device */ 83 84 bus_space_tag_t sc_bustag; 85 bus_dma_tag_t sc_dmatag; 86 87 bus_space_handle_t sc_reg; /* the registers */ 88 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 89 90 int sc_pri; /* SBUS priority */ 91}; 92 93void espattach_sbus __P((struct device *, struct device *, void *)); 94void espattach_dma __P((struct device *, struct device *, void *)); 95int espmatch_sbus __P((struct device *, void *, void *)); 96 97 98/* Linkup to the rest of the kernel */ 99struct cfattach esp_sbus_ca = { 100 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 101}; 102struct cfattach esp_dma_ca = { 103 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 104}; 105 106/* 107 * Functions and the switch for the MI code. 108 */ 109static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 110static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 111static u_char esp_rdreg1 __P((struct ncr53c9x_softc *, int)); 112static void esp_wrreg1 __P((struct ncr53c9x_softc *, int, u_char)); 113static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 114static void esp_dma_reset __P((struct ncr53c9x_softc *)); 115static int esp_dma_intr __P((struct ncr53c9x_softc *)); 116static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 117 size_t *, int, size_t *)); 118static void esp_dma_go __P((struct ncr53c9x_softc *)); 119static void esp_dma_stop __P((struct ncr53c9x_softc *)); 120static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 121 122static struct ncr53c9x_glue esp_sbus_glue = { 123 esp_read_reg, 124 esp_write_reg, 125 esp_dma_isintr, 126 esp_dma_reset, 127 esp_dma_intr, 128 esp_dma_setup, 129 esp_dma_go, 130 esp_dma_stop, 131 esp_dma_isactive, 132 NULL, /* gl_clear_latched_intr */ 133}; 134 135static struct ncr53c9x_glue esp_sbus_glue1 = { 136 esp_rdreg1, 137 esp_wrreg1, 138 esp_dma_isintr, 139 esp_dma_reset, 140 esp_dma_intr, 141 esp_dma_setup, 142 esp_dma_go, 143 esp_dma_stop, 144 esp_dma_isactive, 145 NULL, /* gl_clear_latched_intr */ 146}; 147 148static void espattach __P((struct esp_softc *, struct ncr53c9x_glue *)); 149 150int 151espmatch_sbus(parent, vcf, aux) 152 struct device *parent; 153 void *vcf; 154 void *aux; 155{ 156 struct cfdata *cf = vcf; 157 int rv; 158 struct sbus_attach_args *sa = aux; 159 160 if (strcmp("SUNW,fas", sa->sa_name) == 0) 161 return 1; 162 163 rv = (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0 || 164 strcmp("ptscII", sa->sa_name) == 0); 165 return (rv); 166} 167 168void 169espattach_sbus(parent, self, aux) 170 struct device *parent, *self; 171 void *aux; 172{ 173 struct esp_softc *esc = (void *)self; 174 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 175 struct sbus_attach_args *sa = aux; 176 struct lsi64854_softc *lsc; 177 int burst, sbusburst; 178 179 esc->sc_bustag = sa->sa_bustag; 180 esc->sc_dmatag = sa->sa_dmatag; 181 182 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 183 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 184 if (sc->sc_freq < 0) 185 sc->sc_freq = ((struct sbus_softc *) 186 sc->sc_dev.dv_parent)->sc_clockfreq; 187 188#ifdef ESP_SBUS_DEBUG 189 printf("%s: espattach_sbus: sc_id %d, freq %d\n", 190 self->dv_xname, sc->sc_id, sc->sc_freq); 191#endif 192 193 if (strcmp("SUNW,fas", sa->sa_name) == 0) { 194 195 /* 196 * fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x) 197 */ 198 if (sa->sa_nreg != 2) { 199 printf("%s: %d register spaces\n", self->dv_xname, sa->sa_nreg); 200 return; 201 } 202 203 /* 204 * allocate space for dma, in SUNW,fas there are no separate 205 * dma device 206 */ 207 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT); 208 209 if (lsc == NULL) { 210 printf("%s: out of memory (lsi64854_softc)\n", 211 self->dv_xname); 212 return; 213 } 214 esc->sc_dma = lsc; 215 216 lsc->sc_bustag = sa->sa_bustag; 217 lsc->sc_dmatag = sa->sa_dmatag; 218 219 bcopy(sc->sc_dev.dv_xname, lsc->sc_dev.dv_xname, 220 sizeof (lsc->sc_dev.dv_xname)); 221 222 /* Map dma registers */ 223 if (bus_space_map2(sa->sa_bustag, 224 sa->sa_reg[0].sbr_slot, 225 sa->sa_reg[0].sbr_offset, 226 sa->sa_reg[0].sbr_size, 227 BUS_SPACE_MAP_LINEAR, 228 0, &lsc->sc_regs) != 0) { 229 printf("%s: cannot map dma registers\n", self->dv_xname); 230 return; 231 } 232 233 /* 234 * XXX is this common(from bpp.c), the same in dma_sbus...etc. 235 * 236 * Get transfer burst size from PROM and plug it into the 237 * controller registers. This is needed on the Sun4m; do 238 * others need it too? 239 */ 240 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 241 if (sbusburst == 0) 242 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 243 244 burst = getpropint(sa->sa_node, "burst-sizes", -1); 245 246#if ESP_SBUS_DEBUG 247 printf("espattach_sbus: burst 0x%x, sbus 0x%x\n", 248 burst, sbusburst); 249#endif 250 251 if (burst == -1) 252 /* take SBus burst sizes */ 253 burst = sbusburst; 254 255 /* Clamp at parent's burst sizes */ 256 burst &= sbusburst; 257 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 258 (burst & SBUS_BURST_16) ? 16 : 0; 259 260 lsc->sc_channel = L64854_CHANNEL_SCSI; 261 lsc->sc_client = sc; 262 263 lsi64854_attach(lsc); 264 265 /* 266 * map SCSI core registers 267 */ 268 if (sbus_bus_map(sa->sa_bustag, 269 sa->sa_reg[1].sbr_slot, 270 sa->sa_reg[1].sbr_offset, 271 sa->sa_reg[1].sbr_size, 272 BUS_SPACE_MAP_LINEAR, 273 0, &esc->sc_reg) != 0) { 274 printf("%s: cannot map scsi core registers\n", 275 self->dv_xname); 276 return; 277 } 278 279 if (sa->sa_nintr == 0) { 280 printf("%s: no interrupt property\n", self->dv_xname); 281 return; 282 } 283 284 esc->sc_pri = sa->sa_pri; 285 286 /* add me to the sbus structures */ 287 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 288 sbus_establish(&esc->sc_sd, &sc->sc_dev); 289 290 printf("%s", self->dv_xname); 291 espattach(esc, &esp_sbus_glue); 292 293 return; 294 } 295 296 /* 297 * Find the DMA by poking around the dma device structures 298 * 299 * What happens here is that if the dma driver has not been 300 * configured, then this returns a NULL pointer. Then when the 301 * dma actually gets configured, it does the opposing test, and 302 * if the sc->sc_esp field in it's softc is NULL, then tries to 303 * find the matching esp driver. 304 */ 305 esc->sc_dma = (struct lsi64854_softc *) 306 getdevunit("dma", sc->sc_dev.dv_unit); 307 308 /* 309 * and a back pointer to us, for DMA 310 */ 311 if (esc->sc_dma) 312 esc->sc_dma->sc_client = sc; 313 else { 314 printf("\n"); 315 panic("espattach: no dma found"); 316 } 317 318 /* 319 * The `ESC' DMA chip must be reset before we can access 320 * the esp registers. 321 */ 322 if (esc->sc_dma->sc_rev == DMAREV_ESC) 323 DMA_RESET(esc->sc_dma); 324 325 /* 326 * Map my registers in, if they aren't already in virtual 327 * address space. 328 */ 329 if (sa->sa_npromvaddrs) 330 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 331 else { 332 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 333 sa->sa_offset, 334 sa->sa_size, 335 BUS_SPACE_MAP_LINEAR, 336 0, &esc->sc_reg) != 0) { 337 printf("%s @ sbus: cannot map registers\n", 338 self->dv_xname); 339 return; 340 } 341 } 342 343 if (sa->sa_nintr == 0) { 344 /* 345 * No interrupt properties: we quit; this might 346 * happen on e.g. a Sparc X terminal. 347 */ 348 printf("\n%s: no interrupt property\n", self->dv_xname); 349 return; 350 } 351 352 esc->sc_pri = sa->sa_pri; 353 354 /* add me to the sbus structures */ 355 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 356 sbus_establish(&esc->sc_sd, &sc->sc_dev); 357 358 if (strcmp("ptscII", sa->sa_name) == 0) { 359 espattach(esc, &esp_sbus_glue1); 360 } else { 361 espattach(esc, &esp_sbus_glue); 362 } 363} 364 365void 366espattach_dma(parent, self, aux) 367 struct device *parent, *self; 368 void *aux; 369{ 370 struct esp_softc *esc = (void *)self; 371 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 372 struct sbus_attach_args *sa = aux; 373 374 if (strcmp("ptscII", sa->sa_name) == 0) { 375 return; 376 } 377 378 esc->sc_bustag = sa->sa_bustag; 379 esc->sc_dmatag = sa->sa_dmatag; 380 381 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 382 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 383 384 esc->sc_dma = (struct lsi64854_softc *)parent; 385 esc->sc_dma->sc_client = sc; 386 387 /* 388 * Map my registers in, if they aren't already in virtual 389 * address space. 390 */ 391 if (sa->sa_npromvaddrs) 392 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 393 else { 394 if (bus_space_map2(sa->sa_bustag, 395 sa->sa_slot, 396 sa->sa_offset, 397 sa->sa_size, 398 BUS_SPACE_MAP_LINEAR, 399 0, &esc->sc_reg) != 0) { 400 printf("%s @ dma: cannot map registers\n", 401 self->dv_xname); 402 return; 403 } 404 } 405 406 if (sa->sa_nintr == 0) { 407 /* 408 * No interrupt properties: we quit; this might 409 * happen on e.g. a Sparc X terminal. 410 */ 411 printf("\n%s: no interrupt property\n", self->dv_xname); 412 return; 413 } 414 415 esc->sc_pri = sa->sa_pri; 416 417 /* Assume SBus is grandparent */ 418 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 419 sbus_establish(&esc->sc_sd, parent); 420 421 espattach(esc, &esp_sbus_glue); 422} 423 424 425/* 426 * Attach this instance, and then all the sub-devices 427 */ 428void 429espattach(esc, gluep) 430 struct esp_softc *esc; 431 struct ncr53c9x_glue *gluep; 432{ 433 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 434 void *icookie; 435 unsigned int uid = 0; 436 437 /* 438 * Set up glue for MI code early; we use some of it here. 439 */ 440 sc->sc_glue = gluep; 441 442 /* gimme Mhz */ 443 sc->sc_freq /= 1000000; 444 445 /* 446 * XXX More of this should be in ncr53c9x_attach(), but 447 * XXX should we really poke around the chip that much in 448 * XXX the MI code? Think about this more... 449 */ 450 451 /* 452 * It is necessary to try to load the 2nd config register here, 453 * to find out what rev the esp chip is, else the ncr53c9x_reset 454 * will not set up the defaults correctly. 455 */ 456 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 457 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 458 sc->sc_cfg3 = NCRCFG3_CDB; 459 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 460 461 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 462 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 463 sc->sc_rev = NCR_VARIANT_ESP100; 464 } else { 465 sc->sc_cfg2 = NCRCFG2_SCSI2; 466 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 467 sc->sc_cfg3 = 0; 468 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 469 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 470 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 471 if (NCR_READ_REG(sc, NCR_CFG3) != 472 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 473 sc->sc_rev = NCR_VARIANT_ESP100A; 474 } else { 475 /* NCRCFG2_FE enables > 64K transfers */ 476 sc->sc_cfg2 |= NCRCFG2_FE; 477 sc->sc_cfg3 = 0; 478 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 479 sc->sc_rev = NCR_VARIANT_ESP200; 480 481 /* XXX spec says it's valid after power up or chip reset */ 482 uid = NCR_READ_REG(sc, NCR_UID); 483 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 484 sc->sc_rev = NCR_VARIANT_FAS366; 485 } 486 } 487 488#ifdef ESP_SBUS_DEBUG 489 printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid); 490#endif 491 492 /* 493 * XXX minsync and maxxfer _should_ be set up in MI code, 494 * XXX but it appears to have some dependency on what sort 495 * XXX of DMA we're hooked up to, etc. 496 */ 497 498 /* 499 * This is the value used to start sync negotiations 500 * Note that the NCR register "SYNCTP" is programmed 501 * in "clocks per byte", and has a minimum value of 4. 502 * The SCSI period used in negotiation is one-fourth 503 * of the time (in nanoseconds) needed to transfer one byte. 504 * Since the chip's clock is given in MHz, we have the following 505 * formula: 4 * period = (1000 / freq) * 4 506 */ 507 sc->sc_minsync = 1000 / sc->sc_freq; 508 509 /* 510 * Alas, we must now modify the value a bit, because it's 511 * only valid when can switch on FASTCLK and FASTSCSI bits 512 * in config register 3... 513 */ 514 switch (sc->sc_rev) { 515 case NCR_VARIANT_ESP100: 516 sc->sc_maxxfer = 64 * 1024; 517 sc->sc_minsync = 0; /* No synch on old chip? */ 518 break; 519 520 case NCR_VARIANT_ESP100A: 521 sc->sc_maxxfer = 64 * 1024; 522 /* Min clocks/byte is 5 */ 523 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 524 break; 525 526 case NCR_VARIANT_ESP200: 527 case NCR_VARIANT_FAS366: 528 sc->sc_maxxfer = 16 * 1024 * 1024; 529 /* XXX - do actually set FAST* bits */ 530 break; 531 } 532 533 /* Establish interrupt channel */ 534 icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO, 0, 535 ncr53c9x_intr, sc); 536 537 /* register interrupt stats */ 538 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 539 540 /* Turn on target selection using the `dma' method */ 541 if (sc->sc_rev != NCR_VARIANT_FAS366) 542 sc->sc_features |= NCR_F_DMASELECT; 543 544 /* Do the common parts of attachment. */ 545 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 546} 547 548/* 549 * Glue functions. 550 */ 551 552#ifdef ESP_SBUS_DEBUG 553int esp_sbus_debug = 0; 554 555static struct { 556 char *r_name; 557 int r_flag; 558} esp__read_regnames [] = { 559 { "TCL", 0}, /* 0/00 */ 560 { "TCM", 0}, /* 1/04 */ 561 { "FIFO", 0}, /* 2/08 */ 562 { "CMD", 0}, /* 3/0c */ 563 { "STAT", 0}, /* 4/10 */ 564 { "INTR", 0}, /* 5/14 */ 565 { "STEP", 0}, /* 6/18 */ 566 { "FFLAGS", 1}, /* 7/1c */ 567 { "CFG1", 1}, /* 8/20 */ 568 { "STAT2", 0}, /* 9/24 */ 569 { "CFG4", 1}, /* a/28 */ 570 { "CFG2", 1}, /* b/2c */ 571 { "CFG3", 1}, /* c/30 */ 572 { "-none", 1}, /* d/34 */ 573 { "TCH", 1}, /* e/38 */ 574 { "TCX", 1}, /* f/3c */ 575}; 576 577static struct { 578 char *r_name; 579 int r_flag; 580} esp__write_regnames[] = { 581 { "TCL", 1}, /* 0/00 */ 582 { "TCM", 1}, /* 1/04 */ 583 { "FIFO", 0}, /* 2/08 */ 584 { "CMD", 0}, /* 3/0c */ 585 { "SELID", 1}, /* 4/10 */ 586 { "TIMEOUT", 1}, /* 5/14 */ 587 { "SYNCTP", 1}, /* 6/18 */ 588 { "SYNCOFF", 1}, /* 7/1c */ 589 { "CFG1", 1}, /* 8/20 */ 590 { "CCF", 1}, /* 9/24 */ 591 { "TEST", 1}, /* a/28 */ 592 { "CFG2", 1}, /* b/2c */ 593 { "CFG3", 1}, /* c/30 */ 594 { "-none", 1}, /* d/34 */ 595 { "TCH", 1}, /* e/38 */ 596 { "TCX", 1}, /* f/3c */ 597}; 598#endif 599 600u_char 601esp_read_reg(sc, reg) 602 struct ncr53c9x_softc *sc; 603 int reg; 604{ 605 struct esp_softc *esc = (struct esp_softc *)sc; 606 u_char v; 607 608 v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4); 609#ifdef ESP_SBUS_DEBUG 610 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 611 printf("RD:%x <%s> %x\n", reg * 4, 612 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 613#endif 614 return v; 615} 616 617void 618esp_write_reg(sc, reg, v) 619 struct ncr53c9x_softc *sc; 620 int reg; 621 u_char v; 622{ 623 struct esp_softc *esc = (struct esp_softc *)sc; 624 625#ifdef ESP_SBUS_DEBUG 626 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 627 printf("WR:%x <%s> %x\n", reg * 4, 628 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 629#endif 630 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 631} 632 633u_char 634esp_rdreg1(sc, reg) 635 struct ncr53c9x_softc *sc; 636 int reg; 637{ 638 struct esp_softc *esc = (struct esp_softc *)sc; 639 640 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg)); 641} 642 643void 644esp_wrreg1(sc, reg, v) 645 struct ncr53c9x_softc *sc; 646 int reg; 647 u_char v; 648{ 649 struct esp_softc *esc = (struct esp_softc *)sc; 650 651 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 652} 653 654int 655esp_dma_isintr(sc) 656 struct ncr53c9x_softc *sc; 657{ 658 struct esp_softc *esc = (struct esp_softc *)sc; 659 660 return (DMA_ISINTR(esc->sc_dma)); 661} 662 663void 664esp_dma_reset(sc) 665 struct ncr53c9x_softc *sc; 666{ 667 struct esp_softc *esc = (struct esp_softc *)sc; 668 669 DMA_RESET(esc->sc_dma); 670} 671 672int 673esp_dma_intr(sc) 674 struct ncr53c9x_softc *sc; 675{ 676 struct esp_softc *esc = (struct esp_softc *)sc; 677 678 return (DMA_INTR(esc->sc_dma)); 679} 680 681int 682esp_dma_setup(sc, addr, len, datain, dmasize) 683 struct ncr53c9x_softc *sc; 684 caddr_t *addr; 685 size_t *len; 686 int datain; 687 size_t *dmasize; 688{ 689 struct esp_softc *esc = (struct esp_softc *)sc; 690 691 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 692} 693 694void 695esp_dma_go(sc) 696 struct ncr53c9x_softc *sc; 697{ 698 struct esp_softc *esc = (struct esp_softc *)sc; 699 700 DMA_GO(esc->sc_dma); 701} 702 703void 704esp_dma_stop(sc) 705 struct ncr53c9x_softc *sc; 706{ 707 struct esp_softc *esc = (struct esp_softc *)sc; 708 u_int32_t csr; 709 710 csr = L64854_GCSR(esc->sc_dma); 711 csr &= ~D_EN_DMA; 712 L64854_SCSR(esc->sc_dma, csr); 713} 714 715int 716esp_dma_isactive(sc) 717 struct ncr53c9x_softc *sc; 718{ 719 struct esp_softc *esc = (struct esp_softc *)sc; 720 721 return (DMA_ISACTIVE(esc->sc_dma)); 722} 723 724#if defined(DDB) && defined(notyet) 725#include <machine/db_machdep.h> 726#include <ddb/db_output.h> 727 728void db_esp __P((db_expr_t, int, db_expr_t, char*)); 729 730void 731db_esp(addr, have_addr, count, modif) 732 db_expr_t addr; 733 int have_addr; 734 db_expr_t count; 735 char *modif; 736{ 737 struct ncr53c9x_softc *sc; 738 struct ncr53c9x_ecb *ecb; 739 struct ncr53c9x_linfo *li; 740 int u, t, i; 741 742 for (u=0; u<10; u++) { 743 sc = (struct ncr53c9x_softc *) 744 getdevunit("esp", u); 745 if (!sc) continue; 746 747 db_printf("esp%d: nexus %p phase %x prev %x dp %p dleft %lx ify %x\n", 748 u, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 749 sc->sc_dp, sc->sc_dleft, sc->sc_msgify); 750 db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n", 751 sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0], 752 sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3], 753 sc->sc_imess[0]); 754 db_printf("ready: "); 755 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 756 db_printf("ecb %p ", ecb); 757 if (ecb == ecb->chain.tqe_next) { 758 db_printf("\nWARNING: tailq loop on ecb %p", ecb); 759 break; 760 } 761 } 762 db_printf("\n"); 763 764 for (t=0; t<NCR_NTARG; t++) { 765 LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) { 766 db_printf("t%d lun %d untagged %p busy %d used %x\n", 767 t, (int)li->lun, li->untagged, li->busy, 768 li->used); 769 for (i=0; i<256; i++) 770 if ((ecb = li->queued[i])) { 771 db_printf("ecb %p tag %x\n", ecb, i); 772 } 773 } 774 } 775 } 776} 777#endif 778 779