esp_sbus.c revision 1.26
1/* $OpenBSD: esp_sbus.c,v 1.26 2022/03/13 13:34:54 mpi Exp $ */ 2/* $NetBSD: esp_sbus.c,v 1.14 2001/04/25 17:53:37 bouyer Exp $ */ 3 4/*- 5 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 10 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/device.h> 37#include <sys/buf.h> 38#include <sys/malloc.h> 39 40#include <scsi/scsi_all.h> 41#include <scsi/scsiconf.h> 42#include <scsi/scsi_message.h> 43 44#include <machine/bus.h> 45#include <machine/intr.h> 46#include <machine/autoconf.h> 47 48#include <dev/ic/lsi64854reg.h> 49#include <dev/ic/lsi64854var.h> 50 51#include <dev/ic/ncr53c9xreg.h> 52#include <dev/ic/ncr53c9xvar.h> 53 54#include <dev/sbus/sbusvar.h> 55 56/* #define ESP_SBUS_DEBUG */ 57 58static int esp_unit_offset; 59 60struct esp_softc { 61 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 62 63 bus_space_tag_t sc_bustag; 64 bus_dma_tag_t sc_dmatag; 65 66 bus_space_handle_t sc_reg; /* the registers */ 67 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 68 69 int sc_pri; /* SBUS priority */ 70}; 71 72void espattach_sbus(struct device *, struct device *, void *); 73void espattach_dma(struct device *, struct device *, void *); 74int espmatch_sbus(struct device *, void *, void *); 75 76 77/* Linkup to the rest of the kernel */ 78const struct cfattach esp_sbus_ca = { 79 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 80}; 81const struct cfattach esp_dma_ca = { 82 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 83}; 84 85/* 86 * Functions and the switch for the MI code. 87 */ 88static u_char esp_read_reg(struct ncr53c9x_softc *, int); 89static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 90static u_char esp_rdreg1(struct ncr53c9x_softc *, int); 91static void esp_wrreg1(struct ncr53c9x_softc *, int, u_char); 92static int esp_dma_isintr(struct ncr53c9x_softc *); 93static void esp_dma_reset(struct ncr53c9x_softc *); 94static int esp_dma_intr(struct ncr53c9x_softc *); 95static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, 96 size_t *, int, size_t *); 97static void esp_dma_go(struct ncr53c9x_softc *); 98static void esp_dma_stop(struct ncr53c9x_softc *); 99static int esp_dma_isactive(struct ncr53c9x_softc *); 100 101static struct ncr53c9x_glue esp_sbus_glue = { 102 esp_read_reg, 103 esp_write_reg, 104 esp_dma_isintr, 105 esp_dma_reset, 106 esp_dma_intr, 107 esp_dma_setup, 108 esp_dma_go, 109 esp_dma_stop, 110 esp_dma_isactive, 111 NULL, /* gl_clear_latched_intr */ 112}; 113 114static struct ncr53c9x_glue esp_sbus_glue1 = { 115 esp_rdreg1, 116 esp_wrreg1, 117 esp_dma_isintr, 118 esp_dma_reset, 119 esp_dma_intr, 120 esp_dma_setup, 121 esp_dma_go, 122 esp_dma_stop, 123 esp_dma_isactive, 124 NULL, /* gl_clear_latched_intr */ 125}; 126 127static void espattach(struct esp_softc *, struct ncr53c9x_glue *); 128 129int 130espmatch_sbus(struct device *parent, void *vcf, void *aux) 131{ 132 struct cfdata *cf = vcf; 133 int rv; 134 struct sbus_attach_args *sa = aux; 135 136 if (strcmp("SUNW,fas", sa->sa_name) == 0) 137 return 1; 138 139 rv = (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0 || 140 strcmp("ptscII", sa->sa_name) == 0); 141 return (rv); 142} 143 144void 145espattach_sbus(struct device *parent, struct device *self, void *aux) 146{ 147 struct esp_softc *esc = (void *)self; 148 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 149 struct sbus_attach_args *sa = aux; 150 struct lsi64854_softc *lsc; 151 int burst, sbusburst; 152 153 esc->sc_bustag = sa->sa_bustag; 154 esc->sc_dmatag = sa->sa_dmatag; 155 156 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 157 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 158 if (sc->sc_freq < 0) 159 sc->sc_freq = sa->sa_frequency; 160 161#ifdef ESP_SBUS_DEBUG 162 printf("%s: espattach_sbus: sc_id %d, freq %d\n", 163 self->dv_xname, sc->sc_id, sc->sc_freq); 164#endif 165 166 if (strcmp("SUNW,fas", sa->sa_name) == 0) { 167 /* 168 * offset searches for other esp/dma devices. 169 */ 170 esp_unit_offset++; 171 172 /* 173 * fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x) 174 */ 175 if (sa->sa_nreg != 2) { 176 printf("%s: %d register spaces\n", self->dv_xname, sa->sa_nreg); 177 return; 178 } 179 180 /* 181 * allocate space for dma, in SUNW,fas there are no separate 182 * dma device 183 */ 184 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT); 185 186 if (lsc == NULL) { 187 printf("%s: out of memory (lsi64854_softc)\n", 188 self->dv_xname); 189 return; 190 } 191 esc->sc_dma = lsc; 192 193 lsc->sc_bustag = sa->sa_bustag; 194 lsc->sc_dmatag = sa->sa_dmatag; 195 196 bcopy(sc->sc_dev.dv_xname, lsc->sc_dev.dv_xname, 197 sizeof (lsc->sc_dev.dv_xname)); 198 199 /* Map dma registers */ 200 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, 201 sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size, 202 0, 0, &lsc->sc_regs) != 0) { 203 printf("%s: cannot map dma registers\n", self->dv_xname); 204 return; 205 } 206 207 /* 208 * XXX is this common(from bpp.c), the same in dma_sbus...etc. 209 * 210 * Get transfer burst size from PROM and plug it into the 211 * controller registers. This is needed on the Sun4m; do 212 * others need it too? 213 */ 214 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 215 if (sbusburst == 0) 216 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 217 218 burst = getpropint(sa->sa_node, "burst-sizes", -1); 219 220#ifdef ESP_SBUS_DEBUG 221 printf("espattach_sbus: burst 0x%x, sbus 0x%x\n", 222 burst, sbusburst); 223#endif 224 225 if (burst == -1) 226 /* take SBus burst sizes */ 227 burst = sbusburst; 228 229 /* Clamp at parent's burst sizes */ 230 burst &= sbusburst; 231 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 232 (burst & SBUS_BURST_16) ? 16 : 0; 233 234 lsc->sc_channel = L64854_CHANNEL_SCSI; 235 lsc->sc_client = sc; 236 237 lsi64854_attach(lsc); 238 239 /* 240 * map SCSI core registers 241 */ 242 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot, 243 sa->sa_reg[1].sbr_offset, sa->sa_reg[1].sbr_size, 244 0, 0, &esc->sc_reg) != 0) { 245 printf("%s: cannot map scsi core registers\n", 246 self->dv_xname); 247 return; 248 } 249 250 if (sa->sa_nintr == 0) { 251 printf("%s: no interrupt property\n", self->dv_xname); 252 return; 253 } 254 255 esc->sc_pri = sa->sa_pri; 256 257 printf("%s", self->dv_xname); 258 espattach(esc, &esp_sbus_glue); 259 260 return; 261 } 262 263 /* 264 * Find the DMA by poking around the dma device structures 265 * 266 * What happens here is that if the dma driver has not been 267 * configured, then this returns a NULL pointer. Then when the 268 * dma actually gets configured, it does the opposing test, and 269 * if the sc->sc_esp field in its softc is NULL, then tries to 270 * find the matching esp driver. 271 */ 272 esc->sc_dma = (struct lsi64854_softc *) 273 getdevunit("dma", sc->sc_dev.dv_unit - esp_unit_offset); 274 275 /* 276 * and a back pointer to us, for DMA 277 */ 278 if (esc->sc_dma) 279 esc->sc_dma->sc_client = sc; 280 else { 281 printf("\n"); 282 panic("espattach: no dma found"); 283 } 284 285 /* 286 * The `ESC' DMA chip must be reset before we can access 287 * the esp registers. 288 */ 289 if (esc->sc_dma->sc_rev == DMAREV_ESC) 290 DMA_RESET(esc->sc_dma); 291 292 /* 293 * Map my registers in, if they aren't already in virtual 294 * address space. 295 */ 296 if (sa->sa_npromvaddrs) { 297 if (bus_space_map(sa->sa_bustag, sa->sa_promvaddrs[0], 298 sa->sa_size, BUS_SPACE_MAP_PROMADDRESS, 299 &esc->sc_reg) != 0) { 300 printf("%s @ sbus: cannot map registers\n", 301 self->dv_xname); 302 return; 303 } 304 } else { 305 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 306 sa->sa_offset, sa->sa_size, 0, 0, &esc->sc_reg) != 0) { 307 printf("%s @ sbus: cannot map registers\n", 308 self->dv_xname); 309 return; 310 } 311 } 312 313 if (sa->sa_nintr == 0) { 314 /* 315 * No interrupt properties: we quit; this might 316 * happen on e.g. a Sparc X terminal. 317 */ 318 printf("\n%s: no interrupt property\n", self->dv_xname); 319 return; 320 } 321 322 esc->sc_pri = sa->sa_pri; 323 324 if (strcmp("ptscII", sa->sa_name) == 0) { 325 espattach(esc, &esp_sbus_glue1); 326 } else { 327 espattach(esc, &esp_sbus_glue); 328 } 329} 330 331void 332espattach_dma(struct device *parent, struct device *self, void *aux) 333{ 334 struct esp_softc *esc = (void *)self; 335 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 336 struct sbus_attach_args *sa = aux; 337 338 if (strcmp("ptscII", sa->sa_name) == 0) { 339 return; 340 } 341 342 esc->sc_bustag = sa->sa_bustag; 343 esc->sc_dmatag = sa->sa_dmatag; 344 345 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 346 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 347 348 esc->sc_dma = (struct lsi64854_softc *)parent; 349 esc->sc_dma->sc_client = sc; 350 351 /* 352 * Map my registers in, if they aren't already in virtual 353 * address space. 354 */ 355 if (sa->sa_npromvaddrs) { 356 if (bus_space_map(sa->sa_bustag, sa->sa_promvaddrs[0], 357 sa->sa_size /* ??? */, BUS_SPACE_MAP_PROMADDRESS, 358 &esc->sc_reg) != 0) { 359 printf("%s @ dma: cannot map registers\n", 360 self->dv_xname); 361 return; 362 } 363 } else { 364 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, sa->sa_offset, 365 sa->sa_size, 0, 0, &esc->sc_reg) != 0) { 366 printf("%s @ dma: cannot map registers\n", 367 self->dv_xname); 368 return; 369 } 370 } 371 372 if (sa->sa_nintr == 0) { 373 /* 374 * No interrupt properties: we quit; this might 375 * happen on e.g. a Sparc X terminal. 376 */ 377 printf("\n%s: no interrupt property\n", self->dv_xname); 378 return; 379 } 380 381 esc->sc_pri = sa->sa_pri; 382 383 espattach(esc, &esp_sbus_glue); 384} 385 386 387/* 388 * Attach this instance, and then all the sub-devices 389 */ 390void 391espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep) 392{ 393 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 394 void *icookie; 395 unsigned int uid = 0; 396 397 /* 398 * Set up glue for MI code early; we use some of it here. 399 */ 400 sc->sc_glue = gluep; 401 402 /* gimme MHz */ 403 sc->sc_freq /= 1000000; 404 405 /* 406 * XXX More of this should be in ncr53c9x_attach(), but 407 * XXX should we really poke around the chip that much in 408 * XXX the MI code? Think about this more... 409 */ 410 411 /* 412 * It is necessary to try to load the 2nd config register here, 413 * to find out what rev the esp chip is, else the ncr53c9x_reset 414 * will not set up the defaults correctly. 415 */ 416 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 417 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 418 sc->sc_cfg3 = NCRCFG3_CDB; 419 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 420 421 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 422 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 423 sc->sc_rev = NCR_VARIANT_ESP100; 424 } else { 425 sc->sc_cfg2 = NCRCFG2_SCSI2; 426 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 427 sc->sc_cfg3 = 0; 428 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 429 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 430 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 431 if (NCR_READ_REG(sc, NCR_CFG3) != 432 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 433 sc->sc_rev = NCR_VARIANT_ESP100A; 434 } else { 435 /* NCRCFG2_FE enables > 64K transfers */ 436 sc->sc_cfg2 |= NCRCFG2_FE; 437 sc->sc_cfg3 = 0; 438 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 439 sc->sc_rev = NCR_VARIANT_ESP200; 440 441 /* XXX spec says it's valid after power up or chip reset */ 442 uid = NCR_READ_REG(sc, NCR_UID); 443 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 444 sc->sc_rev = NCR_VARIANT_FAS366; 445 } 446 } 447 448#ifdef ESP_SBUS_DEBUG 449 printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid); 450#endif 451 452 /* 453 * XXX minsync and maxxfer _should_ be set up in MI code, 454 * XXX but it appears to have some dependency on what sort 455 * XXX of DMA we're hooked up to, etc. 456 */ 457 458 /* 459 * This is the value used to start sync negotiations 460 * Note that the NCR register "SYNCTP" is programmed 461 * in "clocks per byte", and has a minimum value of 4. 462 * The SCSI period used in negotiation is one-fourth 463 * of the time (in nanoseconds) needed to transfer one byte. 464 * Since the chip's clock is given in MHz, we have the following 465 * formula: 4 * period = (1000 / freq) * 4 466 */ 467 sc->sc_minsync = 1000 / sc->sc_freq; 468 469 /* 470 * Alas, we must now modify the value a bit, because it's 471 * only valid when can switch on FASTCLK and FASTSCSI bits 472 * in config register 3... 473 */ 474 switch (sc->sc_rev) { 475 case NCR_VARIANT_ESP100: 476 sc->sc_maxxfer = 64 * 1024; 477 sc->sc_minsync = 0; /* No synch on old chip? */ 478 break; 479 480 case NCR_VARIANT_ESP100A: 481 sc->sc_maxxfer = 64 * 1024; 482 /* Min clocks/byte is 5 */ 483 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 484 break; 485 486 case NCR_VARIANT_ESP200: 487 case NCR_VARIANT_FAS366: 488 sc->sc_maxxfer = 16 * 1024 * 1024; 489 /* XXX - do actually set FAST* bits */ 490 break; 491 } 492 493 /* Establish interrupt channel */ 494 icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO, 0, 495 ncr53c9x_intr, sc, sc->sc_dev.dv_xname); 496 497 /* Turn on target selection using the `dma' method */ 498 if (sc->sc_rev != NCR_VARIANT_FAS366) 499 sc->sc_features |= NCR_F_DMASELECT; 500 501 /* Do the common parts of attachment. */ 502 ncr53c9x_attach(sc); 503} 504 505/* 506 * Glue functions. 507 */ 508 509#ifdef ESP_SBUS_DEBUG 510int esp_sbus_debug = 0; 511 512static struct { 513 char *r_name; 514 int r_flag; 515} esp__read_regnames [] = { 516 { "TCL", 0}, /* 0/00 */ 517 { "TCM", 0}, /* 1/04 */ 518 { "FIFO", 0}, /* 2/08 */ 519 { "CMD", 0}, /* 3/0c */ 520 { "STAT", 0}, /* 4/10 */ 521 { "INTR", 0}, /* 5/14 */ 522 { "STEP", 0}, /* 6/18 */ 523 { "FFLAGS", 1}, /* 7/1c */ 524 { "CFG1", 1}, /* 8/20 */ 525 { "STAT2", 0}, /* 9/24 */ 526 { "CFG4", 1}, /* a/28 */ 527 { "CFG2", 1}, /* b/2c */ 528 { "CFG3", 1}, /* c/30 */ 529 { "-none", 1}, /* d/34 */ 530 { "TCH", 1}, /* e/38 */ 531 { "TCX", 1}, /* f/3c */ 532}; 533 534static struct { 535 char *r_name; 536 int r_flag; 537} esp__write_regnames[] = { 538 { "TCL", 1}, /* 0/00 */ 539 { "TCM", 1}, /* 1/04 */ 540 { "FIFO", 0}, /* 2/08 */ 541 { "CMD", 0}, /* 3/0c */ 542 { "SELID", 1}, /* 4/10 */ 543 { "TIMEOUT", 1}, /* 5/14 */ 544 { "SYNCTP", 1}, /* 6/18 */ 545 { "SYNCOFF", 1}, /* 7/1c */ 546 { "CFG1", 1}, /* 8/20 */ 547 { "CCF", 1}, /* 9/24 */ 548 { "TEST", 1}, /* a/28 */ 549 { "CFG2", 1}, /* b/2c */ 550 { "CFG3", 1}, /* c/30 */ 551 { "-none", 1}, /* d/34 */ 552 { "TCH", 1}, /* e/38 */ 553 { "TCX", 1}, /* f/3c */ 554}; 555#endif 556 557u_char 558esp_read_reg(struct ncr53c9x_softc *sc, int reg) 559{ 560 struct esp_softc *esc = (struct esp_softc *)sc; 561 u_char v; 562 563 v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4); 564#ifdef ESP_SBUS_DEBUG 565 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 566 printf("RD:%x <%s> %x\n", reg * 4, 567 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 568#endif 569 return v; 570} 571 572void 573esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v) 574{ 575 struct esp_softc *esc = (struct esp_softc *)sc; 576 577#ifdef ESP_SBUS_DEBUG 578 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 579 printf("WR:%x <%s> %x\n", reg * 4, 580 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 581#endif 582 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 583} 584 585u_char 586esp_rdreg1(struct ncr53c9x_softc *sc, int reg) 587{ 588 struct esp_softc *esc = (struct esp_softc *)sc; 589 590 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg)); 591} 592 593void 594esp_wrreg1(struct ncr53c9x_softc *sc, int reg, u_char v) 595{ 596 struct esp_softc *esc = (struct esp_softc *)sc; 597 598 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 599} 600 601int 602esp_dma_isintr(struct ncr53c9x_softc *sc) 603{ 604 struct esp_softc *esc = (struct esp_softc *)sc; 605 606 return (DMA_ISINTR(esc->sc_dma)); 607} 608 609void 610esp_dma_reset(struct ncr53c9x_softc *sc) 611{ 612 struct esp_softc *esc = (struct esp_softc *)sc; 613 614 DMA_RESET(esc->sc_dma); 615} 616 617int 618esp_dma_intr(struct ncr53c9x_softc *sc) 619{ 620 struct esp_softc *esc = (struct esp_softc *)sc; 621 622 return (DMA_INTR(esc->sc_dma)); 623} 624 625int 626esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 627 int datain, size_t *dmasize) 628{ 629 struct esp_softc *esc = (struct esp_softc *)sc; 630 631 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 632} 633 634void 635esp_dma_go(struct ncr53c9x_softc *sc) 636{ 637 struct esp_softc *esc = (struct esp_softc *)sc; 638 639 DMA_GO(esc->sc_dma); 640} 641 642void 643esp_dma_stop(struct ncr53c9x_softc *sc) 644{ 645 struct esp_softc *esc = (struct esp_softc *)sc; 646 u_int32_t csr; 647 648 csr = L64854_GCSR(esc->sc_dma); 649 csr &= ~D_EN_DMA; 650 L64854_SCSR(esc->sc_dma, csr); 651} 652 653int 654esp_dma_isactive(struct ncr53c9x_softc *sc) 655{ 656 struct esp_softc *esc = (struct esp_softc *)sc; 657 658 return (DMA_ISACTIVE(esc->sc_dma)); 659} 660 661#if defined(DDB) && defined(notyet) 662#include <machine/db_machdep.h> 663#include <ddb/db_output.h> 664 665void db_esp(db_expr_t, int, db_expr_t, char *); 666 667void 668db_esp(db_expr_t addr, int have_addr, db_expr_t count, char *modif) 669{ 670 struct ncr53c9x_softc *sc; 671 struct ncr53c9x_ecb *ecb; 672 struct ncr53c9x_linfo *li; 673 int u, t, i; 674 675 for (u=0; u<10; u++) { 676 sc = (struct ncr53c9x_softc *) 677 getdevunit("esp", u); 678 if (!sc) continue; 679 680 db_printf("esp%d: nexus %p phase %x prev %x dp %p dleft %lx ify %x\n", 681 u, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 682 sc->sc_dp, sc->sc_dleft, sc->sc_msgify); 683 db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n", 684 sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0], 685 sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3], 686 sc->sc_imess[0]); 687 db_printf("ready: "); 688 TAILQ_FOREACH(ecb, &sc->ready_list, chain) { 689 db_printf("ecb %p ", ecb); 690 if (ecb == TAILQ_NEXT(ecb, chain)) { 691 db_printf("\nWARNING: tailq loop on ecb %p", ecb); 692 break; 693 } 694 } 695 db_printf("\n"); 696 697 for (t=0; t<NCR_NTARG; t++) { 698 LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) { 699 db_printf("t%d lun %d untagged %p busy %d used %x\n", 700 t, (int)li->lun, li->untagged, li->busy, 701 li->used); 702 for (i=0; i<256; i++) 703 if ((ecb = li->queued[i])) { 704 db_printf("ecb %p tag %x\n", ecb, i); 705 } 706 } 707 } 708 } 709} 710#endif 711 712