esp_sbus.c revision 1.18
1/* $OpenBSD: esp_sbus.c,v 1.18 2006/06/02 20:00:56 miod Exp $ */ 2/* $NetBSD: esp_sbus.c,v 1.14 2001/04/25 17:53:37 bouyer Exp $ */ 3 4/*- 5 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 10 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41#include <sys/types.h> 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/device.h> 45#include <sys/buf.h> 46#include <sys/malloc.h> 47 48#include <scsi/scsi_all.h> 49#include <scsi/scsiconf.h> 50#include <scsi/scsi_message.h> 51 52#include <machine/bus.h> 53#include <machine/intr.h> 54#include <machine/autoconf.h> 55 56#include <dev/ic/lsi64854reg.h> 57#include <dev/ic/lsi64854var.h> 58 59#include <dev/ic/ncr53c9xreg.h> 60#include <dev/ic/ncr53c9xvar.h> 61 62#include <dev/sbus/sbusvar.h> 63 64struct scsi_adapter esp_switch = { 65 ncr53c9x_scsi_cmd, 66 minphys, /* no max at this level; handled by DMA code */ 67 NULL, 68 NULL, 69}; 70 71struct scsi_device esp_dev = { 72 NULL, /* Use default error handler */ 73 NULL, /* have a queue, served by this */ 74 NULL, /* have no async handler */ 75 NULL, /* Use default 'done' routine */ 76}; 77 78/* #define ESP_SBUS_DEBUG */ 79 80static int esp_unit_offset; 81 82struct esp_softc { 83 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 84 85 bus_space_tag_t sc_bustag; 86 bus_dma_tag_t sc_dmatag; 87 88 bus_space_handle_t sc_reg; /* the registers */ 89 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 90 91 int sc_pri; /* SBUS priority */ 92}; 93 94void espattach_sbus(struct device *, struct device *, void *); 95void espattach_dma(struct device *, struct device *, void *); 96int espmatch_sbus(struct device *, void *, void *); 97 98 99/* Linkup to the rest of the kernel */ 100struct cfattach esp_sbus_ca = { 101 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 102}; 103struct cfattach esp_dma_ca = { 104 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 105}; 106 107/* 108 * Functions and the switch for the MI code. 109 */ 110static u_char esp_read_reg(struct ncr53c9x_softc *, int); 111static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 112static u_char esp_rdreg1(struct ncr53c9x_softc *, int); 113static void esp_wrreg1(struct ncr53c9x_softc *, int, u_char); 114static int esp_dma_isintr(struct ncr53c9x_softc *); 115static void esp_dma_reset(struct ncr53c9x_softc *); 116static int esp_dma_intr(struct ncr53c9x_softc *); 117static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, 118 size_t *, int, size_t *); 119static void esp_dma_go(struct ncr53c9x_softc *); 120static void esp_dma_stop(struct ncr53c9x_softc *); 121static int esp_dma_isactive(struct ncr53c9x_softc *); 122 123static struct ncr53c9x_glue esp_sbus_glue = { 124 esp_read_reg, 125 esp_write_reg, 126 esp_dma_isintr, 127 esp_dma_reset, 128 esp_dma_intr, 129 esp_dma_setup, 130 esp_dma_go, 131 esp_dma_stop, 132 esp_dma_isactive, 133 NULL, /* gl_clear_latched_intr */ 134}; 135 136static struct ncr53c9x_glue esp_sbus_glue1 = { 137 esp_rdreg1, 138 esp_wrreg1, 139 esp_dma_isintr, 140 esp_dma_reset, 141 esp_dma_intr, 142 esp_dma_setup, 143 esp_dma_go, 144 esp_dma_stop, 145 esp_dma_isactive, 146 NULL, /* gl_clear_latched_intr */ 147}; 148 149static void espattach(struct esp_softc *, struct ncr53c9x_glue *); 150 151int 152espmatch_sbus(struct device *parent, void *vcf, void *aux) 153{ 154 struct cfdata *cf = vcf; 155 int rv; 156 struct sbus_attach_args *sa = aux; 157 158 if (strcmp("SUNW,fas", sa->sa_name) == 0) 159 return 1; 160 161 rv = (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0 || 162 strcmp("ptscII", sa->sa_name) == 0); 163 return (rv); 164} 165 166void 167espattach_sbus(struct device *parent, struct device *self, void *aux) 168{ 169 struct esp_softc *esc = (void *)self; 170 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 171 struct sbus_attach_args *sa = aux; 172 struct lsi64854_softc *lsc; 173 int burst, sbusburst; 174 175 esc->sc_bustag = sa->sa_bustag; 176 esc->sc_dmatag = sa->sa_dmatag; 177 178 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 179 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 180 if (sc->sc_freq < 0) 181 sc->sc_freq = ((struct sbus_softc *) 182 sc->sc_dev.dv_parent)->sc_clockfreq; 183 184#ifdef ESP_SBUS_DEBUG 185 printf("%s: espattach_sbus: sc_id %d, freq %d\n", 186 self->dv_xname, sc->sc_id, sc->sc_freq); 187#endif 188 189 if (strcmp("SUNW,fas", sa->sa_name) == 0) { 190 /* 191 * offset searches for other esp/dma devices. 192 */ 193 esp_unit_offset++; 194 195 /* 196 * fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x) 197 */ 198 if (sa->sa_nreg != 2) { 199 printf("%s: %d register spaces\n", self->dv_xname, sa->sa_nreg); 200 return; 201 } 202 203 /* 204 * allocate space for dma, in SUNW,fas there are no separate 205 * dma device 206 */ 207 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT); 208 209 if (lsc == NULL) { 210 printf("%s: out of memory (lsi64854_softc)\n", 211 self->dv_xname); 212 return; 213 } 214 esc->sc_dma = lsc; 215 216 lsc->sc_bustag = sa->sa_bustag; 217 lsc->sc_dmatag = sa->sa_dmatag; 218 219 bcopy(sc->sc_dev.dv_xname, lsc->sc_dev.dv_xname, 220 sizeof (lsc->sc_dev.dv_xname)); 221 222 /* Map dma registers */ 223 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, 224 sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size, 225 0, 0, &lsc->sc_regs) != 0) { 226 printf("%s: cannot map dma registers\n", self->dv_xname); 227 return; 228 } 229 230 /* 231 * XXX is this common(from bpp.c), the same in dma_sbus...etc. 232 * 233 * Get transfer burst size from PROM and plug it into the 234 * controller registers. This is needed on the Sun4m; do 235 * others need it too? 236 */ 237 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 238 if (sbusburst == 0) 239 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 240 241 burst = getpropint(sa->sa_node, "burst-sizes", -1); 242 243#ifdef ESP_SBUS_DEBUG 244 printf("espattach_sbus: burst 0x%x, sbus 0x%x\n", 245 burst, sbusburst); 246#endif 247 248 if (burst == -1) 249 /* take SBus burst sizes */ 250 burst = sbusburst; 251 252 /* Clamp at parent's burst sizes */ 253 burst &= sbusburst; 254 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 255 (burst & SBUS_BURST_16) ? 16 : 0; 256 257 lsc->sc_channel = L64854_CHANNEL_SCSI; 258 lsc->sc_client = sc; 259 260 lsi64854_attach(lsc); 261 262 /* 263 * map SCSI core registers 264 */ 265 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot, 266 sa->sa_reg[1].sbr_offset, sa->sa_reg[1].sbr_size, 267 0, 0, &esc->sc_reg) != 0) { 268 printf("%s: cannot map scsi core registers\n", 269 self->dv_xname); 270 return; 271 } 272 273 if (sa->sa_nintr == 0) { 274 printf("%s: no interrupt property\n", self->dv_xname); 275 return; 276 } 277 278 esc->sc_pri = sa->sa_pri; 279 280 printf("%s", self->dv_xname); 281 espattach(esc, &esp_sbus_glue); 282 283 return; 284 } 285 286 /* 287 * Find the DMA by poking around the dma device structures 288 * 289 * What happens here is that if the dma driver has not been 290 * configured, then this returns a NULL pointer. Then when the 291 * dma actually gets configured, it does the opposing test, and 292 * if the sc->sc_esp field in it's softc is NULL, then tries to 293 * find the matching esp driver. 294 */ 295 esc->sc_dma = (struct lsi64854_softc *) 296 getdevunit("dma", sc->sc_dev.dv_unit - esp_unit_offset); 297 298 /* 299 * and a back pointer to us, for DMA 300 */ 301 if (esc->sc_dma) 302 esc->sc_dma->sc_client = sc; 303 else { 304 printf("\n"); 305 panic("espattach: no dma found"); 306 } 307 308 /* 309 * The `ESC' DMA chip must be reset before we can access 310 * the esp registers. 311 */ 312 if (esc->sc_dma->sc_rev == DMAREV_ESC) 313 DMA_RESET(esc->sc_dma); 314 315 /* 316 * Map my registers in, if they aren't already in virtual 317 * address space. 318 */ 319 if (sa->sa_npromvaddrs) { 320 if (bus_space_map(sa->sa_bustag, sa->sa_promvaddrs[0], 321 sa->sa_size, BUS_SPACE_MAP_PROMADDRESS, 322 &esc->sc_reg) != 0) { 323 printf("%s @ sbus: cannot map registers\n", 324 self->dv_xname); 325 return; 326 } 327 } else { 328 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 329 sa->sa_offset, sa->sa_size, 0, 0, &esc->sc_reg) != 0) { 330 printf("%s @ sbus: cannot map registers\n", 331 self->dv_xname); 332 return; 333 } 334 } 335 336 if (sa->sa_nintr == 0) { 337 /* 338 * No interrupt properties: we quit; this might 339 * happen on e.g. a Sparc X terminal. 340 */ 341 printf("\n%s: no interrupt property\n", self->dv_xname); 342 return; 343 } 344 345 esc->sc_pri = sa->sa_pri; 346 347 if (strcmp("ptscII", sa->sa_name) == 0) { 348 espattach(esc, &esp_sbus_glue1); 349 } else { 350 espattach(esc, &esp_sbus_glue); 351 } 352} 353 354void 355espattach_dma(struct device *parent, struct device *self, void *aux) 356{ 357 struct esp_softc *esc = (void *)self; 358 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 359 struct sbus_attach_args *sa = aux; 360 361 if (strcmp("ptscII", sa->sa_name) == 0) { 362 return; 363 } 364 365 esc->sc_bustag = sa->sa_bustag; 366 esc->sc_dmatag = sa->sa_dmatag; 367 368 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 369 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 370 371 esc->sc_dma = (struct lsi64854_softc *)parent; 372 esc->sc_dma->sc_client = sc; 373 374 /* 375 * Map my registers in, if they aren't already in virtual 376 * address space. 377 */ 378 if (sa->sa_npromvaddrs) { 379 if (bus_space_map(sa->sa_bustag, sa->sa_promvaddrs[0], 380 sa->sa_size /* ??? */, BUS_SPACE_MAP_PROMADDRESS, 381 &esc->sc_reg) != 0) { 382 printf("%s @ dma: cannot map registers\n", 383 self->dv_xname); 384 return; 385 } 386 } else { 387 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, sa->sa_offset, 388 sa->sa_size, 0, 0, &esc->sc_reg) != 0) { 389 printf("%s @ dma: cannot map registers\n", 390 self->dv_xname); 391 return; 392 } 393 } 394 395 if (sa->sa_nintr == 0) { 396 /* 397 * No interrupt properties: we quit; this might 398 * happen on e.g. a Sparc X terminal. 399 */ 400 printf("\n%s: no interrupt property\n", self->dv_xname); 401 return; 402 } 403 404 esc->sc_pri = sa->sa_pri; 405 406 espattach(esc, &esp_sbus_glue); 407} 408 409 410/* 411 * Attach this instance, and then all the sub-devices 412 */ 413void 414espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep) 415{ 416 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 417 void *icookie; 418 unsigned int uid = 0; 419 420 /* 421 * Set up glue for MI code early; we use some of it here. 422 */ 423 sc->sc_glue = gluep; 424 425 /* gimme MHz */ 426 sc->sc_freq /= 1000000; 427 428 /* 429 * XXX More of this should be in ncr53c9x_attach(), but 430 * XXX should we really poke around the chip that much in 431 * XXX the MI code? Think about this more... 432 */ 433 434 /* 435 * It is necessary to try to load the 2nd config register here, 436 * to find out what rev the esp chip is, else the ncr53c9x_reset 437 * will not set up the defaults correctly. 438 */ 439 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 440 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 441 sc->sc_cfg3 = NCRCFG3_CDB; 442 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 443 444 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 445 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 446 sc->sc_rev = NCR_VARIANT_ESP100; 447 } else { 448 sc->sc_cfg2 = NCRCFG2_SCSI2; 449 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 450 sc->sc_cfg3 = 0; 451 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 452 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 453 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 454 if (NCR_READ_REG(sc, NCR_CFG3) != 455 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 456 sc->sc_rev = NCR_VARIANT_ESP100A; 457 } else { 458 /* NCRCFG2_FE enables > 64K transfers */ 459 sc->sc_cfg2 |= NCRCFG2_FE; 460 sc->sc_cfg3 = 0; 461 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 462 sc->sc_rev = NCR_VARIANT_ESP200; 463 464 /* XXX spec says it's valid after power up or chip reset */ 465 uid = NCR_READ_REG(sc, NCR_UID); 466 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 467 sc->sc_rev = NCR_VARIANT_FAS366; 468 } 469 } 470 471#ifdef ESP_SBUS_DEBUG 472 printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid); 473#endif 474 475 /* 476 * XXX minsync and maxxfer _should_ be set up in MI code, 477 * XXX but it appears to have some dependency on what sort 478 * XXX of DMA we're hooked up to, etc. 479 */ 480 481 /* 482 * This is the value used to start sync negotiations 483 * Note that the NCR register "SYNCTP" is programmed 484 * in "clocks per byte", and has a minimum value of 4. 485 * The SCSI period used in negotiation is one-fourth 486 * of the time (in nanoseconds) needed to transfer one byte. 487 * Since the chip's clock is given in MHz, we have the following 488 * formula: 4 * period = (1000 / freq) * 4 489 */ 490 sc->sc_minsync = 1000 / sc->sc_freq; 491 492 /* 493 * Alas, we must now modify the value a bit, because it's 494 * only valid when can switch on FASTCLK and FASTSCSI bits 495 * in config register 3... 496 */ 497 switch (sc->sc_rev) { 498 case NCR_VARIANT_ESP100: 499 sc->sc_maxxfer = 64 * 1024; 500 sc->sc_minsync = 0; /* No synch on old chip? */ 501 break; 502 503 case NCR_VARIANT_ESP100A: 504 sc->sc_maxxfer = 64 * 1024; 505 /* Min clocks/byte is 5 */ 506 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 507 break; 508 509 case NCR_VARIANT_ESP200: 510 case NCR_VARIANT_FAS366: 511 sc->sc_maxxfer = 16 * 1024 * 1024; 512 /* XXX - do actually set FAST* bits */ 513 break; 514 } 515 516 /* Establish interrupt channel */ 517 icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO, 0, 518 ncr53c9x_intr, sc, sc->sc_dev.dv_xname); 519 520 /* Turn on target selection using the `dma' method */ 521 if (sc->sc_rev != NCR_VARIANT_FAS366) 522 sc->sc_features |= NCR_F_DMASELECT; 523 524 /* Do the common parts of attachment. */ 525 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 526} 527 528/* 529 * Glue functions. 530 */ 531 532#ifdef ESP_SBUS_DEBUG 533int esp_sbus_debug = 0; 534 535static struct { 536 char *r_name; 537 int r_flag; 538} esp__read_regnames [] = { 539 { "TCL", 0}, /* 0/00 */ 540 { "TCM", 0}, /* 1/04 */ 541 { "FIFO", 0}, /* 2/08 */ 542 { "CMD", 0}, /* 3/0c */ 543 { "STAT", 0}, /* 4/10 */ 544 { "INTR", 0}, /* 5/14 */ 545 { "STEP", 0}, /* 6/18 */ 546 { "FFLAGS", 1}, /* 7/1c */ 547 { "CFG1", 1}, /* 8/20 */ 548 { "STAT2", 0}, /* 9/24 */ 549 { "CFG4", 1}, /* a/28 */ 550 { "CFG2", 1}, /* b/2c */ 551 { "CFG3", 1}, /* c/30 */ 552 { "-none", 1}, /* d/34 */ 553 { "TCH", 1}, /* e/38 */ 554 { "TCX", 1}, /* f/3c */ 555}; 556 557static struct { 558 char *r_name; 559 int r_flag; 560} esp__write_regnames[] = { 561 { "TCL", 1}, /* 0/00 */ 562 { "TCM", 1}, /* 1/04 */ 563 { "FIFO", 0}, /* 2/08 */ 564 { "CMD", 0}, /* 3/0c */ 565 { "SELID", 1}, /* 4/10 */ 566 { "TIMEOUT", 1}, /* 5/14 */ 567 { "SYNCTP", 1}, /* 6/18 */ 568 { "SYNCOFF", 1}, /* 7/1c */ 569 { "CFG1", 1}, /* 8/20 */ 570 { "CCF", 1}, /* 9/24 */ 571 { "TEST", 1}, /* a/28 */ 572 { "CFG2", 1}, /* b/2c */ 573 { "CFG3", 1}, /* c/30 */ 574 { "-none", 1}, /* d/34 */ 575 { "TCH", 1}, /* e/38 */ 576 { "TCX", 1}, /* f/3c */ 577}; 578#endif 579 580u_char 581esp_read_reg(struct ncr53c9x_softc *sc, int reg) 582{ 583 struct esp_softc *esc = (struct esp_softc *)sc; 584 u_char v; 585 586 v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4); 587#ifdef ESP_SBUS_DEBUG 588 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 589 printf("RD:%x <%s> %x\n", reg * 4, 590 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 591#endif 592 return v; 593} 594 595void 596esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v) 597{ 598 struct esp_softc *esc = (struct esp_softc *)sc; 599 600#ifdef ESP_SBUS_DEBUG 601 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 602 printf("WR:%x <%s> %x\n", reg * 4, 603 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 604#endif 605 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 606} 607 608u_char 609esp_rdreg1(struct ncr53c9x_softc *sc, int reg) 610{ 611 struct esp_softc *esc = (struct esp_softc *)sc; 612 613 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg)); 614} 615 616void 617esp_wrreg1(struct ncr53c9x_softc *sc, int reg, u_char v) 618{ 619 struct esp_softc *esc = (struct esp_softc *)sc; 620 621 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 622} 623 624int 625esp_dma_isintr(struct ncr53c9x_softc *sc) 626{ 627 struct esp_softc *esc = (struct esp_softc *)sc; 628 629 return (DMA_ISINTR(esc->sc_dma)); 630} 631 632void 633esp_dma_reset(struct ncr53c9x_softc *sc) 634{ 635 struct esp_softc *esc = (struct esp_softc *)sc; 636 637 DMA_RESET(esc->sc_dma); 638} 639 640int 641esp_dma_intr(struct ncr53c9x_softc *sc) 642{ 643 struct esp_softc *esc = (struct esp_softc *)sc; 644 645 return (DMA_INTR(esc->sc_dma)); 646} 647 648int 649esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 650 int datain, size_t *dmasize) 651{ 652 struct esp_softc *esc = (struct esp_softc *)sc; 653 654 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 655} 656 657void 658esp_dma_go(struct ncr53c9x_softc *sc) 659{ 660 struct esp_softc *esc = (struct esp_softc *)sc; 661 662 DMA_GO(esc->sc_dma); 663} 664 665void 666esp_dma_stop(struct ncr53c9x_softc *sc) 667{ 668 struct esp_softc *esc = (struct esp_softc *)sc; 669 u_int32_t csr; 670 671 csr = L64854_GCSR(esc->sc_dma); 672 csr &= ~D_EN_DMA; 673 L64854_SCSR(esc->sc_dma, csr); 674} 675 676int 677esp_dma_isactive(struct ncr53c9x_softc *sc) 678{ 679 struct esp_softc *esc = (struct esp_softc *)sc; 680 681 return (DMA_ISACTIVE(esc->sc_dma)); 682} 683 684#if defined(DDB) && defined(notyet) 685#include <machine/db_machdep.h> 686#include <ddb/db_output.h> 687 688void db_esp(db_expr_t, int, db_expr_t, char *); 689 690void 691db_esp(db_expr_t addr, int have_addr, db_expr_t count, char *modif) 692{ 693 struct ncr53c9x_softc *sc; 694 struct ncr53c9x_ecb *ecb; 695 struct ncr53c9x_linfo *li; 696 int u, t, i; 697 698 for (u=0; u<10; u++) { 699 sc = (struct ncr53c9x_softc *) 700 getdevunit("esp", u); 701 if (!sc) continue; 702 703 db_printf("esp%d: nexus %p phase %x prev %x dp %p dleft %lx ify %x\n", 704 u, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 705 sc->sc_dp, sc->sc_dleft, sc->sc_msgify); 706 db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n", 707 sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0], 708 sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3], 709 sc->sc_imess[0]); 710 db_printf("ready: "); 711 TAILQ_FOREACH(ecb, &sc->ready_list, chain) { 712 db_printf("ecb %p ", ecb); 713 if (ecb == TAILQ_NEXT(ecb, chain)) { 714 db_printf("\nWARNING: tailq loop on ecb %p", ecb); 715 break; 716 } 717 } 718 db_printf("\n"); 719 720 for (t=0; t<NCR_NTARG; t++) { 721 LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) { 722 db_printf("t%d lun %d untagged %p busy %d used %x\n", 723 t, (int)li->lun, li->untagged, li->busy, 724 li->used); 725 for (i=0; i<256; i++) 726 if ((ecb = li->queued[i])) { 727 db_printf("ecb %p tag %x\n", ecb, i); 728 } 729 } 730 } 731 } 732} 733#endif 734 735