esp_sbus.c revision 1.16
1/* $OpenBSD: esp_sbus.c,v 1.16 2004/09/29 19:17:43 miod Exp $ */ 2/* $NetBSD: esp_sbus.c,v 1.14 2001/04/25 17:53:37 bouyer Exp $ */ 3 4/*- 5 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 10 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41#include <sys/types.h> 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/device.h> 45#include <sys/buf.h> 46#include <sys/malloc.h> 47 48#include <scsi/scsi_all.h> 49#include <scsi/scsiconf.h> 50#include <scsi/scsi_message.h> 51 52#include <machine/bus.h> 53#include <machine/intr.h> 54#include <machine/autoconf.h> 55 56#include <dev/ic/lsi64854reg.h> 57#include <dev/ic/lsi64854var.h> 58 59#include <dev/ic/ncr53c9xreg.h> 60#include <dev/ic/ncr53c9xvar.h> 61 62#include <dev/sbus/sbusvar.h> 63 64struct scsi_adapter esp_switch = { 65 ncr53c9x_scsi_cmd, 66 minphys, /* no max at this level; handled by DMA code */ 67 NULL, 68 NULL, 69}; 70 71struct scsi_device esp_dev = { 72 NULL, /* Use default error handler */ 73 NULL, /* have a queue, served by this */ 74 NULL, /* have no async handler */ 75 NULL, /* Use default 'done' routine */ 76}; 77 78/* #define ESP_SBUS_DEBUG */ 79 80static int esp_unit_offset; 81 82struct esp_softc { 83 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 84 struct sbusdev sc_sd; /* sbus device */ 85 86 bus_space_tag_t sc_bustag; 87 bus_dma_tag_t sc_dmatag; 88 89 bus_space_handle_t sc_reg; /* the registers */ 90 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 91 92 int sc_pri; /* SBUS priority */ 93}; 94 95void espattach_sbus(struct device *, struct device *, void *); 96void espattach_dma(struct device *, struct device *, void *); 97int espmatch_sbus(struct device *, void *, void *); 98 99 100/* Linkup to the rest of the kernel */ 101struct cfattach esp_sbus_ca = { 102 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 103}; 104struct cfattach esp_dma_ca = { 105 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 106}; 107 108/* 109 * Functions and the switch for the MI code. 110 */ 111static u_char esp_read_reg(struct ncr53c9x_softc *, int); 112static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 113static u_char esp_rdreg1(struct ncr53c9x_softc *, int); 114static void esp_wrreg1(struct ncr53c9x_softc *, int, u_char); 115static int esp_dma_isintr(struct ncr53c9x_softc *); 116static void esp_dma_reset(struct ncr53c9x_softc *); 117static int esp_dma_intr(struct ncr53c9x_softc *); 118static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, 119 size_t *, int, size_t *); 120static void esp_dma_go(struct ncr53c9x_softc *); 121static void esp_dma_stop(struct ncr53c9x_softc *); 122static int esp_dma_isactive(struct ncr53c9x_softc *); 123 124static struct ncr53c9x_glue esp_sbus_glue = { 125 esp_read_reg, 126 esp_write_reg, 127 esp_dma_isintr, 128 esp_dma_reset, 129 esp_dma_intr, 130 esp_dma_setup, 131 esp_dma_go, 132 esp_dma_stop, 133 esp_dma_isactive, 134 NULL, /* gl_clear_latched_intr */ 135}; 136 137static struct ncr53c9x_glue esp_sbus_glue1 = { 138 esp_rdreg1, 139 esp_wrreg1, 140 esp_dma_isintr, 141 esp_dma_reset, 142 esp_dma_intr, 143 esp_dma_setup, 144 esp_dma_go, 145 esp_dma_stop, 146 esp_dma_isactive, 147 NULL, /* gl_clear_latched_intr */ 148}; 149 150static void espattach(struct esp_softc *, struct ncr53c9x_glue *); 151 152int 153espmatch_sbus(struct device *parent, void *vcf, void *aux) 154{ 155 struct cfdata *cf = vcf; 156 int rv; 157 struct sbus_attach_args *sa = aux; 158 159 if (strcmp("SUNW,fas", sa->sa_name) == 0) 160 return 1; 161 162 rv = (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0 || 163 strcmp("ptscII", sa->sa_name) == 0); 164 return (rv); 165} 166 167void 168espattach_sbus(struct device *parent, struct device *self, void *aux) 169{ 170 struct esp_softc *esc = (void *)self; 171 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 172 struct sbus_attach_args *sa = aux; 173 struct lsi64854_softc *lsc; 174 int burst, sbusburst; 175 176 esc->sc_bustag = sa->sa_bustag; 177 esc->sc_dmatag = sa->sa_dmatag; 178 179 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 180 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 181 if (sc->sc_freq < 0) 182 sc->sc_freq = ((struct sbus_softc *) 183 sc->sc_dev.dv_parent)->sc_clockfreq; 184 185#ifdef ESP_SBUS_DEBUG 186 printf("%s: espattach_sbus: sc_id %d, freq %d\n", 187 self->dv_xname, sc->sc_id, sc->sc_freq); 188#endif 189 190 if (strcmp("SUNW,fas", sa->sa_name) == 0) { 191 /* 192 * offset searches for other esp/dma devices. 193 */ 194 esp_unit_offset++; 195 196 /* 197 * fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x) 198 */ 199 if (sa->sa_nreg != 2) { 200 printf("%s: %d register spaces\n", self->dv_xname, sa->sa_nreg); 201 return; 202 } 203 204 /* 205 * allocate space for dma, in SUNW,fas there are no separate 206 * dma device 207 */ 208 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT); 209 210 if (lsc == NULL) { 211 printf("%s: out of memory (lsi64854_softc)\n", 212 self->dv_xname); 213 return; 214 } 215 esc->sc_dma = lsc; 216 217 lsc->sc_bustag = sa->sa_bustag; 218 lsc->sc_dmatag = sa->sa_dmatag; 219 220 bcopy(sc->sc_dev.dv_xname, lsc->sc_dev.dv_xname, 221 sizeof (lsc->sc_dev.dv_xname)); 222 223 /* Map dma registers */ 224 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, 225 sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size, 226 0, 0, &lsc->sc_regs) != 0) { 227 printf("%s: cannot map dma registers\n", self->dv_xname); 228 return; 229 } 230 231 /* 232 * XXX is this common(from bpp.c), the same in dma_sbus...etc. 233 * 234 * Get transfer burst size from PROM and plug it into the 235 * controller registers. This is needed on the Sun4m; do 236 * others need it too? 237 */ 238 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 239 if (sbusburst == 0) 240 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 241 242 burst = getpropint(sa->sa_node, "burst-sizes", -1); 243 244#ifdef ESP_SBUS_DEBUG 245 printf("espattach_sbus: burst 0x%x, sbus 0x%x\n", 246 burst, sbusburst); 247#endif 248 249 if (burst == -1) 250 /* take SBus burst sizes */ 251 burst = sbusburst; 252 253 /* Clamp at parent's burst sizes */ 254 burst &= sbusburst; 255 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 256 (burst & SBUS_BURST_16) ? 16 : 0; 257 258 lsc->sc_channel = L64854_CHANNEL_SCSI; 259 lsc->sc_client = sc; 260 261 lsi64854_attach(lsc); 262 263 /* 264 * map SCSI core registers 265 */ 266 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot, 267 sa->sa_reg[1].sbr_offset, sa->sa_reg[1].sbr_size, 268 0, 0, &esc->sc_reg) != 0) { 269 printf("%s: cannot map scsi core registers\n", 270 self->dv_xname); 271 return; 272 } 273 274 if (sa->sa_nintr == 0) { 275 printf("%s: no interrupt property\n", self->dv_xname); 276 return; 277 } 278 279 esc->sc_pri = sa->sa_pri; 280 281 /* add me to the sbus structures */ 282 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 283 sbus_establish(&esc->sc_sd, &sc->sc_dev); 284 285 printf("%s", self->dv_xname); 286 espattach(esc, &esp_sbus_glue); 287 288 return; 289 } 290 291 /* 292 * Find the DMA by poking around the dma device structures 293 * 294 * What happens here is that if the dma driver has not been 295 * configured, then this returns a NULL pointer. Then when the 296 * dma actually gets configured, it does the opposing test, and 297 * if the sc->sc_esp field in it's softc is NULL, then tries to 298 * find the matching esp driver. 299 */ 300 esc->sc_dma = (struct lsi64854_softc *) 301 getdevunit("dma", sc->sc_dev.dv_unit - esp_unit_offset); 302 303 /* 304 * and a back pointer to us, for DMA 305 */ 306 if (esc->sc_dma) 307 esc->sc_dma->sc_client = sc; 308 else { 309 printf("\n"); 310 panic("espattach: no dma found"); 311 } 312 313 /* 314 * The `ESC' DMA chip must be reset before we can access 315 * the esp registers. 316 */ 317 if (esc->sc_dma->sc_rev == DMAREV_ESC) 318 DMA_RESET(esc->sc_dma); 319 320 /* 321 * Map my registers in, if they aren't already in virtual 322 * address space. 323 */ 324 if (sa->sa_npromvaddrs) { 325 if (bus_space_map(sa->sa_bustag, sa->sa_promvaddrs[0], 326 sa->sa_size, BUS_SPACE_MAP_PROMADDRESS, 327 &esc->sc_reg) != 0) { 328 printf("%s @ sbus: cannot map registers\n", 329 self->dv_xname); 330 return; 331 } 332 } else { 333 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 334 sa->sa_offset, sa->sa_size, 0, 0, &esc->sc_reg) != 0) { 335 printf("%s @ sbus: cannot map registers\n", 336 self->dv_xname); 337 return; 338 } 339 } 340 341 if (sa->sa_nintr == 0) { 342 /* 343 * No interrupt properties: we quit; this might 344 * happen on e.g. a Sparc X terminal. 345 */ 346 printf("\n%s: no interrupt property\n", self->dv_xname); 347 return; 348 } 349 350 esc->sc_pri = sa->sa_pri; 351 352 /* add me to the sbus structures */ 353 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 354 sbus_establish(&esc->sc_sd, &sc->sc_dev); 355 356 if (strcmp("ptscII", sa->sa_name) == 0) { 357 espattach(esc, &esp_sbus_glue1); 358 } else { 359 espattach(esc, &esp_sbus_glue); 360 } 361} 362 363void 364espattach_dma(struct device *parent, struct device *self, void *aux) 365{ 366 struct esp_softc *esc = (void *)self; 367 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 368 struct sbus_attach_args *sa = aux; 369 370 if (strcmp("ptscII", sa->sa_name) == 0) { 371 return; 372 } 373 374 esc->sc_bustag = sa->sa_bustag; 375 esc->sc_dmatag = sa->sa_dmatag; 376 377 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 378 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 379 380 esc->sc_dma = (struct lsi64854_softc *)parent; 381 esc->sc_dma->sc_client = sc; 382 383 /* 384 * Map my registers in, if they aren't already in virtual 385 * address space. 386 */ 387 if (sa->sa_npromvaddrs) { 388 if (bus_space_map(sa->sa_bustag, sa->sa_promvaddrs[0], 389 sa->sa_size /* ??? */, BUS_SPACE_MAP_PROMADDRESS, 390 &esc->sc_reg) != 0) { 391 printf("%s @ dma: cannot map registers\n", 392 self->dv_xname); 393 return; 394 } 395 } else { 396 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, sa->sa_offset, 397 sa->sa_size, 0, 0, &esc->sc_reg) != 0) { 398 printf("%s @ dma: cannot map registers\n", 399 self->dv_xname); 400 return; 401 } 402 } 403 404 if (sa->sa_nintr == 0) { 405 /* 406 * No interrupt properties: we quit; this might 407 * happen on e.g. a Sparc X terminal. 408 */ 409 printf("\n%s: no interrupt property\n", self->dv_xname); 410 return; 411 } 412 413 esc->sc_pri = sa->sa_pri; 414 415 /* Assume SBus is grandparent */ 416 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 417 sbus_establish(&esc->sc_sd, parent); 418 419 espattach(esc, &esp_sbus_glue); 420} 421 422 423/* 424 * Attach this instance, and then all the sub-devices 425 */ 426void 427espattach(struct esp_softc *esc, struct ncr53c9x_glue *gluep) 428{ 429 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 430 void *icookie; 431 unsigned int uid = 0; 432 433 /* 434 * Set up glue for MI code early; we use some of it here. 435 */ 436 sc->sc_glue = gluep; 437 438 /* gimme MHz */ 439 sc->sc_freq /= 1000000; 440 441 /* 442 * XXX More of this should be in ncr53c9x_attach(), but 443 * XXX should we really poke around the chip that much in 444 * XXX the MI code? Think about this more... 445 */ 446 447 /* 448 * It is necessary to try to load the 2nd config register here, 449 * to find out what rev the esp chip is, else the ncr53c9x_reset 450 * will not set up the defaults correctly. 451 */ 452 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 453 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 454 sc->sc_cfg3 = NCRCFG3_CDB; 455 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 456 457 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 458 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 459 sc->sc_rev = NCR_VARIANT_ESP100; 460 } else { 461 sc->sc_cfg2 = NCRCFG2_SCSI2; 462 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 463 sc->sc_cfg3 = 0; 464 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 465 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 466 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 467 if (NCR_READ_REG(sc, NCR_CFG3) != 468 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 469 sc->sc_rev = NCR_VARIANT_ESP100A; 470 } else { 471 /* NCRCFG2_FE enables > 64K transfers */ 472 sc->sc_cfg2 |= NCRCFG2_FE; 473 sc->sc_cfg3 = 0; 474 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 475 sc->sc_rev = NCR_VARIANT_ESP200; 476 477 /* XXX spec says it's valid after power up or chip reset */ 478 uid = NCR_READ_REG(sc, NCR_UID); 479 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 480 sc->sc_rev = NCR_VARIANT_FAS366; 481 } 482 } 483 484#ifdef ESP_SBUS_DEBUG 485 printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid); 486#endif 487 488 /* 489 * XXX minsync and maxxfer _should_ be set up in MI code, 490 * XXX but it appears to have some dependency on what sort 491 * XXX of DMA we're hooked up to, etc. 492 */ 493 494 /* 495 * This is the value used to start sync negotiations 496 * Note that the NCR register "SYNCTP" is programmed 497 * in "clocks per byte", and has a minimum value of 4. 498 * The SCSI period used in negotiation is one-fourth 499 * of the time (in nanoseconds) needed to transfer one byte. 500 * Since the chip's clock is given in MHz, we have the following 501 * formula: 4 * period = (1000 / freq) * 4 502 */ 503 sc->sc_minsync = 1000 / sc->sc_freq; 504 505 /* 506 * Alas, we must now modify the value a bit, because it's 507 * only valid when can switch on FASTCLK and FASTSCSI bits 508 * in config register 3... 509 */ 510 switch (sc->sc_rev) { 511 case NCR_VARIANT_ESP100: 512 sc->sc_maxxfer = 64 * 1024; 513 sc->sc_minsync = 0; /* No synch on old chip? */ 514 break; 515 516 case NCR_VARIANT_ESP100A: 517 sc->sc_maxxfer = 64 * 1024; 518 /* Min clocks/byte is 5 */ 519 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 520 break; 521 522 case NCR_VARIANT_ESP200: 523 case NCR_VARIANT_FAS366: 524 sc->sc_maxxfer = 16 * 1024 * 1024; 525 /* XXX - do actually set FAST* bits */ 526 break; 527 } 528 529 /* Establish interrupt channel */ 530 icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO, 0, 531 ncr53c9x_intr, sc, sc->sc_dev.dv_xname); 532 533 /* Turn on target selection using the `dma' method */ 534 if (sc->sc_rev != NCR_VARIANT_FAS366) 535 sc->sc_features |= NCR_F_DMASELECT; 536 537 /* Do the common parts of attachment. */ 538 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 539} 540 541/* 542 * Glue functions. 543 */ 544 545#ifdef ESP_SBUS_DEBUG 546int esp_sbus_debug = 0; 547 548static struct { 549 char *r_name; 550 int r_flag; 551} esp__read_regnames [] = { 552 { "TCL", 0}, /* 0/00 */ 553 { "TCM", 0}, /* 1/04 */ 554 { "FIFO", 0}, /* 2/08 */ 555 { "CMD", 0}, /* 3/0c */ 556 { "STAT", 0}, /* 4/10 */ 557 { "INTR", 0}, /* 5/14 */ 558 { "STEP", 0}, /* 6/18 */ 559 { "FFLAGS", 1}, /* 7/1c */ 560 { "CFG1", 1}, /* 8/20 */ 561 { "STAT2", 0}, /* 9/24 */ 562 { "CFG4", 1}, /* a/28 */ 563 { "CFG2", 1}, /* b/2c */ 564 { "CFG3", 1}, /* c/30 */ 565 { "-none", 1}, /* d/34 */ 566 { "TCH", 1}, /* e/38 */ 567 { "TCX", 1}, /* f/3c */ 568}; 569 570static struct { 571 char *r_name; 572 int r_flag; 573} esp__write_regnames[] = { 574 { "TCL", 1}, /* 0/00 */ 575 { "TCM", 1}, /* 1/04 */ 576 { "FIFO", 0}, /* 2/08 */ 577 { "CMD", 0}, /* 3/0c */ 578 { "SELID", 1}, /* 4/10 */ 579 { "TIMEOUT", 1}, /* 5/14 */ 580 { "SYNCTP", 1}, /* 6/18 */ 581 { "SYNCOFF", 1}, /* 7/1c */ 582 { "CFG1", 1}, /* 8/20 */ 583 { "CCF", 1}, /* 9/24 */ 584 { "TEST", 1}, /* a/28 */ 585 { "CFG2", 1}, /* b/2c */ 586 { "CFG3", 1}, /* c/30 */ 587 { "-none", 1}, /* d/34 */ 588 { "TCH", 1}, /* e/38 */ 589 { "TCX", 1}, /* f/3c */ 590}; 591#endif 592 593u_char 594esp_read_reg(struct ncr53c9x_softc *sc, int reg) 595{ 596 struct esp_softc *esc = (struct esp_softc *)sc; 597 u_char v; 598 599 v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4); 600#ifdef ESP_SBUS_DEBUG 601 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 602 printf("RD:%x <%s> %x\n", reg * 4, 603 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 604#endif 605 return v; 606} 607 608void 609esp_write_reg(struct ncr53c9x_softc *sc, int reg, u_char v) 610{ 611 struct esp_softc *esc = (struct esp_softc *)sc; 612 613#ifdef ESP_SBUS_DEBUG 614 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 615 printf("WR:%x <%s> %x\n", reg * 4, 616 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 617#endif 618 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 619} 620 621u_char 622esp_rdreg1(struct ncr53c9x_softc *sc, int reg) 623{ 624 struct esp_softc *esc = (struct esp_softc *)sc; 625 626 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg)); 627} 628 629void 630esp_wrreg1(struct ncr53c9x_softc *sc, int reg, u_char v) 631{ 632 struct esp_softc *esc = (struct esp_softc *)sc; 633 634 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 635} 636 637int 638esp_dma_isintr(struct ncr53c9x_softc *sc) 639{ 640 struct esp_softc *esc = (struct esp_softc *)sc; 641 642 return (DMA_ISINTR(esc->sc_dma)); 643} 644 645void 646esp_dma_reset(struct ncr53c9x_softc *sc) 647{ 648 struct esp_softc *esc = (struct esp_softc *)sc; 649 650 DMA_RESET(esc->sc_dma); 651} 652 653int 654esp_dma_intr(struct ncr53c9x_softc *sc) 655{ 656 struct esp_softc *esc = (struct esp_softc *)sc; 657 658 return (DMA_INTR(esc->sc_dma)); 659} 660 661int 662esp_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 663 int datain, size_t *dmasize) 664{ 665 struct esp_softc *esc = (struct esp_softc *)sc; 666 667 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 668} 669 670void 671esp_dma_go(struct ncr53c9x_softc *sc) 672{ 673 struct esp_softc *esc = (struct esp_softc *)sc; 674 675 DMA_GO(esc->sc_dma); 676} 677 678void 679esp_dma_stop(struct ncr53c9x_softc *sc) 680{ 681 struct esp_softc *esc = (struct esp_softc *)sc; 682 u_int32_t csr; 683 684 csr = L64854_GCSR(esc->sc_dma); 685 csr &= ~D_EN_DMA; 686 L64854_SCSR(esc->sc_dma, csr); 687} 688 689int 690esp_dma_isactive(struct ncr53c9x_softc *sc) 691{ 692 struct esp_softc *esc = (struct esp_softc *)sc; 693 694 return (DMA_ISACTIVE(esc->sc_dma)); 695} 696 697#if defined(DDB) && defined(notyet) 698#include <machine/db_machdep.h> 699#include <ddb/db_output.h> 700 701void db_esp(db_expr_t, int, db_expr_t, char *); 702 703void 704db_esp(db_expr_t addr, int have_addr, db_expr_t count, char *modif) 705{ 706 struct ncr53c9x_softc *sc; 707 struct ncr53c9x_ecb *ecb; 708 struct ncr53c9x_linfo *li; 709 int u, t, i; 710 711 for (u=0; u<10; u++) { 712 sc = (struct ncr53c9x_softc *) 713 getdevunit("esp", u); 714 if (!sc) continue; 715 716 db_printf("esp%d: nexus %p phase %x prev %x dp %p dleft %lx ify %x\n", 717 u, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 718 sc->sc_dp, sc->sc_dleft, sc->sc_msgify); 719 db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n", 720 sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0], 721 sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3], 722 sc->sc_imess[0]); 723 db_printf("ready: "); 724 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 725 db_printf("ecb %p ", ecb); 726 if (ecb == ecb->chain.tqe_next) { 727 db_printf("\nWARNING: tailq loop on ecb %p", ecb); 728 break; 729 } 730 } 731 db_printf("\n"); 732 733 for (t=0; t<NCR_NTARG; t++) { 734 LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) { 735 db_printf("t%d lun %d untagged %p busy %d used %x\n", 736 t, (int)li->lun, li->untagged, li->busy, 737 li->used); 738 for (i=0; i<256; i++) 739 if ((ecb = li->queued[i])) { 740 db_printf("ecb %p tag %x\n", ecb, i); 741 } 742 } 743 } 744 } 745} 746#endif 747 748