esp_sbus.c revision 1.14
1/* $OpenBSD: esp_sbus.c,v 1.14 2003/06/27 01:36:53 jason Exp $ */ 2/* $NetBSD: esp_sbus.c,v 1.14 2001/04/25 17:53:37 bouyer Exp $ */ 3 4/*- 5 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 10 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41#include <sys/types.h> 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/device.h> 45#include <sys/buf.h> 46#include <sys/malloc.h> 47 48#include <scsi/scsi_all.h> 49#include <scsi/scsiconf.h> 50#include <scsi/scsi_message.h> 51 52#include <machine/bus.h> 53#include <machine/intr.h> 54#include <machine/autoconf.h> 55 56#include <dev/ic/lsi64854reg.h> 57#include <dev/ic/lsi64854var.h> 58 59#include <dev/ic/ncr53c9xreg.h> 60#include <dev/ic/ncr53c9xvar.h> 61 62#include <dev/sbus/sbusvar.h> 63 64struct scsi_adapter esp_switch = { 65 ncr53c9x_scsi_cmd, 66 minphys, /* no max at this level; handled by DMA code */ 67 NULL, 68 NULL, 69}; 70 71struct scsi_device esp_dev = { 72 NULL, /* Use default error handler */ 73 NULL, /* have a queue, served by this */ 74 NULL, /* have no async handler */ 75 NULL, /* Use default 'done' routine */ 76}; 77 78/* #define ESP_SBUS_DEBUG */ 79 80static int esp_unit_offset; 81 82struct esp_softc { 83 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 84 struct sbusdev sc_sd; /* sbus device */ 85 86 bus_space_tag_t sc_bustag; 87 bus_dma_tag_t sc_dmatag; 88 89 bus_space_handle_t sc_reg; /* the registers */ 90 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 91 92 int sc_pri; /* SBUS priority */ 93}; 94 95void espattach_sbus(struct device *, struct device *, void *); 96void espattach_dma(struct device *, struct device *, void *); 97int espmatch_sbus(struct device *, void *, void *); 98 99 100/* Linkup to the rest of the kernel */ 101struct cfattach esp_sbus_ca = { 102 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 103}; 104struct cfattach esp_dma_ca = { 105 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 106}; 107 108/* 109 * Functions and the switch for the MI code. 110 */ 111static u_char esp_read_reg(struct ncr53c9x_softc *, int); 112static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 113static u_char esp_rdreg1(struct ncr53c9x_softc *, int); 114static void esp_wrreg1(struct ncr53c9x_softc *, int, u_char); 115static int esp_dma_isintr(struct ncr53c9x_softc *); 116static void esp_dma_reset(struct ncr53c9x_softc *); 117static int esp_dma_intr(struct ncr53c9x_softc *); 118static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, 119 size_t *, int, size_t *); 120static void esp_dma_go(struct ncr53c9x_softc *); 121static void esp_dma_stop(struct ncr53c9x_softc *); 122static int esp_dma_isactive(struct ncr53c9x_softc *); 123 124static struct ncr53c9x_glue esp_sbus_glue = { 125 esp_read_reg, 126 esp_write_reg, 127 esp_dma_isintr, 128 esp_dma_reset, 129 esp_dma_intr, 130 esp_dma_setup, 131 esp_dma_go, 132 esp_dma_stop, 133 esp_dma_isactive, 134 NULL, /* gl_clear_latched_intr */ 135}; 136 137static struct ncr53c9x_glue esp_sbus_glue1 = { 138 esp_rdreg1, 139 esp_wrreg1, 140 esp_dma_isintr, 141 esp_dma_reset, 142 esp_dma_intr, 143 esp_dma_setup, 144 esp_dma_go, 145 esp_dma_stop, 146 esp_dma_isactive, 147 NULL, /* gl_clear_latched_intr */ 148}; 149 150static void espattach(struct esp_softc *, struct ncr53c9x_glue *); 151 152int 153espmatch_sbus(parent, vcf, aux) 154 struct device *parent; 155 void *vcf; 156 void *aux; 157{ 158 struct cfdata *cf = vcf; 159 int rv; 160 struct sbus_attach_args *sa = aux; 161 162 if (strcmp("SUNW,fas", sa->sa_name) == 0) 163 return 1; 164 165 rv = (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0 || 166 strcmp("ptscII", sa->sa_name) == 0); 167 return (rv); 168} 169 170void 171espattach_sbus(parent, self, aux) 172 struct device *parent, *self; 173 void *aux; 174{ 175 struct esp_softc *esc = (void *)self; 176 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 177 struct sbus_attach_args *sa = aux; 178 struct lsi64854_softc *lsc; 179 int burst, sbusburst; 180 181 esc->sc_bustag = sa->sa_bustag; 182 esc->sc_dmatag = sa->sa_dmatag; 183 184 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 185 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 186 if (sc->sc_freq < 0) 187 sc->sc_freq = ((struct sbus_softc *) 188 sc->sc_dev.dv_parent)->sc_clockfreq; 189 190#ifdef ESP_SBUS_DEBUG 191 printf("%s: espattach_sbus: sc_id %d, freq %d\n", 192 self->dv_xname, sc->sc_id, sc->sc_freq); 193#endif 194 195 if (strcmp("SUNW,fas", sa->sa_name) == 0) { 196 /* 197 * offset searches for other esp/dma devices. 198 */ 199 esp_unit_offset++; 200 201 /* 202 * fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x) 203 */ 204 if (sa->sa_nreg != 2) { 205 printf("%s: %d register spaces\n", self->dv_xname, sa->sa_nreg); 206 return; 207 } 208 209 /* 210 * allocate space for dma, in SUNW,fas there are no separate 211 * dma device 212 */ 213 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT); 214 215 if (lsc == NULL) { 216 printf("%s: out of memory (lsi64854_softc)\n", 217 self->dv_xname); 218 return; 219 } 220 esc->sc_dma = lsc; 221 222 lsc->sc_bustag = sa->sa_bustag; 223 lsc->sc_dmatag = sa->sa_dmatag; 224 225 bcopy(sc->sc_dev.dv_xname, lsc->sc_dev.dv_xname, 226 sizeof (lsc->sc_dev.dv_xname)); 227 228 /* Map dma registers */ 229 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot, 230 sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size, 231 0, 0, &lsc->sc_regs) != 0) { 232 printf("%s: cannot map dma registers\n", self->dv_xname); 233 return; 234 } 235 236 /* 237 * XXX is this common(from bpp.c), the same in dma_sbus...etc. 238 * 239 * Get transfer burst size from PROM and plug it into the 240 * controller registers. This is needed on the Sun4m; do 241 * others need it too? 242 */ 243 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 244 if (sbusburst == 0) 245 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 246 247 burst = getpropint(sa->sa_node, "burst-sizes", -1); 248 249#ifdef ESP_SBUS_DEBUG 250 printf("espattach_sbus: burst 0x%x, sbus 0x%x\n", 251 burst, sbusburst); 252#endif 253 254 if (burst == -1) 255 /* take SBus burst sizes */ 256 burst = sbusburst; 257 258 /* Clamp at parent's burst sizes */ 259 burst &= sbusburst; 260 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 261 (burst & SBUS_BURST_16) ? 16 : 0; 262 263 lsc->sc_channel = L64854_CHANNEL_SCSI; 264 lsc->sc_client = sc; 265 266 lsi64854_attach(lsc); 267 268 /* 269 * map SCSI core registers 270 */ 271 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot, 272 sa->sa_reg[1].sbr_offset, sa->sa_reg[1].sbr_size, 273 0, 0, &esc->sc_reg) != 0) { 274 printf("%s: cannot map scsi core registers\n", 275 self->dv_xname); 276 return; 277 } 278 279 if (sa->sa_nintr == 0) { 280 printf("%s: no interrupt property\n", self->dv_xname); 281 return; 282 } 283 284 esc->sc_pri = sa->sa_pri; 285 286 /* add me to the sbus structures */ 287 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 288 sbus_establish(&esc->sc_sd, &sc->sc_dev); 289 290 printf("%s", self->dv_xname); 291 espattach(esc, &esp_sbus_glue); 292 293 return; 294 } 295 296 /* 297 * Find the DMA by poking around the dma device structures 298 * 299 * What happens here is that if the dma driver has not been 300 * configured, then this returns a NULL pointer. Then when the 301 * dma actually gets configured, it does the opposing test, and 302 * if the sc->sc_esp field in it's softc is NULL, then tries to 303 * find the matching esp driver. 304 */ 305 esc->sc_dma = (struct lsi64854_softc *) 306 getdevunit("dma", sc->sc_dev.dv_unit - esp_unit_offset); 307 308 /* 309 * and a back pointer to us, for DMA 310 */ 311 if (esc->sc_dma) 312 esc->sc_dma->sc_client = sc; 313 else { 314 printf("\n"); 315 panic("espattach: no dma found"); 316 } 317 318 /* 319 * The `ESC' DMA chip must be reset before we can access 320 * the esp registers. 321 */ 322 if (esc->sc_dma->sc_rev == DMAREV_ESC) 323 DMA_RESET(esc->sc_dma); 324 325 /* 326 * Map my registers in, if they aren't already in virtual 327 * address space. 328 */ 329 if (sa->sa_npromvaddrs) { 330 if (bus_space_map(sa->sa_bustag, sa->sa_promvaddrs[0], 331 sa->sa_size, BUS_SPACE_MAP_PROMADDRESS, 332 &esc->sc_reg) != 0) { 333 printf("%s @ sbus: cannot map registers\n", 334 self->dv_xname); 335 return; 336 } 337 } else { 338 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 339 sa->sa_offset, sa->sa_size, 0, 0, &esc->sc_reg) != 0) { 340 printf("%s @ sbus: cannot map registers\n", 341 self->dv_xname); 342 return; 343 } 344 } 345 346 if (sa->sa_nintr == 0) { 347 /* 348 * No interrupt properties: we quit; this might 349 * happen on e.g. a Sparc X terminal. 350 */ 351 printf("\n%s: no interrupt property\n", self->dv_xname); 352 return; 353 } 354 355 esc->sc_pri = sa->sa_pri; 356 357 /* add me to the sbus structures */ 358 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 359 sbus_establish(&esc->sc_sd, &sc->sc_dev); 360 361 if (strcmp("ptscII", sa->sa_name) == 0) { 362 espattach(esc, &esp_sbus_glue1); 363 } else { 364 espattach(esc, &esp_sbus_glue); 365 } 366} 367 368void 369espattach_dma(parent, self, aux) 370 struct device *parent, *self; 371 void *aux; 372{ 373 struct esp_softc *esc = (void *)self; 374 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 375 struct sbus_attach_args *sa = aux; 376 377 if (strcmp("ptscII", sa->sa_name) == 0) { 378 return; 379 } 380 381 esc->sc_bustag = sa->sa_bustag; 382 esc->sc_dmatag = sa->sa_dmatag; 383 384 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 385 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 386 387 esc->sc_dma = (struct lsi64854_softc *)parent; 388 esc->sc_dma->sc_client = sc; 389 390 /* 391 * Map my registers in, if they aren't already in virtual 392 * address space. 393 */ 394 if (sa->sa_npromvaddrs) { 395 if (bus_space_map(sa->sa_bustag, sa->sa_promvaddrs[0], 396 sa->sa_size /* ??? */, BUS_SPACE_MAP_PROMADDRESS, 397 &esc->sc_reg) != 0) { 398 printf("%s @ dma: cannot map registers\n", 399 self->dv_xname); 400 return; 401 } 402 } else { 403 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, sa->sa_offset, 404 sa->sa_size, 0, 0, &esc->sc_reg) != 0) { 405 printf("%s @ dma: cannot map registers\n", 406 self->dv_xname); 407 return; 408 } 409 } 410 411 if (sa->sa_nintr == 0) { 412 /* 413 * No interrupt properties: we quit; this might 414 * happen on e.g. a Sparc X terminal. 415 */ 416 printf("\n%s: no interrupt property\n", self->dv_xname); 417 return; 418 } 419 420 esc->sc_pri = sa->sa_pri; 421 422 /* Assume SBus is grandparent */ 423 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 424 sbus_establish(&esc->sc_sd, parent); 425 426 espattach(esc, &esp_sbus_glue); 427} 428 429 430/* 431 * Attach this instance, and then all the sub-devices 432 */ 433void 434espattach(esc, gluep) 435 struct esp_softc *esc; 436 struct ncr53c9x_glue *gluep; 437{ 438 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 439 void *icookie; 440 unsigned int uid = 0; 441 442 /* 443 * Set up glue for MI code early; we use some of it here. 444 */ 445 sc->sc_glue = gluep; 446 447 /* gimme MHz */ 448 sc->sc_freq /= 1000000; 449 450 /* 451 * XXX More of this should be in ncr53c9x_attach(), but 452 * XXX should we really poke around the chip that much in 453 * XXX the MI code? Think about this more... 454 */ 455 456 /* 457 * It is necessary to try to load the 2nd config register here, 458 * to find out what rev the esp chip is, else the ncr53c9x_reset 459 * will not set up the defaults correctly. 460 */ 461 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 462 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 463 sc->sc_cfg3 = NCRCFG3_CDB; 464 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 465 466 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 467 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 468 sc->sc_rev = NCR_VARIANT_ESP100; 469 } else { 470 sc->sc_cfg2 = NCRCFG2_SCSI2; 471 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 472 sc->sc_cfg3 = 0; 473 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 474 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 475 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 476 if (NCR_READ_REG(sc, NCR_CFG3) != 477 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 478 sc->sc_rev = NCR_VARIANT_ESP100A; 479 } else { 480 /* NCRCFG2_FE enables > 64K transfers */ 481 sc->sc_cfg2 |= NCRCFG2_FE; 482 sc->sc_cfg3 = 0; 483 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 484 sc->sc_rev = NCR_VARIANT_ESP200; 485 486 /* XXX spec says it's valid after power up or chip reset */ 487 uid = NCR_READ_REG(sc, NCR_UID); 488 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 489 sc->sc_rev = NCR_VARIANT_FAS366; 490 } 491 } 492 493#ifdef ESP_SBUS_DEBUG 494 printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid); 495#endif 496 497 /* 498 * XXX minsync and maxxfer _should_ be set up in MI code, 499 * XXX but it appears to have some dependency on what sort 500 * XXX of DMA we're hooked up to, etc. 501 */ 502 503 /* 504 * This is the value used to start sync negotiations 505 * Note that the NCR register "SYNCTP" is programmed 506 * in "clocks per byte", and has a minimum value of 4. 507 * The SCSI period used in negotiation is one-fourth 508 * of the time (in nanoseconds) needed to transfer one byte. 509 * Since the chip's clock is given in MHz, we have the following 510 * formula: 4 * period = (1000 / freq) * 4 511 */ 512 sc->sc_minsync = 1000 / sc->sc_freq; 513 514 /* 515 * Alas, we must now modify the value a bit, because it's 516 * only valid when can switch on FASTCLK and FASTSCSI bits 517 * in config register 3... 518 */ 519 switch (sc->sc_rev) { 520 case NCR_VARIANT_ESP100: 521 sc->sc_maxxfer = 64 * 1024; 522 sc->sc_minsync = 0; /* No synch on old chip? */ 523 break; 524 525 case NCR_VARIANT_ESP100A: 526 sc->sc_maxxfer = 64 * 1024; 527 /* Min clocks/byte is 5 */ 528 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 529 break; 530 531 case NCR_VARIANT_ESP200: 532 case NCR_VARIANT_FAS366: 533 sc->sc_maxxfer = 16 * 1024 * 1024; 534 /* XXX - do actually set FAST* bits */ 535 break; 536 } 537 538 /* Establish interrupt channel */ 539 icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO, 0, 540 ncr53c9x_intr, sc, sc->sc_dev.dv_xname); 541 542 /* register interrupt stats */ 543 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 544 545 /* Turn on target selection using the `dma' method */ 546 if (sc->sc_rev != NCR_VARIANT_FAS366) 547 sc->sc_features |= NCR_F_DMASELECT; 548 549 /* Do the common parts of attachment. */ 550 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 551} 552 553/* 554 * Glue functions. 555 */ 556 557#ifdef ESP_SBUS_DEBUG 558int esp_sbus_debug = 0; 559 560static struct { 561 char *r_name; 562 int r_flag; 563} esp__read_regnames [] = { 564 { "TCL", 0}, /* 0/00 */ 565 { "TCM", 0}, /* 1/04 */ 566 { "FIFO", 0}, /* 2/08 */ 567 { "CMD", 0}, /* 3/0c */ 568 { "STAT", 0}, /* 4/10 */ 569 { "INTR", 0}, /* 5/14 */ 570 { "STEP", 0}, /* 6/18 */ 571 { "FFLAGS", 1}, /* 7/1c */ 572 { "CFG1", 1}, /* 8/20 */ 573 { "STAT2", 0}, /* 9/24 */ 574 { "CFG4", 1}, /* a/28 */ 575 { "CFG2", 1}, /* b/2c */ 576 { "CFG3", 1}, /* c/30 */ 577 { "-none", 1}, /* d/34 */ 578 { "TCH", 1}, /* e/38 */ 579 { "TCX", 1}, /* f/3c */ 580}; 581 582static struct { 583 char *r_name; 584 int r_flag; 585} esp__write_regnames[] = { 586 { "TCL", 1}, /* 0/00 */ 587 { "TCM", 1}, /* 1/04 */ 588 { "FIFO", 0}, /* 2/08 */ 589 { "CMD", 0}, /* 3/0c */ 590 { "SELID", 1}, /* 4/10 */ 591 { "TIMEOUT", 1}, /* 5/14 */ 592 { "SYNCTP", 1}, /* 6/18 */ 593 { "SYNCOFF", 1}, /* 7/1c */ 594 { "CFG1", 1}, /* 8/20 */ 595 { "CCF", 1}, /* 9/24 */ 596 { "TEST", 1}, /* a/28 */ 597 { "CFG2", 1}, /* b/2c */ 598 { "CFG3", 1}, /* c/30 */ 599 { "-none", 1}, /* d/34 */ 600 { "TCH", 1}, /* e/38 */ 601 { "TCX", 1}, /* f/3c */ 602}; 603#endif 604 605u_char 606esp_read_reg(sc, reg) 607 struct ncr53c9x_softc *sc; 608 int reg; 609{ 610 struct esp_softc *esc = (struct esp_softc *)sc; 611 u_char v; 612 613 v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4); 614#ifdef ESP_SBUS_DEBUG 615 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 616 printf("RD:%x <%s> %x\n", reg * 4, 617 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 618#endif 619 return v; 620} 621 622void 623esp_write_reg(sc, reg, v) 624 struct ncr53c9x_softc *sc; 625 int reg; 626 u_char v; 627{ 628 struct esp_softc *esc = (struct esp_softc *)sc; 629 630#ifdef ESP_SBUS_DEBUG 631 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 632 printf("WR:%x <%s> %x\n", reg * 4, 633 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 634#endif 635 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 636} 637 638u_char 639esp_rdreg1(sc, reg) 640 struct ncr53c9x_softc *sc; 641 int reg; 642{ 643 struct esp_softc *esc = (struct esp_softc *)sc; 644 645 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg)); 646} 647 648void 649esp_wrreg1(sc, reg, v) 650 struct ncr53c9x_softc *sc; 651 int reg; 652 u_char v; 653{ 654 struct esp_softc *esc = (struct esp_softc *)sc; 655 656 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 657} 658 659int 660esp_dma_isintr(sc) 661 struct ncr53c9x_softc *sc; 662{ 663 struct esp_softc *esc = (struct esp_softc *)sc; 664 665 return (DMA_ISINTR(esc->sc_dma)); 666} 667 668void 669esp_dma_reset(sc) 670 struct ncr53c9x_softc *sc; 671{ 672 struct esp_softc *esc = (struct esp_softc *)sc; 673 674 DMA_RESET(esc->sc_dma); 675} 676 677int 678esp_dma_intr(sc) 679 struct ncr53c9x_softc *sc; 680{ 681 struct esp_softc *esc = (struct esp_softc *)sc; 682 683 return (DMA_INTR(esc->sc_dma)); 684} 685 686int 687esp_dma_setup(sc, addr, len, datain, dmasize) 688 struct ncr53c9x_softc *sc; 689 caddr_t *addr; 690 size_t *len; 691 int datain; 692 size_t *dmasize; 693{ 694 struct esp_softc *esc = (struct esp_softc *)sc; 695 696 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 697} 698 699void 700esp_dma_go(sc) 701 struct ncr53c9x_softc *sc; 702{ 703 struct esp_softc *esc = (struct esp_softc *)sc; 704 705 DMA_GO(esc->sc_dma); 706} 707 708void 709esp_dma_stop(sc) 710 struct ncr53c9x_softc *sc; 711{ 712 struct esp_softc *esc = (struct esp_softc *)sc; 713 u_int32_t csr; 714 715 csr = L64854_GCSR(esc->sc_dma); 716 csr &= ~D_EN_DMA; 717 L64854_SCSR(esc->sc_dma, csr); 718} 719 720int 721esp_dma_isactive(sc) 722 struct ncr53c9x_softc *sc; 723{ 724 struct esp_softc *esc = (struct esp_softc *)sc; 725 726 return (DMA_ISACTIVE(esc->sc_dma)); 727} 728 729#if defined(DDB) && defined(notyet) 730#include <machine/db_machdep.h> 731#include <ddb/db_output.h> 732 733void db_esp(db_expr_t, int, db_expr_t, char *); 734 735void 736db_esp(addr, have_addr, count, modif) 737 db_expr_t addr; 738 int have_addr; 739 db_expr_t count; 740 char *modif; 741{ 742 struct ncr53c9x_softc *sc; 743 struct ncr53c9x_ecb *ecb; 744 struct ncr53c9x_linfo *li; 745 int u, t, i; 746 747 for (u=0; u<10; u++) { 748 sc = (struct ncr53c9x_softc *) 749 getdevunit("esp", u); 750 if (!sc) continue; 751 752 db_printf("esp%d: nexus %p phase %x prev %x dp %p dleft %lx ify %x\n", 753 u, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 754 sc->sc_dp, sc->sc_dleft, sc->sc_msgify); 755 db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n", 756 sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0], 757 sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3], 758 sc->sc_imess[0]); 759 db_printf("ready: "); 760 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 761 db_printf("ecb %p ", ecb); 762 if (ecb == ecb->chain.tqe_next) { 763 db_printf("\nWARNING: tailq loop on ecb %p", ecb); 764 break; 765 } 766 } 767 db_printf("\n"); 768 769 for (t=0; t<NCR_NTARG; t++) { 770 LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) { 771 db_printf("t%d lun %d untagged %p busy %d used %x\n", 772 t, (int)li->lun, li->untagged, li->busy, 773 li->used); 774 for (i=0; i<256; i++) 775 if ((ecb = li->queued[i])) { 776 db_printf("ecb %p tag %x\n", ecb, i); 777 } 778 } 779 } 780 } 781} 782#endif 783 784