esp_sbus.c revision 1.10
1/* $OpenBSD: esp_sbus.c,v 1.10 2003/02/11 19:20:28 mickey Exp $ */ 2/* $NetBSD: esp_sbus.c,v 1.14 2001/04/25 17:53:37 bouyer Exp $ */ 3 4/*- 5 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 10 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41#include <sys/types.h> 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/device.h> 45#include <sys/buf.h> 46#include <sys/malloc.h> 47 48#include <scsi/scsi_all.h> 49#include <scsi/scsiconf.h> 50#include <scsi/scsi_message.h> 51 52#include <machine/bus.h> 53#include <machine/intr.h> 54#include <machine/autoconf.h> 55 56#include <dev/ic/lsi64854reg.h> 57#include <dev/ic/lsi64854var.h> 58 59#include <dev/ic/ncr53c9xreg.h> 60#include <dev/ic/ncr53c9xvar.h> 61 62#include <dev/sbus/sbusvar.h> 63 64struct scsi_adapter esp_switch = { 65 ncr53c9x_scsi_cmd, 66 minphys, /* no max at this level; handled by DMA code */ 67 NULL, 68 NULL, 69}; 70 71struct scsi_device esp_dev = { 72 NULL, /* Use default error handler */ 73 NULL, /* have a queue, served by this */ 74 NULL, /* have no async handler */ 75 NULL, /* Use default 'done' routine */ 76}; 77 78/* #define ESP_SBUS_DEBUG */ 79 80static int esp_unit_offset; 81 82struct esp_softc { 83 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 84 struct sbusdev sc_sd; /* sbus device */ 85 86 bus_space_tag_t sc_bustag; 87 bus_dma_tag_t sc_dmatag; 88 89 bus_space_handle_t sc_reg; /* the registers */ 90 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 91 92 int sc_pri; /* SBUS priority */ 93}; 94 95void espattach_sbus(struct device *, struct device *, void *); 96void espattach_dma(struct device *, struct device *, void *); 97int espmatch_sbus(struct device *, void *, void *); 98 99 100/* Linkup to the rest of the kernel */ 101struct cfattach esp_sbus_ca = { 102 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 103}; 104struct cfattach esp_dma_ca = { 105 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 106}; 107 108/* 109 * Functions and the switch for the MI code. 110 */ 111static u_char esp_read_reg(struct ncr53c9x_softc *, int); 112static void esp_write_reg(struct ncr53c9x_softc *, int, u_char); 113static u_char esp_rdreg1(struct ncr53c9x_softc *, int); 114static void esp_wrreg1(struct ncr53c9x_softc *, int, u_char); 115static int esp_dma_isintr(struct ncr53c9x_softc *); 116static void esp_dma_reset(struct ncr53c9x_softc *); 117static int esp_dma_intr(struct ncr53c9x_softc *); 118static int esp_dma_setup(struct ncr53c9x_softc *, caddr_t *, 119 size_t *, int, size_t *); 120static void esp_dma_go(struct ncr53c9x_softc *); 121static void esp_dma_stop(struct ncr53c9x_softc *); 122static int esp_dma_isactive(struct ncr53c9x_softc *); 123 124static struct ncr53c9x_glue esp_sbus_glue = { 125 esp_read_reg, 126 esp_write_reg, 127 esp_dma_isintr, 128 esp_dma_reset, 129 esp_dma_intr, 130 esp_dma_setup, 131 esp_dma_go, 132 esp_dma_stop, 133 esp_dma_isactive, 134 NULL, /* gl_clear_latched_intr */ 135}; 136 137static struct ncr53c9x_glue esp_sbus_glue1 = { 138 esp_rdreg1, 139 esp_wrreg1, 140 esp_dma_isintr, 141 esp_dma_reset, 142 esp_dma_intr, 143 esp_dma_setup, 144 esp_dma_go, 145 esp_dma_stop, 146 esp_dma_isactive, 147 NULL, /* gl_clear_latched_intr */ 148}; 149 150static void espattach(struct esp_softc *, struct ncr53c9x_glue *); 151 152int 153espmatch_sbus(parent, vcf, aux) 154 struct device *parent; 155 void *vcf; 156 void *aux; 157{ 158 struct cfdata *cf = vcf; 159 int rv; 160 struct sbus_attach_args *sa = aux; 161 162 if (strcmp("SUNW,fas", sa->sa_name) == 0) 163 return 1; 164 165 rv = (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0 || 166 strcmp("ptscII", sa->sa_name) == 0); 167 return (rv); 168} 169 170void 171espattach_sbus(parent, self, aux) 172 struct device *parent, *self; 173 void *aux; 174{ 175 struct esp_softc *esc = (void *)self; 176 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 177 struct sbus_attach_args *sa = aux; 178 struct lsi64854_softc *lsc; 179 int burst, sbusburst; 180 181 esc->sc_bustag = sa->sa_bustag; 182 esc->sc_dmatag = sa->sa_dmatag; 183 184 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 185 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 186 if (sc->sc_freq < 0) 187 sc->sc_freq = ((struct sbus_softc *) 188 sc->sc_dev.dv_parent)->sc_clockfreq; 189 190#ifdef ESP_SBUS_DEBUG 191 printf("%s: espattach_sbus: sc_id %d, freq %d\n", 192 self->dv_xname, sc->sc_id, sc->sc_freq); 193#endif 194 195 if (strcmp("SUNW,fas", sa->sa_name) == 0) { 196 /* 197 * offset searches for other esp/dma devices. 198 */ 199 esp_unit_offset++; 200 201 /* 202 * fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x) 203 */ 204 if (sa->sa_nreg != 2) { 205 printf("%s: %d register spaces\n", self->dv_xname, sa->sa_nreg); 206 return; 207 } 208 209 /* 210 * allocate space for dma, in SUNW,fas there are no separate 211 * dma device 212 */ 213 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT); 214 215 if (lsc == NULL) { 216 printf("%s: out of memory (lsi64854_softc)\n", 217 self->dv_xname); 218 return; 219 } 220 esc->sc_dma = lsc; 221 222 lsc->sc_bustag = sa->sa_bustag; 223 lsc->sc_dmatag = sa->sa_dmatag; 224 225 bcopy(sc->sc_dev.dv_xname, lsc->sc_dev.dv_xname, 226 sizeof (lsc->sc_dev.dv_xname)); 227 228 /* Map dma registers */ 229 if (bus_space_map2(sa->sa_bustag, 230 sa->sa_reg[0].sbr_slot, 231 sa->sa_reg[0].sbr_offset, 232 sa->sa_reg[0].sbr_size, 233 BUS_SPACE_MAP_LINEAR, 234 0, &lsc->sc_regs) != 0) { 235 printf("%s: cannot map dma registers\n", self->dv_xname); 236 return; 237 } 238 239 /* 240 * XXX is this common(from bpp.c), the same in dma_sbus...etc. 241 * 242 * Get transfer burst size from PROM and plug it into the 243 * controller registers. This is needed on the Sun4m; do 244 * others need it too? 245 */ 246 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 247 if (sbusburst == 0) 248 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 249 250 burst = getpropint(sa->sa_node, "burst-sizes", -1); 251 252#ifdef ESP_SBUS_DEBUG 253 printf("espattach_sbus: burst 0x%x, sbus 0x%x\n", 254 burst, sbusburst); 255#endif 256 257 if (burst == -1) 258 /* take SBus burst sizes */ 259 burst = sbusburst; 260 261 /* Clamp at parent's burst sizes */ 262 burst &= sbusburst; 263 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 264 (burst & SBUS_BURST_16) ? 16 : 0; 265 266 lsc->sc_channel = L64854_CHANNEL_SCSI; 267 lsc->sc_client = sc; 268 269 lsi64854_attach(lsc); 270 271 /* 272 * map SCSI core registers 273 */ 274 if (sbus_bus_map(sa->sa_bustag, 275 sa->sa_reg[1].sbr_slot, 276 sa->sa_reg[1].sbr_offset, 277 sa->sa_reg[1].sbr_size, 278 BUS_SPACE_MAP_LINEAR, 279 0, &esc->sc_reg) != 0) { 280 printf("%s: cannot map scsi core registers\n", 281 self->dv_xname); 282 return; 283 } 284 285 if (sa->sa_nintr == 0) { 286 printf("%s: no interrupt property\n", self->dv_xname); 287 return; 288 } 289 290 esc->sc_pri = sa->sa_pri; 291 292 /* add me to the sbus structures */ 293 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 294 sbus_establish(&esc->sc_sd, &sc->sc_dev); 295 296 printf("%s", self->dv_xname); 297 espattach(esc, &esp_sbus_glue); 298 299 return; 300 } 301 302 /* 303 * Find the DMA by poking around the dma device structures 304 * 305 * What happens here is that if the dma driver has not been 306 * configured, then this returns a NULL pointer. Then when the 307 * dma actually gets configured, it does the opposing test, and 308 * if the sc->sc_esp field in it's softc is NULL, then tries to 309 * find the matching esp driver. 310 */ 311 esc->sc_dma = (struct lsi64854_softc *) 312 getdevunit("dma", sc->sc_dev.dv_unit - esp_unit_offset); 313 314 /* 315 * and a back pointer to us, for DMA 316 */ 317 if (esc->sc_dma) 318 esc->sc_dma->sc_client = sc; 319 else { 320 printf("\n"); 321 panic("espattach: no dma found"); 322 } 323 324 /* 325 * The `ESC' DMA chip must be reset before we can access 326 * the esp registers. 327 */ 328 if (esc->sc_dma->sc_rev == DMAREV_ESC) 329 DMA_RESET(esc->sc_dma); 330 331 /* 332 * Map my registers in, if they aren't already in virtual 333 * address space. 334 */ 335 if (sa->sa_npromvaddrs) 336 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 337 else { 338 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 339 sa->sa_offset, 340 sa->sa_size, 341 BUS_SPACE_MAP_LINEAR, 342 0, &esc->sc_reg) != 0) { 343 printf("%s @ sbus: cannot map registers\n", 344 self->dv_xname); 345 return; 346 } 347 } 348 349 if (sa->sa_nintr == 0) { 350 /* 351 * No interrupt properties: we quit; this might 352 * happen on e.g. a Sparc X terminal. 353 */ 354 printf("\n%s: no interrupt property\n", self->dv_xname); 355 return; 356 } 357 358 esc->sc_pri = sa->sa_pri; 359 360 /* add me to the sbus structures */ 361 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 362 sbus_establish(&esc->sc_sd, &sc->sc_dev); 363 364 if (strcmp("ptscII", sa->sa_name) == 0) { 365 espattach(esc, &esp_sbus_glue1); 366 } else { 367 espattach(esc, &esp_sbus_glue); 368 } 369} 370 371void 372espattach_dma(parent, self, aux) 373 struct device *parent, *self; 374 void *aux; 375{ 376 struct esp_softc *esc = (void *)self; 377 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 378 struct sbus_attach_args *sa = aux; 379 380 if (strcmp("ptscII", sa->sa_name) == 0) { 381 return; 382 } 383 384 esc->sc_bustag = sa->sa_bustag; 385 esc->sc_dmatag = sa->sa_dmatag; 386 387 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 388 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 389 390 esc->sc_dma = (struct lsi64854_softc *)parent; 391 esc->sc_dma->sc_client = sc; 392 393 /* 394 * Map my registers in, if they aren't already in virtual 395 * address space. 396 */ 397 if (sa->sa_npromvaddrs) 398 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 399 else { 400 if (bus_space_map2(sa->sa_bustag, 401 sa->sa_slot, 402 sa->sa_offset, 403 sa->sa_size, 404 BUS_SPACE_MAP_LINEAR, 405 0, &esc->sc_reg) != 0) { 406 printf("%s @ dma: cannot map registers\n", 407 self->dv_xname); 408 return; 409 } 410 } 411 412 if (sa->sa_nintr == 0) { 413 /* 414 * No interrupt properties: we quit; this might 415 * happen on e.g. a Sparc X terminal. 416 */ 417 printf("\n%s: no interrupt property\n", self->dv_xname); 418 return; 419 } 420 421 esc->sc_pri = sa->sa_pri; 422 423 /* Assume SBus is grandparent */ 424 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 425 sbus_establish(&esc->sc_sd, parent); 426 427 espattach(esc, &esp_sbus_glue); 428} 429 430 431/* 432 * Attach this instance, and then all the sub-devices 433 */ 434void 435espattach(esc, gluep) 436 struct esp_softc *esc; 437 struct ncr53c9x_glue *gluep; 438{ 439 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 440 void *icookie; 441 unsigned int uid = 0; 442 443 /* 444 * Set up glue for MI code early; we use some of it here. 445 */ 446 sc->sc_glue = gluep; 447 448 /* gimme MHz */ 449 sc->sc_freq /= 1000000; 450 451 /* 452 * XXX More of this should be in ncr53c9x_attach(), but 453 * XXX should we really poke around the chip that much in 454 * XXX the MI code? Think about this more... 455 */ 456 457 /* 458 * It is necessary to try to load the 2nd config register here, 459 * to find out what rev the esp chip is, else the ncr53c9x_reset 460 * will not set up the defaults correctly. 461 */ 462 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 463 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 464 sc->sc_cfg3 = NCRCFG3_CDB; 465 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 466 467 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 468 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 469 sc->sc_rev = NCR_VARIANT_ESP100; 470 } else { 471 sc->sc_cfg2 = NCRCFG2_SCSI2; 472 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 473 sc->sc_cfg3 = 0; 474 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 475 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 476 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 477 if (NCR_READ_REG(sc, NCR_CFG3) != 478 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 479 sc->sc_rev = NCR_VARIANT_ESP100A; 480 } else { 481 /* NCRCFG2_FE enables > 64K transfers */ 482 sc->sc_cfg2 |= NCRCFG2_FE; 483 sc->sc_cfg3 = 0; 484 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 485 sc->sc_rev = NCR_VARIANT_ESP200; 486 487 /* XXX spec says it's valid after power up or chip reset */ 488 uid = NCR_READ_REG(sc, NCR_UID); 489 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 490 sc->sc_rev = NCR_VARIANT_FAS366; 491 } 492 } 493 494#ifdef ESP_SBUS_DEBUG 495 printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid); 496#endif 497 498 /* 499 * XXX minsync and maxxfer _should_ be set up in MI code, 500 * XXX but it appears to have some dependency on what sort 501 * XXX of DMA we're hooked up to, etc. 502 */ 503 504 /* 505 * This is the value used to start sync negotiations 506 * Note that the NCR register "SYNCTP" is programmed 507 * in "clocks per byte", and has a minimum value of 4. 508 * The SCSI period used in negotiation is one-fourth 509 * of the time (in nanoseconds) needed to transfer one byte. 510 * Since the chip's clock is given in MHz, we have the following 511 * formula: 4 * period = (1000 / freq) * 4 512 */ 513 sc->sc_minsync = 1000 / sc->sc_freq; 514 515 /* 516 * Alas, we must now modify the value a bit, because it's 517 * only valid when can switch on FASTCLK and FASTSCSI bits 518 * in config register 3... 519 */ 520 switch (sc->sc_rev) { 521 case NCR_VARIANT_ESP100: 522 sc->sc_maxxfer = 64 * 1024; 523 sc->sc_minsync = 0; /* No synch on old chip? */ 524 break; 525 526 case NCR_VARIANT_ESP100A: 527 sc->sc_maxxfer = 64 * 1024; 528 /* Min clocks/byte is 5 */ 529 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 530 break; 531 532 case NCR_VARIANT_ESP200: 533 case NCR_VARIANT_FAS366: 534 sc->sc_maxxfer = 16 * 1024 * 1024; 535 /* XXX - do actually set FAST* bits */ 536 break; 537 } 538 539 /* Establish interrupt channel */ 540 icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO, 0, 541 ncr53c9x_intr, sc); 542 543 /* register interrupt stats */ 544 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 545 546 /* Turn on target selection using the `dma' method */ 547 if (sc->sc_rev != NCR_VARIANT_FAS366) 548 sc->sc_features |= NCR_F_DMASELECT; 549 550 /* Do the common parts of attachment. */ 551 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 552} 553 554/* 555 * Glue functions. 556 */ 557 558#ifdef ESP_SBUS_DEBUG 559int esp_sbus_debug = 0; 560 561static struct { 562 char *r_name; 563 int r_flag; 564} esp__read_regnames [] = { 565 { "TCL", 0}, /* 0/00 */ 566 { "TCM", 0}, /* 1/04 */ 567 { "FIFO", 0}, /* 2/08 */ 568 { "CMD", 0}, /* 3/0c */ 569 { "STAT", 0}, /* 4/10 */ 570 { "INTR", 0}, /* 5/14 */ 571 { "STEP", 0}, /* 6/18 */ 572 { "FFLAGS", 1}, /* 7/1c */ 573 { "CFG1", 1}, /* 8/20 */ 574 { "STAT2", 0}, /* 9/24 */ 575 { "CFG4", 1}, /* a/28 */ 576 { "CFG2", 1}, /* b/2c */ 577 { "CFG3", 1}, /* c/30 */ 578 { "-none", 1}, /* d/34 */ 579 { "TCH", 1}, /* e/38 */ 580 { "TCX", 1}, /* f/3c */ 581}; 582 583static struct { 584 char *r_name; 585 int r_flag; 586} esp__write_regnames[] = { 587 { "TCL", 1}, /* 0/00 */ 588 { "TCM", 1}, /* 1/04 */ 589 { "FIFO", 0}, /* 2/08 */ 590 { "CMD", 0}, /* 3/0c */ 591 { "SELID", 1}, /* 4/10 */ 592 { "TIMEOUT", 1}, /* 5/14 */ 593 { "SYNCTP", 1}, /* 6/18 */ 594 { "SYNCOFF", 1}, /* 7/1c */ 595 { "CFG1", 1}, /* 8/20 */ 596 { "CCF", 1}, /* 9/24 */ 597 { "TEST", 1}, /* a/28 */ 598 { "CFG2", 1}, /* b/2c */ 599 { "CFG3", 1}, /* c/30 */ 600 { "-none", 1}, /* d/34 */ 601 { "TCH", 1}, /* e/38 */ 602 { "TCX", 1}, /* f/3c */ 603}; 604#endif 605 606u_char 607esp_read_reg(sc, reg) 608 struct ncr53c9x_softc *sc; 609 int reg; 610{ 611 struct esp_softc *esc = (struct esp_softc *)sc; 612 u_char v; 613 614 v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4); 615#ifdef ESP_SBUS_DEBUG 616 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 617 printf("RD:%x <%s> %x\n", reg * 4, 618 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 619#endif 620 return v; 621} 622 623void 624esp_write_reg(sc, reg, v) 625 struct ncr53c9x_softc *sc; 626 int reg; 627 u_char v; 628{ 629 struct esp_softc *esc = (struct esp_softc *)sc; 630 631#ifdef ESP_SBUS_DEBUG 632 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 633 printf("WR:%x <%s> %x\n", reg * 4, 634 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 635#endif 636 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 637} 638 639u_char 640esp_rdreg1(sc, reg) 641 struct ncr53c9x_softc *sc; 642 int reg; 643{ 644 struct esp_softc *esc = (struct esp_softc *)sc; 645 646 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg)); 647} 648 649void 650esp_wrreg1(sc, reg, v) 651 struct ncr53c9x_softc *sc; 652 int reg; 653 u_char v; 654{ 655 struct esp_softc *esc = (struct esp_softc *)sc; 656 657 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 658} 659 660int 661esp_dma_isintr(sc) 662 struct ncr53c9x_softc *sc; 663{ 664 struct esp_softc *esc = (struct esp_softc *)sc; 665 666 return (DMA_ISINTR(esc->sc_dma)); 667} 668 669void 670esp_dma_reset(sc) 671 struct ncr53c9x_softc *sc; 672{ 673 struct esp_softc *esc = (struct esp_softc *)sc; 674 675 DMA_RESET(esc->sc_dma); 676} 677 678int 679esp_dma_intr(sc) 680 struct ncr53c9x_softc *sc; 681{ 682 struct esp_softc *esc = (struct esp_softc *)sc; 683 684 return (DMA_INTR(esc->sc_dma)); 685} 686 687int 688esp_dma_setup(sc, addr, len, datain, dmasize) 689 struct ncr53c9x_softc *sc; 690 caddr_t *addr; 691 size_t *len; 692 int datain; 693 size_t *dmasize; 694{ 695 struct esp_softc *esc = (struct esp_softc *)sc; 696 697 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 698} 699 700void 701esp_dma_go(sc) 702 struct ncr53c9x_softc *sc; 703{ 704 struct esp_softc *esc = (struct esp_softc *)sc; 705 706 DMA_GO(esc->sc_dma); 707} 708 709void 710esp_dma_stop(sc) 711 struct ncr53c9x_softc *sc; 712{ 713 struct esp_softc *esc = (struct esp_softc *)sc; 714 u_int32_t csr; 715 716 csr = L64854_GCSR(esc->sc_dma); 717 csr &= ~D_EN_DMA; 718 L64854_SCSR(esc->sc_dma, csr); 719} 720 721int 722esp_dma_isactive(sc) 723 struct ncr53c9x_softc *sc; 724{ 725 struct esp_softc *esc = (struct esp_softc *)sc; 726 727 return (DMA_ISACTIVE(esc->sc_dma)); 728} 729 730#if defined(DDB) && defined(notyet) 731#include <machine/db_machdep.h> 732#include <ddb/db_output.h> 733 734void db_esp(db_expr_t, int, db_expr_t, char *); 735 736void 737db_esp(addr, have_addr, count, modif) 738 db_expr_t addr; 739 int have_addr; 740 db_expr_t count; 741 char *modif; 742{ 743 struct ncr53c9x_softc *sc; 744 struct ncr53c9x_ecb *ecb; 745 struct ncr53c9x_linfo *li; 746 int u, t, i; 747 748 for (u=0; u<10; u++) { 749 sc = (struct ncr53c9x_softc *) 750 getdevunit("esp", u); 751 if (!sc) continue; 752 753 db_printf("esp%d: nexus %p phase %x prev %x dp %p dleft %lx ify %x\n", 754 u, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 755 sc->sc_dp, sc->sc_dleft, sc->sc_msgify); 756 db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n", 757 sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0], 758 sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3], 759 sc->sc_imess[0]); 760 db_printf("ready: "); 761 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 762 db_printf("ecb %p ", ecb); 763 if (ecb == ecb->chain.tqe_next) { 764 db_printf("\nWARNING: tailq loop on ecb %p", ecb); 765 break; 766 } 767 } 768 db_printf("\n"); 769 770 for (t=0; t<NCR_NTARG; t++) { 771 LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) { 772 db_printf("t%d lun %d untagged %p busy %d used %x\n", 773 t, (int)li->lun, li->untagged, li->busy, 774 li->used); 775 for (i=0; i<256; i++) 776 if ((ecb = li->queued[i])) { 777 db_printf("ecb %p tag %x\n", ecb, i); 778 } 779 } 780 } 781 } 782} 783#endif 784 785