esp_sbus.c revision 1.1
1/* $NetBSD: esp_sbus.c,v 1.14 2001/04/25 17:53:37 bouyer Exp $ */ 2 3/*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum; Jason R. Thorpe of the Numerical Aerospace 9 * Simulation Facility, NASA Ames Research Center; Paul Kranenburg. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40#include <sys/types.h> 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/device.h> 44#include <sys/buf.h> 45#include <sys/malloc.h> 46 47#include <scsi/scsi_all.h> 48#include <scsi/scsiconf.h> 49#include <scsi/scsi_message.h> 50 51#include <machine/bus.h> 52#include <machine/intr.h> 53#include <machine/autoconf.h> 54 55#include <dev/ic/lsi64854reg.h> 56#include <dev/ic/lsi64854var.h> 57 58#include <dev/ic/ncr53c9xreg.h> 59#include <dev/ic/ncr53c9xvar.h> 60 61#include <dev/sbus/sbusvar.h> 62 63struct scsi_adapter esp_switch = { 64 ncr53c9x_scsi_cmd, 65 minphys, /* no max at this level; handled by DMA code */ 66 NULL, 67 NULL, 68}; 69 70struct scsi_device esp_dev = { 71 NULL, /* Use default error handler */ 72 NULL, /* have a queue, served by this */ 73 NULL, /* have no async handler */ 74 NULL, /* Use default 'done' routine */ 75}; 76 77/* #define ESP_SBUS_DEBUG */ 78 79struct esp_softc { 80 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 81 struct sbusdev sc_sd; /* sbus device */ 82 83 bus_space_tag_t sc_bustag; 84 bus_dma_tag_t sc_dmatag; 85 86 bus_space_handle_t sc_reg; /* the registers */ 87 struct lsi64854_softc *sc_dma; /* pointer to my dma */ 88 89 int sc_pri; /* SBUS priority */ 90}; 91 92void espattach_sbus __P((struct device *, struct device *, void *)); 93void espattach_dma __P((struct device *, struct device *, void *)); 94int espmatch_sbus __P((struct device *, void *, void *)); 95 96 97/* Linkup to the rest of the kernel */ 98struct cfattach esp_sbus_ca = { 99 sizeof(struct esp_softc), espmatch_sbus, espattach_sbus 100}; 101struct cfattach esp_dma_ca = { 102 sizeof(struct esp_softc), espmatch_sbus, espattach_dma 103}; 104 105/* 106 * Functions and the switch for the MI code. 107 */ 108static u_char esp_read_reg __P((struct ncr53c9x_softc *, int)); 109static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char)); 110static u_char esp_rdreg1 __P((struct ncr53c9x_softc *, int)); 111static void esp_wrreg1 __P((struct ncr53c9x_softc *, int, u_char)); 112static int esp_dma_isintr __P((struct ncr53c9x_softc *)); 113static void esp_dma_reset __P((struct ncr53c9x_softc *)); 114static int esp_dma_intr __P((struct ncr53c9x_softc *)); 115static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *, 116 size_t *, int, size_t *)); 117static void esp_dma_go __P((struct ncr53c9x_softc *)); 118static void esp_dma_stop __P((struct ncr53c9x_softc *)); 119static int esp_dma_isactive __P((struct ncr53c9x_softc *)); 120 121static struct ncr53c9x_glue esp_sbus_glue = { 122 esp_read_reg, 123 esp_write_reg, 124 esp_dma_isintr, 125 esp_dma_reset, 126 esp_dma_intr, 127 esp_dma_setup, 128 esp_dma_go, 129 esp_dma_stop, 130 esp_dma_isactive, 131 NULL, /* gl_clear_latched_intr */ 132}; 133 134static struct ncr53c9x_glue esp_sbus_glue1 = { 135 esp_rdreg1, 136 esp_wrreg1, 137 esp_dma_isintr, 138 esp_dma_reset, 139 esp_dma_intr, 140 esp_dma_setup, 141 esp_dma_go, 142 esp_dma_stop, 143 esp_dma_isactive, 144 NULL, /* gl_clear_latched_intr */ 145}; 146 147static void espattach __P((struct esp_softc *, struct ncr53c9x_glue *)); 148 149int 150espmatch_sbus(parent, vcf, aux) 151 struct device *parent; 152 void *vcf; 153 void *aux; 154{ 155 struct cfdata *cf = vcf; 156 int rv; 157 struct sbus_attach_args *sa = aux; 158 159 if (strcmp("SUNW,fas", sa->sa_name) == 0) 160 return 1; 161 162 rv = (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0 || 163 strcmp("ptscII", sa->sa_name) == 0); 164 return (rv); 165} 166 167void 168espattach_sbus(parent, self, aux) 169 struct device *parent, *self; 170 void *aux; 171{ 172 struct esp_softc *esc = (void *)self; 173 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 174 struct sbus_attach_args *sa = aux; 175 struct lsi64854_softc *lsc; 176 int burst, sbusburst; 177 178 esc->sc_bustag = sa->sa_bustag; 179 esc->sc_dmatag = sa->sa_dmatag; 180 181 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 182 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 183 if (sc->sc_freq < 0) 184 sc->sc_freq = ((struct sbus_softc *) 185 sc->sc_dev.dv_parent)->sc_clockfreq; 186 187#ifdef ESP_SBUS_DEBUG 188 printf("%s: espattach_sbus: sc_id %d, freq %d\n", 189 self->dv_xname, sc->sc_id, sc->sc_freq); 190#endif 191 192 if (strcmp("SUNW,fas", sa->sa_name) == 0) { 193 194 /* 195 * fas has 2 register spaces: dma(lsi64854) and SCSI core (ncr53c9x) 196 */ 197 if (sa->sa_nreg != 2) { 198 printf("%s: %d register spaces\n", self->dv_xname, sa->sa_nreg); 199 return; 200 } 201 202 /* 203 * allocate space for dma, in SUNW,fas there are no separate 204 * dma device 205 */ 206 lsc = malloc(sizeof (struct lsi64854_softc), M_DEVBUF, M_NOWAIT); 207 208 if (lsc == NULL) { 209 printf("%s: out of memory (lsi64854_softc)\n", 210 self->dv_xname); 211 return; 212 } 213 esc->sc_dma = lsc; 214 215 lsc->sc_bustag = sa->sa_bustag; 216 lsc->sc_dmatag = sa->sa_dmatag; 217 218 bcopy(sc->sc_dev.dv_xname, lsc->sc_dev.dv_xname, 219 sizeof (lsc->sc_dev.dv_xname)); 220 221 /* Map dma registers */ 222 if (bus_space_map2(sa->sa_bustag, 223 sa->sa_reg[0].sbr_slot, 224 sa->sa_reg[0].sbr_offset, 225 sa->sa_reg[0].sbr_size, 226 BUS_SPACE_MAP_LINEAR, 227 0, &lsc->sc_regs) != 0) { 228 printf("%s: cannot map dma registers\n", self->dv_xname); 229 return; 230 } 231 232 /* 233 * XXX is this common(from bpp.c), the same in dma_sbus...etc. 234 * 235 * Get transfer burst size from PROM and plug it into the 236 * controller registers. This is needed on the Sun4m; do 237 * others need it too? 238 */ 239 sbusburst = ((struct sbus_softc *)parent)->sc_burst; 240 if (sbusburst == 0) 241 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */ 242 243 burst = getpropint(sa->sa_node, "burst-sizes", -1); 244 245#if ESP_SBUS_DEBUG 246 printf("espattach_sbus: burst 0x%x, sbus 0x%x\n", 247 burst, sbusburst); 248#endif 249 250 if (burst == -1) 251 /* take SBus burst sizes */ 252 burst = sbusburst; 253 254 /* Clamp at parent's burst sizes */ 255 burst &= sbusburst; 256 lsc->sc_burst = (burst & SBUS_BURST_32) ? 32 : 257 (burst & SBUS_BURST_16) ? 16 : 0; 258 259 lsc->sc_channel = L64854_CHANNEL_SCSI; 260 lsc->sc_client = sc; 261 262 lsi64854_attach(lsc); 263 264 /* 265 * map SCSI core registers 266 */ 267 if (sbus_bus_map(sa->sa_bustag, 268 sa->sa_reg[1].sbr_slot, 269 sa->sa_reg[1].sbr_offset, 270 sa->sa_reg[1].sbr_size, 271 BUS_SPACE_MAP_LINEAR, 272 0, &esc->sc_reg) != 0) { 273 printf("%s @ sbus: cannot map scsi core registers\n", 274 self->dv_xname); 275 return; 276 } 277 278 if (sa->sa_nintr == 0) { 279 printf("\n%s: no interrupt property\n", self->dv_xname); 280 return; 281 } 282 283 esc->sc_pri = sa->sa_pri; 284 285 /* add me to the sbus structures */ 286 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 287 sbus_establish(&esc->sc_sd, &sc->sc_dev); 288 289 espattach(esc, &esp_sbus_glue); 290 291 return; 292 } 293 294 /* 295 * Find the DMA by poking around the dma device structures 296 * 297 * What happens here is that if the dma driver has not been 298 * configured, then this returns a NULL pointer. Then when the 299 * dma actually gets configured, it does the opposing test, and 300 * if the sc->sc_esp field in it's softc is NULL, then tries to 301 * find the matching esp driver. 302 */ 303 esc->sc_dma = (struct lsi64854_softc *) 304 getdevunit("dma", sc->sc_dev.dv_unit); 305 306 /* 307 * and a back pointer to us, for DMA 308 */ 309 if (esc->sc_dma) 310 esc->sc_dma->sc_client = sc; 311 else { 312 printf("\n"); 313 panic("espattach: no dma found"); 314 } 315 316 /* 317 * Map my registers in, if they aren't already in virtual 318 * address space. 319 */ 320 if (sa->sa_npromvaddrs) 321 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 322 else { 323 if (sbus_bus_map(sa->sa_bustag, sa->sa_slot, 324 sa->sa_offset, 325 sa->sa_size, 326 BUS_SPACE_MAP_LINEAR, 327 0, &esc->sc_reg) != 0) { 328 printf("%s @ sbus: cannot map registers\n", 329 self->dv_xname); 330 return; 331 } 332 } 333 334 if (sa->sa_nintr == 0) { 335 /* 336 * No interrupt properties: we quit; this might 337 * happen on e.g. a Sparc X terminal. 338 */ 339 printf("\n%s: no interrupt property\n", self->dv_xname); 340 return; 341 } 342 343 esc->sc_pri = sa->sa_pri; 344 345 /* add me to the sbus structures */ 346 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 347 sbus_establish(&esc->sc_sd, &sc->sc_dev); 348 349 if (strcmp("ptscII", sa->sa_name) == 0) { 350 espattach(esc, &esp_sbus_glue1); 351 } else { 352 espattach(esc, &esp_sbus_glue); 353 } 354} 355 356void 357espattach_dma(parent, self, aux) 358 struct device *parent, *self; 359 void *aux; 360{ 361 struct esp_softc *esc = (void *)self; 362 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 363 struct sbus_attach_args *sa = aux; 364 365 if (strcmp("ptscII", sa->sa_name) == 0) { 366 return; 367 } 368 369 esc->sc_bustag = sa->sa_bustag; 370 esc->sc_dmatag = sa->sa_dmatag; 371 372 sc->sc_id = getpropint(sa->sa_node, "initiator-id", 7); 373 sc->sc_freq = getpropint(sa->sa_node, "clock-frequency", -1); 374 375 esc->sc_dma = (struct lsi64854_softc *)parent; 376 esc->sc_dma->sc_client = sc; 377 378 /* 379 * Map my registers in, if they aren't already in virtual 380 * address space. 381 */ 382 if (sa->sa_npromvaddrs) 383 esc->sc_reg = (bus_space_handle_t)sa->sa_promvaddrs[0]; 384 else { 385 if (bus_space_map2(sa->sa_bustag, 386 sa->sa_slot, 387 sa->sa_offset, 388 sa->sa_size, 389 BUS_SPACE_MAP_LINEAR, 390 0, &esc->sc_reg) != 0) { 391 printf("%s @ dma: cannot map registers\n", 392 self->dv_xname); 393 return; 394 } 395 } 396 397 if (sa->sa_nintr == 0) { 398 /* 399 * No interrupt properties: we quit; this might 400 * happen on e.g. a Sparc X terminal. 401 */ 402 printf("\n%s: no interrupt property\n", self->dv_xname); 403 return; 404 } 405 406 esc->sc_pri = sa->sa_pri; 407 408 /* Assume SBus is grandparent */ 409 esc->sc_sd.sd_reset = (void *) ncr53c9x_reset; 410 sbus_establish(&esc->sc_sd, parent); 411 412 espattach(esc, &esp_sbus_glue); 413} 414 415 416/* 417 * Attach this instance, and then all the sub-devices 418 */ 419void 420espattach(esc, gluep) 421 struct esp_softc *esc; 422 struct ncr53c9x_glue *gluep; 423{ 424 struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x; 425 void *icookie; 426 unsigned int uid = 0; 427 428 /* 429 * Set up glue for MI code early; we use some of it here. 430 */ 431 sc->sc_glue = gluep; 432 433 /* gimme Mhz */ 434 sc->sc_freq /= 1000000; 435 436 /* 437 * XXX More of this should be in ncr53c9x_attach(), but 438 * XXX should we really poke around the chip that much in 439 * XXX the MI code? Think about this more... 440 */ 441 442 /* 443 * It is necessary to try to load the 2nd config register here, 444 * to find out what rev the esp chip is, else the ncr53c9x_reset 445 * will not set up the defaults correctly. 446 */ 447 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 448 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE; 449 sc->sc_cfg3 = NCRCFG3_CDB; 450 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 451 452 if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) != 453 (NCRCFG2_SCSI2 | NCRCFG2_RPE)) { 454 sc->sc_rev = NCR_VARIANT_ESP100; 455 } else { 456 sc->sc_cfg2 = NCRCFG2_SCSI2; 457 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 458 sc->sc_cfg3 = 0; 459 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 460 sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK); 461 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 462 if (NCR_READ_REG(sc, NCR_CFG3) != 463 (NCRCFG3_CDB | NCRCFG3_FCLK)) { 464 sc->sc_rev = NCR_VARIANT_ESP100A; 465 } else { 466 /* NCRCFG2_FE enables > 64K transfers */ 467 sc->sc_cfg2 |= NCRCFG2_FE; 468 sc->sc_cfg3 = 0; 469 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 470 sc->sc_rev = NCR_VARIANT_ESP200; 471 472 /* XXX spec says it's valid after power up or chip reset */ 473 uid = NCR_READ_REG(sc, NCR_UID); 474 if (((uid & 0xf8) >> 3) == 0x0a) /* XXX */ 475 sc->sc_rev = NCR_VARIANT_FAS366; 476 } 477 } 478 479#ifdef ESP_SBUS_DEBUG 480 printf("espattach: revision %d, uid 0x%x\n", sc->sc_rev, uid); 481#endif 482 483 /* 484 * XXX minsync and maxxfer _should_ be set up in MI code, 485 * XXX but it appears to have some dependency on what sort 486 * XXX of DMA we're hooked up to, etc. 487 */ 488 489 /* 490 * This is the value used to start sync negotiations 491 * Note that the NCR register "SYNCTP" is programmed 492 * in "clocks per byte", and has a minimum value of 4. 493 * The SCSI period used in negotiation is one-fourth 494 * of the time (in nanoseconds) needed to transfer one byte. 495 * Since the chip's clock is given in MHz, we have the following 496 * formula: 4 * period = (1000 / freq) * 4 497 */ 498 sc->sc_minsync = 1000 / sc->sc_freq; 499 500 /* 501 * Alas, we must now modify the value a bit, because it's 502 * only valid when can switch on FASTCLK and FASTSCSI bits 503 * in config register 3... 504 */ 505 switch (sc->sc_rev) { 506 case NCR_VARIANT_ESP100: 507 sc->sc_maxxfer = 64 * 1024; 508 sc->sc_minsync = 0; /* No synch on old chip? */ 509 break; 510 511 case NCR_VARIANT_ESP100A: 512 sc->sc_maxxfer = 64 * 1024; 513 /* Min clocks/byte is 5 */ 514 sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5); 515 break; 516 517 case NCR_VARIANT_ESP200: 518 case NCR_VARIANT_FAS366: 519 sc->sc_maxxfer = 16 * 1024 * 1024; 520 /* XXX - do actually set FAST* bits */ 521 break; 522 } 523 524 /* Establish interrupt channel */ 525 icookie = bus_intr_establish(esc->sc_bustag, esc->sc_pri, IPL_BIO, 0, 526 ncr53c9x_intr, sc); 527 528 /* register interrupt stats */ 529 evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt); 530 531 /* Turn on target selection using the `dma' method */ 532 if (sc->sc_rev != NCR_VARIANT_FAS366) 533 ncr53c9x_dmaselect = 1; 534 535 /* Do the common parts of attachment. */ 536 ncr53c9x_attach(sc, &esp_switch, &esp_dev); 537} 538 539/* 540 * Glue functions. 541 */ 542 543#ifdef ESP_SBUS_DEBUG 544int esp_sbus_debug = 0; 545 546static struct { 547 char *r_name; 548 int r_flag; 549} esp__read_regnames [] = { 550 { "TCL", 0}, /* 0/00 */ 551 { "TCM", 0}, /* 1/04 */ 552 { "FIFO", 0}, /* 2/08 */ 553 { "CMD", 0}, /* 3/0c */ 554 { "STAT", 0}, /* 4/10 */ 555 { "INTR", 0}, /* 5/14 */ 556 { "STEP", 0}, /* 6/18 */ 557 { "FFLAGS", 1}, /* 7/1c */ 558 { "CFG1", 1}, /* 8/20 */ 559 { "STAT2", 0}, /* 9/24 */ 560 { "CFG4", 1}, /* a/28 */ 561 { "CFG2", 1}, /* b/2c */ 562 { "CFG3", 1}, /* c/30 */ 563 { "-none", 1}, /* d/34 */ 564 { "TCH", 1}, /* e/38 */ 565 { "TCX", 1}, /* f/3c */ 566}; 567 568static struct { 569 char *r_name; 570 int r_flag; 571} esp__write_regnames[] = { 572 { "TCL", 1}, /* 0/00 */ 573 { "TCM", 1}, /* 1/04 */ 574 { "FIFO", 0}, /* 2/08 */ 575 { "CMD", 0}, /* 3/0c */ 576 { "SELID", 1}, /* 4/10 */ 577 { "TIMEOUT", 1}, /* 5/14 */ 578 { "SYNCTP", 1}, /* 6/18 */ 579 { "SYNCOFF", 1}, /* 7/1c */ 580 { "CFG1", 1}, /* 8/20 */ 581 { "CCF", 1}, /* 9/24 */ 582 { "TEST", 1}, /* a/28 */ 583 { "CFG2", 1}, /* b/2c */ 584 { "CFG3", 1}, /* c/30 */ 585 { "-none", 1}, /* d/34 */ 586 { "TCH", 1}, /* e/38 */ 587 { "TCX", 1}, /* f/3c */ 588}; 589#endif 590 591u_char 592esp_read_reg(sc, reg) 593 struct ncr53c9x_softc *sc; 594 int reg; 595{ 596 struct esp_softc *esc = (struct esp_softc *)sc; 597 u_char v; 598 599 v = bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg * 4); 600#ifdef ESP_SBUS_DEBUG 601 if (esp_sbus_debug && (reg < 0x10) && esp__read_regnames[reg].r_flag) 602 printf("RD:%x <%s> %x\n", reg * 4, 603 ((unsigned)reg < 0x10) ? esp__read_regnames[reg].r_name : "<***>", v); 604#endif 605 return v; 606} 607 608void 609esp_write_reg(sc, reg, v) 610 struct ncr53c9x_softc *sc; 611 int reg; 612 u_char v; 613{ 614 struct esp_softc *esc = (struct esp_softc *)sc; 615 616#ifdef ESP_SBUS_DEBUG 617 if (esp_sbus_debug && (reg < 0x10) && esp__write_regnames[reg].r_flag) 618 printf("WR:%x <%s> %x\n", reg * 4, 619 ((unsigned)reg < 0x10) ? esp__write_regnames[reg].r_name : "<***>", v); 620#endif 621 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg * 4, v); 622} 623 624u_char 625esp_rdreg1(sc, reg) 626 struct ncr53c9x_softc *sc; 627 int reg; 628{ 629 struct esp_softc *esc = (struct esp_softc *)sc; 630 631 return (bus_space_read_1(esc->sc_bustag, esc->sc_reg, reg)); 632} 633 634void 635esp_wrreg1(sc, reg, v) 636 struct ncr53c9x_softc *sc; 637 int reg; 638 u_char v; 639{ 640 struct esp_softc *esc = (struct esp_softc *)sc; 641 642 bus_space_write_1(esc->sc_bustag, esc->sc_reg, reg, v); 643} 644 645int 646esp_dma_isintr(sc) 647 struct ncr53c9x_softc *sc; 648{ 649 struct esp_softc *esc = (struct esp_softc *)sc; 650 651 return (DMA_ISINTR(esc->sc_dma)); 652} 653 654void 655esp_dma_reset(sc) 656 struct ncr53c9x_softc *sc; 657{ 658 struct esp_softc *esc = (struct esp_softc *)sc; 659 660 DMA_RESET(esc->sc_dma); 661} 662 663int 664esp_dma_intr(sc) 665 struct ncr53c9x_softc *sc; 666{ 667 struct esp_softc *esc = (struct esp_softc *)sc; 668 669 return (DMA_INTR(esc->sc_dma)); 670} 671 672int 673esp_dma_setup(sc, addr, len, datain, dmasize) 674 struct ncr53c9x_softc *sc; 675 caddr_t *addr; 676 size_t *len; 677 int datain; 678 size_t *dmasize; 679{ 680 struct esp_softc *esc = (struct esp_softc *)sc; 681 682 return (DMA_SETUP(esc->sc_dma, addr, len, datain, dmasize)); 683} 684 685void 686esp_dma_go(sc) 687 struct ncr53c9x_softc *sc; 688{ 689 struct esp_softc *esc = (struct esp_softc *)sc; 690 691 DMA_GO(esc->sc_dma); 692} 693 694void 695esp_dma_stop(sc) 696 struct ncr53c9x_softc *sc; 697{ 698 struct esp_softc *esc = (struct esp_softc *)sc; 699 u_int32_t csr; 700 701 csr = L64854_GCSR(esc->sc_dma); 702 csr &= ~D_EN_DMA; 703 L64854_SCSR(esc->sc_dma, csr); 704} 705 706int 707esp_dma_isactive(sc) 708 struct ncr53c9x_softc *sc; 709{ 710 struct esp_softc *esc = (struct esp_softc *)sc; 711 712 return (DMA_ISACTIVE(esc->sc_dma)); 713} 714 715#if defined(DDB) && defined(notyet) 716#include <machine/db_machdep.h> 717#include <ddb/db_output.h> 718 719void db_esp __P((db_expr_t, int, db_expr_t, char*)); 720 721void 722db_esp(addr, have_addr, count, modif) 723 db_expr_t addr; 724 int have_addr; 725 db_expr_t count; 726 char *modif; 727{ 728 struct ncr53c9x_softc *sc; 729 struct ncr53c9x_ecb *ecb; 730 struct ncr53c9x_linfo *li; 731 int u, t, i; 732 733 for (u=0; u<10; u++) { 734 sc = (struct ncr53c9x_softc *) 735 getdevunit("esp", u); 736 if (!sc) continue; 737 738 db_printf("esp%d: nexus %p phase %x prev %x dp %p dleft %lx ify %x\n", 739 u, sc->sc_nexus, sc->sc_phase, sc->sc_prevphase, 740 sc->sc_dp, sc->sc_dleft, sc->sc_msgify); 741 db_printf("\tmsgout %x msgpriq %x msgin %x:%x:%x:%x:%x\n", 742 sc->sc_msgout, sc->sc_msgpriq, sc->sc_imess[0], 743 sc->sc_imess[1], sc->sc_imess[2], sc->sc_imess[3], 744 sc->sc_imess[0]); 745 db_printf("ready: "); 746 for (ecb = sc->ready_list.tqh_first; ecb; ecb = ecb->chain.tqe_next) { 747 db_printf("ecb %p ", ecb); 748 if (ecb == ecb->chain.tqe_next) { 749 db_printf("\nWARNING: tailq loop on ecb %p", ecb); 750 break; 751 } 752 } 753 db_printf("\n"); 754 755 for (t=0; t<NCR_NTARG; t++) { 756 LIST_FOREACH(li, &sc->sc_tinfo[t].luns, link) { 757 db_printf("t%d lun %d untagged %p busy %d used %x\n", 758 t, (int)li->lun, li->untagged, li->busy, 759 li->used); 760 for (i=0; i<256; i++) 761 if ((ecb = li->queued[i])) { 762 db_printf("ecb %p tag %x\n", ecb, i); 763 } 764 } 765 } 766 } 767} 768#endif 769 770