qlereg.h revision 1.9
1/* $OpenBSD: qlereg.h,v 1.9 2014/04/20 09:49:23 jmatthew Exp $ */ 2 3/* 4 * Copyright (c) 2013, 2014 Jonathan Matthew <jmatthew@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19/* firmware loading */ 20#define QLE_2400_CODE_ORG 0x00100000 21 22/* interrupt types */ 23#define QLE_INT_TYPE_MBOX 1 24#define QLE_INT_TYPE_ASYNC 2 25#define QLE_INT_TYPE_IO 3 26#define QLE_INT_TYPE_OTHER 4 27 28/* 24xx interrupt status codes */ 29#define QLE_24XX_INT_ROM_MBOX 0x01 30#define QLE_24XX_INT_ROM_MBOX_FAIL 0x02 31#define QLE_24XX_INT_MBOX 0x10 32#define QLE_24XX_INT_MBOX_FAIL 0x11 33#define QLE_24XX_INT_ASYNC 0x12 34#define QLE_24XX_INT_RSPQ 0x13 35 36/* ISP registers */ 37#define QLE_FLASH_NVRAM_ADDR 0x000 38#define QLE_FLASH_NVRAM_DATA 0x004 39#define QLE_CTRL_STATUS 0x008 40#define QLE_INT_CTRL 0x00C 41#define QLE_INT_STATUS 0x010 42#define QLE_REQ_IN 0x01C 43#define QLE_REQ_OUT 0x020 44#define QLE_RESP_IN 0x024 45#define QLE_RESP_OUT 0x028 46#define QLE_PRI_REQ_IN 0x02C 47#define QLE_PRI_REQ_OUT 0x030 48#define QLE_RISC_STATUS 0x044 49#define QLE_HOST_CMD_CTRL 0x048 50#define QLE_GPIO_DATA 0x04C 51#define QLE_GPIO_ENABLE 0x050 52#define QLE_HOST_SEMAPHORE 0x058 53 54/* mailbox base moves around between generations */ 55#define QLE_MBOX_BASE_24XX 0x080 56 57/* QLE_CTRL_STATUS */ 58#define QLE_CTRL_DMA_ACTIVE 0x00020000 59#define QLE_CTRL_DMA_SHUTDOWN 0x00010000 60#define QLE_CTRL_RESET 0x00000001 61 62/* QLE_INT_STATUS */ 63#define QLE_RISC_INT_REQ 0x00000008 64 65/* QLE_INT_CTRL */ 66#define QLE_INT_CTRL_ENABLE 0x00000008 67 68/* QLE_RISC_STATUS */ 69#define QLE_INT_INFO_SHIFT 16 70#define QLE_RISC_HOST_INT_REQ 0x00008000 71#define QLE_RISC_PAUSED 0x00000100 72#define QLE_INT_STATUS_MASK 0x000000FF 73 74/* QLE_HOST_CMD_CTRL write */ 75#define QLE_HOST_CMD_SHIFT 28 76#define QLE_HOST_CMD_NOP 0x0 77#define QLE_HOST_CMD_RESET 0x1 78#define QLE_HOST_CMD_CLEAR_RESET 0x2 79#define QLE_HOST_CMD_PAUSE 0x3 80#define QLE_HOST_CMD_RELEASE 0x4 81#define QLE_HOST_CMD_SET_HOST_INT 0x5 82#define QLE_HOST_CMD_CLR_HOST_INT 0x6 83#define QLE_HOST_CMD_CLR_RISC_INT 0xA 84 85/* QLE_HOST_CMD_CTRL read */ 86#define QLE_HOST_STATUS_ERROR_SHIFT 12 87#define QLE_HOST_STATUS_HOST_INT 0x00000040 88#define QLE_HOST_STATUS_RISC_RESET 0x00000020 89 90/* QLE_HOST_SEMAPHORE */ 91#define QLE_HOST_SEMAPHORE_LOCK 0x00000001 92 93 94/* QLE_MBOX_BASE (reg 0) read */ 95#define QLE_MBOX_HAS_STATUS 0x4000 96#define QLE_MBOX_COMPLETE 0x4000 97#define QLE_MBOX_INVALID 0x4001 98#define QLE_MBOX_INTF_ERROR 0x4002 99#define QLE_MBOX_TEST_FAILED 0x4003 100#define QLE_MBOX_CMD_ERROR 0x4005 101#define QLE_MBOX_CMD_PARAM 0x4006 102#define QLE_MBOX_LINK_DOWN 0x400B 103#define QLE_MBOX_DIAG_ERROR 0x400C 104#define QLE_MBOX_CSUM_ERROR 0x4010 105#define QLE_ASYNC_SYSTEM_ERROR 0x8002 106#define QLE_ASYNC_REQ_XFER_ERROR 0x8003 107#define QLE_ASYNC_RSP_XFER_ERROR 0x8004 108#define QLE_ASYNC_LIP_OCCURRED 0x8010 109#define QLE_ASYNC_LOOP_UP 0x8011 110#define QLE_ASYNC_LOOP_DOWN 0x8012 111#define QLE_ASYNC_LIP_RESET 0x8013 112#define QLE_ASYNC_PORT_DB_CHANGE 0x8014 113#define QLE_ASYNC_CHANGE_NOTIFY 0x8015 114#define QLE_ASYNC_LIP_F8 0x8016 115#define QLE_ASYNC_LOOP_INIT_ERROR 0x8017 116#define QLE_ASYNC_POINT_TO_POINT 0x8030 117#define QLE_ASYNC_ZIO_RESP_UPDATE 0x8040 118#define QLE_ASYNC_RECV_ERROR 0x8048 119#define QLE_ASYNC_LOGIN_RJT_SENT 0x8049 120 121 122/* QLE_MBOX_BASE (reg 0) write */ 123#define QLE_MBOX_NOP 0x0000 124#define QLE_MBOX_EXEC_FIRMWARE 0x0002 125#define QLE_MBOX_REGISTER_TEST 0x0006 126#define QLE_MBOX_VERIFY_CSUM 0x0007 127#define QLE_MBOX_ABOUT_FIRMWARE 0x0008 128#define QLE_MBOX_LOAD_RISC_RAM 0x000B 129#define QLE_MBOX_INIT_RISC_RAM 0x000E 130#define QLE_MBOX_READ_RISC_RAM 0x000F 131#define QLE_MBOX_GET_IO_STATUS 0x0012 132#define QLE_MBOX_STOP_FIRMWARE 0x0014 133#define QLE_MBOX_GET_ID 0x0020 134#define QLE_MBOX_SET_FIRMWARE_OPTIONS 0x0038 135#define QLE_MBOX_PLOGO 0x0056 136#define QLE_MBOX_DATA_RATE 0x005D 137#define QLE_MBOX_INIT_FIRMWARE 0x0060 138#define QLE_MBOX_GET_INIT_CB 0x0061 139#define QLE_MBOX_GET_FC_AL_POS 0x0063 140#define QLE_MBOX_GET_PORT_DB 0x0064 141#define QLE_MBOX_GET_FIRMWARE_STATE 0x0069 142#define QLE_MBOX_GET_PORT_NAME 0x006A 143#define QLE_MBOX_GET_LINK_STATUS 0x006B 144#define QLE_MBOX_SEND_CHANGE_REQ 0x0070 145#define QLE_MBOX_LINK_INIT 0x0072 146#define QLE_MBOX_GET_PORT_NAME_LIST 0x0075 147 148#define QLE_MBOX_COUNT 32 149 150/* nvram layout */ 151struct qle_nvram { 152 u_int8_t id[4]; 153 u_int16_t nvram_version; 154 u_int16_t reserved_0; 155 156 u_int16_t version; 157 u_int16_t reserved_1; 158 u_int16_t frame_payload_size; 159 u_int16_t execution_throttle; 160 u_int16_t exchg_count; 161 u_int16_t hard_address; 162 163 u_int64_t port_name; 164 u_int64_t node_name; 165 166 u_int16_t login_retry; 167 u_int16_t link_down_on_nos; 168 u_int16_t int_delay_timer; 169 u_int16_t login_timeout; 170 171 u_int32_t fwoptions1; 172 u_int32_t fwoptions2; 173 u_int32_t fwoptions3; 174 175 u_int16_t serial_options[4]; 176 177 u_int16_t reserved_2[96]; 178 179 u_int32_t host_p; 180 181 u_int64_t alt_port_name; 182 u_int64_t alt_node_name; 183 184 u_int64_t boot_port_name; 185 u_int16_t boot_lun; 186 u_int16_t reserved_3; 187 188 u_int64_t alt1_boot_port_name; 189 u_int16_t alt1_boot_lun; 190 u_int16_t reserved_4; 191 192 u_int64_t alt2_boot_port_name; 193 u_int16_t alt2_boot_lun; 194 u_int16_t reserved_5; 195 196 u_int64_t alt3_boot_port_name; 197 u_int16_t alt3_boot_lun; 198 u_int16_t reserved_6; 199 200 u_int32_t efi_param; 201 202 u_int8_t reset_delay; 203 u_int8_t reserved_7; 204 u_int16_t reserved_8; 205 206 u_int16_t boot_id_num; 207 u_int16_t reserved_9; 208 209 u_int16_t max_luns_per_target; 210 u_int16_t reserved_10; 211 212 u_int16_t port_down_retry_count; 213 u_int16_t link_down_timeout; 214 215 u_int16_t fcode_param; 216 u_int16_t reserved_11[3]; 217 218 u_int8_t prev_drv_ver_major; 219 u_int8_t prev_drv_ver_submajor; 220 u_int8_t prev_drv_ver_minor; 221 u_int8_t prev_drv_ver_subminor; 222 223 u_int16_t prev_bios_ver_major; 224 u_int16_t prev_bios_ver_minor; 225 226 u_int16_t prev_efi_ver_major; 227 u_int16_t prev_efi_ver_minor; 228 229 u_int16_t prev_fw_ver_major; 230 u_int8_t prev_fw_ver_minor; 231 u_int8_t prev_fw_ver_subminor; 232 233 u_int16_t reserved_12[56]; 234 235 u_int8_t model_namep[16]; 236 237 u_int16_t reserved_13[2]; 238 239 u_int16_t pcie_table_sig; 240 u_int16_t pcie_table_offset; 241 u_int16_t subsystem_vendor_id; 242 u_int16_t subsystem_device_id; 243 244 u_int32_t checksum; 245} __packed __aligned(4); 246 247/* init firmware control block */ 248#define QLE_ICB_VERSION 1 249 250#define QLE_ICB_FW1_HARD_ADDR 0x0001 251#define QLE_ICB_FW1_FAIRNESS 0x0002 252#define QLE_ICB_FW1_FULL_DUPLEX 0x0004 253#define QLE_ICB_FW1_TARGET_MODE 0x0010 254#define QLE_ICB_FW1_DISABLE_INITIATOR 0x0020 255#define QLE_ICB_FW1_DISABLE_INIT_LIP 0x0200 256#define QLE_ICB_FW1_DESC_LOOP_ID 0x0400 257#define QLE_ICB_FW1_PREV_LOOP_ID 0x0800 258#define QLE_ICB_FW1_LOGIN_AFTER_LIP 0x2000 259#define QLE_ICB_FW1_NAME_OPTION 0x4000 260 261#define QLE_ICB_FW2_LOOP_ONLY 0x0000 262#define QLE_ICB_FW2_PTP_ONLY 0x0010 263#define QLE_ICB_FW2_LOOP_PTP 0x0020 264#define QLE_ICB_FW2_ZIO_DISABLED 0x0000 265#define QLE_ICB_FW2_ZIO5_ENABLED 0x0005 266#define QLE_ICB_FW2_ZIO6_ENABLED 0x0006 267#define QLE_ICB_FW2_HARD_ADDR_ONLY 0x0080 268 269#define QLE_ICB_FW3_SOFT_ID_ONLY 0x0002 270#define QLE_ICB_FW3_FCP_RSP_12_0 0x0010 271#define QLE_ICB_FW3_FCP_RSP_24_0 0x0020 272#define QLE_ICB_FW3_FCP_RSP_32_BYTES 0x0030 273#define QLE_ICB_FW3_ENABLE_OOO 0x0040 274#define QLE_ICB_FW3_NO_AUTO_PLOGI 0x0080 275#define QLE_ICB_FW3_ENABLE_OOO_RDY 0x0200 276#define QLE_ICB_FW3_1GBPS 0x0000 277#define QLE_ICB_FW3_2GBPS 0x2000 278#define QLE_ICB_FW3_AUTONEG 0x4000 279#define QLE_ICB_FW3_4GBPS 0x6000 280#define QLE_ICB_FW3_50_OHMS 0x8000 281 282 283struct qle_init_cb { 284 u_int16_t icb_version; 285 u_int16_t icb_reserved; 286 u_int16_t icb_max_frame_len; 287 u_int16_t icb_exec_throttle; 288 u_int16_t icb_exchange_count; 289 u_int16_t icb_hardaddr; 290 u_int64_t icb_portname; 291 u_int64_t icb_nodename; 292 u_int16_t icb_resp_in; 293 u_int16_t icb_req_out; 294 u_int16_t icb_login_retry; 295 u_int16_t icb_pri_req_out; 296 u_int16_t icb_resp_queue_len; 297 u_int16_t icb_req_queue_len; 298 u_int16_t icb_link_down_nos; 299 u_int16_t icb_pri_req_queue_len; 300 u_int32_t icb_req_queue_addr_lo; 301 u_int32_t icb_req_queue_addr_hi; 302 u_int32_t icb_resp_queue_addr_lo; 303 u_int32_t icb_resp_queue_addr_hi; 304 u_int32_t icb_pri_req_queue_addr_lo; 305 u_int32_t icb_pri_req_queue_addr_hi; 306 u_int8_t icb_reserved2[8]; 307 u_int16_t icb_atio_queue_in; 308 u_int16_t icb_atio_queue_len; 309 u_int64_t icb_atio_queue_addr; 310 u_int16_t icb_int_delay; 311 u_int16_t icb_login_timeout; 312 u_int32_t icb_fwoptions1; 313 u_int32_t icb_fwoptions2; 314 u_int32_t icb_fwoptions3; 315 u_int8_t icb_reserved3[24]; 316} __packed __aligned(4); 317 318#define QLE_FW_OPTION1_ASYNC_LIP_F8 0x0001 319#define QLE_FW_OPTION1_ASYNC_LIP_RESET 0x0002 320#define QLE_FW_OPTION1_SYNC_LOSS_LIP 0x0010 321#define QLE_FW_OPTION1_ASYNC_LIP_ERROR 0x0080 322#define QLE_FW_OPTION1_ASYNC_LOGIN_RJT 0x0800 323 324#define QLE_FW_OPTION3_EMERG_IOCB 0x0001 325#define QLE_FW_OPTION3_ASYNC_RND_ERROR 0x0002 326 327/* topology types returned from QLE_MBOX_GET_LOOP_ID */ 328#define QLE_TOPO_NL_PORT 0 329#define QLE_TOPO_FL_PORT 1 330#define QLE_TOPO_N_PORT 2 331#define QLE_TOPO_F_PORT 3 332#define QLE_TOPO_N_PORT_NO_TARGET 4 333 334 335struct qle_get_port_db { 336 u_int16_t flags; 337 u_int8_t current_login_state; 338 u_int8_t stable_login_state; 339 u_int8_t adisc_addr[3]; 340 u_int8_t reserved; 341 u_int8_t port_id[3]; 342 u_int8_t sequence_id; 343 u_int16_t retry_timer; 344 u_int16_t nport_handle; 345 u_int16_t recv_data_size; 346 u_int16_t reserved2; 347 u_int16_t prli_svc_word0; 348 u_int16_t prli_svc_word3; 349 u_int64_t port_name; 350 u_int64_t node_name; 351 u_int8_t reserved3[24]; 352} __packed __aligned(4); 353 354struct qle_port_name_list { 355 u_int64_t port_name; 356 u_int16_t loopid; 357 u_int16_t reserved; 358} __packed; 359 360#define QLE_SVC3_TARGET_ROLE 0x0010 361 362/* fabric name server commands */ 363#define QLE_SNS_GA_NXT 0x0100 364#define QLE_SNS_GID_FT 0x0171 365#define QLE_SNS_RFT_ID 0x0217 366 367#define QLE_FC4_SCSI 8 368 369#define QLE_LS_REJECT 0x8001 370#define QLE_LS_ACCEPT 0x8002 371 372struct qle_ct_cmd_hdr { 373 u_int8_t ct_revision; 374 u_int8_t ct_id[3]; 375 u_int8_t ct_gs_type; 376 u_int8_t ct_gs_subtype; 377 u_int8_t ct_gs_options; 378 u_int8_t ct_gs_reserved; 379} __packed __aligned(4); 380 381struct qle_ct_ga_nxt_req { 382 struct qle_ct_cmd_hdr header; 383 u_int16_t subcmd; 384 u_int16_t max_word; 385 u_int32_t reserved3; 386 u_int32_t port_id; 387} __packed __aligned(4); 388 389struct qle_ct_ga_nxt_resp { 390 struct qle_ct_cmd_hdr header; 391 u_int16_t response; 392 u_int16_t residual; 393 u_int8_t fragment_id; 394 u_int8_t reason_code; 395 u_int8_t explanation_code; 396 u_int8_t vendor_unique; 397 398 u_int32_t port_type_id; 399 u_int64_t port_name; 400 u_int8_t sym_port_name_len; 401 u_int8_t sym_port_name[255]; 402 u_int64_t node_name; 403 u_int8_t sym_node_name_len; 404 u_int8_t sym_node_name[255]; 405 u_int64_t initial_assoc; 406 u_int8_t node_ip_addr[16]; 407 u_int32_t cos; 408 u_int32_t fc4_types[8]; 409 u_int8_t ip_addr[16]; 410 u_int64_t fabric_port_name; 411 u_int32_t hard_address; 412} __packed __aligned(4); 413 414struct qle_ct_rft_id_req { 415 struct qle_ct_cmd_hdr header; 416 u_int16_t subcmd; 417 u_int16_t max_word; 418 u_int32_t reserved3; 419 u_int32_t port_id; 420 u_int32_t fc4_types[8]; 421} __packed __aligned(4); 422 423struct qle_ct_rft_id_resp { 424 struct qle_ct_cmd_hdr header; 425 u_int16_t response; 426 u_int16_t residual; 427 u_int8_t fragment_id; 428 u_int8_t reason_code; 429 u_int8_t explanation_code; 430 u_int8_t vendor_unique; 431} __packed __aligned(4); 432 433/* available handle ranges */ 434#define QLE_MIN_HANDLE 0x81 435#define QLE_MAX_HANDLE 0x7EF 436 437#define QLE_F_PORT_HANDLE 0x7FE 438#define QLE_FABRIC_CTRL_HANDLE 0x7FD 439#define QLE_SNS_HANDLE 0x7FC 440#define QLE_IP_BCAST_HANDLE 0xFFF 441 442/* IOCB types */ 443#define QLE_IOCB_STATUS 0x03 444#define QLE_IOCB_MARKER 0x04 445#define QLE_IOCB_STATUS_CONT 0x10 446#define QLE_IOCB_CMD_TYPE_7 0x18 447#define QLE_IOCB_CT_PASSTHROUGH 0x29 448#define QLE_IOCB_MAILBOX 0x39 449#define QLE_IOCB_CMD_TYPE_6 0x48 450#define QLE_IOCB_PLOGX 0x52 451 452#define QLE_REQ_FLAG_CONT 0x01 453#define QLE_REQ_FLAG_FULL 0x02 454#define QLE_REQ_FLAG_BAD_HDR 0x04 455#define QLE_REQ_FLAG_BAD_PKT 0x08 456 457#define QLE_RESP_FLAG_INVALID_COUNT 0x10 458#define QLE_RESP_FLAG_INVALID_ORDER 0x20 459#define QLE_RESP_FLAG_DMA_ERR 0x40 460#define QLE_RESP_FLAG_RESERVED 0x80 461 462#define QLE_IOCB_CTRL_FLAG_WRITE 0x0001 463#define QLE_IOCB_CTRL_FLAG_READ 0x0002 464#define QLE_IOCB_CTRL_FLAG_EXT_SEG 0x0004 465 466#define QLE_IOCB_SEGS_PER_CMD 2 467 468#define QLE_IOCB_MARKER_SYNC_ALL 2 469 470struct qle_iocb_seg { 471 u_int32_t seg_addr_lo; 472 u_int32_t seg_addr_hi; 473 u_int32_t seg_len; 474} __packed __aligned(4); 475 476struct qle_iocb_status { 477 u_int8_t entry_type; /* QLE_IOCB_STATUS */ 478 u_int8_t entry_count; 479 u_int8_t seqno; 480 u_int8_t flags; 481 482 u_int32_t handle; 483 u_int16_t completion; 484 u_int16_t ox_id; 485 u_int32_t resid; 486 u_int16_t reserved; 487 u_int16_t state_flags; 488 u_int16_t reserved2; 489 u_int16_t scsi_status; 490 u_int32_t fcp_rsp_resid; 491 u_int32_t fcp_sense_len; 492 493 u_int32_t fcp_rsp_len; 494 u_int8_t data[28]; 495} __packed __aligned(64); 496 497/* completion */ 498#define QLE_IOCB_STATUS_COMPLETE 0x0000 499#define QLE_IOCB_STATUS_DMA_ERROR 0x0002 500#define QLE_IOCB_STATUS_RESET 0x0004 501#define QLE_IOCB_STATUS_ABORTED 0x0005 502#define QLE_IOCB_STATUS_TIMEOUT 0x0006 503#define QLE_IOCB_STATUS_DATA_OVERRUN 0x0007 504#define QLE_IOCB_STATUS_DATA_UNDERRUN 0x0015 505#define QLE_IOCB_STATUS_QUEUE_FULL 0x001C 506#define QLE_IOCB_STATUS_PORT_UNAVAIL 0x0028 507#define QLE_IOCB_STATUS_PORT_LOGGED_OUT 0x0029 508#define QLE_IOCB_STATUS_PORT_CHANGED 0x002A 509#define QLE_IOCB_STATUS_PORT_BUSY 0x002B 510 511#define QLE_SCSI_STATUS_FCP_LEN_VALID 0x0100 512#define QLE_SCSI_STATUS_SENSE_VALID 0x0200 513#define QLE_SCSI_STATUS_RESID_OVER 0x0400 514#define QLE_SCSI_STATUS_RESID_UNDER 0x0800 515 516 517struct qle_iocb_marker { 518 u_int8_t entry_type; /* QLE_IOCB_MARKER */ 519 u_int8_t entry_count; 520 u_int8_t seqno; 521 u_int8_t flags; 522 523 u_int32_t handle; 524 u_int8_t reserved; 525 u_int8_t target; 526 u_int8_t modifier; 527 u_int8_t vp_index; 528 u_int16_t marker_flags; 529 u_int16_t lun; 530 u_int8_t reserved2[48]; 531} __packed __aligned(64); 532 533struct qle_iocb_status_cont { 534 u_int8_t entry_type; /* QLE_IOCB_STATUS_CONT */ 535 u_int8_t entry_count; 536 u_int8_t seqno; 537 u_int8_t flags; 538 539 u_int8_t sense[44]; 540} __packed __aligned(64); 541 542struct qle_iocb_req6 { 543 u_int8_t entry_type; /* QLE_IOCB_CMD_TYPE_6 */ 544 u_int8_t entry_count; 545 u_int8_t seqno; 546 u_int8_t flags; 547 548 u_int32_t req_handle; 549 u_int16_t req_nport_handle; 550 u_int16_t req_timeout; 551 u_int16_t req_data_seg_count; 552 u_int16_t req_resp_seg_count; 553 554 u_int16_t req_fcp_lun[4]; 555 556 u_int16_t req_ctrl_flags; 557 u_int16_t req_fcp_cmnd_len; 558 559 u_int32_t req_fcp_cmnd_addr_lo; 560 u_int32_t req_fcp_cmnd_addr_hi; 561 562 u_int32_t req_resp_seg_addr_lo; 563 u_int32_t req_resp_seg_addr_hi; 564 565 u_int32_t req_data_len; 566 567 u_int32_t req_target_id; 568 struct qle_iocb_seg req_data_seg; 569} __packed __aligned(64); 570 571struct qle_fcp_cmnd { 572 u_int16_t fcp_lun[4]; 573 u_int8_t fcp_crn; 574 u_int8_t fcp_task_attr; 575 u_int8_t fcp_task_mgmt; 576 u_int8_t fcp_add_cdb_len; 577 578 u_int8_t fcp_cdb[52]; 579 /* 64 bytes total */ 580} __packed __aligned(64); 581 582struct qle_iocb_ct_passthrough { 583 u_int8_t entry_type; /* QLE_IOCB_CT_PASSTHROUGH */ 584 u_int8_t entry_count; 585 u_int8_t seqno; 586 u_int8_t flags; 587 588 u_int32_t req_handle; 589 u_int16_t req_status; 590 u_int16_t req_nport_handle; 591 u_int16_t req_dsd_count; 592 u_int8_t req_vp_index; 593 u_int8_t req_reserved; 594 u_int16_t req_timeout; 595 u_int16_t req_reserved2; 596 u_int16_t req_resp_dsd_count; 597 u_int16_t req_reserved3[5]; 598 u_int32_t req_resp_byte_count; 599 u_int32_t req_cmd_byte_count; 600 struct qle_iocb_seg req_cmd_seg; 601 struct qle_iocb_seg req_resp_seg; 602} __packed __aligned(64); 603 604#define QLE_PLOGX_LOGIN 0x0000 605#define QLE_PLOGX_LOGIN_COND 0x0010 606 607#define QLE_PLOGX_LOGOUT 0x0008 608#define QLE_PLOGX_LOGOUT_IMPLICIT 0x0010 609#define QLE_PLOGX_LOGOUT_ALL 0x0020 610#define QLE_PLOGX_LOGOUT_EXPLICIT 0x0040 611#define QLE_PLOGX_LOGOUT_FREE_HANDLE 0x0080 612 613#define QLE_PLOGX_PORT_UNAVAILABLE 0x28 614#define QLE_PLOGX_PORT_LOGGED_OUT 0x29 615#define QLE_PLOGX_ERROR 0x31 616 617#define QLE_PLOGX_ERROR_PORT_ID_USED 0x1A 618#define QLE_PLOGX_ERROR_HANDLE_USED 0x1B 619#define QLE_PLOGX_ERROR_NO_HANDLE 0x1C 620 621struct qle_iocb_plogx { 622 u_int8_t entry_type; /* QLE_IOCB_PLOGX */ 623 u_int8_t entry_count; 624 u_int8_t seqno; 625 u_int8_t flags; 626 627 u_int32_t req_handle; 628 u_int16_t req_status; 629 u_int16_t req_nport_handle; 630 u_int16_t req_flags; 631 u_int8_t req_vp_index; 632 u_int8_t req_reserved; 633 u_int16_t req_port_id_lo; 634 u_int8_t req_port_id_hi; 635 u_int8_t req_rspsize; 636 u_int32_t req_ioparms[11]; 637} __packed __aligned(64); 638