qlereg.h revision 1.4
1/* $OpenBSD: qlereg.h,v 1.4 2014/03/25 07:15:52 dlg Exp $ */ 2 3/* 4 * Copyright (c) 2013, 2014 Jonathan Matthew <jmatthew@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19/* firmware loading */ 20#define QLE_2400_CODE_ORG 0x00100000 21 22/* interrupt types */ 23#define QLE_INT_TYPE_MBOX 1 24#define QLE_INT_TYPE_ASYNC 2 25#define QLE_INT_TYPE_IO 3 26#define QLE_INT_TYPE_OTHER 4 27 28/* 24xx interrupt status codes */ 29#define QLE_24XX_INT_ROM_MBOX 0x01 30#define QLE_24XX_INT_ROM_MBOX_FAIL 0x02 31#define QLE_24XX_INT_MBOX 0x10 32#define QLE_24XX_INT_MBOX_FAIL 0x11 33#define QLE_24XX_INT_ASYNC 0x12 34#define QLE_24XX_INT_RSPQ 0x13 35 36/* ISP registers */ 37#define QLE_FLASH_NVRAM_ADDR 0x000 38#define QLE_FLASH_NVRAM_DATA 0x004 39#define QLE_CTRL_STATUS 0x008 40#define QLE_INT_CTRL 0x00C 41#define QLE_INT_STATUS 0x010 42#define QLE_REQ_IN 0x01C 43#define QLE_REQ_OUT 0x020 44#define QLE_RESP_IN 0x024 45#define QLE_RESP_OUT 0x028 46#define QLE_PRI_REQ_IN 0x02C 47#define QLE_PRI_REQ_OUT 0x030 48#define QLE_RISC_STATUS 0x044 49#define QLE_HOST_CMD_CTRL 0x048 50#define QLE_GPIO_DATA 0x04C 51#define QLE_GPIO_ENABLE 0x050 52#define QLE_HOST_SEMAPHORE 0x058 53 54/* mailbox base moves around between generations */ 55#define QLE_MBOX_BASE_24XX 0x080 56 57/* QLE_CTRL_STATUS */ 58#define QLE_CTRL_DMA_ACTIVE 0x00020000 59#define QLE_CTRL_DMA_SHUTDOWN 0x00010000 60#define QLE_CTRL_RESET 0x00000001 61 62/* QLE_INT_STATUS */ 63#define QLE_RISC_INT_REQ 0x00000008 64 65/* QLE_INT_CTRL */ 66#define QLE_INT_CTRL_ENABLE 0x00000008 67 68/* QLE_RISC_STATUS */ 69#define QLE_INT_INFO_SHIFT 16 70#define QLE_RISC_HOST_INT_REQ 0x00008000 71#define QLE_RISC_PAUSED 0x00000100 72#define QLE_INT_STATUS_MASK 0x000000FF 73 74/* QLE_HOST_CMD_CTRL write */ 75#define QLE_HOST_CMD_SHIFT 28 76#define QLE_HOST_CMD_NOP 0x0 77#define QLE_HOST_CMD_RESET 0x1 78#define QLE_HOST_CMD_CLEAR_RESET 0x2 79#define QLE_HOST_CMD_PAUSE 0x3 80#define QLE_HOST_CMD_RELEASE 0x4 81#define QLE_HOST_CMD_SET_HOST_INT 0x5 82#define QLE_HOST_CMD_CLR_HOST_INT 0x6 83#define QLE_HOST_CMD_CLR_RISC_INT 0xA 84 85/* QLE_HOST_CMD_CTRL read */ 86#define QLE_HOST_STATUS_ERROR_SHIFT 12 87#define QLE_HOST_STATUS_HOST_INT 0x00000040 88#define QLE_HOST_STATUS_RISC_RESET 0x00000020 89 90/* QLE_HOST_SEMAPHORE */ 91#define QLE_HOST_SEMAPHORE_LOCK 0x00000001 92 93 94/* QLE_MBOX_BASE (reg 0) read */ 95#define QLE_MBOX_HAS_STATUS 0x4000 96#define QLE_MBOX_COMPLETE 0x4000 97#define QLE_MBOX_INVALID 0x4001 98#define QLE_MBOX_INTF_ERROR 0x4002 99#define QLE_MBOX_TEST_FAILED 0x4003 100#define QLE_MBOX_CMD_ERROR 0x4005 101#define QLE_MBOX_CMD_PARAM 0x4006 102#define QLE_MBOX_LINK_DOWN 0x400B 103#define QLE_MBOX_DIAG_ERROR 0x400C 104#define QLE_MBOX_CSUM_ERROR 0x4010 105#define QLE_ASYNC_SYSTEM_ERROR 0x8002 106#define QLE_ASYNC_REQ_XFER_ERROR 0x8003 107#define QLE_ASYNC_RSP_XFER_ERROR 0x8004 108#define QLE_ASYNC_LIP_OCCURRED 0x8010 109#define QLE_ASYNC_LOOP_UP 0x8011 110#define QLE_ASYNC_LOOP_DOWN 0x8012 111#define QLE_ASYNC_LIP_RESET 0x8013 112#define QLE_ASYNC_PORT_DB_CHANGE 0x8014 113#define QLE_ASYNC_CHANGE_NOTIFY 0x8015 114#define QLE_ASYNC_LIP_F8 0x8016 115#define QLE_ASYNC_LOOP_INIT_ERROR 0x8017 116#define QLE_ASYNC_POINT_TO_POINT 0x8030 117#define QLE_ASYNC_ZIO_RESP_UPDATE 0x8040 118#define QLE_ASYNC_RECV_ERROR 0x8048 119#define QLE_ASYNC_LOGIN_RJT_SENT 0x8049 120 121 122/* QLE_MBOX_BASE (reg 0) write */ 123#define QLE_MBOX_NOP 0x0000 124#define QLE_MBOX_EXEC_FIRMWARE 0x0002 125#define QLE_MBOX_REGISTER_TEST 0x0006 126#define QLE_MBOX_VERIFY_CSUM 0x0007 127#define QLE_MBOX_ABOUT_FIRMWARE 0x0008 128#define QLE_MBOX_LOAD_RISC_RAM 0x000B 129#define QLE_MBOX_INIT_RISC_RAM 0x000E 130#define QLE_MBOX_READ_RISC_RAM 0x000F 131#define QLE_MBOX_GET_IO_STATUS 0x0012 132#define QLE_MBOX_STOP_FIRMWARE 0x0014 133#define QLE_MBOX_GET_ID 0x0020 134#define QLE_MBOX_SET_FIRMWARE_OPTIONS 0x0038 135#define QLE_MBOX_PLOGO 0x0056 136#define QLE_MBOX_DATA_RATE 0x005D 137#define QLE_MBOX_INIT_FIRMWARE 0x0060 138#define QLE_MBOX_GET_INIT_CB 0x0061 139#define QLE_MBOX_GET_FC_AL_POS 0x0063 140#define QLE_MBOX_GET_PORT_DB 0x0064 141#define QLE_MBOX_GET_FIRMWARE_STATE 0x0069 142#define QLE_MBOX_GET_PORT_NAME 0x006A 143#define QLE_MBOX_GET_LINK_STATUS 0x006B 144#define QLE_MBOX_SEND_CHANGE_REQ 0x0070 145#define QLE_MBOX_LINK_INIT 0x0072 146#define QLE_MBOX_GET_PORT_NAME_LIST 0x0075 147 148/* mailbox operation register bitfields */ 149#define QLE_MBOX_ABOUT_FIRMWARE_IN 0x00000001 150#define QLE_MBOX_ABOUT_FIRMWARE_OUT 0x0000004f 151#define QLE_MBOX_INIT_FIRMWARE_IN 0x000000fd 152#define QLE_MBOX_SET_FIRMWARE_OPTIONS_IN 0x0000000f 153#define QLE_MBOX_GET_LOOP_ID_OUT 0x000000cf 154 155#define QLE_MBOX_COUNT 32 156 157/* nvram layout */ 158struct qle_nvram { 159 u_int8_t id[4]; 160 u_int16_t nvram_version; 161 u_int16_t reserved_0; 162 163 u_int16_t version; 164 u_int16_t reserved_1; 165 u_int16_t frame_payload_size; 166 u_int16_t execution_throttle; 167 u_int16_t exchg_count; 168 u_int16_t hard_address; 169 170 u_int64_t port_name; 171 u_int64_t node_name; 172 173 u_int16_t login_retry; 174 u_int16_t link_down_on_nos; 175 u_int16_t int_delay_timer; 176 u_int16_t login_timeout; 177 178 u_int32_t fwoptions1; 179 u_int32_t fwoptions2; 180 u_int32_t fwoptions3; 181 182 u_int16_t serial_options[4]; 183 184 u_int16_t reserved_2[96]; 185 186 u_int32_t host_p; 187 188 u_int64_t alt_port_name; 189 u_int64_t alt_node_name; 190 191 u_int64_t boot_port_name; 192 u_int16_t boot_lun; 193 u_int16_t reserved_3; 194 195 u_int64_t alt1_boot_port_name; 196 u_int16_t alt1_boot_lun; 197 u_int16_t reserved_4; 198 199 u_int64_t alt2_boot_port_name; 200 u_int16_t alt2_boot_lun; 201 u_int16_t reserved_5; 202 203 u_int64_t alt3_boot_port_name; 204 u_int16_t alt3_boot_lun; 205 u_int16_t reserved_6; 206 207 u_int32_t efi_param; 208 209 u_int8_t reset_delay; 210 u_int8_t reserved_7; 211 u_int16_t reserved_8; 212 213 u_int16_t boot_id_num; 214 u_int16_t reserved_9; 215 216 u_int16_t max_luns_per_target; 217 u_int16_t reserved_10; 218 219 u_int16_t port_down_retry_count; 220 u_int16_t link_down_timeout; 221 222 u_int16_t fcode_param; 223 u_int16_t reserved_11[3]; 224 225 u_int8_t prev_drv_ver_major; 226 u_int8_t prev_drv_ver_submajor; 227 u_int8_t prev_drv_ver_minor; 228 u_int8_t prev_drv_ver_subminor; 229 230 u_int16_t prev_bios_ver_major; 231 u_int16_t prev_bios_ver_minor; 232 233 u_int16_t prev_efi_ver_major; 234 u_int16_t prev_efi_ver_minor; 235 236 u_int16_t prev_fw_ver_major; 237 u_int8_t prev_fw_ver_minor; 238 u_int8_t prev_fw_ver_subminor; 239 240 u_int16_t reserved_12[56]; 241 242 u_int8_t model_namep[16]; 243 244 u_int16_t reserved_13[2]; 245 246 u_int16_t pcie_table_sig; 247 u_int16_t pcie_table_offset; 248 u_int16_t subsystem_vendor_id; 249 u_int16_t subsystem_device_id; 250 251 u_int32_t checksum; 252} __packed; 253 254/* init firmware control block */ 255#define QLE_ICB_VERSION 1 256 257#define QLE_ICB_FW1_HARD_ADDR 0x0001 258#define QLE_ICB_FW1_FAIRNESS 0x0002 259#define QLE_ICB_FW1_FULL_DUPLEX 0x0004 260#define QLE_ICB_FW1_TARGET_MODE 0x0010 261#define QLE_ICB_FW1_DISABLE_INITIATOR 0x0020 262#define QLE_ICB_FW1_DISABLE_INIT_LIP 0x0200 263#define QLE_ICB_FW1_DESC_LOOP_ID 0x0400 264#define QLE_ICB_FW1_PREV_LOOP_ID 0x0800 265#define QLE_ICB_FW1_LOGIN_AFTER_LIP 0x2000 266#define QLE_ICB_FW1_NAME_OPTION 0x4000 267 268#define QLE_ICB_FW2_LOOP_ONLY 0x0000 269#define QLE_ICB_FW2_PTP_ONLY 0x0010 270#define QLE_ICB_FW2_LOOP_PTP 0x0020 271#define QLE_ICB_FW2_ZIO_DISABLED 0x0000 272#define QLE_ICB_FW2_ZIO5_ENABLED 0x0005 273#define QLE_ICB_FW2_ZIO6_ENABLED 0x0006 274#define QLE_ICB_FW2_HARD_ADDR_ONLY 0x0080 275 276#define QLE_ICB_FW3_SOFT_ID_ONLY 0x0002 277#define QLE_ICB_FW3_FCP_RSP_12_0 0x0010 278#define QLE_ICB_FW3_FCP_RSP_24_0 0x0020 279#define QLE_ICB_FW3_FCP_RSP_32_BYTES 0x0030 280#define QLE_ICB_FW3_ENABLE_OOO 0x0040 281#define QLE_ICB_FW3_NO_AUTO_PLOGI 0x0080 282#define QLE_ICB_FW3_ENABLE_OOO_RDY 0x0200 283#define QLE_ICB_FW3_1GBPS 0x0000 284#define QLE_ICB_FW3_2GBPS 0x2000 285#define QLE_ICB_FW3_AUTONEG 0x4000 286#define QLE_ICB_FW3_4GBPS 0x6000 287#define QLE_ICB_FW3_50_OHMS 0x8000 288 289 290struct qle_init_cb { 291 u_int16_t icb_version; 292 u_int16_t icb_reserved; 293 u_int16_t icb_max_frame_len; 294 u_int16_t icb_exec_throttle; 295 u_int16_t icb_exchange_count; 296 u_int16_t icb_hardaddr; 297 u_int64_t icb_portname; 298 u_int64_t icb_nodename; 299 u_int16_t icb_resp_in; 300 u_int16_t icb_req_out; 301 u_int16_t icb_login_retry; 302 u_int16_t icb_pri_req_out; 303 u_int16_t icb_resp_queue_len; 304 u_int16_t icb_req_queue_len; 305 u_int16_t icb_link_down_nos; 306 u_int16_t icb_pri_req_queue_len; 307 u_int64_t icb_req_queue_addr; 308 u_int64_t icb_resp_queue_addr; 309 u_int64_t icb_pri_req_queue_addr; 310 u_int8_t icb_reserved2[8]; 311 u_int16_t icb_atio_queue_in; 312 u_int16_t icb_atio_queue_len; 313 u_int64_t icb_atio_queue_addr; 314 u_int16_t icb_int_delay; 315 u_int16_t icb_login_timeout; 316 u_int32_t icb_fwoptions1; 317 u_int32_t icb_fwoptions2; 318 u_int32_t icb_fwoptions3; 319 u_int8_t icb_reserved3[24]; 320} __packed; 321 322#define QLE_FW_OPTION1_ASYNC_LIP_F8 0x0001 323#define QLE_FW_OPTION1_ASYNC_LIP_RESET 0x0002 324#define QLE_FW_OPTION1_SYNC_LOSS_LIP 0x0010 325#define QLE_FW_OPTION1_ASYNC_LIP_ERROR 0x0080 326#define QLE_FW_OPTION1_ASYNC_LOGIN_RJT 0x0800 327 328#define QLE_FW_OPTION3_EMERG_IOCB 0x0001 329#define QLE_FW_OPTION3_ASYNC_RND_ERROR 0x0002 330 331/* topology types returned from QLE_MBOX_GET_LOOP_ID */ 332#define QLE_TOPO_NL_PORT 0 333#define QLE_TOPO_FL_PORT 1 334#define QLE_TOPO_N_PORT 2 335#define QLE_TOPO_F_PORT 3 336#define QLE_TOPO_N_PORT_NO_TARGET 4 337 338 339struct qle_get_port_db { 340 u_int16_t flags; 341 u_int8_t current_login_state; 342 u_int8_t stable_login_state; 343 u_int8_t adisc_addr[3]; 344 u_int8_t reserved; 345 u_int8_t port_id[3]; 346 u_int8_t sequence_id; 347 u_int16_t retry_timer; 348 u_int16_t nport_handle; 349 u_int16_t recv_data_size; 350 u_int16_t reserved2; 351 u_int16_t prli_svc_word0; 352 u_int16_t prli_svc_word3; 353 u_int64_t port_name; 354 u_int64_t node_name; 355 u_int8_t reserved3[24]; 356} __packed; 357 358#define QLE_SVC3_TARGET_ROLE 0x0010 359 360/* fabric name server commands */ 361#define QLE_SNS_GA_NXT 0x0100 362#define QLE_SNS_GID_FT 0x0171 363#define QLE_SNS_RFT_ID 0x0217 364 365#define QLE_FC4_SCSI 8 366 367#define QLE_LS_REJECT 0x8001 368#define QLE_LS_ACCEPT 0x8002 369 370struct qle_ct_cmd_hdr { 371 u_int8_t ct_revision; 372 u_int8_t ct_id[3]; 373 u_int8_t ct_gs_type; 374 u_int8_t ct_gs_subtype; 375 u_int8_t ct_gs_options; 376 u_int8_t ct_gs_reserved; 377} __packed; 378 379struct qle_ct_ga_nxt_req { 380 struct qle_ct_cmd_hdr header; 381 u_int16_t subcmd; 382 u_int16_t max_word; 383 u_int32_t reserved3; 384 u_int32_t port_id; 385} __packed; 386 387struct qle_ct_ga_nxt_resp { 388 struct qle_ct_cmd_hdr header; 389 u_int16_t response; 390 u_int16_t residual; 391 u_int8_t fragment_id; 392 u_int8_t reason_code; 393 u_int8_t explanation_code; 394 u_int8_t vendor_unique; 395 396 u_int32_t port_type_id; 397 u_int64_t port_name; 398 u_int8_t sym_port_name_len; 399 u_int8_t sym_port_name[255]; 400 u_int64_t node_name; 401 u_int8_t sym_node_name_len; 402 u_int8_t sym_node_name[255]; 403 u_int64_t initial_assoc; 404 u_int8_t node_ip_addr[16]; 405 u_int32_t cos; 406 u_int32_t fc4_types[8]; 407 u_int8_t ip_addr[16]; 408 u_int64_t fabric_port_name; 409 u_int32_t hard_address; 410} __packed; 411 412struct qle_ct_rft_id_req { 413 struct qle_ct_cmd_hdr header; 414 u_int16_t subcmd; 415 u_int16_t max_word; 416 u_int32_t reserved3; 417 u_int32_t port_id; 418 u_int32_t fc4_types[8]; 419} __packed; 420 421struct qle_ct_rft_id_resp { 422 struct qle_ct_cmd_hdr header; 423 u_int16_t response; 424 u_int16_t residual; 425 u_int8_t fragment_id; 426 u_int8_t reason_code; 427 u_int8_t explanation_code; 428 u_int8_t vendor_unique; 429} __packed; 430 431/* available handle ranges */ 432#define QLE_MIN_HANDLE 0x81 433#define QLE_MAX_HANDLE 0x7EF 434 435#define QLE_F_PORT_HANDLE 0x7FE 436#define QLE_FABRIC_CTRL_HANDLE 0x7FD 437#define QLE_SNS_HANDLE 0x7FC 438#define QLE_IP_BCAST_HANDLE 0xFFF 439 440/* IOCB types */ 441#define QLE_IOCB_STATUS 0x03 442#define QLE_IOCB_MARKER 0x04 443#define QLE_IOCB_STATUS_CONT 0x10 444#define QLE_IOCB_CMD_TYPE_7 0x18 445#define QLE_IOCB_CT_PASSTHROUGH 0x29 446#define QLE_IOCB_MAILBOX 0x39 447#define QLE_IOCB_CMD_TYPE_6 0x48 448#define QLE_IOCB_PLOGX 0x52 449 450#define QLE_REQ_FLAG_CONT 0x01 451#define QLE_REQ_FLAG_FULL 0x02 452#define QLE_REQ_FLAG_BAD_HDR 0x04 453#define QLE_REQ_FLAG_BAD_PKT 0x08 454 455#define QLE_RESP_FLAG_INVALID_COUNT 0x10 456#define QLE_RESP_FLAG_INVALID_ORDER 0x20 457#define QLE_RESP_FLAG_DMA_ERR 0x40 458#define QLE_RESP_FLAG_RESERVED 0x80 459 460#define QLE_IOCB_CTRL_FLAG_WRITE 0x0001 461#define QLE_IOCB_CTRL_FLAG_READ 0x0002 462#define QLE_IOCB_CTRL_FLAG_EXT_SEG 0x0004 463 464#define QLE_IOCB_SEGS_PER_CMD 2 465 466#define QLE_IOCB_MARKER_SYNC_ALL 2 467 468struct qle_iocb_seg { 469 u_int32_t seg_addr_lo; 470 u_int32_t seg_addr_hi; 471 u_int32_t seg_len; 472} __packed __aligned(4); 473 474struct qle_iocb_status { 475 u_int8_t entry_type; /* QLE_IOCB_STATUS */ 476 u_int8_t entry_count; 477 u_int8_t seqno; 478 u_int8_t flags; 479 480 u_int32_t handle; 481 u_int16_t completion; 482 u_int16_t ox_id; 483 u_int32_t resid; 484 u_int16_t reserved; 485 u_int16_t state_flags; 486 u_int16_t reserved2; 487 u_int16_t scsi_status; 488 u_int32_t fcp_rsp_resid; 489 u_int32_t fcp_sense_len; 490 491 u_int32_t fcp_rsp_len; 492 u_int8_t data[28]; 493} __packed; 494 495/* completion */ 496#define QLE_IOCB_STATUS_COMPLETE 0x0000 497#define QLE_IOCB_STATUS_DMA_ERROR 0x0002 498#define QLE_IOCB_STATUS_RESET 0x0004 499#define QLE_IOCB_STATUS_ABORTED 0x0005 500#define QLE_IOCB_STATUS_TIMEOUT 0x0006 501#define QLE_IOCB_STATUS_DATA_OVERRUN 0x0007 502#define QLE_IOCB_STATUS_DATA_UNDERRUN 0x0015 503#define QLE_IOCB_STATUS_QUEUE_FULL 0x001C 504#define QLE_IOCB_STATUS_PORT_UNAVAIL 0x0028 505#define QLE_IOCB_STATUS_PORT_LOGGED_OUT 0x0029 506#define QLE_IOCB_STATUS_PORT_CHANGED 0x002A 507#define QLE_IOCB_STATUS_PORT_BUSY 0x002B 508 509#define QLE_SCSI_STATUS_FCP_LEN_VALID 0x0100 510#define QLE_SCSI_STATUS_SENSE_VALID 0x0200 511#define QLE_SCSI_STATUS_RESID_OVER 0x0400 512#define QLE_SCSI_STATUS_RESID_UNDER 0x0800 513 514 515struct qle_iocb_marker { 516 u_int8_t entry_type; /* QLE_IOCB_MARKER */ 517 u_int8_t entry_count; 518 u_int8_t seqno; 519 u_int8_t flags; 520 521 u_int32_t handle; 522 u_int8_t reserved; 523 u_int8_t target; 524 u_int8_t modifier; 525 u_int8_t vp_index; 526 u_int16_t marker_flags; 527 u_int16_t lun; 528 u_int8_t reserved2[48]; 529} __packed; 530 531struct qle_iocb_status_cont { 532 u_int8_t entry_type; /* QLE_IOCB_STATUS_CONT */ 533 u_int8_t entry_count; 534 u_int8_t seqno; 535 u_int8_t flags; 536 537 u_int8_t sense[44]; 538} __packed; 539 540struct qle_iocb_req6 { 541 u_int8_t entry_type; /* QLE_IOCB_CMD_TYPE_6 */ 542 u_int8_t entry_count; 543 u_int8_t seqno; 544 u_int8_t flags; 545 546 u_int32_t req_handle; 547 u_int16_t req_nport_handle; 548 u_int16_t req_timeout; 549 u_int16_t req_data_seg_count; 550 u_int16_t req_resp_seg_count; 551 552 u_int16_t req_fcp_lun[4]; 553 554 u_int16_t req_ctrl_flags; 555 u_int16_t req_fcp_cmnd_len; 556 557 u_int32_t req_fcp_cmnd_addr_lo; 558 u_int32_t req_fcp_cmnd_addr_hi; 559 560 u_int32_t req_resp_seg_addr_lo; 561 u_int32_t req_resp_seg_addr_hi; 562 563 u_int32_t req_data_len; 564 565 u_int32_t req_target_id; 566 struct qle_iocb_seg req_data_seg; 567} __packed __aligned(4); 568 569struct qle_fcp_cmnd { 570 u_int16_t fcp_lun[4]; 571 u_int8_t fcp_crn; 572 u_int8_t fcp_task_attr; 573 u_int8_t fcp_task_mgmt; 574 u_int8_t fcp_add_cdb_len; 575 576 u_int8_t fcp_cdb[52]; 577 /* 64 bytes total */ 578} __packed; 579 580struct qle_iocb_ct_passthrough { 581 u_int8_t entry_type; /* QLE_IOCB_CT_PASSTHROUGH */ 582 u_int8_t entry_count; 583 u_int8_t seqno; 584 u_int8_t flags; 585 586 u_int32_t req_handle; 587 u_int16_t req_status; 588 u_int16_t req_nport_handle; 589 u_int16_t req_dsd_count; 590 u_int8_t req_vp_index; 591 u_int8_t req_reserved; 592 u_int16_t req_timeout; 593 u_int16_t req_reserved2; 594 u_int16_t req_resp_dsd_count; 595 u_int16_t req_reserved3[5]; 596 u_int32_t req_resp_byte_count; 597 u_int32_t req_cmd_byte_count; 598 struct qle_iocb_seg req_cmd_seg; 599 struct qle_iocb_seg req_resp_seg; 600} __packed; 601 602struct qle_iocb_plogx { 603 u_int8_t entry_type; /* QLE_IOCB_PLOGX */ 604 u_int8_t entry_count; 605 u_int8_t seqno; 606 u_int8_t flags; 607 608 u_int32_t req_handle; 609 u_int16_t req_status; 610 u_int16_t req_nport_handle; 611 u_int16_t req_flags; 612 u_int8_t req_vp_index; 613 u_int8_t req_reserved; 614 u_int16_t req_port_id_lo; 615 u_int8_t req_port_id_hi; 616 u_int8_t req_rspsize; 617 u_int16_t req_ioparms[22]; 618} __packed; 619