pciide_pdc202xx_reg.h revision 1.9
1218799Snwhitehorn/* $OpenBSD: pciide_pdc202xx_reg.h,v 1.9 2003/07/23 22:07:15 grange Exp $ */ 2218799Snwhitehorn/* $NetBSD: pciide_pdc202xx_reg.h,v 1.5 2001/07/05 08:38:27 toshii Exp $ */ 3218799Snwhitehorn 4218799Snwhitehorn/* 5218799Snwhitehorn * Copyright (c) 1999 Manuel Bouyer. 6218799Snwhitehorn * 7218799Snwhitehorn * Redistribution and use in source and binary forms, with or without 8218799Snwhitehorn * modification, are permitted provided that the following conditions 9218799Snwhitehorn * are met: 10218799Snwhitehorn * 1. Redistributions of source code must retain the above copyright 11218799Snwhitehorn * notice, this list of conditions and the following disclaimer. 12218799Snwhitehorn * 2. Redistributions in binary form must reproduce the above copyright 13218799Snwhitehorn * notice, this list of conditions and the following disclaimer in the 14218799Snwhitehorn * documentation and/or other materials provided with the distribution. 15218799Snwhitehorn * 3. All advertising materials mentioning features or use of this software 16218799Snwhitehorn * must display the following acknowledgement: 17218799Snwhitehorn * This product includes software developed by Manuel Bouyer. 18218799Snwhitehorn * 4. Neither the name of the University nor the names of its contributors 19218799Snwhitehorn * may be used to endorse or promote products derived from this software 20218799Snwhitehorn * without specific prior written permission. 21218799Snwhitehorn * 22218799Snwhitehorn * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23218799Snwhitehorn * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24218799Snwhitehorn * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25218799Snwhitehorn * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26218799Snwhitehorn * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27218799Snwhitehorn * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28218799Snwhitehorn * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29218799Snwhitehorn * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30218799Snwhitehorn * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31218799Snwhitehorn * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32220088Snwhitehorn * 33220088Snwhitehorn */ 34218799Snwhitehorn 35218799Snwhitehorn/* 36218799Snwhitehorn * Registers definitions for PROMISE PDC20246/PDC20262 PCI IDE controller. 37218799Snwhitehorn * Unfortunably the HW docs are not publically available. I've been able 38225637Snwhitehorn * to get a partial one for the PDC20246, and a better one for the PDC20262 39218799Snwhitehorn * from Promise. 40218799Snwhitehorn */ 41218799Snwhitehorn 42218799Snwhitehorn#define PDC2xx_STATE 0x50 43218799Snwhitehorn#define PDC2xx_STATE_IDERAID 0x0001 44218799Snwhitehorn#define PDC2xx_STATE_NATIVE 0x0080 45218799Snwhitehorn/* controller initial state values(PDC20246 only) */ 46218799Snwhitehorn#define PDC246_STATE_SHIPID 0x8000 47218799Snwhitehorn#define PDC246_STATE_IOCHRDY 0x0400 48218799Snwhitehorn#define PDC246_STATE_LBA(channel) (0x0100 << (channel)) 49218799Snwhitehorn#define PDC246_STATE_ISAIRQ 0x0008 50218799Snwhitehorn#define PDC246_STATE_EN(channel) (0x0002 << (channel)) 51218799Snwhitehorn/* controller initial state values(PDC20262 only) */ 52218799Snwhitehorn#define PDC262_STATE_EN(chan) (0x1000 << (chan)) 53218799Snwhitehorn#define PDC262_STATE_80P(chan) (0x0400 << (chan)) 54219615Snwhitehorn 55219615Snwhitehorn/* per-drive timings */ 56219615Snwhitehorn#define PDC2xx_TIM(channel, drive) (0x60 + 4 * (drive) + 8 * (channel)) 57218947Snwhitehorn#define PDC2xx_TIM_SET_PA(r, x) (((r) & 0xfffffff0) | ((x) & 0xf)) 58219615Snwhitehorn#define PDC2xx_TIM_SET_PB(r, x) (((r) & 0xffffe0ff) | (((x) & 0x1f) << 8)) 59219615Snwhitehorn#define PDC2xx_TIM_SET_MB(r, x) (((r) & 0xffff1fff) | (((x) & 0x7) << 13)) 60219615Snwhitehorn#define PDC2xx_TIM_SET_MC(r, x) (((r) & 0xfff0ffff) | (((x) & 0xf) << 16)) 61219615Snwhitehorn#define PDC2xx_TIM_PRE 0x00000010 62219615Snwhitehorn#define PDC2xx_TIM_IORDY 0x00000020 63219615Snwhitehorn#define PDC2xx_TIM_ERRDY 0x00000040 64219615Snwhitehorn#define PDC2xx_TIM_SYNC 0x00000080 65219615Snwhitehorn#define PDC2xx_TIM_DMAW 0x00100000 66219615Snwhitehorn#define PDC2xx_TIM_DMAR 0x00200000 67219615Snwhitehorn#define PDC2xx_TIM_IORDYp 0x00400000 68219615Snwhitehorn#define PDC2xx_TIM_DMARQp 0x00800000 69218947Snwhitehorn 70218799Snwhitehorn/* The following are extensions of the DMA registers */ 71218799Snwhitehorn 72218799Snwhitehorn/* Ultra-DMA mode 3/4 control (PDC20262 only, 1 byte) */ 73218799Snwhitehorn#define PDC262_U66 0x11 74218799Snwhitehorn#define PDC262_U66_EN(chan) (0x2 << ((chan) *2)) 75218799Snwhitehorn/* primary mode (1 byte) */ 76220080Snwhitehorn#define PDC2xx_PM 0x1a 77218799Snwhitehorn/* secondary mode (1 byte) */ 78220080Snwhitehorn#define PDC2xx_SM 0x1b 79218799Snwhitehorn/* System control register (4 bytes) */ 80218799Snwhitehorn#define PDC2xx_SCR 0x1c 81218799Snwhitehorn#define PDC2xx_SCR_SET_GEN(r,x) (((r) & 0xffffff00) | ((x) & 0xff)) 82218799Snwhitehorn#define PDC2xx_SCR_EMPTY(channel) (0x00000100 << (4 * channel)) 83218799Snwhitehorn#define PDC2xx_SCR_FULL(channel) (0x00000200 << (4 * channel)) 84220088Snwhitehorn#define PDC2xx_SCR_INT(channel) (0x00000400 << (4 * channel)) 85220080Snwhitehorn#define PDC2xx_SCR_ERR(channel) (0x00000800 << (4 * channel)) 86220834Snwhitehorn#define PDC2xx_SCR_SET_I2C(r,x) (((r) & 0xfff0ffff) | (((x) & 0xf) << 16)) 87220080Snwhitehorn#define PDC2xx_SCR_SET_POLL(r,x) (((r) & 0xff0fffff) | (((x) & 0xf) << 20)) 88220080Snwhitehorn#define PDC2xx_SCR_DMA 0x01000000 89220080Snwhitehorn#define PDC2xx_SCR_IORDY 0x02000000 90220080Snwhitehorn#define PDC2xx_SCR_G2FD 0x04000000 91220080Snwhitehorn#define PDC2xx_SCR_FLOAT 0x08000000 92220080Snwhitehorn#define PDC2xx_SCR_RSET 0x10000000 93218799Snwhitehorn#define PDC2xx_SCR_TST 0x20000000 94218799Snwhitehorn/* Values for "General Purpose Register" (PDC20262 only) */ 95218799Snwhitehorn#define PDC262_SCR_GEN_LAT 0x20 96218799Snwhitehorn 97218799Snwhitehorn/* ATAPI port ((PDC20262 only) (4 bytes) */ 98218799Snwhitehorn#define PDC262_ATAPI(chan) (0x20 + (4 * (chan))) 99218799Snwhitehorn#define PDC262_ATAPI_WC_MASK 0x00000fff 100218799Snwhitehorn#define PDC262_ATAPI_DMA_READ 0x00001000 101218799Snwhitehorn#define PDC262_ATAPI_DMA_WRITE 0x00002000 102218799Snwhitehorn#define PDC262_ATAPI_UDMA 0x00004000 103218799Snwhitehorn#define PDC262_ATAPI_LBA48_READ 0x05000000 104218799Snwhitehorn#define PDC262_ATAPI_LBA48_WRITE 0x06000000 105218799Snwhitehorn 106218799Snwhitehorn/* 107218799Snwhitehorn * The timings provided here cmoes from the PDC20262 docs. I hope they are 108222425Snwhitehorn * rigth for the PDC20246 too ... 109218799Snwhitehorn */ 110218799Snwhitehorn 111218799Snwhitehornstatic int8_t pdc2xx_pa[] = {0x9, 0x5, 0x3, 0x2, 0x1}; 112218799Snwhitehornstatic int8_t pdc2xx_pb[] = {0x13, 0xc, 0x8, 0x6, 0x4}; 113218799Snwhitehornstatic int8_t pdc2xx_dma_mb[] = {0x3, 0x3, 0x3}; 114218799Snwhitehornstatic int8_t pdc2xx_dma_mc[] = {0x5, 0x4, 0x3}; 115218799Snwhitehornstatic int8_t pdc2xx_udma_mb[] = {0x3, 0x2, 0x1, 0x2, 0x1, 0x1}; 116218799Snwhitehornstatic int8_t pdc2xx_udma_mc[] = {0x3, 0x2, 0x1, 0x2, 0x1, 0x1}; 117218799Snwhitehorn 118218799Snwhitehorn/* 119218799Snwhitehorn * Registers definitions for Promise PDC20268 and above chips 120218799Snwhitehorn */ 121218799Snwhitehorn#define PDC268_INDEX(chan) (0x01 + IDEDMA_SCH_OFFSET * (chan)) 122218799Snwhitehorn#define PDC268_DATA(chan) (0x03 + IDEDMA_SCH_OFFSET * (chan)) 123219528Snwhitehorn#define PDC268_CABLE 0x04 124218799Snwhitehorn#define PDC268_INTR 0x20 125218799Snwhitehorn