1/* $OpenBSD: pciide_pdc202xx_reg.h,v 1.16 2022/01/09 05:42:58 jsg Exp $ */ 2/* $NetBSD: pciide_pdc202xx_reg.h,v 1.5 2001/07/05 08:38:27 toshii Exp $ */ 3 4/* 5 * Copyright (c) 1999 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29#ifndef _DEV_PCI_PCIIDE_PDC202XX_REG_H_ 30#define _DEV_PCI_PCIIDE_PDC202XX_REG_H_ 31 32/* 33 * Registers definitions for PROMISE PDC20246/PDC20262 PCI IDE controller. 34 * Unfortunately the HW docs are not publicly available. I've been able 35 * to get a partial one for the PDC20246, and a better one for the PDC20262 36 * from Promise. 37 */ 38 39#define PDC2xx_STATE 0x50 40#define PDC2xx_STATE_IDERAID 0x0001 41#define PDC2xx_STATE_NATIVE 0x0080 42/* controller initial state values(PDC20246 only) */ 43#define PDC246_STATE_SHIPID 0x8000 44#define PDC246_STATE_IOCHRDY 0x0400 45#define PDC246_STATE_LBA(channel) (0x0100 << (channel)) 46#define PDC246_STATE_ISAIRQ 0x0008 47#define PDC246_STATE_EN(channel) (0x0002 << (channel)) 48/* controller initial state values(PDC20262 only) */ 49#define PDC262_STATE_EN(chan) (0x1000 << (chan)) 50#define PDC262_STATE_80P(chan) (0x0400 << (chan)) 51 52/* per-drive timings */ 53#define PDC2xx_TIM(channel, drive) (0x60 + 4 * (drive) + 8 * (channel)) 54#define PDC2xx_TIM_SET_PA(r, x) (((r) & 0xfffffff0) | ((x) & 0xf)) 55#define PDC2xx_TIM_SET_PB(r, x) (((r) & 0xffffe0ff) | (((x) & 0x1f) << 8)) 56#define PDC2xx_TIM_SET_MB(r, x) (((r) & 0xffff1fff) | (((x) & 0x7) << 13)) 57#define PDC2xx_TIM_SET_MC(r, x) (((r) & 0xfff0ffff) | (((x) & 0xf) << 16)) 58#define PDC2xx_TIM_PRE 0x00000010 59#define PDC2xx_TIM_IORDY 0x00000020 60#define PDC2xx_TIM_ERRDY 0x00000040 61#define PDC2xx_TIM_SYNC 0x00000080 62#define PDC2xx_TIM_DMAW 0x00100000 63#define PDC2xx_TIM_DMAR 0x00200000 64#define PDC2xx_TIM_IORDYp 0x00400000 65#define PDC2xx_TIM_DMARQp 0x00800000 66 67/* The following are extensions of the DMA registers */ 68 69/* Ultra-DMA mode 3/4 control (PDC20262 only, 1 byte) */ 70#define PDC262_U66 0x11 71#define PDC262_U66_EN(chan) (0x2 << ((chan) *2)) 72/* primary mode (1 byte) */ 73#define PDC2xx_PM 0x1a 74/* secondary mode (1 byte) */ 75#define PDC2xx_SM 0x1b 76/* System control register (4 bytes) */ 77#define PDC2xx_SCR 0x1c 78#define PDC2xx_SCR_SET_GEN(r,x) (((r) & 0xffffff00) | ((x) & 0xff)) 79#define PDC2xx_SCR_EMPTY(channel) (0x00000100 << (4 * channel)) 80#define PDC2xx_SCR_FULL(channel) (0x00000200 << (4 * channel)) 81#define PDC2xx_SCR_INT(channel) (0x00000400 << (4 * channel)) 82#define PDC2xx_SCR_ERR(channel) (0x00000800 << (4 * channel)) 83#define PDC2xx_SCR_SET_I2C(r,x) (((r) & 0xfff0ffff) | (((x) & 0xf) << 16)) 84#define PDC2xx_SCR_SET_POLL(r,x) (((r) & 0xff0fffff) | (((x) & 0xf) << 20)) 85#define PDC2xx_SCR_DMA 0x01000000 86#define PDC2xx_SCR_IORDY 0x02000000 87#define PDC2xx_SCR_G2FD 0x04000000 88#define PDC2xx_SCR_FLOAT 0x08000000 89#define PDC2xx_SCR_RSET 0x10000000 90#define PDC2xx_SCR_TST 0x20000000 91/* Values for "General Purpose Register" (PDC20262 only) */ 92#define PDC262_SCR_GEN_LAT 0x20 93 94/* ATAPI port ((PDC20262 only) (4 bytes) */ 95#define PDC262_ATAPI(chan) (0x20 + (4 * (chan))) 96#define PDC262_ATAPI_WC_MASK 0x00000fff 97#define PDC262_ATAPI_DMA_READ 0x00001000 98#define PDC262_ATAPI_DMA_WRITE 0x00002000 99#define PDC262_ATAPI_UDMA 0x00004000 100#define PDC262_ATAPI_LBA48_READ 0x05000000 101#define PDC262_ATAPI_LBA48_WRITE 0x06000000 102 103/* 104 * The timings provided here cmoes from the PDC20262 docs. I hope they are 105 * right for the PDC20246 too ... 106 */ 107 108static int8_t pdc2xx_pa[] = {0x9, 0x5, 0x3, 0x2, 0x1}; 109static int8_t pdc2xx_pb[] = {0x13, 0xc, 0x8, 0x6, 0x4}; 110static int8_t pdc2xx_dma_mb[] = {0x3, 0x3, 0x3}; 111static int8_t pdc2xx_dma_mc[] = {0x5, 0x4, 0x3}; 112static int8_t pdc2xx_udma_mb[] = {0x3, 0x2, 0x1, 0x2, 0x1, 0x1}; 113static int8_t pdc2xx_udma_mc[] = {0x3, 0x2, 0x1, 0x2, 0x1, 0x1}; 114 115/* 116 * Registers definitions for Promise PDC20268 and above chips 117 */ 118#define PDC268_INDEX(chan) (0x01 + IDEDMA_SCH_OFFSET * (chan)) 119#define PDC268_DATA(chan) (0x03 + IDEDMA_SCH_OFFSET * (chan)) 120#define PDC268_CABLE 0x04 121#define PDC268_INTR 0x20 122 123/* 124 * PDC203xx register definitions. 125 */ 126#define PDC203xx_NCHANNELS 4 127#define PDC203xx_BAR_IDEREGS 0x1c 128 129/* 130 * PDC205xx register definitions. 131 */ 132#define PDC40718_NCHANNELS 4 133#define PDC20575_NCHANNELS 3 134 135#define PDC205_REGADDR(base,ch) ((base)+((ch)<<8)) 136#define PDC205_SSTATUS(ch) PDC205_REGADDR(0x400,ch) 137#define PDC205_SERROR(ch) PDC205_REGADDR(0x404,ch) 138#define PDC205_SCONTROL(ch) PDC205_REGADDR(0x408,ch) 139#define PDC205_MULTIPLIER(ch) PDC205_REGADDR(0x4e8,ch) 140 141#define SCONTROL_WRITE(ps,channel,scontrol) \ 142 bus_space_write_4((ps)->ba5_st, (ps)->ba5_sh, \ 143 PDC205_SCONTROL(channel), scontrol) 144 145#define SSTATUS_READ(sc,channel) \ 146 bus_space_read_4((ps)->ba5_st, (ps)->ba5_sh, \ 147 PDC205_SSTATUS(channel)) 148 149 150/* Private data */ 151struct pciide_pdcsata { 152 bus_space_tag_t ba5_st; 153 bus_space_handle_t ba5_sh; 154 155 struct { 156 bus_space_tag_t cmd_iot; 157 bus_space_handle_t cmd_iohs[WDC_NREG+WDC_NSHADOWREG]; 158 159 bus_space_tag_t ctl_iot; 160 bus_space_handle_t ctl_ioh; 161 162 bus_space_handle_t dma_iohs[IDEDMA_NREGS]; 163 } regs[PDC203xx_NCHANNELS]; 164}; 165 166u_int8_t pdc203xx_read_reg(struct channel_softc *, enum wdc_regs); 167void pdc203xx_write_reg(struct channel_softc *, enum wdc_regs, u_int8_t); 168 169struct channel_softc_vtbl wdc_pdc203xx_vtbl = { 170 pdc203xx_read_reg, 171 pdc203xx_write_reg, 172 wdc_default_lba48_write_reg, 173 wdc_default_read_raw_multi_2, 174 wdc_default_write_raw_multi_2, 175 wdc_default_read_raw_multi_4, 176 wdc_default_write_raw_multi_4 177}; 178 179#endif /* !_DEV_PCI_PCIIDE_PDC202XX_REG_H_ */ 180