pccbbvar.h revision 1.3 
1/*	$OpenBSD: pccbbvar.h,v 1.3 2000/07/25 00:04:59 mickey Exp $ */
2/*	$NetBSD: pccbbvar.h,v 1.13 2000/06/08 10:28:29 haya Exp $	*/
3/*
4 * Copyright (c) 1999 HAYAKAWA Koichi.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 *    must display the following acknowledgement:
16 *	This product includes software developed by HAYAKAWA Koichi.
17 * 4. The name of the author may not be used to endorse or promote products
18 *    derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/* require sys/device.h */
33/* require sys/queue.h */
34/* require sys/callout.h */
35/* require dev/ic/i82365reg.h */
36/* require dev/ic/i82365var.h */
37
38#ifndef _DEV_PCI_PCCBBVAR_H_
39#define	_DEV_PCI_PCCBBVAR_H_
40
41#include <sys/timeout.h>
42
43#define	PCIC_FLAG_SOCKETP	0x0001
44#define	PCIC_FLAG_CARDP		0x0002
45
46/* Chipset ID */
47#define	CB_UNKNOWN	0	/* NOT Cardbus-PCI bridge */
48#define	CB_TI113X	1	/* TI PCI1130/1131 */
49#define	CB_TI12XX	2	/* TI PCI1250/1220 */
50#define	CB_RX5C47X	3	/* RICOH RX5C475/476/477 */
51#define	CB_RX5C46X	4	/* RICOH RX5C465/466/467 */
52#define	CB_TOPIC95	5	/* Toshiba ToPIC95 */
53#define	CB_TOPIC95B	6	/* Toshiba ToPIC95B */
54#define	CB_TOPIC97	7	/* Toshiba ToPIC97 */
55#define	CB_CIRRUS	8	/* Cirrus Logic CL-PD683X */
56#define	CB_CHIPS_LAST	9	/* Sentinel */
57
58#if 0
59static char *cb_chipset_name[CB_CHIPS_LAST] = {
60	"unknown", "TI 113X", "TI 12XX", "RF5C47X", "RF5C46X", "ToPIC95",
61	"ToPIC95B", "ToPIC97", "CL-PD 683X",
62};
63#endif
64
65struct pccbb_softc;
66struct pccbb_intrhand_list;
67
68
69struct cbb_pcic_handle {
70	struct device *ph_parent;
71	bus_space_tag_t ph_base_t;
72	bus_space_handle_t ph_base_h;
73	u_int8_t (*ph_read) __P((struct cbb_pcic_handle *, int));
74	void (*ph_write) __P((struct cbb_pcic_handle *, int, u_int8_t));
75	int sock;
76
77	int vendor;
78	int flags;
79	int memalloc;
80	struct {
81		bus_addr_t addr;
82		bus_size_t size;
83		long offset;
84		int kind;
85	} mem[PCIC_MEM_WINS];
86	int ioalloc;
87	struct {
88		bus_addr_t addr;
89		bus_size_t size;
90		int width;
91	} io[PCIC_IO_WINS];
92	int ih_irq;
93	struct device *pcmcia;
94
95	int shutdown;
96};
97
98struct pccbb_win_chain {
99	bus_addr_t wc_start;		/* Caution: region [start, end], */
100	bus_addr_t wc_end;		/* instead of [start, end). */
101	int wc_flags;
102	bus_space_handle_t wc_handle;
103	TAILQ_ENTRY(pccbb_win_chain) wc_list;
104};
105#define	PCCBB_MEM_CACHABLE	1
106
107TAILQ_HEAD(pccbb_win_chain_head, pccbb_win_chain);
108
109struct pccbb_softc {
110	struct device sc_dev;
111	bus_space_tag_t sc_iot;
112	bus_space_tag_t sc_memt;
113	bus_dma_tag_t sc_dmat;
114
115#if rbus
116	rbus_tag_t sc_rbus_iot;		/* rbus for i/o donated from parent */
117	rbus_tag_t sc_rbus_memt;	/* rbus for mem donated from parent */
118#endif
119
120	bus_space_tag_t sc_base_memt;
121	bus_space_handle_t sc_base_memh;
122
123	struct timeout sc_ins_tmo;
124	void *sc_ih;			/* interrupt handler */
125	int sc_intrline;		/* interrupt line */
126	pcitag_t sc_intrtag;		/* copy of pa->pa_intrtag */
127	pci_intr_pin_t sc_intrpin;	/* copy of pa->pa_intrpin */
128	int sc_function;
129	u_int32_t sc_flags;
130#define	CBB_CARDEXIST	0x01
131#define	CBB_INSERTING	0x01000000
132#define	CBB_16BITCARD	0x04
133#define	CBB_32BITCARD	0x08
134
135	pci_chipset_tag_t sc_pc;
136	pcitag_t sc_tag;
137	int sc_chipset;			/* chipset id */
138
139	bus_addr_t sc_mem_start;	/* CardBus/PCMCIA memory start */
140	bus_addr_t sc_mem_end;		/* CardBus/PCMCIA memory end */
141	bus_addr_t sc_io_start;		/* CardBus/PCMCIA io start */
142	bus_addr_t sc_io_end;		/* CardBus/PCMCIA io end */
143
144	/* CardBus stuff */
145	struct cardslot_softc *sc_csc;
146
147	struct pccbb_win_chain_head sc_memwindow;
148	struct pccbb_win_chain_head sc_iowindow;
149
150	/* pcmcia stuff */
151	struct pcic_handle sc_pcmcia_h;
152	pcmcia_chipset_tag_t sc_pct;
153	int sc_pcmcia_flags;
154#define	PCCBB_PCMCIA_IO_RELOC	0x01	/* IO addr relocatable stuff exists */
155#define	PCCBB_PCMCIA_MEM_32	0x02	/* 32-bit memory address ready */
156#define	PCCBB_PCMCIA_16BITONLY	0x04	/* 32-bit mode disable */
157
158	struct proc *sc_event_thread;
159	SIMPLEQ_HEAD(, pcic_event) sc_events;
160
161	/* interrupt handler list on the bridge */
162	struct pccbb_intrhand_list *sc_pil;
163	int sc_pil_intr_enable;	/* can i call intr handler for child device? */
164};
165
166/*
167 * struct pccbb_intrhand_list holds interrupt handler and argument for
168 * child devices.
169 */
170
171struct pccbb_intrhand_list {
172	int (*pil_func) __P((void *));
173	void *pil_arg;
174	int pil_level;
175	struct pccbb_intrhand_list *pil_next;
176};
177
178#endif /* _DEV_PCI_PCCBBREG_H_ */
179