pccbbvar.h revision 1.2 
1/*	$OpenBSD: pccbbvar.h,v 1.2 2000/07/06 19:49:11 aaron Exp $ */
2/*	$NetBSD: pccbbvar.h,v 1.13 2000/06/08 10:28:29 haya Exp $	*/
3/*
4 * Copyright (c) 1999 HAYAKAWA Koichi.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 *    must display the following acknowledgement:
16 *	This product includes software developed by HAYAKAWA Koichi.
17 * 4. The name of the author may not be used to endorse or promote products
18 *    derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32/* require sys/device.h */
33/* require sys/queue.h */
34/* require sys/callout.h */
35/* require dev/ic/i82365reg.h */
36/* require dev/ic/i82365var.h */
37
38#ifndef _DEV_PCI_PCCBBVAR_H_
39#define	_DEV_PCI_PCCBBVAR_H_
40
41#define	PCIC_FLAG_SOCKETP	0x0001
42#define	PCIC_FLAG_CARDP		0x0002
43
44/* Chipset ID */
45#define	CB_UNKNOWN	0	/* NOT Cardbus-PCI bridge */
46#define	CB_TI113X	1	/* TI PCI1130/1131 */
47#define	CB_TI12XX	2	/* TI PCI1250/1220 */
48#define	CB_RX5C47X	3	/* RICOH RX5C475/476/477 */
49#define	CB_RX5C46X	4	/* RICOH RX5C465/466/467 */
50#define	CB_TOPIC95	5	/* Toshiba ToPIC95 */
51#define	CB_TOPIC95B	6	/* Toshiba ToPIC95B */
52#define	CB_TOPIC97	7	/* Toshiba ToPIC97 */
53#define	CB_CIRRUS	8	/* Cirrus Logic CL-PD683X */
54#define	CB_CHIPS_LAST	9	/* Sentinel */
55
56#if 0
57static char *cb_chipset_name[CB_CHIPS_LAST] = {
58	"unknown", "TI 113X", "TI 12XX", "RF5C47X", "RF5C46X", "ToPIC95",
59	"ToPIC95B", "ToPIC97", "CL-PD 683X",
60};
61#endif
62
63struct pccbb_softc;
64struct pccbb_intrhand_list;
65
66
67struct cbb_pcic_handle {
68	struct device *ph_parent;
69	bus_space_tag_t ph_base_t;
70	bus_space_handle_t ph_base_h;
71	u_int8_t (*ph_read) __P((struct cbb_pcic_handle *, int));
72	void (*ph_write) __P((struct cbb_pcic_handle *, int, u_int8_t));
73	int sock;
74
75	int vendor;
76	int flags;
77	int memalloc;
78	struct {
79		bus_addr_t addr;
80		bus_size_t size;
81		long offset;
82		int kind;
83	} mem[PCIC_MEM_WINS];
84	int ioalloc;
85	struct {
86		bus_addr_t addr;
87		bus_size_t size;
88		int width;
89	} io[PCIC_IO_WINS];
90	int ih_irq;
91	struct device *pcmcia;
92
93	int shutdown;
94};
95
96struct pccbb_win_chain {
97	bus_addr_t wc_start;		/* Caution: region [start, end], */
98	bus_addr_t wc_end;		/* instead of [start, end). */
99	int wc_flags;
100	bus_space_handle_t wc_handle;
101	TAILQ_ENTRY(pccbb_win_chain) wc_list;
102};
103#define	PCCBB_MEM_CACHABLE	1
104
105TAILQ_HEAD(pccbb_win_chain_head, pccbb_win_chain);
106
107struct pccbb_softc {
108	struct device sc_dev;
109	bus_space_tag_t sc_iot;
110	bus_space_tag_t sc_memt;
111	bus_dma_tag_t sc_dmat;
112
113#if rbus
114	rbus_tag_t sc_rbus_iot;		/* rbus for i/o donated from parent */
115	rbus_tag_t sc_rbus_memt;	/* rbus for mem donated from parent */
116#endif
117
118	bus_space_tag_t sc_base_memt;
119	bus_space_handle_t sc_base_memh;
120
121	void *sc_ih;			/* interrupt handler */
122	int sc_intrline;		/* interrupt line */
123	pcitag_t sc_intrtag;		/* copy of pa->pa_intrtag */
124	pci_intr_pin_t sc_intrpin;	/* copy of pa->pa_intrpin */
125	int sc_function;
126	u_int32_t sc_flags;
127#define	CBB_CARDEXIST	0x01
128#define	CBB_INSERTING	0x01000000
129#define	CBB_16BITCARD	0x04
130#define	CBB_32BITCARD	0x08
131
132	pci_chipset_tag_t sc_pc;
133	pcitag_t sc_tag;
134	int sc_chipset;			/* chipset id */
135
136	bus_addr_t sc_mem_start;	/* CardBus/PCMCIA memory start */
137	bus_addr_t sc_mem_end;		/* CardBus/PCMCIA memory end */
138	bus_addr_t sc_io_start;		/* CardBus/PCMCIA io start */
139	bus_addr_t sc_io_end;		/* CardBus/PCMCIA io end */
140
141	/* CardBus stuff */
142	struct cardslot_softc *sc_csc;
143
144	struct pccbb_win_chain_head sc_memwindow;
145	struct pccbb_win_chain_head sc_iowindow;
146
147	/* pcmcia stuff */
148	struct pcic_handle sc_pcmcia_h;
149	pcmcia_chipset_tag_t sc_pct;
150	int sc_pcmcia_flags;
151#define	PCCBB_PCMCIA_IO_RELOC	0x01	/* IO addr relocatable stuff exists */
152#define	PCCBB_PCMCIA_MEM_32	0x02	/* 32-bit memory address ready */
153#define	PCCBB_PCMCIA_16BITONLY	0x04	/* 32-bit mode disable */
154
155	struct proc *sc_event_thread;
156	SIMPLEQ_HEAD(, pcic_event) sc_events;
157
158	/* interrupt handler list on the bridge */
159	struct pccbb_intrhand_list *sc_pil;
160	int sc_pil_intr_enable;	/* can i call intr handler for child device? */
161};
162
163/*
164 * struct pccbb_intrhand_list holds interrupt handler and argument for
165 * child devices.
166 */
167
168struct pccbb_intrhand_list {
169	int (*pil_func) __P((void *));
170	void *pil_arg;
171	int pil_level;
172	struct pccbb_intrhand_list *pil_next;
173};
174
175#endif /* _DEV_PCI_PCCBBREG_H_ */
176