pccbbvar.h revision 1.15 
1/*	$OpenBSD: pccbbvar.h,v 1.15 2010/01/13 09:10:33 jsg Exp $	*/
2/*	$NetBSD: pccbbvar.h,v 1.13 2000/06/08 10:28:29 haya Exp $	*/
3/*
4 * Copyright (c) 1999 HAYAKAWA Koichi.  All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27/* require sys/device.h */
28/* require sys/queue.h */
29/* require sys/callout.h */
30/* require dev/ic/i82365reg.h */
31/* require dev/ic/i82365var.h */
32
33#ifndef _DEV_PCI_PCCBBVAR_H_
34#define	_DEV_PCI_PCCBBVAR_H_
35
36#include <sys/timeout.h>
37
38#define	PCIC_FLAG_SOCKETP	0x0001
39#define	PCIC_FLAG_CARDP		0x0002
40
41/* Chipset ID */
42#define	CB_UNKNOWN	0	/* NOT Cardbus-PCI bridge */
43#define	CB_TI113X	1	/* TI PCI1130/1131 */
44#define	CB_TI12XX	2	/* TI PCI1250/1220 */
45#define	CB_RX5C47X	3	/* RICOH RX5C475/476/477 */
46#define	CB_RX5C46X	4	/* RICOH RX5C465/466/467 */
47#define	CB_TOPIC95	5	/* Toshiba ToPIC95 */
48#define	CB_TOPIC95B	6	/* Toshiba ToPIC95B */
49#define	CB_TOPIC97	7	/* Toshiba ToPIC97 */
50#define	CB_CIRRUS	8	/* Cirrus Logic CL-PD683X */
51#define	CB_TI125X	9	/* TI PCI1250/1251(B)/1450 */
52#define	CB_OLDO2MICRO	10	/* O2Micro */
53#define	CB_CHIPS_LAST	11	/* Sentinel */
54
55#define PCCARD_VCC_UKN		0x00	/* Unknown */
56#define PCCARD_VCC_5V		0x01
57#define PCCARD_VCC_3V		0x02
58#define PCCARD_VCC_XV		0x04
59#define PCCARD_VCC_YV		0x08
60
61#if 0
62static char *cb_chipset_name[CB_CHIPS_LAST] = {
63	"unknown", "TI 113X", "TI 12XX", "RF5C47X", "RF5C46X", "ToPIC95",
64	"ToPIC95B", "ToPIC97", "CL-PD 683X", "TI 125X",
65};
66#endif
67
68struct pccbb_softc;
69struct pccbb_intrhand_list;
70
71
72struct cbb_pcic_handle {
73	struct device *ph_parent;
74	bus_space_tag_t ph_base_t;
75	bus_space_handle_t ph_base_h;
76	u_int8_t (*ph_read)(struct cbb_pcic_handle *, int);
77	void (*ph_write)(struct cbb_pcic_handle *, int, u_int8_t);
78	int sock;
79
80	int vendor;
81	int flags;
82	int memalloc;
83	struct {
84		bus_addr_t addr;
85		bus_size_t size;
86		long offset;
87		int kind;
88	} mem[PCIC_MEM_WINS];
89	int ioalloc;
90	struct {
91		bus_addr_t addr;
92		bus_size_t size;
93		int width;
94	} io[PCIC_IO_WINS];
95	int ih_irq;
96	struct device *pcmcia;
97
98	int shutdown;
99};
100
101struct pccbb_win_chain {
102	bus_addr_t wc_start;		/* Caution: region [start, end], */
103	bus_addr_t wc_end;		/* instead of [start, end). */
104	int wc_flags;
105	bus_space_handle_t wc_handle;
106	TAILQ_ENTRY(pccbb_win_chain) wc_list;
107};
108#define	PCCBB_MEM_CACHABLE	1
109
110TAILQ_HEAD(pccbb_win_chain_head, pccbb_win_chain);
111
112struct pccbb_softc {
113	struct device sc_dev;
114	bus_space_tag_t sc_iot;
115	bus_space_tag_t sc_memt;
116	bus_dma_tag_t sc_dmat;
117
118	rbus_tag_t sc_rbus_iot;		/* rbus for i/o donated from parent */
119	rbus_tag_t sc_rbus_memt;	/* rbus for mem donated from parent */
120
121	bus_space_tag_t sc_base_memt;
122	bus_space_handle_t sc_base_memh;
123
124	struct timeout sc_ins_tmo;
125	void *sc_ih;			/* interrupt handler */
126	int sc_intrline;		/* interrupt line */
127	pcitag_t sc_intrtag;		/* copy of pa->pa_intrtag */
128	pci_intr_pin_t sc_intrpin;	/* copy of pa->pa_intrpin */
129	int sc_function;
130	u_int32_t sc_flags;
131#define	CBB_CARDEXIST	0x01
132#define	CBB_INSERTING	0x01000000
133#define	CBB_16BITCARD	0x04
134#define	CBB_32BITCARD	0x08
135
136	pci_chipset_tag_t sc_pc;
137	pcitag_t sc_tag;
138	pcireg_t sc_id;
139	int sc_chipset;			/* chipset id */
140	int sc_ints_on;
141
142	pcireg_t sc_sockbase;		/* Socket base register */
143	pcireg_t sc_busnum;		/* bus number */
144
145	/* CardBus stuff */
146	struct cardslot_softc *sc_csc;
147
148	struct pccbb_win_chain_head sc_memwindow;
149	struct pccbb_win_chain_head sc_iowindow;
150
151	/* pcmcia stuff */
152	struct pcic_handle sc_pcmcia_h;
153	pcmcia_chipset_tag_t sc_pct;
154	int sc_pcmcia_flags;
155#define	PCCBB_PCMCIA_IO_RELOC	0x01	/* IO addr relocatable stuff exists */
156#define	PCCBB_PCMCIA_MEM_32	0x02	/* 32-bit memory address ready */
157#define	PCCBB_PCMCIA_16BITONLY	0x04	/* 32-bit mode disable */
158
159	struct proc *sc_event_thread;
160	SIMPLEQ_HEAD(, pcic_event) sc_events;
161
162	/* interrupt handler list on the bridge */
163	struct pccbb_intrhand_list *sc_pil;
164	int sc_pil_intr_enable;	/* can i call intr handler for child device? */
165};
166
167/*
168 * struct pccbb_intrhand_list holds interrupt handler and argument for
169 * child devices.
170 */
171
172struct pccbb_intrhand_list {
173	int (*pil_func)(void *);
174	void *pil_arg;
175	int pil_level;
176	struct evcount pil_count;
177	struct pccbb_intrhand_list *pil_next;
178};
179
180#endif /* _DEV_PCI_PCCBBREG_H_ */
181