nviic.c revision 1.12 
1/*	$OpenBSD: nviic.c,v 1.12 2007/09/13 16:49:03 brad Exp $ */
2
3/*
4 * Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19#include <sys/param.h>
20#include <sys/systm.h>
21#include <sys/device.h>
22#include <sys/kernel.h>
23#include <sys/rwlock.h>
24#include <sys/proc.h>
25
26#include <machine/bus.h>
27
28#include <dev/pci/pcidevs.h>
29#include <dev/pci/pcireg.h>
30#include <dev/pci/pcivar.h>
31
32#include <dev/i2c/i2cvar.h>
33
34/* PCI Configuration space registers */
35#define NVI_PCI_SMBASE1		0x20
36#define NVI_PCI_SMBASE2		0x24
37
38#define NVI_OLD_PCI_SMBASE1	0x50
39#define NVI_OLD_PCI_SMBASE2	0x54
40
41#define NVI_SMBASE(x)		((x) & 0xfffc)
42#define NVI_SMBASE_SIZE		8
43
44/* SMBus 2.0 registers */
45#define NVI_SMB_PRTCL		0x00	/* protocol, PEC */
46#define NVI_SMB_STS		0x01	/* status */
47#define NVI_SMB_ADDR		0x02	/* address */
48#define NVI_SMB_CMD		0x03	/* command */
49#define NVI_SMB_DATA(o)		(0x04 + (o))	/* 32 data registers */
50#define NVI_SMB_BCNT		0x24	/* number of data bytes */
51#define NVI_SMB_ALRM_A		0x25	/* alarm address */
52#define NVI_SMB_ALRM_D		0x26	/* 2 bytes alarm data */
53
54#define NVI_SMB_STS_DONE	0x80
55#define NVI_SMB_STS_ALRM	0x40
56#define NVI_SMB_STS_RES		0x20
57#define NVI_SMB_STS_STATUS	0x1f
58
59#define NVI_SMB_PRTCL_WRITE	0x00
60#define NVI_SMB_PRTCL_READ	0x01
61#define NVI_SMB_PRTCL_QUICK	0x02
62#define NVI_SMB_PRTCL_BYTE	0x04
63#define NVI_SMB_PRTCL_BYTE_DATA	0x06
64#define NVI_SMB_PRTCL_WORD_DATA	0x08
65#define NVI_SMB_PRTCL_BLOCK_DATA 0x0a
66#define NVI_SMB_PRTCL_PROC_CALL	0x0c
67#define NVI_SMB_PRTCL_BLOCK_PROC_CALL 0x0d
68#define NVI_SMB_PRTCL_PEC	0x80
69
70#ifdef NVIIC_DEBUG
71#define DPRINTF(x...)		do { if (nviic_debug) printf(x); } while (0)
72int nviic_debug = 1;
73#else
74#define DPRINTF(x...)		/* x */
75#endif
76
77/* there are two iic busses on this pci device */
78#define NVIIC_NBUS		2
79
80int		nviic_match(struct device *, void *, void *);
81void		nviic_attach(struct device *, struct device *, void *);
82
83struct nviic_softc;
84
85struct nviic_controller {
86	struct nviic_softc	*nc_sc;
87	bus_space_handle_t	nc_ioh;
88	struct rwlock		nc_lock;
89	struct i2c_controller	nc_i2c;
90};
91
92struct nviic_softc {
93	struct device		sc_dev;
94	bus_space_tag_t		sc_iot;
95	struct nviic_controller	sc_nc[NVIIC_NBUS];
96};
97
98struct cfattach nviic_ca = {
99	sizeof(struct nviic_softc), nviic_match, nviic_attach
100};
101
102struct cfdriver nviic_cd = {
103	NULL, "nviic", DV_DULL
104};
105
106int		nviic_i2c_acquire_bus(void *, int);
107void		nviic_i2c_release_bus(void *, int);
108int		nviic_i2c_exec(void *, i2c_op_t, i2c_addr_t, const void *,
109		    size_t, void *, size_t, int);
110
111u_int8_t	nviic_read(struct nviic_controller *, bus_size_t);
112void		nviic_write(struct nviic_controller *, bus_size_t, u_int8_t);
113
114#define DEVNAME(s)		((sc)->sc_dev.dv_xname)
115
116const struct pci_matchid nviic_ids[] = {
117	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_SMB },
118	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_SMB },
119	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_SMB },
120	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_SMB },
121	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_SMB },
122	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP51_SMB },
123	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_SMB },
124	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_SMB },
125	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_SMB },
126	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_SMB },
127	{ PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_SMB }
128};
129
130int
131nviic_match(struct device *parent, void *match, void *aux)
132{
133	return (pci_matchbyid(aux, nviic_ids,
134	    sizeof(nviic_ids) / sizeof(nviic_ids[0])));
135}
136
137void
138nviic_attach(struct device *parent, struct device *self, void *aux)
139{
140	struct nviic_softc		*sc = (struct nviic_softc *)self;
141	struct pci_attach_args		*pa = aux;
142	struct nviic_controller		*nc;
143	struct i2cbus_attach_args	iba;
144	int				baseregs[NVIIC_NBUS];
145	pcireg_t			reg;
146	int				i;
147
148	sc->sc_iot = pa->pa_iot;
149
150	printf("\n");
151
152	/* Older chipsets used non-standard BARs */
153	switch (PCI_PRODUCT(pa->pa_id)) {
154	case PCI_PRODUCT_NVIDIA_NFORCE2_SMB:
155	case PCI_PRODUCT_NVIDIA_NFORCE2_400_SMB:
156	case PCI_PRODUCT_NVIDIA_NFORCE3_SMB:
157	case PCI_PRODUCT_NVIDIA_NFORCE3_250_SMB:
158	case PCI_PRODUCT_NVIDIA_NFORCE4_SMB:
159		baseregs[0] = NVI_OLD_PCI_SMBASE1;
160		baseregs[1] = NVI_OLD_PCI_SMBASE2;
161		break;
162	default:
163		baseregs[0] = NVI_PCI_SMBASE1;
164		baseregs[1] = NVI_PCI_SMBASE2;
165	}
166
167	for (i = 0; i < NVIIC_NBUS; i++) {
168		nc = &sc->sc_nc[i];
169
170		reg = pci_conf_read(pa->pa_pc, pa->pa_tag, baseregs[i]);
171		if (NVI_SMBASE(reg) == 0 ||
172		    bus_space_map(sc->sc_iot, NVI_SMBASE(reg), NVI_SMBASE_SIZE,
173		    0, &nc->nc_ioh)) {
174			printf("%s: unable to map space for bus %d\n",
175			    DEVNAME(sc), i);
176			continue;
177		}
178
179		nc->nc_sc = sc;
180		rw_init(&nc->nc_lock, "nviic");
181		nc->nc_i2c.ic_cookie = nc;
182		nc->nc_i2c.ic_acquire_bus = nviic_i2c_acquire_bus;
183		nc->nc_i2c.ic_release_bus = nviic_i2c_release_bus;
184		nc->nc_i2c.ic_exec = nviic_i2c_exec;
185
186		bzero(&iba, sizeof(iba));
187		iba.iba_name = "iic";
188		iba.iba_tag = &nc->nc_i2c;
189		config_found(self, &iba, iicbus_print);
190	}
191}
192
193int
194nviic_i2c_acquire_bus(void *arg, int flags)
195{
196	struct nviic_controller		*nc = arg;
197
198	if (cold || (flags & I2C_F_POLL))
199		return (0);
200
201	return (rw_enter(&nc->nc_lock, RW_WRITE | RW_INTR));
202}
203
204void
205nviic_i2c_release_bus(void *arg, int flags)
206{
207	struct nviic_controller		*nc = arg;
208
209	if (cold || (flags & I2C_F_POLL))
210		return;
211
212	rw_exit(&nc->nc_lock);
213}
214
215int
216nviic_i2c_exec(void *arg, i2c_op_t op, i2c_addr_t addr,
217    const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
218{
219	struct nviic_controller		*nc = arg;
220#ifdef NVIIC_DEBUG
221	struct nviic_softc		*sc = nc->nc_sc;
222#endif
223	u_int8_t			protocol;
224	u_int8_t			*b;
225	u_int8_t			sts;
226	int				i;
227
228	DPRINTF("%s: exec op: %d addr: 0x%x cmdlen: %d len: %d flags 0x%x\n",
229	    DEVNAME(sc), op, addr, cmdlen, len, flags);
230
231	if (cold)
232		flags |= I2C_F_POLL;
233
234	if (I2C_OP_STOP_P(op) == 0 || cmdlen > 1 || len > 2)
235		return (1);
236
237	/* set slave address */
238	nviic_write(nc, NVI_SMB_ADDR, addr << 1);
239
240	/* set command byte */
241	if (cmdlen > 0) {
242		b = (u_int8_t *)cmdbuf;
243		nviic_write(nc, NVI_SMB_CMD, b[0]);
244	}
245
246	b = (u_int8_t *)buf;
247
248	/* write data */
249	if (I2C_OP_WRITE_P(op)) {
250		for (i = 0; i < len; i++)
251			nviic_write(nc, NVI_SMB_DATA(i), b[i]);
252	}
253
254	switch (len) {
255	case 0:
256		protocol = NVI_SMB_PRTCL_BYTE;
257		break;
258	case 1:
259		protocol = NVI_SMB_PRTCL_BYTE_DATA;
260		break;
261	case 2:
262		protocol = NVI_SMB_PRTCL_WORD_DATA;
263		break;
264	}
265
266	/* set direction */
267	if (I2C_OP_READ_P(op))
268		protocol |= NVI_SMB_PRTCL_READ;
269
270	/* start transaction */
271	nviic_write(nc, NVI_SMB_PRTCL, protocol);
272
273	for (i = 1000; i > 0; i--) {
274		delay(100);
275		if (nviic_read(nc, NVI_SMB_PRTCL) == 0)
276			break;
277	}
278	if (i == 0) {
279		DPRINTF("%s: timeout\n", DEVNAME(sc));
280		return (1);
281	}
282
283	sts = nviic_read(nc, NVI_SMB_STS);
284	if (sts & NVI_SMB_STS_STATUS)
285		return (1);
286
287	/* read data */
288	if (I2C_OP_READ_P(op)) {
289		for (i = 0; i < len; i++)
290			b[i] = nviic_read(nc, NVI_SMB_DATA(i));
291	}
292
293	return (0);
294}
295
296u_int8_t
297nviic_read(struct nviic_controller *nc, bus_size_t r)
298{
299	struct nviic_softc		*sc = nc->nc_sc;
300
301	bus_space_barrier(sc->sc_iot, nc->nc_ioh, r, 1,
302	    BUS_SPACE_BARRIER_READ);
303	return (bus_space_read_1(sc->sc_iot, nc->nc_ioh, r));
304}
305
306void
307nviic_write(struct nviic_controller *nc, bus_size_t r, u_int8_t v)
308{
309	struct nviic_softc		*sc = nc->nc_sc;
310
311	bus_space_write_1(sc->sc_iot, nc->nc_ioh, r, v);
312	bus_space_barrier(sc->sc_iot, nc->nc_ioh, r, 1,
313	    BUS_SPACE_BARRIER_WRITE);
314}
315